be.c revision 1.73
1 /* $NetBSD: be.c,v 1.73 2009/09/18 14:35:11 tsutsui Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Copyright (c) 1998 Theo de Raadt and Jason L. Wright. 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. The name of the authors may not be used to endorse or promote products 45 * derived from this software without specific prior written permission. 46 * 47 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR 48 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 49 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 50 * IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, 51 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 52 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 53 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 54 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 55 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 56 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 57 */ 58 59 #include <sys/cdefs.h> 60 __KERNEL_RCSID(0, "$NetBSD: be.c,v 1.73 2009/09/18 14:35:11 tsutsui Exp $"); 61 62 #include "opt_ddb.h" 63 #include "opt_inet.h" 64 #include "bpfilter.h" 65 #include "rnd.h" 66 67 #include <sys/param.h> 68 #include <sys/systm.h> 69 #include <sys/callout.h> 70 #include <sys/kernel.h> 71 #include <sys/errno.h> 72 #include <sys/ioctl.h> 73 #include <sys/mbuf.h> 74 #include <sys/socket.h> 75 #include <sys/syslog.h> 76 #include <sys/device.h> 77 #include <sys/malloc.h> 78 #if NRND > 0 79 #include <sys/rnd.h> 80 #endif 81 82 #include <net/if.h> 83 #include <net/if_dl.h> 84 #include <net/if_types.h> 85 #include <net/netisr.h> 86 #include <net/if_media.h> 87 #include <net/if_ether.h> 88 89 #ifdef INET 90 #include <netinet/in.h> 91 #include <netinet/if_inarp.h> 92 #include <netinet/in_systm.h> 93 #include <netinet/in_var.h> 94 #include <netinet/ip.h> 95 #endif 96 97 98 #if NBPFILTER > 0 99 #include <net/bpf.h> 100 #include <net/bpfdesc.h> 101 #endif 102 103 #include <sys/bus.h> 104 #include <sys/intr.h> 105 #include <machine/autoconf.h> 106 107 #include <dev/sbus/sbusvar.h> 108 109 #include <dev/mii/mii.h> 110 #include <dev/mii/miivar.h> 111 112 #include <dev/sbus/qecreg.h> 113 #include <dev/sbus/qecvar.h> 114 #include <dev/sbus/bereg.h> 115 116 struct be_softc { 117 device_t sc_dev; 118 bus_space_tag_t sc_bustag; /* bus & DMA tags */ 119 bus_dma_tag_t sc_dmatag; 120 bus_dmamap_t sc_dmamap; 121 struct ethercom sc_ethercom; 122 /*struct ifmedia sc_ifmedia; -* interface media */ 123 struct mii_data sc_mii; /* MII media control */ 124 #define sc_media sc_mii.mii_media/* shorthand */ 125 int sc_phys[2]; /* MII instance -> phy */ 126 127 struct callout sc_tick_ch; 128 129 /* 130 * Some `mii_softc' items we need to emulate MII operation 131 * for our internal transceiver. 132 */ 133 int sc_mii_inst; /* instance of internal phy */ 134 int sc_mii_active; /* currently active medium */ 135 int sc_mii_ticks; /* tick counter */ 136 int sc_mii_flags; /* phy status flags */ 137 #define MIIF_HAVELINK 0x04000000 138 int sc_intphy_curspeed; /* Established link speed */ 139 140 struct qec_softc *sc_qec; /* QEC parent */ 141 142 bus_space_handle_t sc_qr; /* QEC registers */ 143 bus_space_handle_t sc_br; /* BE registers */ 144 bus_space_handle_t sc_cr; /* channel registers */ 145 bus_space_handle_t sc_tr; /* transceiver registers */ 146 147 u_int sc_rev; 148 149 int sc_channel; /* channel number */ 150 int sc_burst; 151 152 struct qec_ring sc_rb; /* Packet Ring Buffer */ 153 154 /* MAC address */ 155 uint8_t sc_enaddr[ETHER_ADDR_LEN]; 156 #ifdef BEDEBUG 157 int sc_debug; 158 #endif 159 }; 160 161 static int bematch(device_t, cfdata_t, void *); 162 static void beattach(device_t, device_t, void *); 163 164 static int beinit(struct ifnet *); 165 static void bestart(struct ifnet *); 166 static void bestop(struct ifnet *, int); 167 static void bewatchdog(struct ifnet *); 168 static int beioctl(struct ifnet *, u_long, void *); 169 static void bereset(struct be_softc *); 170 static void behwreset(struct be_softc *); 171 172 static int beintr(void *); 173 static int berint(struct be_softc *); 174 static int betint(struct be_softc *); 175 static int beqint(struct be_softc *, uint32_t); 176 static int beeint(struct be_softc *, uint32_t); 177 178 static void be_read(struct be_softc *, int, int); 179 static int be_put(struct be_softc *, int, struct mbuf *); 180 static struct mbuf *be_get(struct be_softc *, int, int); 181 182 static void be_pal_gate(struct be_softc *, int); 183 184 /* ifmedia callbacks */ 185 static void be_ifmedia_sts(struct ifnet *, struct ifmediareq *); 186 static int be_ifmedia_upd(struct ifnet *); 187 188 static void be_mcreset(struct be_softc *); 189 190 /* MII methods & callbacks */ 191 static int be_mii_readreg(device_t, int, int); 192 static void be_mii_writereg(device_t, int, int, int); 193 static void be_mii_statchg(device_t); 194 195 /* MII helpers */ 196 static void be_mii_sync(struct be_softc *); 197 static void be_mii_sendbits(struct be_softc *, int, uint32_t, int); 198 static int be_mii_reset(struct be_softc *, int); 199 static int be_tcvr_read_bit(struct be_softc *, int); 200 static void be_tcvr_write_bit(struct be_softc *, int, int); 201 202 static void be_tick(void *); 203 #if 0 204 static void be_intphy_auto(struct be_softc *); 205 #endif 206 static void be_intphy_status(struct be_softc *); 207 static int be_intphy_service(struct be_softc *, struct mii_data *, int); 208 209 210 CFATTACH_DECL_NEW(be, sizeof(struct be_softc), 211 bematch, beattach, NULL, NULL); 212 213 int 214 bematch(device_t parent, cfdata_t cf, void *aux) 215 { 216 struct sbus_attach_args *sa = aux; 217 218 return strcmp(cf->cf_name, sa->sa_name) == 0; 219 } 220 221 void 222 beattach(device_t parent, device_t self, void *aux) 223 { 224 struct sbus_attach_args *sa = aux; 225 struct qec_softc *qec = device_private(parent); 226 struct be_softc *sc = device_private(self); 227 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 228 struct mii_data *mii = &sc->sc_mii; 229 struct mii_softc *child; 230 int node = sa->sa_node; 231 bus_dma_tag_t dmatag = sa->sa_dmatag; 232 bus_dma_segment_t seg; 233 bus_size_t size; 234 int instance; 235 int rseg, error; 236 uint32_t v; 237 238 sc->sc_dev = self; 239 240 if (sa->sa_nreg < 3) { 241 printf(": only %d register sets\n", sa->sa_nreg); 242 return; 243 } 244 245 if (bus_space_map(sa->sa_bustag, 246 (bus_addr_t)BUS_ADDR(sa->sa_reg[0].oa_space, sa->sa_reg[0].oa_base), 247 (bus_size_t)sa->sa_reg[0].oa_size, 248 0, &sc->sc_cr) != 0) { 249 printf(": cannot map registers\n"); 250 return; 251 } 252 253 if (bus_space_map(sa->sa_bustag, 254 (bus_addr_t)BUS_ADDR(sa->sa_reg[1].oa_space, sa->sa_reg[1].oa_base), 255 (bus_size_t)sa->sa_reg[1].oa_size, 256 0, &sc->sc_br) != 0) { 257 printf(": cannot map registers\n"); 258 return; 259 } 260 261 if (bus_space_map(sa->sa_bustag, 262 (bus_addr_t)BUS_ADDR(sa->sa_reg[2].oa_space, sa->sa_reg[2].oa_base), 263 (bus_size_t)sa->sa_reg[2].oa_size, 264 0, &sc->sc_tr) != 0) { 265 printf(": cannot map registers\n"); 266 return; 267 } 268 269 sc->sc_bustag = sa->sa_bustag; 270 sc->sc_qec = qec; 271 sc->sc_qr = qec->sc_regs; 272 273 sc->sc_rev = prom_getpropint(node, "board-version", -1); 274 printf(": rev %x,", sc->sc_rev); 275 276 callout_init(&sc->sc_tick_ch, 0); 277 278 sc->sc_channel = prom_getpropint(node, "channel#", -1); 279 if (sc->sc_channel == -1) 280 sc->sc_channel = 0; 281 282 sc->sc_burst = prom_getpropint(node, "burst-sizes", -1); 283 if (sc->sc_burst == -1) 284 sc->sc_burst = qec->sc_burst; 285 286 /* Clamp at parent's burst sizes */ 287 sc->sc_burst &= qec->sc_burst; 288 289 /* Establish interrupt handler */ 290 if (sa->sa_nintr) 291 (void)bus_intr_establish(sa->sa_bustag, sa->sa_pri, IPL_NET, 292 beintr, sc); 293 294 prom_getether(node, sc->sc_enaddr); 295 printf(" address %s\n", ether_sprintf(sc->sc_enaddr)); 296 297 /* 298 * Allocate descriptor ring and buffers. 299 */ 300 301 /* for now, allocate as many bufs as there are ring descriptors */ 302 sc->sc_rb.rb_ntbuf = QEC_XD_RING_MAXSIZE; 303 sc->sc_rb.rb_nrbuf = QEC_XD_RING_MAXSIZE; 304 305 size = 306 QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd) + 307 QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd) + 308 sc->sc_rb.rb_ntbuf * BE_PKT_BUF_SZ + 309 sc->sc_rb.rb_nrbuf * BE_PKT_BUF_SZ; 310 311 /* Get a DMA handle */ 312 if ((error = bus_dmamap_create(dmatag, size, 1, size, 0, 313 BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) { 314 aprint_error_dev(self, "DMA map create error %d\n", error); 315 return; 316 } 317 318 /* Allocate DMA buffer */ 319 if ((error = bus_dmamem_alloc(sa->sa_dmatag, size, 0, 0, 320 &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 321 aprint_error_dev(self, "DMA buffer alloc error %d\n", error); 322 return; 323 } 324 325 /* Map DMA memory in CPU addressable space */ 326 if ((error = bus_dmamem_map(sa->sa_dmatag, &seg, rseg, size, 327 &sc->sc_rb.rb_membase, BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 328 aprint_error_dev(self, "DMA buffer map error %d\n", error); 329 bus_dmamem_free(sa->sa_dmatag, &seg, rseg); 330 return; 331 } 332 333 /* Load the buffer */ 334 if ((error = bus_dmamap_load(dmatag, sc->sc_dmamap, 335 sc->sc_rb.rb_membase, size, NULL, BUS_DMA_NOWAIT)) != 0) { 336 aprint_error_dev(self, "DMA buffer map load error %d\n", error); 337 bus_dmamem_unmap(dmatag, sc->sc_rb.rb_membase, size); 338 bus_dmamem_free(dmatag, &seg, rseg); 339 return; 340 } 341 sc->sc_rb.rb_dmabase = sc->sc_dmamap->dm_segs[0].ds_addr; 342 343 /* 344 * Initialize our media structures and MII info. 345 */ 346 mii->mii_ifp = ifp; 347 mii->mii_readreg = be_mii_readreg; 348 mii->mii_writereg = be_mii_writereg; 349 mii->mii_statchg = be_mii_statchg; 350 351 ifmedia_init(&mii->mii_media, 0, be_ifmedia_upd, be_ifmedia_sts); 352 353 /* 354 * Initialize transceiver and determine which PHY connection to use. 355 */ 356 be_mii_sync(sc); 357 v = bus_space_read_4(sc->sc_bustag, sc->sc_tr, BE_TRI_MGMTPAL); 358 359 instance = 0; 360 361 if ((v & MGMT_PAL_EXT_MDIO) != 0) { 362 363 mii_attach(self, mii, 0xffffffff, BE_PHY_EXTERNAL, 364 MII_OFFSET_ANY, 0); 365 366 child = LIST_FIRST(&mii->mii_phys); 367 if (child == NULL) { 368 /* No PHY attached */ 369 ifmedia_add(&sc->sc_media, 370 IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, instance), 371 0, NULL); 372 ifmedia_set(&sc->sc_media, 373 IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, instance)); 374 } else { 375 /* 376 * Note: we support just one PHY on the external 377 * MII connector. 378 */ 379 #ifdef DIAGNOSTIC 380 if (LIST_NEXT(child, mii_list) != NULL) { 381 aprint_error_dev(self, 382 "spurious MII device %s attached\n", 383 device_xname(child->mii_dev)); 384 } 385 #endif 386 if (child->mii_phy != BE_PHY_EXTERNAL || 387 child->mii_inst > 0) { 388 aprint_error_dev(self, 389 "cannot accommodate MII device %s" 390 " at phy %d, instance %d\n", 391 device_xname(child->mii_dev), 392 child->mii_phy, child->mii_inst); 393 } else { 394 sc->sc_phys[instance] = child->mii_phy; 395 } 396 397 /* 398 * XXX - we can really do the following ONLY if the 399 * phy indeed has the auto negotiation capability!! 400 */ 401 ifmedia_set(&sc->sc_media, 402 IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, instance)); 403 404 /* Mark our current media setting */ 405 be_pal_gate(sc, BE_PHY_EXTERNAL); 406 instance++; 407 } 408 409 } 410 411 if ((v & MGMT_PAL_INT_MDIO) != 0) { 412 /* 413 * The be internal phy looks vaguely like MII hardware, 414 * but not enough to be able to use the MII device 415 * layer. Hence, we have to take care of media selection 416 * ourselves. 417 */ 418 419 sc->sc_mii_inst = instance; 420 sc->sc_phys[instance] = BE_PHY_INTERNAL; 421 422 /* Use `ifm_data' to store BMCR bits */ 423 ifmedia_add(&sc->sc_media, 424 IFM_MAKEWORD(IFM_ETHER, IFM_10_T, 0, instance), 425 0, NULL); 426 ifmedia_add(&sc->sc_media, 427 IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, 0, instance), 428 BMCR_S100, NULL); 429 ifmedia_add(&sc->sc_media, 430 IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, instance), 431 0, NULL); 432 433 printf("on-board transceiver at %s: 10baseT, 100baseTX, auto\n", 434 device_xname(self)); 435 436 be_mii_reset(sc, BE_PHY_INTERNAL); 437 /* Only set default medium here if there's no external PHY */ 438 if (instance == 0) { 439 be_pal_gate(sc, BE_PHY_INTERNAL); 440 ifmedia_set(&sc->sc_media, 441 IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, instance)); 442 } else 443 be_mii_writereg(self, 444 BE_PHY_INTERNAL, MII_BMCR, BMCR_ISO); 445 } 446 447 memcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 448 ifp->if_softc = sc; 449 ifp->if_start = bestart; 450 ifp->if_ioctl = beioctl; 451 ifp->if_watchdog = bewatchdog; 452 ifp->if_init = beinit; 453 ifp->if_stop = bestop; 454 ifp->if_flags = 455 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 456 IFQ_SET_READY(&ifp->if_snd); 457 458 /* claim 802.1q capability */ 459 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 460 461 /* Attach the interface. */ 462 if_attach(ifp); 463 ether_ifattach(ifp, sc->sc_enaddr); 464 } 465 466 467 /* 468 * Routine to copy from mbuf chain to transmit buffer in 469 * network buffer memory. 470 */ 471 static inline int 472 be_put(struct be_softc *sc, int idx, struct mbuf *m) 473 { 474 struct mbuf *n; 475 int len, tlen = 0, boff = 0; 476 void *bp; 477 478 bp = sc->sc_rb.rb_txbuf + (idx % sc->sc_rb.rb_ntbuf) * BE_PKT_BUF_SZ; 479 480 for (; m; m = n) { 481 len = m->m_len; 482 if (len == 0) { 483 MFREE(m, n); 484 continue; 485 } 486 memcpy((char *)bp + boff, mtod(m, void *), len); 487 boff += len; 488 tlen += len; 489 MFREE(m, n); 490 } 491 return tlen; 492 } 493 494 /* 495 * Pull data off an interface. 496 * Len is the length of data, with local net header stripped. 497 * We copy the data into mbufs. When full cluster sized units are present, 498 * we copy into clusters. 499 */ 500 static inline struct mbuf * 501 be_get(struct be_softc *sc, int idx, int totlen) 502 { 503 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 504 struct mbuf *m; 505 struct mbuf *top, **mp; 506 int len, pad, boff = 0; 507 void *bp; 508 509 bp = sc->sc_rb.rb_rxbuf + (idx % sc->sc_rb.rb_nrbuf) * BE_PKT_BUF_SZ; 510 511 MGETHDR(m, M_DONTWAIT, MT_DATA); 512 if (m == NULL) 513 return (NULL); 514 m->m_pkthdr.rcvif = ifp; 515 m->m_pkthdr.len = totlen; 516 517 pad = ALIGN(sizeof(struct ether_header)) - sizeof(struct ether_header); 518 m->m_data += pad; 519 len = MHLEN - pad; 520 top = NULL; 521 mp = ⊤ 522 523 while (totlen > 0) { 524 if (top) { 525 MGET(m, M_DONTWAIT, MT_DATA); 526 if (m == NULL) { 527 m_freem(top); 528 return (NULL); 529 } 530 len = MLEN; 531 } 532 if (top && totlen >= MINCLSIZE) { 533 MCLGET(m, M_DONTWAIT); 534 if (m->m_flags & M_EXT) 535 len = MCLBYTES; 536 } 537 m->m_len = len = min(totlen, len); 538 memcpy(mtod(m, void *), (char *)bp + boff, len); 539 boff += len; 540 totlen -= len; 541 *mp = m; 542 mp = &m->m_next; 543 } 544 545 return top; 546 } 547 548 /* 549 * Pass a packet to the higher levels. 550 */ 551 static inline void 552 be_read(struct be_softc *sc, int idx, int len) 553 { 554 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 555 struct mbuf *m; 556 557 if (len <= sizeof(struct ether_header) || 558 len > ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN) { 559 #ifdef BEDEBUG 560 if (sc->sc_debug) 561 printf("%s: invalid packet size %d; dropping\n", 562 ifp->if_xname, len); 563 #endif 564 ifp->if_ierrors++; 565 return; 566 } 567 568 /* 569 * Pull packet off interface. 570 */ 571 m = be_get(sc, idx, len); 572 if (m == NULL) { 573 ifp->if_ierrors++; 574 return; 575 } 576 ifp->if_ipackets++; 577 578 #if NBPFILTER > 0 579 /* 580 * Check if there's a BPF listener on this interface. 581 * If so, hand off the raw packet to BPF. 582 */ 583 if (ifp->if_bpf) 584 bpf_mtap(ifp->if_bpf, m); 585 #endif 586 /* Pass the packet up. */ 587 (*ifp->if_input)(ifp, m); 588 } 589 590 /* 591 * Start output on interface. 592 * We make two assumptions here: 593 * 1) that the current priority is set to splnet _before_ this code 594 * is called *and* is returned to the appropriate priority after 595 * return 596 * 2) that the IFF_OACTIVE flag is checked before this code is called 597 * (i.e. that the output part of the interface is idle) 598 */ 599 void 600 bestart(struct ifnet *ifp) 601 { 602 struct be_softc *sc = ifp->if_softc; 603 struct qec_xd *txd = sc->sc_rb.rb_txd; 604 struct mbuf *m; 605 unsigned int bix, len; 606 unsigned int ntbuf = sc->sc_rb.rb_ntbuf; 607 608 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 609 return; 610 611 bix = sc->sc_rb.rb_tdhead; 612 613 for (;;) { 614 IFQ_DEQUEUE(&ifp->if_snd, m); 615 if (m == 0) 616 break; 617 618 #if NBPFILTER > 0 619 /* 620 * If BPF is listening on this interface, let it see the 621 * packet before we commit it to the wire. 622 */ 623 if (ifp->if_bpf) 624 bpf_mtap(ifp->if_bpf, m); 625 #endif 626 627 /* 628 * Copy the mbuf chain into the transmit buffer. 629 */ 630 len = be_put(sc, bix, m); 631 632 /* 633 * Initialize transmit registers and start transmission 634 */ 635 txd[bix].xd_flags = QEC_XD_OWN | QEC_XD_SOP | QEC_XD_EOP | 636 (len & QEC_XD_LENGTH); 637 bus_space_write_4(sc->sc_bustag, sc->sc_cr, 638 BE_CRI_CTRL, BE_CR_CTRL_TWAKEUP); 639 640 if (++bix == QEC_XD_RING_MAXSIZE) 641 bix = 0; 642 643 if (++sc->sc_rb.rb_td_nbusy == ntbuf) { 644 ifp->if_flags |= IFF_OACTIVE; 645 break; 646 } 647 } 648 649 sc->sc_rb.rb_tdhead = bix; 650 } 651 652 void 653 bestop(struct ifnet *ifp, int disable) 654 { 655 struct be_softc *sc = ifp->if_softc; 656 657 callout_stop(&sc->sc_tick_ch); 658 659 /* Down the MII. */ 660 mii_down(&sc->sc_mii); 661 (void)be_intphy_service(sc, &sc->sc_mii, MII_DOWN); 662 663 behwreset(sc); 664 } 665 666 void 667 behwreset(struct be_softc *sc) 668 { 669 int n; 670 bus_space_tag_t t = sc->sc_bustag; 671 bus_space_handle_t br = sc->sc_br; 672 673 /* Stop the transmitter */ 674 bus_space_write_4(t, br, BE_BRI_TXCFG, 0); 675 for (n = 32; n > 0; n--) { 676 if (bus_space_read_4(t, br, BE_BRI_TXCFG) == 0) 677 break; 678 DELAY(20); 679 } 680 681 /* Stop the receiver */ 682 bus_space_write_4(t, br, BE_BRI_RXCFG, 0); 683 for (n = 32; n > 0; n--) { 684 if (bus_space_read_4(t, br, BE_BRI_RXCFG) == 0) 685 break; 686 DELAY(20); 687 } 688 } 689 690 /* 691 * Reset interface. 692 */ 693 void 694 bereset(struct be_softc *sc) 695 { 696 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 697 int s; 698 699 s = splnet(); 700 behwreset(sc); 701 if ((sc->sc_ethercom.ec_if.if_flags & IFF_UP) != 0) 702 beinit(ifp); 703 splx(s); 704 } 705 706 void 707 bewatchdog(struct ifnet *ifp) 708 { 709 struct be_softc *sc = ifp->if_softc; 710 711 log(LOG_ERR, "%s: device timeout\n", device_xname(sc->sc_dev)); 712 ++sc->sc_ethercom.ec_if.if_oerrors; 713 714 bereset(sc); 715 } 716 717 int 718 beintr(void *arg) 719 { 720 struct be_softc *sc = arg; 721 bus_space_tag_t t = sc->sc_bustag; 722 uint32_t whyq, whyb, whyc; 723 int r = 0; 724 725 /* Read QEC status, channel status and BE status */ 726 whyq = bus_space_read_4(t, sc->sc_qr, QEC_QRI_STAT); 727 whyc = bus_space_read_4(t, sc->sc_cr, BE_CRI_STAT); 728 whyb = bus_space_read_4(t, sc->sc_br, BE_BRI_STAT); 729 730 if (whyq & QEC_STAT_BM) 731 r |= beeint(sc, whyb); 732 733 if (whyq & QEC_STAT_ER) 734 r |= beqint(sc, whyc); 735 736 if (whyq & QEC_STAT_TX && whyc & BE_CR_STAT_TXIRQ) 737 r |= betint(sc); 738 739 if (whyq & QEC_STAT_RX && whyc & BE_CR_STAT_RXIRQ) 740 r |= berint(sc); 741 742 return r; 743 } 744 745 /* 746 * QEC Interrupt. 747 */ 748 int 749 beqint(struct be_softc *sc, uint32_t why) 750 { 751 device_t self = sc->sc_dev; 752 int r = 0, rst = 0; 753 754 if (why & BE_CR_STAT_TXIRQ) 755 r |= 1; 756 if (why & BE_CR_STAT_RXIRQ) 757 r |= 1; 758 759 if (why & BE_CR_STAT_BERROR) { 760 r |= 1; 761 rst = 1; 762 aprint_error_dev(self, "bigmac error\n"); 763 } 764 765 if (why & BE_CR_STAT_TXDERR) { 766 r |= 1; 767 rst = 1; 768 aprint_error_dev(self, "bogus tx descriptor\n"); 769 } 770 771 if (why & (BE_CR_STAT_TXLERR | BE_CR_STAT_TXPERR | BE_CR_STAT_TXSERR)) { 772 r |= 1; 773 rst = 1; 774 aprint_error_dev(self, "tx DMA error ( "); 775 if (why & BE_CR_STAT_TXLERR) 776 printf("Late "); 777 if (why & BE_CR_STAT_TXPERR) 778 printf("Parity "); 779 if (why & BE_CR_STAT_TXSERR) 780 printf("Generic "); 781 printf(")\n"); 782 } 783 784 if (why & BE_CR_STAT_RXDROP) { 785 r |= 1; 786 rst = 1; 787 aprint_error_dev(self, "out of rx descriptors\n"); 788 } 789 790 if (why & BE_CR_STAT_RXSMALL) { 791 r |= 1; 792 rst = 1; 793 aprint_error_dev(self, "rx descriptor too small\n"); 794 } 795 796 if (why & (BE_CR_STAT_RXLERR | BE_CR_STAT_RXPERR | BE_CR_STAT_RXSERR)) { 797 r |= 1; 798 rst = 1; 799 aprint_error_dev(self, "rx DMA error ( "); 800 if (why & BE_CR_STAT_RXLERR) 801 printf("Late "); 802 if (why & BE_CR_STAT_RXPERR) 803 printf("Parity "); 804 if (why & BE_CR_STAT_RXSERR) 805 printf("Generic "); 806 printf(")\n"); 807 } 808 809 if (!r) { 810 rst = 1; 811 aprint_error_dev(self, "unexpected error interrupt %08x\n", 812 why); 813 } 814 815 if (rst) { 816 printf("%s: resetting\n", device_xname(self)); 817 bereset(sc); 818 } 819 820 return r; 821 } 822 823 /* 824 * Error interrupt. 825 */ 826 int 827 beeint(struct be_softc *sc, uint32_t why) 828 { 829 device_t self = sc->sc_dev; 830 int r = 0, rst = 0; 831 832 if (why & BE_BR_STAT_RFIFOVF) { 833 r |= 1; 834 rst = 1; 835 aprint_error_dev(self, "receive fifo overrun\n"); 836 } 837 if (why & BE_BR_STAT_TFIFO_UND) { 838 r |= 1; 839 rst = 1; 840 aprint_error_dev(self, "transmit fifo underrun\n"); 841 } 842 if (why & BE_BR_STAT_MAXPKTERR) { 843 r |= 1; 844 rst = 1; 845 aprint_error_dev(self, "max packet size error\n"); 846 } 847 848 if (!r) { 849 rst = 1; 850 aprint_error_dev(self, "unexpected error interrupt %08x\n", 851 why); 852 } 853 854 if (rst) { 855 printf("%s: resetting\n", device_xname(self)); 856 bereset(sc); 857 } 858 859 return r; 860 } 861 862 /* 863 * Transmit interrupt. 864 */ 865 int 866 betint(struct be_softc *sc) 867 { 868 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 869 bus_space_tag_t t = sc->sc_bustag; 870 bus_space_handle_t br = sc->sc_br; 871 unsigned int bix, txflags; 872 873 /* 874 * Unload collision counters 875 */ 876 ifp->if_collisions += 877 bus_space_read_4(t, br, BE_BRI_NCCNT) + 878 bus_space_read_4(t, br, BE_BRI_FCCNT) + 879 bus_space_read_4(t, br, BE_BRI_EXCNT) + 880 bus_space_read_4(t, br, BE_BRI_LTCNT); 881 882 /* 883 * the clear the hardware counters 884 */ 885 bus_space_write_4(t, br, BE_BRI_NCCNT, 0); 886 bus_space_write_4(t, br, BE_BRI_FCCNT, 0); 887 bus_space_write_4(t, br, BE_BRI_EXCNT, 0); 888 bus_space_write_4(t, br, BE_BRI_LTCNT, 0); 889 890 bix = sc->sc_rb.rb_tdtail; 891 892 for (;;) { 893 if (sc->sc_rb.rb_td_nbusy <= 0) 894 break; 895 896 txflags = sc->sc_rb.rb_txd[bix].xd_flags; 897 898 if (txflags & QEC_XD_OWN) 899 break; 900 901 ifp->if_flags &= ~IFF_OACTIVE; 902 ifp->if_opackets++; 903 904 if (++bix == QEC_XD_RING_MAXSIZE) 905 bix = 0; 906 907 --sc->sc_rb.rb_td_nbusy; 908 } 909 910 sc->sc_rb.rb_tdtail = bix; 911 912 bestart(ifp); 913 914 if (sc->sc_rb.rb_td_nbusy == 0) 915 ifp->if_timer = 0; 916 917 return 1; 918 } 919 920 /* 921 * Receive interrupt. 922 */ 923 int 924 berint(struct be_softc *sc) 925 { 926 struct qec_xd *xd = sc->sc_rb.rb_rxd; 927 unsigned int bix, len; 928 unsigned int nrbuf = sc->sc_rb.rb_nrbuf; 929 930 bix = sc->sc_rb.rb_rdtail; 931 932 /* 933 * Process all buffers with valid data. 934 */ 935 for (;;) { 936 len = xd[bix].xd_flags; 937 if (len & QEC_XD_OWN) 938 break; 939 940 len &= QEC_XD_LENGTH; 941 be_read(sc, bix, len); 942 943 /* ... */ 944 xd[(bix+nrbuf) % QEC_XD_RING_MAXSIZE].xd_flags = 945 QEC_XD_OWN | (BE_PKT_BUF_SZ & QEC_XD_LENGTH); 946 947 if (++bix == QEC_XD_RING_MAXSIZE) 948 bix = 0; 949 } 950 951 sc->sc_rb.rb_rdtail = bix; 952 953 return 1; 954 } 955 956 int 957 beioctl(struct ifnet *ifp, u_long cmd, void *data) 958 { 959 struct be_softc *sc = ifp->if_softc; 960 struct ifaddr *ifa = data; 961 struct ifreq *ifr = data; 962 int s, error = 0; 963 964 s = splnet(); 965 966 switch (cmd) { 967 case SIOCINITIFADDR: 968 ifp->if_flags |= IFF_UP; 969 beinit(ifp); 970 switch (ifa->ifa_addr->sa_family) { 971 #ifdef INET 972 case AF_INET: 973 arp_ifinit(ifp, ifa); 974 break; 975 #endif /* INET */ 976 default: 977 break; 978 } 979 break; 980 981 case SIOCSIFFLAGS: 982 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 983 break; 984 /* XXX re-use ether_ioctl() */ 985 switch (ifp->if_flags & (IFF_UP|IFF_RUNNING)) { 986 case IFF_RUNNING: 987 /* 988 * If interface is marked down and it is running, then 989 * stop it. 990 */ 991 bestop(ifp, 0); 992 ifp->if_flags &= ~IFF_RUNNING; 993 break; 994 case IFF_UP: 995 /* 996 * If interface is marked up and it is stopped, then 997 * start it. 998 */ 999 beinit(ifp); 1000 break; 1001 default: 1002 /* 1003 * Reset the interface to pick up changes in any other 1004 * flags that affect hardware registers. 1005 */ 1006 bestop(ifp, 0); 1007 beinit(ifp); 1008 break; 1009 } 1010 #ifdef BEDEBUG 1011 if (ifp->if_flags & IFF_DEBUG) 1012 sc->sc_debug = 1; 1013 else 1014 sc->sc_debug = 0; 1015 #endif 1016 break; 1017 1018 case SIOCGIFMEDIA: 1019 case SIOCSIFMEDIA: 1020 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd); 1021 break; 1022 default: 1023 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 1024 /* 1025 * Multicast list has changed; set the hardware filter 1026 * accordingly. 1027 */ 1028 if (ifp->if_flags & IFF_RUNNING) 1029 error = beinit(ifp); 1030 else 1031 error = 0; 1032 } 1033 break; 1034 } 1035 splx(s); 1036 return error; 1037 } 1038 1039 1040 int 1041 beinit(struct ifnet *ifp) 1042 { 1043 struct be_softc *sc = ifp->if_softc; 1044 bus_space_tag_t t = sc->sc_bustag; 1045 bus_space_handle_t br = sc->sc_br; 1046 bus_space_handle_t cr = sc->sc_cr; 1047 struct qec_softc *qec = sc->sc_qec; 1048 uint32_t v; 1049 uint32_t qecaddr; 1050 uint8_t *ea; 1051 int rc, s; 1052 1053 s = splnet(); 1054 1055 qec_meminit(&sc->sc_rb, BE_PKT_BUF_SZ); 1056 1057 bestop(ifp, 1); 1058 1059 ea = sc->sc_enaddr; 1060 bus_space_write_4(t, br, BE_BRI_MACADDR0, (ea[0] << 8) | ea[1]); 1061 bus_space_write_4(t, br, BE_BRI_MACADDR1, (ea[2] << 8) | ea[3]); 1062 bus_space_write_4(t, br, BE_BRI_MACADDR2, (ea[4] << 8) | ea[5]); 1063 1064 /* Clear hash table */ 1065 bus_space_write_4(t, br, BE_BRI_HASHTAB0, 0); 1066 bus_space_write_4(t, br, BE_BRI_HASHTAB1, 0); 1067 bus_space_write_4(t, br, BE_BRI_HASHTAB2, 0); 1068 bus_space_write_4(t, br, BE_BRI_HASHTAB3, 0); 1069 1070 /* Re-initialize RX configuration */ 1071 v = BE_BR_RXCFG_FIFO; 1072 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1073 1074 be_mcreset(sc); 1075 1076 bus_space_write_4(t, br, BE_BRI_RANDSEED, 0xbd); 1077 1078 bus_space_write_4(t, br, 1079 BE_BRI_XIFCFG, BE_BR_XCFG_ODENABLE | BE_BR_XCFG_RESV); 1080 1081 bus_space_write_4(t, br, BE_BRI_JSIZE, 4); 1082 1083 /* 1084 * Turn off counter expiration interrupts as well as 1085 * 'gotframe' and 'sentframe' 1086 */ 1087 bus_space_write_4(t, br, BE_BRI_IMASK, 1088 BE_BR_IMASK_GOTFRAME | 1089 BE_BR_IMASK_RCNTEXP | 1090 BE_BR_IMASK_ACNTEXP | 1091 BE_BR_IMASK_CCNTEXP | 1092 BE_BR_IMASK_LCNTEXP | 1093 BE_BR_IMASK_CVCNTEXP | 1094 BE_BR_IMASK_SENTFRAME | 1095 BE_BR_IMASK_NCNTEXP | 1096 BE_BR_IMASK_ECNTEXP | 1097 BE_BR_IMASK_LCCNTEXP | 1098 BE_BR_IMASK_FCNTEXP | 1099 BE_BR_IMASK_DTIMEXP); 1100 1101 /* Channel registers: */ 1102 bus_space_write_4(t, cr, BE_CRI_RXDS, (uint32_t)sc->sc_rb.rb_rxddma); 1103 bus_space_write_4(t, cr, BE_CRI_TXDS, (uint32_t)sc->sc_rb.rb_txddma); 1104 1105 qecaddr = sc->sc_channel * qec->sc_msize; 1106 bus_space_write_4(t, cr, BE_CRI_RXWBUF, qecaddr); 1107 bus_space_write_4(t, cr, BE_CRI_RXRBUF, qecaddr); 1108 bus_space_write_4(t, cr, BE_CRI_TXWBUF, qecaddr + qec->sc_rsize); 1109 bus_space_write_4(t, cr, BE_CRI_TXRBUF, qecaddr + qec->sc_rsize); 1110 1111 bus_space_write_4(t, cr, BE_CRI_RIMASK, 0); 1112 bus_space_write_4(t, cr, BE_CRI_TIMASK, 0); 1113 bus_space_write_4(t, cr, BE_CRI_QMASK, 0); 1114 bus_space_write_4(t, cr, BE_CRI_BMASK, 0); 1115 bus_space_write_4(t, cr, BE_CRI_CCNT, 0); 1116 1117 /* Set max packet length */ 1118 v = ETHER_MAX_LEN; 1119 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) 1120 v += ETHER_VLAN_ENCAP_LEN; 1121 bus_space_write_4(t, br, BE_BRI_RXMAX, v); 1122 bus_space_write_4(t, br, BE_BRI_TXMAX, v); 1123 1124 /* Enable transmitter */ 1125 bus_space_write_4(t, br, 1126 BE_BRI_TXCFG, BE_BR_TXCFG_FIFO | BE_BR_TXCFG_ENABLE); 1127 1128 /* Enable receiver */ 1129 v = bus_space_read_4(t, br, BE_BRI_RXCFG); 1130 v |= BE_BR_RXCFG_FIFO | BE_BR_RXCFG_ENABLE; 1131 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1132 1133 if ((rc = be_ifmedia_upd(ifp)) != 0) 1134 goto out; 1135 1136 ifp->if_flags |= IFF_RUNNING; 1137 ifp->if_flags &= ~IFF_OACTIVE; 1138 1139 callout_reset(&sc->sc_tick_ch, hz, be_tick, sc); 1140 1141 return 0; 1142 out: 1143 splx(s); 1144 return rc; 1145 } 1146 1147 void 1148 be_mcreset(struct be_softc *sc) 1149 { 1150 struct ethercom *ec = &sc->sc_ethercom; 1151 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1152 bus_space_tag_t t = sc->sc_bustag; 1153 bus_space_handle_t br = sc->sc_br; 1154 uint32_t crc; 1155 uint16_t hash[4]; 1156 uint8_t octet; 1157 uint32_t v; 1158 int i, j; 1159 struct ether_multi *enm; 1160 struct ether_multistep step; 1161 1162 if (ifp->if_flags & IFF_PROMISC) { 1163 v = bus_space_read_4(t, br, BE_BRI_RXCFG); 1164 v |= BE_BR_RXCFG_PMISC; 1165 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1166 return; 1167 } 1168 1169 if (ifp->if_flags & IFF_ALLMULTI) { 1170 hash[3] = hash[2] = hash[1] = hash[0] = 0xffff; 1171 goto chipit; 1172 } 1173 1174 hash[3] = hash[2] = hash[1] = hash[0] = 0; 1175 1176 ETHER_FIRST_MULTI(step, ec, enm); 1177 while (enm != NULL) { 1178 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1179 /* 1180 * We must listen to a range of multicast 1181 * addresses. For now, just accept all 1182 * multicasts, rather than trying to set only 1183 * those filter bits needed to match the range. 1184 * (At this time, the only use of address 1185 * ranges is for IP multicast routing, for 1186 * which the range is big enough to require 1187 * all bits set.) 1188 */ 1189 hash[3] = hash[2] = hash[1] = hash[0] = 0xffff; 1190 ifp->if_flags |= IFF_ALLMULTI; 1191 goto chipit; 1192 } 1193 1194 crc = 0xffffffff; 1195 1196 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1197 octet = enm->enm_addrlo[i]; 1198 1199 for (j = 0; j < 8; j++) { 1200 if ((crc & 1) ^ (octet & 1)) { 1201 crc >>= 1; 1202 crc ^= MC_POLY_LE; 1203 } 1204 else 1205 crc >>= 1; 1206 octet >>= 1; 1207 } 1208 } 1209 1210 crc >>= 26; 1211 hash[crc >> 4] |= 1 << (crc & 0xf); 1212 ETHER_NEXT_MULTI(step, enm); 1213 } 1214 1215 ifp->if_flags &= ~IFF_ALLMULTI; 1216 1217 chipit: 1218 /* Enable the hash filter */ 1219 bus_space_write_4(t, br, BE_BRI_HASHTAB0, hash[0]); 1220 bus_space_write_4(t, br, BE_BRI_HASHTAB1, hash[1]); 1221 bus_space_write_4(t, br, BE_BRI_HASHTAB2, hash[2]); 1222 bus_space_write_4(t, br, BE_BRI_HASHTAB3, hash[3]); 1223 1224 v = bus_space_read_4(t, br, BE_BRI_RXCFG); 1225 v &= ~BE_BR_RXCFG_PMISC; 1226 v |= BE_BR_RXCFG_HENABLE; 1227 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1228 } 1229 1230 /* 1231 * Set the tcvr to an idle state 1232 */ 1233 void 1234 be_mii_sync(struct be_softc *sc) 1235 { 1236 bus_space_tag_t t = sc->sc_bustag; 1237 bus_space_handle_t tr = sc->sc_tr; 1238 int n = 32; 1239 1240 while (n--) { 1241 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, 1242 MGMT_PAL_INT_MDIO | MGMT_PAL_EXT_MDIO | MGMT_PAL_OENAB); 1243 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1244 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, 1245 MGMT_PAL_INT_MDIO | MGMT_PAL_EXT_MDIO | 1246 MGMT_PAL_OENAB | MGMT_PAL_DCLOCK); 1247 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1248 } 1249 } 1250 1251 void 1252 be_pal_gate(struct be_softc *sc, int phy) 1253 { 1254 bus_space_tag_t t = sc->sc_bustag; 1255 bus_space_handle_t tr = sc->sc_tr; 1256 uint32_t v; 1257 1258 be_mii_sync(sc); 1259 1260 v = ~(TCVR_PAL_EXTLBACK | TCVR_PAL_MSENSE | TCVR_PAL_LTENABLE); 1261 if (phy == BE_PHY_INTERNAL) 1262 v &= ~TCVR_PAL_SERIAL; 1263 1264 bus_space_write_4(t, tr, BE_TRI_TCVRPAL, v); 1265 (void)bus_space_read_4(t, tr, BE_TRI_TCVRPAL); 1266 } 1267 1268 static int 1269 be_tcvr_read_bit(struct be_softc *sc, int phy) 1270 { 1271 bus_space_tag_t t = sc->sc_bustag; 1272 bus_space_handle_t tr = sc->sc_tr; 1273 int ret; 1274 1275 if (phy == BE_PHY_INTERNAL) { 1276 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, MGMT_PAL_EXT_MDIO); 1277 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1278 bus_space_write_4(t, tr, 1279 BE_TRI_MGMTPAL, MGMT_PAL_EXT_MDIO | MGMT_PAL_DCLOCK); 1280 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1281 ret = (bus_space_read_4(t, tr, BE_TRI_MGMTPAL) & 1282 MGMT_PAL_INT_MDIO) >> MGMT_PAL_INT_MDIO_SHIFT; 1283 } else { 1284 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, MGMT_PAL_INT_MDIO); 1285 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1286 ret = (bus_space_read_4(t, tr, BE_TRI_MGMTPAL) & 1287 MGMT_PAL_EXT_MDIO) >> MGMT_PAL_EXT_MDIO_SHIFT; 1288 bus_space_write_4(t, tr, 1289 BE_TRI_MGMTPAL, MGMT_PAL_INT_MDIO | MGMT_PAL_DCLOCK); 1290 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1291 } 1292 1293 return ret; 1294 } 1295 1296 static void 1297 be_tcvr_write_bit(struct be_softc *sc, int phy, int bit) 1298 { 1299 bus_space_tag_t t = sc->sc_bustag; 1300 bus_space_handle_t tr = sc->sc_tr; 1301 uint32_t v; 1302 1303 if (phy == BE_PHY_INTERNAL) { 1304 v = ((bit & 1) << MGMT_PAL_INT_MDIO_SHIFT) | 1305 MGMT_PAL_OENAB | MGMT_PAL_EXT_MDIO; 1306 } else { 1307 v = ((bit & 1) << MGMT_PAL_EXT_MDIO_SHIFT) | 1308 MGMT_PAL_OENAB | MGMT_PAL_INT_MDIO; 1309 } 1310 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, v); 1311 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1312 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, v | MGMT_PAL_DCLOCK); 1313 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1314 } 1315 1316 static void 1317 be_mii_sendbits(struct be_softc *sc, int phy, uint32_t data, int nbits) 1318 { 1319 int i; 1320 1321 for (i = 1 << (nbits - 1); i != 0; i >>= 1) { 1322 be_tcvr_write_bit(sc, phy, (data & i) != 0); 1323 } 1324 } 1325 1326 static int 1327 be_mii_readreg(device_t self, int phy, int reg) 1328 { 1329 struct be_softc *sc = device_private(self); 1330 int val = 0, i; 1331 1332 /* 1333 * Read the PHY register by manually driving the MII control lines. 1334 */ 1335 be_mii_sync(sc); 1336 be_mii_sendbits(sc, phy, MII_COMMAND_START, 2); 1337 be_mii_sendbits(sc, phy, MII_COMMAND_READ, 2); 1338 be_mii_sendbits(sc, phy, phy, 5); 1339 be_mii_sendbits(sc, phy, reg, 5); 1340 1341 (void)be_tcvr_read_bit(sc, phy); 1342 (void)be_tcvr_read_bit(sc, phy); 1343 1344 for (i = 15; i >= 0; i--) 1345 val |= (be_tcvr_read_bit(sc, phy) << i); 1346 1347 (void)be_tcvr_read_bit(sc, phy); 1348 (void)be_tcvr_read_bit(sc, phy); 1349 (void)be_tcvr_read_bit(sc, phy); 1350 1351 return val; 1352 } 1353 1354 void 1355 be_mii_writereg(device_t self, int phy, int reg, int val) 1356 { 1357 struct be_softc *sc = device_private(self); 1358 int i; 1359 1360 /* 1361 * Write the PHY register by manually driving the MII control lines. 1362 */ 1363 be_mii_sync(sc); 1364 be_mii_sendbits(sc, phy, MII_COMMAND_START, 2); 1365 be_mii_sendbits(sc, phy, MII_COMMAND_WRITE, 2); 1366 be_mii_sendbits(sc, phy, phy, 5); 1367 be_mii_sendbits(sc, phy, reg, 5); 1368 1369 be_tcvr_write_bit(sc, phy, 1); 1370 be_tcvr_write_bit(sc, phy, 0); 1371 1372 for (i = 15; i >= 0; i--) 1373 be_tcvr_write_bit(sc, phy, (val >> i) & 1); 1374 } 1375 1376 int 1377 be_mii_reset(struct be_softc *sc, int phy) 1378 { 1379 device_t self = sc->sc_dev; 1380 int n; 1381 1382 be_mii_writereg(self, phy, MII_BMCR, BMCR_LOOP | BMCR_PDOWN | BMCR_ISO); 1383 be_mii_writereg(self, phy, MII_BMCR, BMCR_RESET); 1384 1385 for (n = 16; n >= 0; n--) { 1386 int bmcr = be_mii_readreg(self, phy, MII_BMCR); 1387 if ((bmcr & BMCR_RESET) == 0) 1388 break; 1389 DELAY(20); 1390 } 1391 if (n == 0) { 1392 aprint_error_dev(self, "bmcr reset failed\n"); 1393 return EIO; 1394 } 1395 1396 return 0; 1397 } 1398 1399 void 1400 be_tick(void *arg) 1401 { 1402 struct be_softc *sc = arg; 1403 int s = splnet(); 1404 1405 mii_tick(&sc->sc_mii); 1406 (void)be_intphy_service(sc, &sc->sc_mii, MII_TICK); 1407 1408 splx(s); 1409 callout_reset(&sc->sc_tick_ch, hz, be_tick, sc); 1410 } 1411 1412 void 1413 be_mii_statchg(device_t self) 1414 { 1415 struct be_softc *sc = device_private(self); 1416 bus_space_tag_t t = sc->sc_bustag; 1417 bus_space_handle_t br = sc->sc_br; 1418 uint instance; 1419 uint32_t v; 1420 1421 instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media); 1422 #ifdef DIAGNOSTIC 1423 if (instance > 1) 1424 panic("be_mii_statchg: instance %d out of range", instance); 1425 #endif 1426 1427 /* Update duplex mode in TX configuration */ 1428 v = bus_space_read_4(t, br, BE_BRI_TXCFG); 1429 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 1430 v |= BE_BR_TXCFG_FULLDPLX; 1431 else 1432 v &= ~BE_BR_TXCFG_FULLDPLX; 1433 bus_space_write_4(t, br, BE_BRI_TXCFG, v); 1434 1435 /* Change to appropriate gate in transceiver PAL */ 1436 be_pal_gate(sc, sc->sc_phys[instance]); 1437 } 1438 1439 /* 1440 * Get current media settings. 1441 */ 1442 void 1443 be_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1444 { 1445 struct be_softc *sc = ifp->if_softc; 1446 1447 mii_pollstat(&sc->sc_mii); 1448 (void)be_intphy_service(sc, &sc->sc_mii, MII_POLLSTAT); 1449 1450 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1451 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1452 } 1453 1454 /* 1455 * Set media options. 1456 */ 1457 int 1458 be_ifmedia_upd(struct ifnet *ifp) 1459 { 1460 struct be_softc *sc = ifp->if_softc; 1461 int error; 1462 1463 if ((error = mii_mediachg(&sc->sc_mii)) == ENXIO) 1464 error = 0; 1465 else if (error != 0) 1466 return error; 1467 1468 return be_intphy_service(sc, &sc->sc_mii, MII_MEDIACHG); 1469 } 1470 1471 /* 1472 * Service routine for our pseudo-MII internal transceiver. 1473 */ 1474 int 1475 be_intphy_service(struct be_softc *sc, struct mii_data *mii, int cmd) 1476 { 1477 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 1478 device_t self = sc->sc_dev; 1479 int bmcr, bmsr; 1480 int error; 1481 1482 switch (cmd) { 1483 case MII_POLLSTAT: 1484 /* 1485 * If we're not polling our PHY instance, just return. 1486 */ 1487 if (IFM_INST(ife->ifm_media) != sc->sc_mii_inst) 1488 return 0; 1489 1490 break; 1491 1492 case MII_MEDIACHG: 1493 1494 /* 1495 * If the media indicates a different PHY instance, 1496 * isolate ourselves. 1497 */ 1498 if (IFM_INST(ife->ifm_media) != sc->sc_mii_inst) { 1499 bmcr = be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMCR); 1500 be_mii_writereg(self, 1501 BE_PHY_INTERNAL, MII_BMCR, bmcr | BMCR_ISO); 1502 sc->sc_mii_flags &= ~MIIF_HAVELINK; 1503 sc->sc_intphy_curspeed = 0; 1504 return 0; 1505 } 1506 1507 1508 if ((error = be_mii_reset(sc, BE_PHY_INTERNAL)) != 0) 1509 return error; 1510 1511 bmcr = be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMCR); 1512 1513 /* 1514 * Select the new mode and take out of isolation 1515 */ 1516 if (IFM_SUBTYPE(ife->ifm_media) == IFM_100_TX) 1517 bmcr |= BMCR_S100; 1518 else if (IFM_SUBTYPE(ife->ifm_media) == IFM_10_T) 1519 bmcr &= ~BMCR_S100; 1520 else if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) { 1521 if ((sc->sc_mii_flags & MIIF_HAVELINK) != 0) { 1522 bmcr &= ~BMCR_S100; 1523 bmcr |= sc->sc_intphy_curspeed; 1524 } else { 1525 /* Keep isolated until link is up */ 1526 bmcr |= BMCR_ISO; 1527 sc->sc_mii_flags |= MIIF_DOINGAUTO; 1528 } 1529 } 1530 1531 if ((IFM_OPTIONS(ife->ifm_media) & IFM_FDX) != 0) 1532 bmcr |= BMCR_FDX; 1533 else 1534 bmcr &= ~BMCR_FDX; 1535 1536 be_mii_writereg(self, BE_PHY_INTERNAL, MII_BMCR, bmcr); 1537 break; 1538 1539 case MII_TICK: 1540 /* 1541 * If we're not currently selected, just return. 1542 */ 1543 if (IFM_INST(ife->ifm_media) != sc->sc_mii_inst) 1544 return 0; 1545 1546 /* Only used for automatic media selection */ 1547 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) 1548 return 0; 1549 1550 /* Is the interface even up? */ 1551 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 1552 return 0; 1553 1554 /* 1555 * Check link status; if we don't have a link, try another 1556 * speed. We can't detect duplex mode, so half-duplex is 1557 * what we have to settle for. 1558 */ 1559 1560 /* Read twice in case the register is latched */ 1561 bmsr = 1562 be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMSR) | 1563 be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMSR); 1564 1565 if ((bmsr & BMSR_LINK) != 0) { 1566 /* We have a carrier */ 1567 bmcr = be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMCR); 1568 1569 if ((sc->sc_mii_flags & MIIF_DOINGAUTO) != 0) { 1570 bmcr = be_mii_readreg(self, 1571 BE_PHY_INTERNAL, MII_BMCR); 1572 1573 sc->sc_mii_flags |= MIIF_HAVELINK; 1574 sc->sc_intphy_curspeed = (bmcr & BMCR_S100); 1575 sc->sc_mii_flags &= ~MIIF_DOINGAUTO; 1576 1577 bmcr &= ~BMCR_ISO; 1578 be_mii_writereg(self, 1579 BE_PHY_INTERNAL, MII_BMCR, bmcr); 1580 1581 printf("%s: link up at %s Mbps\n", 1582 device_xname(self), 1583 (bmcr & BMCR_S100) ? "100" : "10"); 1584 } 1585 return 0; 1586 } 1587 1588 if ((sc->sc_mii_flags & MIIF_DOINGAUTO) == 0) { 1589 sc->sc_mii_flags |= MIIF_DOINGAUTO; 1590 sc->sc_mii_flags &= ~MIIF_HAVELINK; 1591 sc->sc_intphy_curspeed = 0; 1592 printf("%s: link down\n", device_xname(self)); 1593 } 1594 1595 /* Only retry autonegotiation every 5 seconds. */ 1596 if (++sc->sc_mii_ticks < 5) 1597 return 0; 1598 1599 sc->sc_mii_ticks = 0; 1600 bmcr = be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMCR); 1601 /* Just flip the fast speed bit */ 1602 bmcr ^= BMCR_S100; 1603 be_mii_writereg(self, BE_PHY_INTERNAL, MII_BMCR, bmcr); 1604 1605 break; 1606 1607 case MII_DOWN: 1608 /* Isolate this phy */ 1609 bmcr = be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMCR); 1610 be_mii_writereg(self, 1611 BE_PHY_INTERNAL, MII_BMCR, bmcr | BMCR_ISO); 1612 return 0; 1613 } 1614 1615 /* Update the media status. */ 1616 be_intphy_status(sc); 1617 1618 /* Callback if something changed. */ 1619 if (sc->sc_mii_active != mii->mii_media_active || cmd == MII_MEDIACHG) { 1620 (*mii->mii_statchg)(self); 1621 sc->sc_mii_active = mii->mii_media_active; 1622 } 1623 return 0; 1624 } 1625 1626 /* 1627 * Determine status of internal transceiver 1628 */ 1629 void 1630 be_intphy_status(struct be_softc *sc) 1631 { 1632 struct mii_data *mii = &sc->sc_mii; 1633 device_t self = sc->sc_dev; 1634 int media_active, media_status; 1635 int bmcr, bmsr; 1636 1637 media_status = IFM_AVALID; 1638 media_active = 0; 1639 1640 /* 1641 * Internal transceiver; do the work here. 1642 */ 1643 bmcr = be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMCR); 1644 1645 switch (bmcr & (BMCR_S100 | BMCR_FDX)) { 1646 case (BMCR_S100 | BMCR_FDX): 1647 media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 1648 break; 1649 case BMCR_S100: 1650 media_active = IFM_ETHER | IFM_100_TX | IFM_HDX; 1651 break; 1652 case BMCR_FDX: 1653 media_active = IFM_ETHER | IFM_10_T | IFM_FDX; 1654 break; 1655 case 0: 1656 media_active = IFM_ETHER | IFM_10_T | IFM_HDX; 1657 break; 1658 } 1659 1660 /* Read twice in case the register is latched */ 1661 bmsr = 1662 be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMSR) | 1663 be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMSR); 1664 if (bmsr & BMSR_LINK) 1665 media_status |= IFM_ACTIVE; 1666 1667 mii->mii_media_status = media_status; 1668 mii->mii_media_active = media_active; 1669 } 1670
Indexes created Tue Sep 30 11:09:46 GMT 2025