be.c revision 1.77
1 /* $NetBSD: be.c,v 1.77 2010/04/05 07:21:47 joerg Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Copyright (c) 1998 Theo de Raadt and Jason L. Wright. 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. The name of the authors may not be used to endorse or promote products 45 * derived from this software without specific prior written permission. 46 * 47 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR 48 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 49 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 50 * IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, 51 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 52 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 53 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 54 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 55 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 56 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 57 */ 58 59 #include <sys/cdefs.h> 60 __KERNEL_RCSID(0, "$NetBSD: be.c,v 1.77 2010/04/05 07:21:47 joerg Exp $"); 61 62 #include "opt_ddb.h" 63 #include "opt_inet.h" 64 #include "rnd.h" 65 66 #include <sys/param.h> 67 #include <sys/systm.h> 68 #include <sys/callout.h> 69 #include <sys/kernel.h> 70 #include <sys/errno.h> 71 #include <sys/ioctl.h> 72 #include <sys/mbuf.h> 73 #include <sys/socket.h> 74 #include <sys/syslog.h> 75 #include <sys/device.h> 76 #include <sys/malloc.h> 77 #if NRND > 0 78 #include <sys/rnd.h> 79 #endif 80 81 #include <net/if.h> 82 #include <net/if_dl.h> 83 #include <net/if_types.h> 84 #include <net/netisr.h> 85 #include <net/if_media.h> 86 #include <net/if_ether.h> 87 88 #ifdef INET 89 #include <netinet/in.h> 90 #include <netinet/if_inarp.h> 91 #include <netinet/in_systm.h> 92 #include <netinet/in_var.h> 93 #include <netinet/ip.h> 94 #endif 95 96 97 #include <net/bpf.h> 98 #include <net/bpfdesc.h> 99 100 #include <sys/bus.h> 101 #include <sys/intr.h> 102 #include <machine/autoconf.h> 103 104 #include <dev/sbus/sbusvar.h> 105 106 #include <dev/mii/mii.h> 107 #include <dev/mii/miivar.h> 108 109 #include <dev/sbus/qecreg.h> 110 #include <dev/sbus/qecvar.h> 111 #include <dev/sbus/bereg.h> 112 113 struct be_softc { 114 device_t sc_dev; 115 bus_space_tag_t sc_bustag; /* bus & DMA tags */ 116 bus_dma_tag_t sc_dmatag; 117 bus_dmamap_t sc_dmamap; 118 struct ethercom sc_ethercom; 119 /*struct ifmedia sc_ifmedia; -* interface media */ 120 struct mii_data sc_mii; /* MII media control */ 121 #define sc_media sc_mii.mii_media/* shorthand */ 122 int sc_phys[2]; /* MII instance -> phy */ 123 124 struct callout sc_tick_ch; 125 126 /* 127 * Some `mii_softc' items we need to emulate MII operation 128 * for our internal transceiver. 129 */ 130 int sc_mii_inst; /* instance of internal phy */ 131 int sc_mii_active; /* currently active medium */ 132 int sc_mii_ticks; /* tick counter */ 133 int sc_mii_flags; /* phy status flags */ 134 #define MIIF_HAVELINK 0x04000000 135 int sc_intphy_curspeed; /* Established link speed */ 136 137 struct qec_softc *sc_qec; /* QEC parent */ 138 139 bus_space_handle_t sc_qr; /* QEC registers */ 140 bus_space_handle_t sc_br; /* BE registers */ 141 bus_space_handle_t sc_cr; /* channel registers */ 142 bus_space_handle_t sc_tr; /* transceiver registers */ 143 144 u_int sc_rev; 145 146 int sc_channel; /* channel number */ 147 int sc_burst; 148 149 struct qec_ring sc_rb; /* Packet Ring Buffer */ 150 151 /* MAC address */ 152 uint8_t sc_enaddr[ETHER_ADDR_LEN]; 153 #ifdef BEDEBUG 154 int sc_debug; 155 #endif 156 }; 157 158 static int bematch(device_t, cfdata_t, void *); 159 static void beattach(device_t, device_t, void *); 160 161 static int beinit(struct ifnet *); 162 static void bestart(struct ifnet *); 163 static void bestop(struct ifnet *, int); 164 static void bewatchdog(struct ifnet *); 165 static int beioctl(struct ifnet *, u_long, void *); 166 static void bereset(struct be_softc *); 167 static void behwreset(struct be_softc *); 168 169 static int beintr(void *); 170 static int berint(struct be_softc *); 171 static int betint(struct be_softc *); 172 static int beqint(struct be_softc *, uint32_t); 173 static int beeint(struct be_softc *, uint32_t); 174 175 static void be_read(struct be_softc *, int, int); 176 static int be_put(struct be_softc *, int, struct mbuf *); 177 static struct mbuf *be_get(struct be_softc *, int, int); 178 179 static void be_pal_gate(struct be_softc *, int); 180 181 /* ifmedia callbacks */ 182 static void be_ifmedia_sts(struct ifnet *, struct ifmediareq *); 183 static int be_ifmedia_upd(struct ifnet *); 184 185 static void be_mcreset(struct be_softc *); 186 187 /* MII methods & callbacks */ 188 static int be_mii_readreg(device_t, int, int); 189 static void be_mii_writereg(device_t, int, int, int); 190 static void be_mii_statchg(device_t); 191 192 /* MII helpers */ 193 static void be_mii_sync(struct be_softc *); 194 static void be_mii_sendbits(struct be_softc *, int, uint32_t, int); 195 static int be_mii_reset(struct be_softc *, int); 196 static int be_tcvr_read_bit(struct be_softc *, int); 197 static void be_tcvr_write_bit(struct be_softc *, int, int); 198 199 static void be_tick(void *); 200 #if 0 201 static void be_intphy_auto(struct be_softc *); 202 #endif 203 static void be_intphy_status(struct be_softc *); 204 static int be_intphy_service(struct be_softc *, struct mii_data *, int); 205 206 207 CFATTACH_DECL_NEW(be, sizeof(struct be_softc), 208 bematch, beattach, NULL, NULL); 209 210 int 211 bematch(device_t parent, cfdata_t cf, void *aux) 212 { 213 struct sbus_attach_args *sa = aux; 214 215 return strcmp(cf->cf_name, sa->sa_name) == 0; 216 } 217 218 void 219 beattach(device_t parent, device_t self, void *aux) 220 { 221 struct sbus_attach_args *sa = aux; 222 struct qec_softc *qec = device_private(parent); 223 struct be_softc *sc = device_private(self); 224 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 225 struct mii_data *mii = &sc->sc_mii; 226 struct mii_softc *child; 227 int node = sa->sa_node; 228 bus_dma_tag_t dmatag = sa->sa_dmatag; 229 bus_dma_segment_t seg; 230 bus_size_t size; 231 int instance; 232 int rseg, error; 233 uint32_t v; 234 235 sc->sc_dev = self; 236 237 if (sa->sa_nreg < 3) { 238 printf(": only %d register sets\n", sa->sa_nreg); 239 return; 240 } 241 242 if (bus_space_map(sa->sa_bustag, 243 (bus_addr_t)BUS_ADDR(sa->sa_reg[0].oa_space, sa->sa_reg[0].oa_base), 244 (bus_size_t)sa->sa_reg[0].oa_size, 245 0, &sc->sc_cr) != 0) { 246 printf(": cannot map registers\n"); 247 return; 248 } 249 250 if (bus_space_map(sa->sa_bustag, 251 (bus_addr_t)BUS_ADDR(sa->sa_reg[1].oa_space, sa->sa_reg[1].oa_base), 252 (bus_size_t)sa->sa_reg[1].oa_size, 253 0, &sc->sc_br) != 0) { 254 printf(": cannot map registers\n"); 255 return; 256 } 257 258 if (bus_space_map(sa->sa_bustag, 259 (bus_addr_t)BUS_ADDR(sa->sa_reg[2].oa_space, sa->sa_reg[2].oa_base), 260 (bus_size_t)sa->sa_reg[2].oa_size, 261 0, &sc->sc_tr) != 0) { 262 printf(": cannot map registers\n"); 263 return; 264 } 265 266 sc->sc_bustag = sa->sa_bustag; 267 sc->sc_qec = qec; 268 sc->sc_qr = qec->sc_regs; 269 270 sc->sc_rev = prom_getpropint(node, "board-version", -1); 271 printf(": rev %x,", sc->sc_rev); 272 273 callout_init(&sc->sc_tick_ch, 0); 274 275 sc->sc_channel = prom_getpropint(node, "channel#", -1); 276 if (sc->sc_channel == -1) 277 sc->sc_channel = 0; 278 279 sc->sc_burst = prom_getpropint(node, "burst-sizes", -1); 280 if (sc->sc_burst == -1) 281 sc->sc_burst = qec->sc_burst; 282 283 /* Clamp at parent's burst sizes */ 284 sc->sc_burst &= qec->sc_burst; 285 286 /* Establish interrupt handler */ 287 if (sa->sa_nintr) 288 (void)bus_intr_establish(sa->sa_bustag, sa->sa_pri, IPL_NET, 289 beintr, sc); 290 291 prom_getether(node, sc->sc_enaddr); 292 printf(" address %s\n", ether_sprintf(sc->sc_enaddr)); 293 294 /* 295 * Allocate descriptor ring and buffers. 296 */ 297 298 /* for now, allocate as many bufs as there are ring descriptors */ 299 sc->sc_rb.rb_ntbuf = QEC_XD_RING_MAXSIZE; 300 sc->sc_rb.rb_nrbuf = QEC_XD_RING_MAXSIZE; 301 302 size = 303 QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd) + 304 QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd) + 305 sc->sc_rb.rb_ntbuf * BE_PKT_BUF_SZ + 306 sc->sc_rb.rb_nrbuf * BE_PKT_BUF_SZ; 307 308 /* Get a DMA handle */ 309 if ((error = bus_dmamap_create(dmatag, size, 1, size, 0, 310 BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) { 311 aprint_error_dev(self, "DMA map create error %d\n", error); 312 return; 313 } 314 315 /* Allocate DMA buffer */ 316 if ((error = bus_dmamem_alloc(sa->sa_dmatag, size, 0, 0, 317 &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 318 aprint_error_dev(self, "DMA buffer alloc error %d\n", error); 319 return; 320 } 321 322 /* Map DMA memory in CPU addressable space */ 323 if ((error = bus_dmamem_map(sa->sa_dmatag, &seg, rseg, size, 324 &sc->sc_rb.rb_membase, BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 325 aprint_error_dev(self, "DMA buffer map error %d\n", error); 326 bus_dmamem_free(sa->sa_dmatag, &seg, rseg); 327 return; 328 } 329 330 /* Load the buffer */ 331 if ((error = bus_dmamap_load(dmatag, sc->sc_dmamap, 332 sc->sc_rb.rb_membase, size, NULL, BUS_DMA_NOWAIT)) != 0) { 333 aprint_error_dev(self, "DMA buffer map load error %d\n", error); 334 bus_dmamem_unmap(dmatag, sc->sc_rb.rb_membase, size); 335 bus_dmamem_free(dmatag, &seg, rseg); 336 return; 337 } 338 sc->sc_rb.rb_dmabase = sc->sc_dmamap->dm_segs[0].ds_addr; 339 340 /* 341 * Initialize our media structures and MII info. 342 */ 343 mii->mii_ifp = ifp; 344 mii->mii_readreg = be_mii_readreg; 345 mii->mii_writereg = be_mii_writereg; 346 mii->mii_statchg = be_mii_statchg; 347 348 ifmedia_init(&mii->mii_media, 0, be_ifmedia_upd, be_ifmedia_sts); 349 350 /* 351 * Initialize transceiver and determine which PHY connection to use. 352 */ 353 be_mii_sync(sc); 354 v = bus_space_read_4(sc->sc_bustag, sc->sc_tr, BE_TRI_MGMTPAL); 355 356 instance = 0; 357 358 if ((v & MGMT_PAL_EXT_MDIO) != 0) { 359 360 mii_attach(self, mii, 0xffffffff, BE_PHY_EXTERNAL, 361 MII_OFFSET_ANY, 0); 362 363 child = LIST_FIRST(&mii->mii_phys); 364 if (child == NULL) { 365 /* No PHY attached */ 366 ifmedia_add(&sc->sc_media, 367 IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, instance), 368 0, NULL); 369 ifmedia_set(&sc->sc_media, 370 IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, instance)); 371 } else { 372 /* 373 * Note: we support just one PHY on the external 374 * MII connector. 375 */ 376 #ifdef DIAGNOSTIC 377 if (LIST_NEXT(child, mii_list) != NULL) { 378 aprint_error_dev(self, 379 "spurious MII device %s attached\n", 380 device_xname(child->mii_dev)); 381 } 382 #endif 383 if (child->mii_phy != BE_PHY_EXTERNAL || 384 child->mii_inst > 0) { 385 aprint_error_dev(self, 386 "cannot accommodate MII device %s" 387 " at phy %d, instance %d\n", 388 device_xname(child->mii_dev), 389 child->mii_phy, child->mii_inst); 390 } else { 391 sc->sc_phys[instance] = child->mii_phy; 392 } 393 394 /* 395 * XXX - we can really do the following ONLY if the 396 * phy indeed has the auto negotiation capability!! 397 */ 398 ifmedia_set(&sc->sc_media, 399 IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, instance)); 400 401 /* Mark our current media setting */ 402 be_pal_gate(sc, BE_PHY_EXTERNAL); 403 instance++; 404 } 405 406 } 407 408 if ((v & MGMT_PAL_INT_MDIO) != 0) { 409 /* 410 * The be internal phy looks vaguely like MII hardware, 411 * but not enough to be able to use the MII device 412 * layer. Hence, we have to take care of media selection 413 * ourselves. 414 */ 415 416 sc->sc_mii_inst = instance; 417 sc->sc_phys[instance] = BE_PHY_INTERNAL; 418 419 /* Use `ifm_data' to store BMCR bits */ 420 ifmedia_add(&sc->sc_media, 421 IFM_MAKEWORD(IFM_ETHER, IFM_10_T, 0, instance), 422 0, NULL); 423 ifmedia_add(&sc->sc_media, 424 IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, 0, instance), 425 BMCR_S100, NULL); 426 ifmedia_add(&sc->sc_media, 427 IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, instance), 428 0, NULL); 429 430 printf("on-board transceiver at %s: 10baseT, 100baseTX, auto\n", 431 device_xname(self)); 432 433 be_mii_reset(sc, BE_PHY_INTERNAL); 434 /* Only set default medium here if there's no external PHY */ 435 if (instance == 0) { 436 be_pal_gate(sc, BE_PHY_INTERNAL); 437 ifmedia_set(&sc->sc_media, 438 IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, instance)); 439 } else 440 be_mii_writereg(self, 441 BE_PHY_INTERNAL, MII_BMCR, BMCR_ISO); 442 } 443 444 memcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 445 ifp->if_softc = sc; 446 ifp->if_start = bestart; 447 ifp->if_ioctl = beioctl; 448 ifp->if_watchdog = bewatchdog; 449 ifp->if_init = beinit; 450 ifp->if_stop = bestop; 451 ifp->if_flags = 452 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 453 IFQ_SET_READY(&ifp->if_snd); 454 455 /* claim 802.1q capability */ 456 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 457 458 /* Attach the interface. */ 459 if_attach(ifp); 460 ether_ifattach(ifp, sc->sc_enaddr); 461 } 462 463 464 /* 465 * Routine to copy from mbuf chain to transmit buffer in 466 * network buffer memory. 467 */ 468 static inline int 469 be_put(struct be_softc *sc, int idx, struct mbuf *m) 470 { 471 struct mbuf *n; 472 int len, tlen = 0, boff = 0; 473 uint8_t *bp; 474 475 bp = sc->sc_rb.rb_txbuf + (idx % sc->sc_rb.rb_ntbuf) * BE_PKT_BUF_SZ; 476 477 for (; m; m = n) { 478 len = m->m_len; 479 if (len == 0) { 480 MFREE(m, n); 481 continue; 482 } 483 memcpy(bp + boff, mtod(m, void *), len); 484 boff += len; 485 tlen += len; 486 MFREE(m, n); 487 } 488 return tlen; 489 } 490 491 /* 492 * Pull data off an interface. 493 * Len is the length of data, with local net header stripped. 494 * We copy the data into mbufs. When full cluster sized units are present, 495 * we copy into clusters. 496 */ 497 static inline struct mbuf * 498 be_get(struct be_softc *sc, int idx, int totlen) 499 { 500 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 501 struct mbuf *m; 502 struct mbuf *top, **mp; 503 int len, pad, boff = 0; 504 uint8_t *bp; 505 506 bp = sc->sc_rb.rb_rxbuf + (idx % sc->sc_rb.rb_nrbuf) * BE_PKT_BUF_SZ; 507 508 MGETHDR(m, M_DONTWAIT, MT_DATA); 509 if (m == NULL) 510 return (NULL); 511 m->m_pkthdr.rcvif = ifp; 512 m->m_pkthdr.len = totlen; 513 514 pad = ALIGN(sizeof(struct ether_header)) - sizeof(struct ether_header); 515 m->m_data += pad; 516 len = MHLEN - pad; 517 top = NULL; 518 mp = ⊤ 519 520 while (totlen > 0) { 521 if (top) { 522 MGET(m, M_DONTWAIT, MT_DATA); 523 if (m == NULL) { 524 m_freem(top); 525 return (NULL); 526 } 527 len = MLEN; 528 } 529 if (top && totlen >= MINCLSIZE) { 530 MCLGET(m, M_DONTWAIT); 531 if (m->m_flags & M_EXT) 532 len = MCLBYTES; 533 } 534 m->m_len = len = min(totlen, len); 535 memcpy(mtod(m, void *), bp + boff, len); 536 boff += len; 537 totlen -= len; 538 *mp = m; 539 mp = &m->m_next; 540 } 541 542 return top; 543 } 544 545 /* 546 * Pass a packet to the higher levels. 547 */ 548 static inline void 549 be_read(struct be_softc *sc, int idx, int len) 550 { 551 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 552 struct mbuf *m; 553 554 if (len <= sizeof(struct ether_header) || 555 len > ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN) { 556 #ifdef BEDEBUG 557 if (sc->sc_debug) 558 printf("%s: invalid packet size %d; dropping\n", 559 ifp->if_xname, len); 560 #endif 561 ifp->if_ierrors++; 562 return; 563 } 564 565 /* 566 * Pull packet off interface. 567 */ 568 m = be_get(sc, idx, len); 569 if (m == NULL) { 570 ifp->if_ierrors++; 571 return; 572 } 573 ifp->if_ipackets++; 574 575 /* 576 * Check if there's a BPF listener on this interface. 577 * If so, hand off the raw packet to BPF. 578 */ 579 bpf_mtap(ifp, m); 580 /* Pass the packet up. */ 581 (*ifp->if_input)(ifp, m); 582 } 583 584 /* 585 * Start output on interface. 586 * We make two assumptions here: 587 * 1) that the current priority is set to splnet _before_ this code 588 * is called *and* is returned to the appropriate priority after 589 * return 590 * 2) that the IFF_OACTIVE flag is checked before this code is called 591 * (i.e. that the output part of the interface is idle) 592 */ 593 void 594 bestart(struct ifnet *ifp) 595 { 596 struct be_softc *sc = ifp->if_softc; 597 struct qec_xd *txd = sc->sc_rb.rb_txd; 598 struct mbuf *m; 599 unsigned int bix, len; 600 unsigned int ntbuf = sc->sc_rb.rb_ntbuf; 601 602 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 603 return; 604 605 bix = sc->sc_rb.rb_tdhead; 606 607 for (;;) { 608 IFQ_DEQUEUE(&ifp->if_snd, m); 609 if (m == 0) 610 break; 611 612 /* 613 * If BPF is listening on this interface, let it see the 614 * packet before we commit it to the wire. 615 */ 616 bpf_mtap(ifp, m); 617 618 /* 619 * Copy the mbuf chain into the transmit buffer. 620 */ 621 len = be_put(sc, bix, m); 622 623 /* 624 * Initialize transmit registers and start transmission 625 */ 626 txd[bix].xd_flags = QEC_XD_OWN | QEC_XD_SOP | QEC_XD_EOP | 627 (len & QEC_XD_LENGTH); 628 bus_space_write_4(sc->sc_bustag, sc->sc_cr, 629 BE_CRI_CTRL, BE_CR_CTRL_TWAKEUP); 630 631 if (++bix == QEC_XD_RING_MAXSIZE) 632 bix = 0; 633 634 if (++sc->sc_rb.rb_td_nbusy == ntbuf) { 635 ifp->if_flags |= IFF_OACTIVE; 636 break; 637 } 638 } 639 640 sc->sc_rb.rb_tdhead = bix; 641 } 642 643 void 644 bestop(struct ifnet *ifp, int disable) 645 { 646 struct be_softc *sc = ifp->if_softc; 647 648 callout_stop(&sc->sc_tick_ch); 649 650 /* Down the MII. */ 651 mii_down(&sc->sc_mii); 652 (void)be_intphy_service(sc, &sc->sc_mii, MII_DOWN); 653 654 behwreset(sc); 655 } 656 657 void 658 behwreset(struct be_softc *sc) 659 { 660 int n; 661 bus_space_tag_t t = sc->sc_bustag; 662 bus_space_handle_t br = sc->sc_br; 663 664 /* Stop the transmitter */ 665 bus_space_write_4(t, br, BE_BRI_TXCFG, 0); 666 for (n = 32; n > 0; n--) { 667 if (bus_space_read_4(t, br, BE_BRI_TXCFG) == 0) 668 break; 669 DELAY(20); 670 } 671 672 /* Stop the receiver */ 673 bus_space_write_4(t, br, BE_BRI_RXCFG, 0); 674 for (n = 32; n > 0; n--) { 675 if (bus_space_read_4(t, br, BE_BRI_RXCFG) == 0) 676 break; 677 DELAY(20); 678 } 679 } 680 681 /* 682 * Reset interface. 683 */ 684 void 685 bereset(struct be_softc *sc) 686 { 687 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 688 int s; 689 690 s = splnet(); 691 behwreset(sc); 692 if ((sc->sc_ethercom.ec_if.if_flags & IFF_UP) != 0) 693 beinit(ifp); 694 splx(s); 695 } 696 697 void 698 bewatchdog(struct ifnet *ifp) 699 { 700 struct be_softc *sc = ifp->if_softc; 701 702 log(LOG_ERR, "%s: device timeout\n", device_xname(sc->sc_dev)); 703 ++sc->sc_ethercom.ec_if.if_oerrors; 704 705 bereset(sc); 706 } 707 708 int 709 beintr(void *arg) 710 { 711 struct be_softc *sc = arg; 712 bus_space_tag_t t = sc->sc_bustag; 713 uint32_t whyq, whyb, whyc; 714 int r = 0; 715 716 /* Read QEC status, channel status and BE status */ 717 whyq = bus_space_read_4(t, sc->sc_qr, QEC_QRI_STAT); 718 whyc = bus_space_read_4(t, sc->sc_cr, BE_CRI_STAT); 719 whyb = bus_space_read_4(t, sc->sc_br, BE_BRI_STAT); 720 721 if (whyq & QEC_STAT_BM) 722 r |= beeint(sc, whyb); 723 724 if (whyq & QEC_STAT_ER) 725 r |= beqint(sc, whyc); 726 727 if (whyq & QEC_STAT_TX && whyc & BE_CR_STAT_TXIRQ) 728 r |= betint(sc); 729 730 if (whyq & QEC_STAT_RX && whyc & BE_CR_STAT_RXIRQ) 731 r |= berint(sc); 732 733 return r; 734 } 735 736 /* 737 * QEC Interrupt. 738 */ 739 int 740 beqint(struct be_softc *sc, uint32_t why) 741 { 742 device_t self = sc->sc_dev; 743 int r = 0, rst = 0; 744 745 if (why & BE_CR_STAT_TXIRQ) 746 r |= 1; 747 if (why & BE_CR_STAT_RXIRQ) 748 r |= 1; 749 750 if (why & BE_CR_STAT_BERROR) { 751 r |= 1; 752 rst = 1; 753 aprint_error_dev(self, "bigmac error\n"); 754 } 755 756 if (why & BE_CR_STAT_TXDERR) { 757 r |= 1; 758 rst = 1; 759 aprint_error_dev(self, "bogus tx descriptor\n"); 760 } 761 762 if (why & (BE_CR_STAT_TXLERR | BE_CR_STAT_TXPERR | BE_CR_STAT_TXSERR)) { 763 r |= 1; 764 rst = 1; 765 aprint_error_dev(self, "tx DMA error ( "); 766 if (why & BE_CR_STAT_TXLERR) 767 printf("Late "); 768 if (why & BE_CR_STAT_TXPERR) 769 printf("Parity "); 770 if (why & BE_CR_STAT_TXSERR) 771 printf("Generic "); 772 printf(")\n"); 773 } 774 775 if (why & BE_CR_STAT_RXDROP) { 776 r |= 1; 777 rst = 1; 778 aprint_error_dev(self, "out of rx descriptors\n"); 779 } 780 781 if (why & BE_CR_STAT_RXSMALL) { 782 r |= 1; 783 rst = 1; 784 aprint_error_dev(self, "rx descriptor too small\n"); 785 } 786 787 if (why & (BE_CR_STAT_RXLERR | BE_CR_STAT_RXPERR | BE_CR_STAT_RXSERR)) { 788 r |= 1; 789 rst = 1; 790 aprint_error_dev(self, "rx DMA error ( "); 791 if (why & BE_CR_STAT_RXLERR) 792 printf("Late "); 793 if (why & BE_CR_STAT_RXPERR) 794 printf("Parity "); 795 if (why & BE_CR_STAT_RXSERR) 796 printf("Generic "); 797 printf(")\n"); 798 } 799 800 if (!r) { 801 rst = 1; 802 aprint_error_dev(self, "unexpected error interrupt %08x\n", 803 why); 804 } 805 806 if (rst) { 807 printf("%s: resetting\n", device_xname(self)); 808 bereset(sc); 809 } 810 811 return r; 812 } 813 814 /* 815 * Error interrupt. 816 */ 817 int 818 beeint(struct be_softc *sc, uint32_t why) 819 { 820 device_t self = sc->sc_dev; 821 int r = 0, rst = 0; 822 823 if (why & BE_BR_STAT_RFIFOVF) { 824 r |= 1; 825 rst = 1; 826 aprint_error_dev(self, "receive fifo overrun\n"); 827 } 828 if (why & BE_BR_STAT_TFIFO_UND) { 829 r |= 1; 830 rst = 1; 831 aprint_error_dev(self, "transmit fifo underrun\n"); 832 } 833 if (why & BE_BR_STAT_MAXPKTERR) { 834 r |= 1; 835 rst = 1; 836 aprint_error_dev(self, "max packet size error\n"); 837 } 838 839 if (!r) { 840 rst = 1; 841 aprint_error_dev(self, "unexpected error interrupt %08x\n", 842 why); 843 } 844 845 if (rst) { 846 printf("%s: resetting\n", device_xname(self)); 847 bereset(sc); 848 } 849 850 return r; 851 } 852 853 /* 854 * Transmit interrupt. 855 */ 856 int 857 betint(struct be_softc *sc) 858 { 859 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 860 bus_space_tag_t t = sc->sc_bustag; 861 bus_space_handle_t br = sc->sc_br; 862 unsigned int bix, txflags; 863 864 /* 865 * Unload collision counters 866 */ 867 ifp->if_collisions += 868 bus_space_read_4(t, br, BE_BRI_NCCNT) + 869 bus_space_read_4(t, br, BE_BRI_FCCNT) + 870 bus_space_read_4(t, br, BE_BRI_EXCNT) + 871 bus_space_read_4(t, br, BE_BRI_LTCNT); 872 873 /* 874 * the clear the hardware counters 875 */ 876 bus_space_write_4(t, br, BE_BRI_NCCNT, 0); 877 bus_space_write_4(t, br, BE_BRI_FCCNT, 0); 878 bus_space_write_4(t, br, BE_BRI_EXCNT, 0); 879 bus_space_write_4(t, br, BE_BRI_LTCNT, 0); 880 881 bix = sc->sc_rb.rb_tdtail; 882 883 for (;;) { 884 if (sc->sc_rb.rb_td_nbusy <= 0) 885 break; 886 887 txflags = sc->sc_rb.rb_txd[bix].xd_flags; 888 889 if (txflags & QEC_XD_OWN) 890 break; 891 892 ifp->if_flags &= ~IFF_OACTIVE; 893 ifp->if_opackets++; 894 895 if (++bix == QEC_XD_RING_MAXSIZE) 896 bix = 0; 897 898 --sc->sc_rb.rb_td_nbusy; 899 } 900 901 sc->sc_rb.rb_tdtail = bix; 902 903 bestart(ifp); 904 905 if (sc->sc_rb.rb_td_nbusy == 0) 906 ifp->if_timer = 0; 907 908 return 1; 909 } 910 911 /* 912 * Receive interrupt. 913 */ 914 int 915 berint(struct be_softc *sc) 916 { 917 struct qec_xd *xd = sc->sc_rb.rb_rxd; 918 unsigned int bix, len; 919 unsigned int nrbuf = sc->sc_rb.rb_nrbuf; 920 921 bix = sc->sc_rb.rb_rdtail; 922 923 /* 924 * Process all buffers with valid data. 925 */ 926 for (;;) { 927 len = xd[bix].xd_flags; 928 if (len & QEC_XD_OWN) 929 break; 930 931 len &= QEC_XD_LENGTH; 932 be_read(sc, bix, len); 933 934 /* ... */ 935 xd[(bix+nrbuf) % QEC_XD_RING_MAXSIZE].xd_flags = 936 QEC_XD_OWN | (BE_PKT_BUF_SZ & QEC_XD_LENGTH); 937 938 if (++bix == QEC_XD_RING_MAXSIZE) 939 bix = 0; 940 } 941 942 sc->sc_rb.rb_rdtail = bix; 943 944 return 1; 945 } 946 947 int 948 beioctl(struct ifnet *ifp, u_long cmd, void *data) 949 { 950 struct be_softc *sc = ifp->if_softc; 951 struct ifaddr *ifa = data; 952 struct ifreq *ifr = data; 953 int s, error = 0; 954 955 s = splnet(); 956 957 switch (cmd) { 958 case SIOCINITIFADDR: 959 ifp->if_flags |= IFF_UP; 960 beinit(ifp); 961 switch (ifa->ifa_addr->sa_family) { 962 #ifdef INET 963 case AF_INET: 964 arp_ifinit(ifp, ifa); 965 break; 966 #endif /* INET */ 967 default: 968 break; 969 } 970 break; 971 972 case SIOCSIFFLAGS: 973 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 974 break; 975 /* XXX re-use ether_ioctl() */ 976 switch (ifp->if_flags & (IFF_UP|IFF_RUNNING)) { 977 case IFF_RUNNING: 978 /* 979 * If interface is marked down and it is running, then 980 * stop it. 981 */ 982 bestop(ifp, 0); 983 ifp->if_flags &= ~IFF_RUNNING; 984 break; 985 case IFF_UP: 986 /* 987 * If interface is marked up and it is stopped, then 988 * start it. 989 */ 990 beinit(ifp); 991 break; 992 default: 993 /* 994 * Reset the interface to pick up changes in any other 995 * flags that affect hardware registers. 996 */ 997 bestop(ifp, 0); 998 beinit(ifp); 999 break; 1000 } 1001 #ifdef BEDEBUG 1002 if (ifp->if_flags & IFF_DEBUG) 1003 sc->sc_debug = 1; 1004 else 1005 sc->sc_debug = 0; 1006 #endif 1007 break; 1008 1009 case SIOCGIFMEDIA: 1010 case SIOCSIFMEDIA: 1011 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd); 1012 break; 1013 default: 1014 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 1015 /* 1016 * Multicast list has changed; set the hardware filter 1017 * accordingly. 1018 */ 1019 if (ifp->if_flags & IFF_RUNNING) 1020 error = beinit(ifp); 1021 else 1022 error = 0; 1023 } 1024 break; 1025 } 1026 splx(s); 1027 return error; 1028 } 1029 1030 1031 int 1032 beinit(struct ifnet *ifp) 1033 { 1034 struct be_softc *sc = ifp->if_softc; 1035 bus_space_tag_t t = sc->sc_bustag; 1036 bus_space_handle_t br = sc->sc_br; 1037 bus_space_handle_t cr = sc->sc_cr; 1038 struct qec_softc *qec = sc->sc_qec; 1039 uint32_t v; 1040 uint32_t qecaddr; 1041 uint8_t *ea; 1042 int rc, s; 1043 1044 s = splnet(); 1045 1046 qec_meminit(&sc->sc_rb, BE_PKT_BUF_SZ); 1047 1048 bestop(ifp, 1); 1049 1050 ea = sc->sc_enaddr; 1051 bus_space_write_4(t, br, BE_BRI_MACADDR0, (ea[0] << 8) | ea[1]); 1052 bus_space_write_4(t, br, BE_BRI_MACADDR1, (ea[2] << 8) | ea[3]); 1053 bus_space_write_4(t, br, BE_BRI_MACADDR2, (ea[4] << 8) | ea[5]); 1054 1055 /* Clear hash table */ 1056 bus_space_write_4(t, br, BE_BRI_HASHTAB0, 0); 1057 bus_space_write_4(t, br, BE_BRI_HASHTAB1, 0); 1058 bus_space_write_4(t, br, BE_BRI_HASHTAB2, 0); 1059 bus_space_write_4(t, br, BE_BRI_HASHTAB3, 0); 1060 1061 /* Re-initialize RX configuration */ 1062 v = BE_BR_RXCFG_FIFO; 1063 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1064 1065 be_mcreset(sc); 1066 1067 bus_space_write_4(t, br, BE_BRI_RANDSEED, 0xbd); 1068 1069 bus_space_write_4(t, br, 1070 BE_BRI_XIFCFG, BE_BR_XCFG_ODENABLE | BE_BR_XCFG_RESV); 1071 1072 bus_space_write_4(t, br, BE_BRI_JSIZE, 4); 1073 1074 /* 1075 * Turn off counter expiration interrupts as well as 1076 * 'gotframe' and 'sentframe' 1077 */ 1078 bus_space_write_4(t, br, BE_BRI_IMASK, 1079 BE_BR_IMASK_GOTFRAME | 1080 BE_BR_IMASK_RCNTEXP | 1081 BE_BR_IMASK_ACNTEXP | 1082 BE_BR_IMASK_CCNTEXP | 1083 BE_BR_IMASK_LCNTEXP | 1084 BE_BR_IMASK_CVCNTEXP | 1085 BE_BR_IMASK_SENTFRAME | 1086 BE_BR_IMASK_NCNTEXP | 1087 BE_BR_IMASK_ECNTEXP | 1088 BE_BR_IMASK_LCCNTEXP | 1089 BE_BR_IMASK_FCNTEXP | 1090 BE_BR_IMASK_DTIMEXP); 1091 1092 /* Channel registers: */ 1093 bus_space_write_4(t, cr, BE_CRI_RXDS, (uint32_t)sc->sc_rb.rb_rxddma); 1094 bus_space_write_4(t, cr, BE_CRI_TXDS, (uint32_t)sc->sc_rb.rb_txddma); 1095 1096 qecaddr = sc->sc_channel * qec->sc_msize; 1097 bus_space_write_4(t, cr, BE_CRI_RXWBUF, qecaddr); 1098 bus_space_write_4(t, cr, BE_CRI_RXRBUF, qecaddr); 1099 bus_space_write_4(t, cr, BE_CRI_TXWBUF, qecaddr + qec->sc_rsize); 1100 bus_space_write_4(t, cr, BE_CRI_TXRBUF, qecaddr + qec->sc_rsize); 1101 1102 bus_space_write_4(t, cr, BE_CRI_RIMASK, 0); 1103 bus_space_write_4(t, cr, BE_CRI_TIMASK, 0); 1104 bus_space_write_4(t, cr, BE_CRI_QMASK, 0); 1105 bus_space_write_4(t, cr, BE_CRI_BMASK, 0); 1106 bus_space_write_4(t, cr, BE_CRI_CCNT, 0); 1107 1108 /* Set max packet length */ 1109 v = ETHER_MAX_LEN; 1110 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) 1111 v += ETHER_VLAN_ENCAP_LEN; 1112 bus_space_write_4(t, br, BE_BRI_RXMAX, v); 1113 bus_space_write_4(t, br, BE_BRI_TXMAX, v); 1114 1115 /* Enable transmitter */ 1116 bus_space_write_4(t, br, 1117 BE_BRI_TXCFG, BE_BR_TXCFG_FIFO | BE_BR_TXCFG_ENABLE); 1118 1119 /* Enable receiver */ 1120 v = bus_space_read_4(t, br, BE_BRI_RXCFG); 1121 v |= BE_BR_RXCFG_FIFO | BE_BR_RXCFG_ENABLE; 1122 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1123 1124 if ((rc = be_ifmedia_upd(ifp)) != 0) 1125 goto out; 1126 1127 ifp->if_flags |= IFF_RUNNING; 1128 ifp->if_flags &= ~IFF_OACTIVE; 1129 1130 callout_reset(&sc->sc_tick_ch, hz, be_tick, sc); 1131 1132 return 0; 1133 out: 1134 splx(s); 1135 return rc; 1136 } 1137 1138 void 1139 be_mcreset(struct be_softc *sc) 1140 { 1141 struct ethercom *ec = &sc->sc_ethercom; 1142 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1143 bus_space_tag_t t = sc->sc_bustag; 1144 bus_space_handle_t br = sc->sc_br; 1145 uint32_t v; 1146 uint32_t crc; 1147 uint16_t hash[4]; 1148 struct ether_multi *enm; 1149 struct ether_multistep step; 1150 1151 if (ifp->if_flags & IFF_PROMISC) { 1152 v = bus_space_read_4(t, br, BE_BRI_RXCFG); 1153 v |= BE_BR_RXCFG_PMISC; 1154 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1155 return; 1156 } 1157 1158 if (ifp->if_flags & IFF_ALLMULTI) { 1159 hash[3] = hash[2] = hash[1] = hash[0] = 0xffff; 1160 goto chipit; 1161 } 1162 1163 hash[3] = hash[2] = hash[1] = hash[0] = 0; 1164 1165 ETHER_FIRST_MULTI(step, ec, enm); 1166 while (enm != NULL) { 1167 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1168 /* 1169 * We must listen to a range of multicast 1170 * addresses. For now, just accept all 1171 * multicasts, rather than trying to set only 1172 * those filter bits needed to match the range. 1173 * (At this time, the only use of address 1174 * ranges is for IP multicast routing, for 1175 * which the range is big enough to require 1176 * all bits set.) 1177 */ 1178 hash[3] = hash[2] = hash[1] = hash[0] = 0xffff; 1179 ifp->if_flags |= IFF_ALLMULTI; 1180 goto chipit; 1181 } 1182 1183 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 1184 /* Just want the 6 most significant bits. */ 1185 crc >>= 26; 1186 1187 hash[crc >> 4] |= 1 << (crc & 0xf); 1188 ETHER_NEXT_MULTI(step, enm); 1189 } 1190 1191 ifp->if_flags &= ~IFF_ALLMULTI; 1192 1193 chipit: 1194 /* Enable the hash filter */ 1195 bus_space_write_4(t, br, BE_BRI_HASHTAB0, hash[0]); 1196 bus_space_write_4(t, br, BE_BRI_HASHTAB1, hash[1]); 1197 bus_space_write_4(t, br, BE_BRI_HASHTAB2, hash[2]); 1198 bus_space_write_4(t, br, BE_BRI_HASHTAB3, hash[3]); 1199 1200 v = bus_space_read_4(t, br, BE_BRI_RXCFG); 1201 v &= ~BE_BR_RXCFG_PMISC; 1202 v |= BE_BR_RXCFG_HENABLE; 1203 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1204 } 1205 1206 /* 1207 * Set the tcvr to an idle state 1208 */ 1209 void 1210 be_mii_sync(struct be_softc *sc) 1211 { 1212 bus_space_tag_t t = sc->sc_bustag; 1213 bus_space_handle_t tr = sc->sc_tr; 1214 int n = 32; 1215 1216 while (n--) { 1217 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, 1218 MGMT_PAL_INT_MDIO | MGMT_PAL_EXT_MDIO | MGMT_PAL_OENAB); 1219 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1220 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, 1221 MGMT_PAL_INT_MDIO | MGMT_PAL_EXT_MDIO | 1222 MGMT_PAL_OENAB | MGMT_PAL_DCLOCK); 1223 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1224 } 1225 } 1226 1227 void 1228 be_pal_gate(struct be_softc *sc, int phy) 1229 { 1230 bus_space_tag_t t = sc->sc_bustag; 1231 bus_space_handle_t tr = sc->sc_tr; 1232 uint32_t v; 1233 1234 be_mii_sync(sc); 1235 1236 v = ~(TCVR_PAL_EXTLBACK | TCVR_PAL_MSENSE | TCVR_PAL_LTENABLE); 1237 if (phy == BE_PHY_INTERNAL) 1238 v &= ~TCVR_PAL_SERIAL; 1239 1240 bus_space_write_4(t, tr, BE_TRI_TCVRPAL, v); 1241 (void)bus_space_read_4(t, tr, BE_TRI_TCVRPAL); 1242 } 1243 1244 static int 1245 be_tcvr_read_bit(struct be_softc *sc, int phy) 1246 { 1247 bus_space_tag_t t = sc->sc_bustag; 1248 bus_space_handle_t tr = sc->sc_tr; 1249 int ret; 1250 1251 if (phy == BE_PHY_INTERNAL) { 1252 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, MGMT_PAL_EXT_MDIO); 1253 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1254 bus_space_write_4(t, tr, 1255 BE_TRI_MGMTPAL, MGMT_PAL_EXT_MDIO | MGMT_PAL_DCLOCK); 1256 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1257 ret = (bus_space_read_4(t, tr, BE_TRI_MGMTPAL) & 1258 MGMT_PAL_INT_MDIO) >> MGMT_PAL_INT_MDIO_SHIFT; 1259 } else { 1260 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, MGMT_PAL_INT_MDIO); 1261 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1262 ret = (bus_space_read_4(t, tr, BE_TRI_MGMTPAL) & 1263 MGMT_PAL_EXT_MDIO) >> MGMT_PAL_EXT_MDIO_SHIFT; 1264 bus_space_write_4(t, tr, 1265 BE_TRI_MGMTPAL, MGMT_PAL_INT_MDIO | MGMT_PAL_DCLOCK); 1266 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1267 } 1268 1269 return ret; 1270 } 1271 1272 static void 1273 be_tcvr_write_bit(struct be_softc *sc, int phy, int bit) 1274 { 1275 bus_space_tag_t t = sc->sc_bustag; 1276 bus_space_handle_t tr = sc->sc_tr; 1277 uint32_t v; 1278 1279 if (phy == BE_PHY_INTERNAL) { 1280 v = ((bit & 1) << MGMT_PAL_INT_MDIO_SHIFT) | 1281 MGMT_PAL_OENAB | MGMT_PAL_EXT_MDIO; 1282 } else { 1283 v = ((bit & 1) << MGMT_PAL_EXT_MDIO_SHIFT) | 1284 MGMT_PAL_OENAB | MGMT_PAL_INT_MDIO; 1285 } 1286 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, v); 1287 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1288 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, v | MGMT_PAL_DCLOCK); 1289 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1290 } 1291 1292 static void 1293 be_mii_sendbits(struct be_softc *sc, int phy, uint32_t data, int nbits) 1294 { 1295 int i; 1296 1297 for (i = 1 << (nbits - 1); i != 0; i >>= 1) { 1298 be_tcvr_write_bit(sc, phy, (data & i) != 0); 1299 } 1300 } 1301 1302 static int 1303 be_mii_readreg(device_t self, int phy, int reg) 1304 { 1305 struct be_softc *sc = device_private(self); 1306 int val = 0, i; 1307 1308 /* 1309 * Read the PHY register by manually driving the MII control lines. 1310 */ 1311 be_mii_sync(sc); 1312 be_mii_sendbits(sc, phy, MII_COMMAND_START, 2); 1313 be_mii_sendbits(sc, phy, MII_COMMAND_READ, 2); 1314 be_mii_sendbits(sc, phy, phy, 5); 1315 be_mii_sendbits(sc, phy, reg, 5); 1316 1317 (void)be_tcvr_read_bit(sc, phy); 1318 (void)be_tcvr_read_bit(sc, phy); 1319 1320 for (i = 15; i >= 0; i--) 1321 val |= (be_tcvr_read_bit(sc, phy) << i); 1322 1323 (void)be_tcvr_read_bit(sc, phy); 1324 (void)be_tcvr_read_bit(sc, phy); 1325 (void)be_tcvr_read_bit(sc, phy); 1326 1327 return val; 1328 } 1329 1330 void 1331 be_mii_writereg(device_t self, int phy, int reg, int val) 1332 { 1333 struct be_softc *sc = device_private(self); 1334 int i; 1335 1336 /* 1337 * Write the PHY register by manually driving the MII control lines. 1338 */ 1339 be_mii_sync(sc); 1340 be_mii_sendbits(sc, phy, MII_COMMAND_START, 2); 1341 be_mii_sendbits(sc, phy, MII_COMMAND_WRITE, 2); 1342 be_mii_sendbits(sc, phy, phy, 5); 1343 be_mii_sendbits(sc, phy, reg, 5); 1344 1345 be_tcvr_write_bit(sc, phy, 1); 1346 be_tcvr_write_bit(sc, phy, 0); 1347 1348 for (i = 15; i >= 0; i--) 1349 be_tcvr_write_bit(sc, phy, (val >> i) & 1); 1350 } 1351 1352 int 1353 be_mii_reset(struct be_softc *sc, int phy) 1354 { 1355 device_t self = sc->sc_dev; 1356 int n; 1357 1358 be_mii_writereg(self, phy, MII_BMCR, BMCR_LOOP | BMCR_PDOWN | BMCR_ISO); 1359 be_mii_writereg(self, phy, MII_BMCR, BMCR_RESET); 1360 1361 for (n = 16; n >= 0; n--) { 1362 int bmcr = be_mii_readreg(self, phy, MII_BMCR); 1363 if ((bmcr & BMCR_RESET) == 0) 1364 break; 1365 DELAY(20); 1366 } 1367 if (n == 0) { 1368 aprint_error_dev(self, "bmcr reset failed\n"); 1369 return EIO; 1370 } 1371 1372 return 0; 1373 } 1374 1375 void 1376 be_tick(void *arg) 1377 { 1378 struct be_softc *sc = arg; 1379 int s = splnet(); 1380 1381 mii_tick(&sc->sc_mii); 1382 (void)be_intphy_service(sc, &sc->sc_mii, MII_TICK); 1383 1384 splx(s); 1385 callout_reset(&sc->sc_tick_ch, hz, be_tick, sc); 1386 } 1387 1388 void 1389 be_mii_statchg(device_t self) 1390 { 1391 struct be_softc *sc = device_private(self); 1392 bus_space_tag_t t = sc->sc_bustag; 1393 bus_space_handle_t br = sc->sc_br; 1394 uint instance; 1395 uint32_t v; 1396 1397 instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media); 1398 #ifdef DIAGNOSTIC 1399 if (instance > 1) 1400 panic("be_mii_statchg: instance %d out of range", instance); 1401 #endif 1402 1403 /* Update duplex mode in TX configuration */ 1404 v = bus_space_read_4(t, br, BE_BRI_TXCFG); 1405 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 1406 v |= BE_BR_TXCFG_FULLDPLX; 1407 else 1408 v &= ~BE_BR_TXCFG_FULLDPLX; 1409 bus_space_write_4(t, br, BE_BRI_TXCFG, v); 1410 1411 /* Change to appropriate gate in transceiver PAL */ 1412 be_pal_gate(sc, sc->sc_phys[instance]); 1413 } 1414 1415 /* 1416 * Get current media settings. 1417 */ 1418 void 1419 be_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1420 { 1421 struct be_softc *sc = ifp->if_softc; 1422 1423 mii_pollstat(&sc->sc_mii); 1424 (void)be_intphy_service(sc, &sc->sc_mii, MII_POLLSTAT); 1425 1426 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1427 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1428 } 1429 1430 /* 1431 * Set media options. 1432 */ 1433 int 1434 be_ifmedia_upd(struct ifnet *ifp) 1435 { 1436 struct be_softc *sc = ifp->if_softc; 1437 int error; 1438 1439 if ((error = mii_mediachg(&sc->sc_mii)) == ENXIO) 1440 error = 0; 1441 else if (error != 0) 1442 return error; 1443 1444 return be_intphy_service(sc, &sc->sc_mii, MII_MEDIACHG); 1445 } 1446 1447 /* 1448 * Service routine for our pseudo-MII internal transceiver. 1449 */ 1450 int 1451 be_intphy_service(struct be_softc *sc, struct mii_data *mii, int cmd) 1452 { 1453 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 1454 device_t self = sc->sc_dev; 1455 int bmcr, bmsr; 1456 int error; 1457 1458 switch (cmd) { 1459 case MII_POLLSTAT: 1460 /* 1461 * If we're not polling our PHY instance, just return. 1462 */ 1463 if (IFM_INST(ife->ifm_media) != sc->sc_mii_inst) 1464 return 0; 1465 1466 break; 1467 1468 case MII_MEDIACHG: 1469 1470 /* 1471 * If the media indicates a different PHY instance, 1472 * isolate ourselves. 1473 */ 1474 if (IFM_INST(ife->ifm_media) != sc->sc_mii_inst) { 1475 bmcr = be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMCR); 1476 be_mii_writereg(self, 1477 BE_PHY_INTERNAL, MII_BMCR, bmcr | BMCR_ISO); 1478 sc->sc_mii_flags &= ~MIIF_HAVELINK; 1479 sc->sc_intphy_curspeed = 0; 1480 return 0; 1481 } 1482 1483 1484 if ((error = be_mii_reset(sc, BE_PHY_INTERNAL)) != 0) 1485 return error; 1486 1487 bmcr = be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMCR); 1488 1489 /* 1490 * Select the new mode and take out of isolation 1491 */ 1492 if (IFM_SUBTYPE(ife->ifm_media) == IFM_100_TX) 1493 bmcr |= BMCR_S100; 1494 else if (IFM_SUBTYPE(ife->ifm_media) == IFM_10_T) 1495 bmcr &= ~BMCR_S100; 1496 else if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) { 1497 if ((sc->sc_mii_flags & MIIF_HAVELINK) != 0) { 1498 bmcr &= ~BMCR_S100; 1499 bmcr |= sc->sc_intphy_curspeed; 1500 } else { 1501 /* Keep isolated until link is up */ 1502 bmcr |= BMCR_ISO; 1503 sc->sc_mii_flags |= MIIF_DOINGAUTO; 1504 } 1505 } 1506 1507 if ((IFM_OPTIONS(ife->ifm_media) & IFM_FDX) != 0) 1508 bmcr |= BMCR_FDX; 1509 else 1510 bmcr &= ~BMCR_FDX; 1511 1512 be_mii_writereg(self, BE_PHY_INTERNAL, MII_BMCR, bmcr); 1513 break; 1514 1515 case MII_TICK: 1516 /* 1517 * If we're not currently selected, just return. 1518 */ 1519 if (IFM_INST(ife->ifm_media) != sc->sc_mii_inst) 1520 return 0; 1521 1522 /* Only used for automatic media selection */ 1523 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) 1524 return 0; 1525 1526 /* Is the interface even up? */ 1527 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 1528 return 0; 1529 1530 /* 1531 * Check link status; if we don't have a link, try another 1532 * speed. We can't detect duplex mode, so half-duplex is 1533 * what we have to settle for. 1534 */ 1535 1536 /* Read twice in case the register is latched */ 1537 bmsr = 1538 be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMSR) | 1539 be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMSR); 1540 1541 if ((bmsr & BMSR_LINK) != 0) { 1542 /* We have a carrier */ 1543 bmcr = be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMCR); 1544 1545 if ((sc->sc_mii_flags & MIIF_DOINGAUTO) != 0) { 1546 bmcr = be_mii_readreg(self, 1547 BE_PHY_INTERNAL, MII_BMCR); 1548 1549 sc->sc_mii_flags |= MIIF_HAVELINK; 1550 sc->sc_intphy_curspeed = (bmcr & BMCR_S100); 1551 sc->sc_mii_flags &= ~MIIF_DOINGAUTO; 1552 1553 bmcr &= ~BMCR_ISO; 1554 be_mii_writereg(self, 1555 BE_PHY_INTERNAL, MII_BMCR, bmcr); 1556 1557 printf("%s: link up at %s Mbps\n", 1558 device_xname(self), 1559 (bmcr & BMCR_S100) ? "100" : "10"); 1560 } 1561 return 0; 1562 } 1563 1564 if ((sc->sc_mii_flags & MIIF_DOINGAUTO) == 0) { 1565 sc->sc_mii_flags |= MIIF_DOINGAUTO; 1566 sc->sc_mii_flags &= ~MIIF_HAVELINK; 1567 sc->sc_intphy_curspeed = 0; 1568 printf("%s: link down\n", device_xname(self)); 1569 } 1570 1571 /* Only retry autonegotiation every 5 seconds. */ 1572 if (++sc->sc_mii_ticks < 5) 1573 return 0; 1574 1575 sc->sc_mii_ticks = 0; 1576 bmcr = be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMCR); 1577 /* Just flip the fast speed bit */ 1578 bmcr ^= BMCR_S100; 1579 be_mii_writereg(self, BE_PHY_INTERNAL, MII_BMCR, bmcr); 1580 1581 break; 1582 1583 case MII_DOWN: 1584 /* Isolate this phy */ 1585 bmcr = be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMCR); 1586 be_mii_writereg(self, 1587 BE_PHY_INTERNAL, MII_BMCR, bmcr | BMCR_ISO); 1588 return 0; 1589 } 1590 1591 /* Update the media status. */ 1592 be_intphy_status(sc); 1593 1594 /* Callback if something changed. */ 1595 if (sc->sc_mii_active != mii->mii_media_active || cmd == MII_MEDIACHG) { 1596 (*mii->mii_statchg)(self); 1597 sc->sc_mii_active = mii->mii_media_active; 1598 } 1599 return 0; 1600 } 1601 1602 /* 1603 * Determine status of internal transceiver 1604 */ 1605 void 1606 be_intphy_status(struct be_softc *sc) 1607 { 1608 struct mii_data *mii = &sc->sc_mii; 1609 device_t self = sc->sc_dev; 1610 int media_active, media_status; 1611 int bmcr, bmsr; 1612 1613 media_status = IFM_AVALID; 1614 media_active = 0; 1615 1616 /* 1617 * Internal transceiver; do the work here. 1618 */ 1619 bmcr = be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMCR); 1620 1621 switch (bmcr & (BMCR_S100 | BMCR_FDX)) { 1622 case (BMCR_S100 | BMCR_FDX): 1623 media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 1624 break; 1625 case BMCR_S100: 1626 media_active = IFM_ETHER | IFM_100_TX | IFM_HDX; 1627 break; 1628 case BMCR_FDX: 1629 media_active = IFM_ETHER | IFM_10_T | IFM_FDX; 1630 break; 1631 case 0: 1632 media_active = IFM_ETHER | IFM_10_T | IFM_HDX; 1633 break; 1634 } 1635 1636 /* Read twice in case the register is latched */ 1637 bmsr = 1638 be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMSR) | 1639 be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMSR); 1640 if (bmsr & BMSR_LINK) 1641 media_status |= IFM_ACTIVE; 1642 1643 mii->mii_media_status = media_status; 1644 mii->mii_media_active = media_active; 1645 } 1646
Indexes created Tue Sep 30 07:10:03 GMT 2025