be.c revision 1.80.8.1
1 /* $NetBSD: be.c,v 1.80.8.1 2018/03/03 20:14:20 snj Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Copyright (c) 1998 Theo de Raadt and Jason L. Wright. 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. The name of the authors may not be used to endorse or promote products 45 * derived from this software without specific prior written permission. 46 * 47 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR 48 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 49 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 50 * IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, 51 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 52 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 53 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 54 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 55 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 56 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 57 */ 58 59 #include <sys/cdefs.h> 60 __KERNEL_RCSID(0, "$NetBSD: be.c,v 1.80.8.1 2018/03/03 20:14:20 snj Exp $"); 61 62 #include "opt_ddb.h" 63 #include "opt_inet.h" 64 65 #include <sys/param.h> 66 #include <sys/systm.h> 67 #include <sys/callout.h> 68 #include <sys/kernel.h> 69 #include <sys/errno.h> 70 #include <sys/ioctl.h> 71 #include <sys/mbuf.h> 72 #include <sys/socket.h> 73 #include <sys/syslog.h> 74 #include <sys/device.h> 75 #include <sys/malloc.h> 76 #include <sys/rnd.h> 77 78 #include <net/if.h> 79 #include <net/if_dl.h> 80 #include <net/if_types.h> 81 #include <net/netisr.h> 82 #include <net/if_media.h> 83 #include <net/if_ether.h> 84 85 #ifdef INET 86 #include <netinet/in.h> 87 #include <netinet/if_inarp.h> 88 #include <netinet/in_systm.h> 89 #include <netinet/in_var.h> 90 #include <netinet/ip.h> 91 #endif 92 93 94 #include <net/bpf.h> 95 #include <net/bpfdesc.h> 96 97 #include <sys/bus.h> 98 #include <sys/intr.h> 99 #include <machine/autoconf.h> 100 101 #include <dev/sbus/sbusvar.h> 102 103 #include <dev/mii/mii.h> 104 #include <dev/mii/miivar.h> 105 106 #include <dev/sbus/qecreg.h> 107 #include <dev/sbus/qecvar.h> 108 #include <dev/sbus/bereg.h> 109 110 struct be_softc { 111 device_t sc_dev; 112 bus_space_tag_t sc_bustag; /* bus & DMA tags */ 113 bus_dma_tag_t sc_dmatag; 114 bus_dmamap_t sc_dmamap; 115 struct ethercom sc_ethercom; 116 /*struct ifmedia sc_ifmedia; -* interface media */ 117 struct mii_data sc_mii; /* MII media control */ 118 #define sc_media sc_mii.mii_media/* shorthand */ 119 int sc_phys[2]; /* MII instance -> phy */ 120 121 struct callout sc_tick_ch; 122 123 /* 124 * Some `mii_softc' items we need to emulate MII operation 125 * for our internal transceiver. 126 */ 127 int sc_mii_inst; /* instance of internal phy */ 128 int sc_mii_active; /* currently active medium */ 129 int sc_mii_ticks; /* tick counter */ 130 int sc_mii_flags; /* phy status flags */ 131 #define MIIF_HAVELINK 0x04000000 132 int sc_intphy_curspeed; /* Established link speed */ 133 134 struct qec_softc *sc_qec; /* QEC parent */ 135 136 bus_space_handle_t sc_qr; /* QEC registers */ 137 bus_space_handle_t sc_br; /* BE registers */ 138 bus_space_handle_t sc_cr; /* channel registers */ 139 bus_space_handle_t sc_tr; /* transceiver registers */ 140 141 u_int sc_rev; 142 143 int sc_channel; /* channel number */ 144 int sc_burst; 145 146 struct qec_ring sc_rb; /* Packet Ring Buffer */ 147 148 /* MAC address */ 149 uint8_t sc_enaddr[ETHER_ADDR_LEN]; 150 #ifdef BEDEBUG 151 int sc_debug; 152 #endif 153 }; 154 155 static int bematch(device_t, cfdata_t, void *); 156 static void beattach(device_t, device_t, void *); 157 158 static int beinit(struct ifnet *); 159 static void bestart(struct ifnet *); 160 static void bestop(struct ifnet *, int); 161 static void bewatchdog(struct ifnet *); 162 static int beioctl(struct ifnet *, u_long, void *); 163 static void bereset(struct be_softc *); 164 static void behwreset(struct be_softc *); 165 166 static int beintr(void *); 167 static int berint(struct be_softc *); 168 static int betint(struct be_softc *); 169 static int beqint(struct be_softc *, uint32_t); 170 static int beeint(struct be_softc *, uint32_t); 171 172 static void be_read(struct be_softc *, int, int); 173 static int be_put(struct be_softc *, int, struct mbuf *); 174 static struct mbuf *be_get(struct be_softc *, int, int); 175 176 static void be_pal_gate(struct be_softc *, int); 177 178 /* ifmedia callbacks */ 179 static void be_ifmedia_sts(struct ifnet *, struct ifmediareq *); 180 static int be_ifmedia_upd(struct ifnet *); 181 182 static void be_mcreset(struct be_softc *); 183 184 /* MII methods & callbacks */ 185 static int be_mii_readreg(device_t, int, int); 186 static void be_mii_writereg(device_t, int, int, int); 187 static void be_mii_statchg(struct ifnet *); 188 189 /* MII helpers */ 190 static void be_mii_sync(struct be_softc *); 191 static void be_mii_sendbits(struct be_softc *, int, uint32_t, int); 192 static int be_mii_reset(struct be_softc *, int); 193 static int be_tcvr_read_bit(struct be_softc *, int); 194 static void be_tcvr_write_bit(struct be_softc *, int, int); 195 196 static void be_tick(void *); 197 #if 0 198 static void be_intphy_auto(struct be_softc *); 199 #endif 200 static void be_intphy_status(struct be_softc *); 201 static int be_intphy_service(struct be_softc *, struct mii_data *, int); 202 203 204 CFATTACH_DECL_NEW(be, sizeof(struct be_softc), 205 bematch, beattach, NULL, NULL); 206 207 int 208 bematch(device_t parent, cfdata_t cf, void *aux) 209 { 210 struct sbus_attach_args *sa = aux; 211 212 return strcmp(cf->cf_name, sa->sa_name) == 0; 213 } 214 215 void 216 beattach(device_t parent, device_t self, void *aux) 217 { 218 struct sbus_attach_args *sa = aux; 219 struct qec_softc *qec = device_private(parent); 220 struct be_softc *sc = device_private(self); 221 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 222 struct mii_data *mii = &sc->sc_mii; 223 struct mii_softc *child; 224 int node = sa->sa_node; 225 bus_dma_tag_t dmatag = sa->sa_dmatag; 226 bus_dma_segment_t seg; 227 bus_size_t size; 228 int instance; 229 int rseg, error; 230 uint32_t v; 231 232 sc->sc_dev = self; 233 234 if (sa->sa_nreg < 3) { 235 printf(": only %d register sets\n", sa->sa_nreg); 236 return; 237 } 238 239 if (bus_space_map(sa->sa_bustag, 240 (bus_addr_t)BUS_ADDR(sa->sa_reg[0].oa_space, sa->sa_reg[0].oa_base), 241 (bus_size_t)sa->sa_reg[0].oa_size, 242 0, &sc->sc_cr) != 0) { 243 printf(": cannot map registers\n"); 244 return; 245 } 246 247 if (bus_space_map(sa->sa_bustag, 248 (bus_addr_t)BUS_ADDR(sa->sa_reg[1].oa_space, sa->sa_reg[1].oa_base), 249 (bus_size_t)sa->sa_reg[1].oa_size, 250 0, &sc->sc_br) != 0) { 251 printf(": cannot map registers\n"); 252 return; 253 } 254 255 if (bus_space_map(sa->sa_bustag, 256 (bus_addr_t)BUS_ADDR(sa->sa_reg[2].oa_space, sa->sa_reg[2].oa_base), 257 (bus_size_t)sa->sa_reg[2].oa_size, 258 0, &sc->sc_tr) != 0) { 259 printf(": cannot map registers\n"); 260 return; 261 } 262 263 sc->sc_bustag = sa->sa_bustag; 264 sc->sc_qec = qec; 265 sc->sc_qr = qec->sc_regs; 266 267 sc->sc_rev = prom_getpropint(node, "board-version", -1); 268 printf(": rev %x,", sc->sc_rev); 269 270 callout_init(&sc->sc_tick_ch, 0); 271 272 sc->sc_channel = prom_getpropint(node, "channel#", -1); 273 if (sc->sc_channel == -1) 274 sc->sc_channel = 0; 275 276 sc->sc_burst = prom_getpropint(node, "burst-sizes", -1); 277 if (sc->sc_burst == -1) 278 sc->sc_burst = qec->sc_burst; 279 280 /* Clamp at parent's burst sizes */ 281 sc->sc_burst &= qec->sc_burst; 282 283 /* Establish interrupt handler */ 284 if (sa->sa_nintr) 285 (void)bus_intr_establish(sa->sa_bustag, sa->sa_pri, IPL_NET, 286 beintr, sc); 287 288 prom_getether(node, sc->sc_enaddr); 289 printf(" address %s\n", ether_sprintf(sc->sc_enaddr)); 290 291 /* 292 * Allocate descriptor ring and buffers. 293 */ 294 295 /* for now, allocate as many bufs as there are ring descriptors */ 296 sc->sc_rb.rb_ntbuf = QEC_XD_RING_MAXSIZE; 297 sc->sc_rb.rb_nrbuf = QEC_XD_RING_MAXSIZE; 298 299 size = 300 QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd) + 301 QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd) + 302 sc->sc_rb.rb_ntbuf * BE_PKT_BUF_SZ + 303 sc->sc_rb.rb_nrbuf * BE_PKT_BUF_SZ; 304 305 /* Get a DMA handle */ 306 if ((error = bus_dmamap_create(dmatag, size, 1, size, 0, 307 BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) { 308 aprint_error_dev(self, "DMA map create error %d\n", error); 309 return; 310 } 311 312 /* Allocate DMA buffer */ 313 if ((error = bus_dmamem_alloc(sa->sa_dmatag, size, 0, 0, 314 &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 315 aprint_error_dev(self, "DMA buffer alloc error %d\n", error); 316 return; 317 } 318 319 /* Map DMA memory in CPU addressable space */ 320 if ((error = bus_dmamem_map(sa->sa_dmatag, &seg, rseg, size, 321 &sc->sc_rb.rb_membase, BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 322 aprint_error_dev(self, "DMA buffer map error %d\n", error); 323 bus_dmamem_free(sa->sa_dmatag, &seg, rseg); 324 return; 325 } 326 327 /* Load the buffer */ 328 if ((error = bus_dmamap_load(dmatag, sc->sc_dmamap, 329 sc->sc_rb.rb_membase, size, NULL, BUS_DMA_NOWAIT)) != 0) { 330 aprint_error_dev(self, "DMA buffer map load error %d\n", error); 331 bus_dmamem_unmap(dmatag, sc->sc_rb.rb_membase, size); 332 bus_dmamem_free(dmatag, &seg, rseg); 333 return; 334 } 335 sc->sc_rb.rb_dmabase = sc->sc_dmamap->dm_segs[0].ds_addr; 336 337 /* 338 * Initialize our media structures and MII info. 339 */ 340 mii->mii_ifp = ifp; 341 mii->mii_readreg = be_mii_readreg; 342 mii->mii_writereg = be_mii_writereg; 343 mii->mii_statchg = be_mii_statchg; 344 345 ifmedia_init(&mii->mii_media, 0, be_ifmedia_upd, be_ifmedia_sts); 346 347 /* 348 * Initialize transceiver and determine which PHY connection to use. 349 */ 350 be_mii_sync(sc); 351 v = bus_space_read_4(sc->sc_bustag, sc->sc_tr, BE_TRI_MGMTPAL); 352 353 instance = 0; 354 355 if ((v & MGMT_PAL_EXT_MDIO) != 0) { 356 357 mii_attach(self, mii, 0xffffffff, BE_PHY_EXTERNAL, 358 MII_OFFSET_ANY, 0); 359 360 child = LIST_FIRST(&mii->mii_phys); 361 if (child == NULL) { 362 /* No PHY attached */ 363 ifmedia_add(&sc->sc_media, 364 IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, instance), 365 0, NULL); 366 ifmedia_set(&sc->sc_media, 367 IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, instance)); 368 } else { 369 /* 370 * Note: we support just one PHY on the external 371 * MII connector. 372 */ 373 #ifdef DIAGNOSTIC 374 if (LIST_NEXT(child, mii_list) != NULL) { 375 aprint_error_dev(self, 376 "spurious MII device %s attached\n", 377 device_xname(child->mii_dev)); 378 } 379 #endif 380 if (child->mii_phy != BE_PHY_EXTERNAL || 381 child->mii_inst > 0) { 382 aprint_error_dev(self, 383 "cannot accommodate MII device %s" 384 " at phy %d, instance %d\n", 385 device_xname(child->mii_dev), 386 child->mii_phy, child->mii_inst); 387 } else { 388 sc->sc_phys[instance] = child->mii_phy; 389 } 390 391 /* 392 * XXX - we can really do the following ONLY if the 393 * phy indeed has the auto negotiation capability!! 394 */ 395 ifmedia_set(&sc->sc_media, 396 IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, instance)); 397 398 /* Mark our current media setting */ 399 be_pal_gate(sc, BE_PHY_EXTERNAL); 400 instance++; 401 } 402 403 } 404 405 if ((v & MGMT_PAL_INT_MDIO) != 0) { 406 /* 407 * The be internal phy looks vaguely like MII hardware, 408 * but not enough to be able to use the MII device 409 * layer. Hence, we have to take care of media selection 410 * ourselves. 411 */ 412 413 sc->sc_mii_inst = instance; 414 sc->sc_phys[instance] = BE_PHY_INTERNAL; 415 416 /* Use `ifm_data' to store BMCR bits */ 417 ifmedia_add(&sc->sc_media, 418 IFM_MAKEWORD(IFM_ETHER, IFM_10_T, 0, instance), 419 0, NULL); 420 ifmedia_add(&sc->sc_media, 421 IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, 0, instance), 422 BMCR_S100, NULL); 423 ifmedia_add(&sc->sc_media, 424 IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, instance), 425 0, NULL); 426 427 printf("on-board transceiver at %s: 10baseT, 100baseTX, auto\n", 428 device_xname(self)); 429 430 be_mii_reset(sc, BE_PHY_INTERNAL); 431 /* Only set default medium here if there's no external PHY */ 432 if (instance == 0) { 433 be_pal_gate(sc, BE_PHY_INTERNAL); 434 ifmedia_set(&sc->sc_media, 435 IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, instance)); 436 } else 437 be_mii_writereg(self, 438 BE_PHY_INTERNAL, MII_BMCR, BMCR_ISO); 439 } 440 441 memcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 442 ifp->if_softc = sc; 443 ifp->if_start = bestart; 444 ifp->if_ioctl = beioctl; 445 ifp->if_watchdog = bewatchdog; 446 ifp->if_init = beinit; 447 ifp->if_stop = bestop; 448 ifp->if_flags = 449 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 450 IFQ_SET_READY(&ifp->if_snd); 451 452 /* claim 802.1q capability */ 453 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 454 455 /* Attach the interface. */ 456 if_attach(ifp); 457 ether_ifattach(ifp, sc->sc_enaddr); 458 } 459 460 461 /* 462 * Routine to copy from mbuf chain to transmit buffer in 463 * network buffer memory. 464 */ 465 static inline int 466 be_put(struct be_softc *sc, int idx, struct mbuf *m) 467 { 468 struct mbuf *n; 469 int len, tlen = 0, boff = 0; 470 uint8_t *bp; 471 472 bp = sc->sc_rb.rb_txbuf + (idx % sc->sc_rb.rb_ntbuf) * BE_PKT_BUF_SZ; 473 474 for (; m; m = n) { 475 len = m->m_len; 476 if (len == 0) { 477 MFREE(m, n); 478 continue; 479 } 480 memcpy(bp + boff, mtod(m, void *), len); 481 boff += len; 482 tlen += len; 483 MFREE(m, n); 484 } 485 return tlen; 486 } 487 488 /* 489 * Pull data off an interface. 490 * Len is the length of data, with local net header stripped. 491 * We copy the data into mbufs. When full cluster sized units are present, 492 * we copy into clusters. 493 */ 494 static inline struct mbuf * 495 be_get(struct be_softc *sc, int idx, int totlen) 496 { 497 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 498 struct mbuf *m; 499 struct mbuf *top, **mp; 500 int len, pad, boff = 0; 501 uint8_t *bp; 502 503 bp = sc->sc_rb.rb_rxbuf + (idx % sc->sc_rb.rb_nrbuf) * BE_PKT_BUF_SZ; 504 505 MGETHDR(m, M_DONTWAIT, MT_DATA); 506 if (m == NULL) 507 return (NULL); 508 m->m_pkthdr.rcvif = ifp; 509 m->m_pkthdr.len = totlen; 510 511 pad = ALIGN(sizeof(struct ether_header)) - sizeof(struct ether_header); 512 m->m_data += pad; 513 len = MHLEN - pad; 514 top = NULL; 515 mp = ⊤ 516 517 while (totlen > 0) { 518 if (top) { 519 MGET(m, M_DONTWAIT, MT_DATA); 520 if (m == NULL) { 521 m_freem(top); 522 return (NULL); 523 } 524 len = MLEN; 525 } 526 if (top && totlen >= MINCLSIZE) { 527 MCLGET(m, M_DONTWAIT); 528 if (m->m_flags & M_EXT) 529 len = MCLBYTES; 530 } 531 m->m_len = len = min(totlen, len); 532 memcpy(mtod(m, void *), bp + boff, len); 533 boff += len; 534 totlen -= len; 535 *mp = m; 536 mp = &m->m_next; 537 } 538 539 return top; 540 } 541 542 /* 543 * Pass a packet to the higher levels. 544 */ 545 static inline void 546 be_read(struct be_softc *sc, int idx, int len) 547 { 548 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 549 struct mbuf *m; 550 551 if (len <= sizeof(struct ether_header) || 552 len > ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN) { 553 #ifdef BEDEBUG 554 if (sc->sc_debug) 555 printf("%s: invalid packet size %d; dropping\n", 556 ifp->if_xname, len); 557 #endif 558 ifp->if_ierrors++; 559 return; 560 } 561 562 /* 563 * Pull packet off interface. 564 */ 565 m = be_get(sc, idx, len); 566 if (m == NULL) { 567 ifp->if_ierrors++; 568 return; 569 } 570 ifp->if_ipackets++; 571 572 /* 573 * Check if there's a BPF listener on this interface. 574 * If so, hand off the raw packet to BPF. 575 */ 576 bpf_mtap(ifp, m); 577 /* Pass the packet up. */ 578 (*ifp->if_input)(ifp, m); 579 } 580 581 /* 582 * Start output on interface. 583 * We make two assumptions here: 584 * 1) that the current priority is set to splnet _before_ this code 585 * is called *and* is returned to the appropriate priority after 586 * return 587 * 2) that the IFF_OACTIVE flag is checked before this code is called 588 * (i.e. that the output part of the interface is idle) 589 */ 590 void 591 bestart(struct ifnet *ifp) 592 { 593 struct be_softc *sc = ifp->if_softc; 594 struct qec_xd *txd = sc->sc_rb.rb_txd; 595 struct mbuf *m; 596 unsigned int bix, len; 597 unsigned int ntbuf = sc->sc_rb.rb_ntbuf; 598 599 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 600 return; 601 602 bix = sc->sc_rb.rb_tdhead; 603 604 for (;;) { 605 IFQ_DEQUEUE(&ifp->if_snd, m); 606 if (m == 0) 607 break; 608 609 /* 610 * If BPF is listening on this interface, let it see the 611 * packet before we commit it to the wire. 612 */ 613 bpf_mtap(ifp, m); 614 615 /* 616 * Copy the mbuf chain into the transmit buffer. 617 */ 618 len = be_put(sc, bix, m); 619 620 /* 621 * Initialize transmit registers and start transmission 622 */ 623 txd[bix].xd_flags = QEC_XD_OWN | QEC_XD_SOP | QEC_XD_EOP | 624 (len & QEC_XD_LENGTH); 625 bus_space_write_4(sc->sc_bustag, sc->sc_cr, 626 BE_CRI_CTRL, BE_CR_CTRL_TWAKEUP); 627 628 if (++bix == QEC_XD_RING_MAXSIZE) 629 bix = 0; 630 631 if (++sc->sc_rb.rb_td_nbusy == ntbuf) { 632 ifp->if_flags |= IFF_OACTIVE; 633 break; 634 } 635 } 636 637 sc->sc_rb.rb_tdhead = bix; 638 } 639 640 void 641 bestop(struct ifnet *ifp, int disable) 642 { 643 struct be_softc *sc = ifp->if_softc; 644 645 callout_stop(&sc->sc_tick_ch); 646 647 /* Down the MII. */ 648 mii_down(&sc->sc_mii); 649 (void)be_intphy_service(sc, &sc->sc_mii, MII_DOWN); 650 651 behwreset(sc); 652 } 653 654 void 655 behwreset(struct be_softc *sc) 656 { 657 int n; 658 bus_space_tag_t t = sc->sc_bustag; 659 bus_space_handle_t br = sc->sc_br; 660 661 /* Stop the transmitter */ 662 bus_space_write_4(t, br, BE_BRI_TXCFG, 0); 663 for (n = 32; n > 0; n--) { 664 if (bus_space_read_4(t, br, BE_BRI_TXCFG) == 0) 665 break; 666 DELAY(20); 667 } 668 669 /* Stop the receiver */ 670 bus_space_write_4(t, br, BE_BRI_RXCFG, 0); 671 for (n = 32; n > 0; n--) { 672 if (bus_space_read_4(t, br, BE_BRI_RXCFG) == 0) 673 break; 674 DELAY(20); 675 } 676 } 677 678 /* 679 * Reset interface. 680 */ 681 void 682 bereset(struct be_softc *sc) 683 { 684 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 685 int s; 686 687 s = splnet(); 688 behwreset(sc); 689 if ((sc->sc_ethercom.ec_if.if_flags & IFF_UP) != 0) 690 beinit(ifp); 691 splx(s); 692 } 693 694 void 695 bewatchdog(struct ifnet *ifp) 696 { 697 struct be_softc *sc = ifp->if_softc; 698 699 log(LOG_ERR, "%s: device timeout\n", device_xname(sc->sc_dev)); 700 ++sc->sc_ethercom.ec_if.if_oerrors; 701 702 bereset(sc); 703 } 704 705 int 706 beintr(void *arg) 707 { 708 struct be_softc *sc = arg; 709 bus_space_tag_t t = sc->sc_bustag; 710 uint32_t whyq, whyb, whyc; 711 int r = 0; 712 713 /* Read QEC status, channel status and BE status */ 714 whyq = bus_space_read_4(t, sc->sc_qr, QEC_QRI_STAT); 715 whyc = bus_space_read_4(t, sc->sc_cr, BE_CRI_STAT); 716 whyb = bus_space_read_4(t, sc->sc_br, BE_BRI_STAT); 717 718 if (whyq & QEC_STAT_BM) 719 r |= beeint(sc, whyb); 720 721 if (whyq & QEC_STAT_ER) 722 r |= beqint(sc, whyc); 723 724 if (whyq & QEC_STAT_TX && whyc & BE_CR_STAT_TXIRQ) 725 r |= betint(sc); 726 727 if (whyq & QEC_STAT_RX && whyc & BE_CR_STAT_RXIRQ) 728 r |= berint(sc); 729 730 return r; 731 } 732 733 /* 734 * QEC Interrupt. 735 */ 736 int 737 beqint(struct be_softc *sc, uint32_t why) 738 { 739 device_t self = sc->sc_dev; 740 int r = 0, rst = 0; 741 742 if (why & BE_CR_STAT_TXIRQ) 743 r |= 1; 744 if (why & BE_CR_STAT_RXIRQ) 745 r |= 1; 746 747 if (why & BE_CR_STAT_BERROR) { 748 r |= 1; 749 rst = 1; 750 aprint_error_dev(self, "bigmac error\n"); 751 } 752 753 if (why & BE_CR_STAT_TXDERR) { 754 r |= 1; 755 rst = 1; 756 aprint_error_dev(self, "bogus tx descriptor\n"); 757 } 758 759 if (why & (BE_CR_STAT_TXLERR | BE_CR_STAT_TXPERR | BE_CR_STAT_TXSERR)) { 760 r |= 1; 761 rst = 1; 762 aprint_error_dev(self, "tx DMA error ( "); 763 if (why & BE_CR_STAT_TXLERR) 764 printf("Late "); 765 if (why & BE_CR_STAT_TXPERR) 766 printf("Parity "); 767 if (why & BE_CR_STAT_TXSERR) 768 printf("Generic "); 769 printf(")\n"); 770 } 771 772 if (why & BE_CR_STAT_RXDROP) { 773 r |= 1; 774 rst = 1; 775 aprint_error_dev(self, "out of rx descriptors\n"); 776 } 777 778 if (why & BE_CR_STAT_RXSMALL) { 779 r |= 1; 780 rst = 1; 781 aprint_error_dev(self, "rx descriptor too small\n"); 782 } 783 784 if (why & (BE_CR_STAT_RXLERR | BE_CR_STAT_RXPERR | BE_CR_STAT_RXSERR)) { 785 r |= 1; 786 rst = 1; 787 aprint_error_dev(self, "rx DMA error ( "); 788 if (why & BE_CR_STAT_RXLERR) 789 printf("Late "); 790 if (why & BE_CR_STAT_RXPERR) 791 printf("Parity "); 792 if (why & BE_CR_STAT_RXSERR) 793 printf("Generic "); 794 printf(")\n"); 795 } 796 797 if (!r) { 798 rst = 1; 799 aprint_error_dev(self, "unexpected error interrupt %08x\n", 800 why); 801 } 802 803 if (rst) { 804 printf("%s: resetting\n", device_xname(self)); 805 bereset(sc); 806 } 807 808 return r; 809 } 810 811 /* 812 * Error interrupt. 813 */ 814 int 815 beeint(struct be_softc *sc, uint32_t why) 816 { 817 device_t self = sc->sc_dev; 818 int r = 0, rst = 0; 819 820 if (why & BE_BR_STAT_RFIFOVF) { 821 r |= 1; 822 rst = 1; 823 aprint_error_dev(self, "receive fifo overrun\n"); 824 } 825 if (why & BE_BR_STAT_TFIFO_UND) { 826 r |= 1; 827 rst = 1; 828 aprint_error_dev(self, "transmit fifo underrun\n"); 829 } 830 if (why & BE_BR_STAT_MAXPKTERR) { 831 r |= 1; 832 rst = 1; 833 aprint_error_dev(self, "max packet size error\n"); 834 } 835 836 if (!r) { 837 rst = 1; 838 aprint_error_dev(self, "unexpected error interrupt %08x\n", 839 why); 840 } 841 842 if (rst) { 843 printf("%s: resetting\n", device_xname(self)); 844 bereset(sc); 845 } 846 847 return r; 848 } 849 850 /* 851 * Transmit interrupt. 852 */ 853 int 854 betint(struct be_softc *sc) 855 { 856 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 857 bus_space_tag_t t = sc->sc_bustag; 858 bus_space_handle_t br = sc->sc_br; 859 unsigned int bix, txflags; 860 861 /* 862 * Unload collision counters 863 */ 864 ifp->if_collisions += 865 bus_space_read_4(t, br, BE_BRI_NCCNT) + 866 bus_space_read_4(t, br, BE_BRI_FCCNT) + 867 bus_space_read_4(t, br, BE_BRI_EXCNT) + 868 bus_space_read_4(t, br, BE_BRI_LTCNT); 869 870 /* 871 * the clear the hardware counters 872 */ 873 bus_space_write_4(t, br, BE_BRI_NCCNT, 0); 874 bus_space_write_4(t, br, BE_BRI_FCCNT, 0); 875 bus_space_write_4(t, br, BE_BRI_EXCNT, 0); 876 bus_space_write_4(t, br, BE_BRI_LTCNT, 0); 877 878 bix = sc->sc_rb.rb_tdtail; 879 880 for (;;) { 881 if (sc->sc_rb.rb_td_nbusy <= 0) 882 break; 883 884 txflags = sc->sc_rb.rb_txd[bix].xd_flags; 885 886 if (txflags & QEC_XD_OWN) 887 break; 888 889 ifp->if_flags &= ~IFF_OACTIVE; 890 ifp->if_opackets++; 891 892 if (++bix == QEC_XD_RING_MAXSIZE) 893 bix = 0; 894 895 --sc->sc_rb.rb_td_nbusy; 896 } 897 898 sc->sc_rb.rb_tdtail = bix; 899 900 bestart(ifp); 901 902 if (sc->sc_rb.rb_td_nbusy == 0) 903 ifp->if_timer = 0; 904 905 return 1; 906 } 907 908 /* 909 * Receive interrupt. 910 */ 911 int 912 berint(struct be_softc *sc) 913 { 914 struct qec_xd *xd = sc->sc_rb.rb_rxd; 915 unsigned int bix, len; 916 unsigned int nrbuf = sc->sc_rb.rb_nrbuf; 917 918 bix = sc->sc_rb.rb_rdtail; 919 920 /* 921 * Process all buffers with valid data. 922 */ 923 for (;;) { 924 len = xd[bix].xd_flags; 925 if (len & QEC_XD_OWN) 926 break; 927 928 len &= QEC_XD_LENGTH; 929 be_read(sc, bix, len); 930 931 /* ... */ 932 xd[(bix+nrbuf) % QEC_XD_RING_MAXSIZE].xd_flags = 933 QEC_XD_OWN | (BE_PKT_BUF_SZ & QEC_XD_LENGTH); 934 935 if (++bix == QEC_XD_RING_MAXSIZE) 936 bix = 0; 937 } 938 939 sc->sc_rb.rb_rdtail = bix; 940 941 return 1; 942 } 943 944 int 945 beioctl(struct ifnet *ifp, u_long cmd, void *data) 946 { 947 struct be_softc *sc = ifp->if_softc; 948 struct ifaddr *ifa = data; 949 struct ifreq *ifr = data; 950 int s, error = 0; 951 952 s = splnet(); 953 954 switch (cmd) { 955 case SIOCINITIFADDR: 956 ifp->if_flags |= IFF_UP; 957 beinit(ifp); 958 switch (ifa->ifa_addr->sa_family) { 959 #ifdef INET 960 case AF_INET: 961 arp_ifinit(ifp, ifa); 962 break; 963 #endif /* INET */ 964 default: 965 break; 966 } 967 break; 968 969 case SIOCSIFFLAGS: 970 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 971 break; 972 /* XXX re-use ether_ioctl() */ 973 switch (ifp->if_flags & (IFF_UP|IFF_RUNNING)) { 974 case IFF_RUNNING: 975 /* 976 * If interface is marked down and it is running, then 977 * stop it. 978 */ 979 bestop(ifp, 0); 980 ifp->if_flags &= ~IFF_RUNNING; 981 break; 982 case IFF_UP: 983 /* 984 * If interface is marked up and it is stopped, then 985 * start it. 986 */ 987 beinit(ifp); 988 break; 989 default: 990 /* 991 * Reset the interface to pick up changes in any other 992 * flags that affect hardware registers. 993 */ 994 bestop(ifp, 0); 995 beinit(ifp); 996 break; 997 } 998 #ifdef BEDEBUG 999 if (ifp->if_flags & IFF_DEBUG) 1000 sc->sc_debug = 1; 1001 else 1002 sc->sc_debug = 0; 1003 #endif 1004 break; 1005 1006 case SIOCGIFMEDIA: 1007 case SIOCSIFMEDIA: 1008 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd); 1009 break; 1010 default: 1011 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 1012 /* 1013 * Multicast list has changed; set the hardware filter 1014 * accordingly. 1015 */ 1016 if (ifp->if_flags & IFF_RUNNING) 1017 error = beinit(ifp); 1018 else 1019 error = 0; 1020 } 1021 break; 1022 } 1023 splx(s); 1024 return error; 1025 } 1026 1027 1028 int 1029 beinit(struct ifnet *ifp) 1030 { 1031 struct be_softc *sc = ifp->if_softc; 1032 bus_space_tag_t t = sc->sc_bustag; 1033 bus_space_handle_t br = sc->sc_br; 1034 bus_space_handle_t cr = sc->sc_cr; 1035 struct qec_softc *qec = sc->sc_qec; 1036 uint32_t v; 1037 uint32_t qecaddr; 1038 uint8_t *ea; 1039 int rc, s; 1040 1041 s = splnet(); 1042 1043 qec_meminit(&sc->sc_rb, BE_PKT_BUF_SZ); 1044 1045 bestop(ifp, 1); 1046 1047 ea = sc->sc_enaddr; 1048 bus_space_write_4(t, br, BE_BRI_MACADDR0, (ea[0] << 8) | ea[1]); 1049 bus_space_write_4(t, br, BE_BRI_MACADDR1, (ea[2] << 8) | ea[3]); 1050 bus_space_write_4(t, br, BE_BRI_MACADDR2, (ea[4] << 8) | ea[5]); 1051 1052 /* Clear hash table */ 1053 bus_space_write_4(t, br, BE_BRI_HASHTAB0, 0); 1054 bus_space_write_4(t, br, BE_BRI_HASHTAB1, 0); 1055 bus_space_write_4(t, br, BE_BRI_HASHTAB2, 0); 1056 bus_space_write_4(t, br, BE_BRI_HASHTAB3, 0); 1057 1058 /* Re-initialize RX configuration */ 1059 v = BE_BR_RXCFG_FIFO; 1060 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1061 1062 be_mcreset(sc); 1063 1064 bus_space_write_4(t, br, BE_BRI_RANDSEED, 0xbd); 1065 1066 bus_space_write_4(t, br, 1067 BE_BRI_XIFCFG, BE_BR_XCFG_ODENABLE | BE_BR_XCFG_RESV); 1068 1069 bus_space_write_4(t, br, BE_BRI_JSIZE, 4); 1070 1071 /* 1072 * Turn off counter expiration interrupts as well as 1073 * 'gotframe' and 'sentframe' 1074 */ 1075 bus_space_write_4(t, br, BE_BRI_IMASK, 1076 BE_BR_IMASK_GOTFRAME | 1077 BE_BR_IMASK_RCNTEXP | 1078 BE_BR_IMASK_ACNTEXP | 1079 BE_BR_IMASK_CCNTEXP | 1080 BE_BR_IMASK_LCNTEXP | 1081 BE_BR_IMASK_CVCNTEXP | 1082 BE_BR_IMASK_SENTFRAME | 1083 BE_BR_IMASK_NCNTEXP | 1084 BE_BR_IMASK_ECNTEXP | 1085 BE_BR_IMASK_LCCNTEXP | 1086 BE_BR_IMASK_FCNTEXP | 1087 BE_BR_IMASK_DTIMEXP); 1088 1089 /* Channel registers: */ 1090 bus_space_write_4(t, cr, BE_CRI_RXDS, (uint32_t)sc->sc_rb.rb_rxddma); 1091 bus_space_write_4(t, cr, BE_CRI_TXDS, (uint32_t)sc->sc_rb.rb_txddma); 1092 1093 qecaddr = sc->sc_channel * qec->sc_msize; 1094 bus_space_write_4(t, cr, BE_CRI_RXWBUF, qecaddr); 1095 bus_space_write_4(t, cr, BE_CRI_RXRBUF, qecaddr); 1096 bus_space_write_4(t, cr, BE_CRI_TXWBUF, qecaddr + qec->sc_rsize); 1097 bus_space_write_4(t, cr, BE_CRI_TXRBUF, qecaddr + qec->sc_rsize); 1098 1099 bus_space_write_4(t, cr, BE_CRI_RIMASK, 0); 1100 bus_space_write_4(t, cr, BE_CRI_TIMASK, 0); 1101 bus_space_write_4(t, cr, BE_CRI_QMASK, 0); 1102 bus_space_write_4(t, cr, BE_CRI_BMASK, 0); 1103 bus_space_write_4(t, cr, BE_CRI_CCNT, 0); 1104 1105 /* Set max packet length */ 1106 v = ETHER_MAX_LEN; 1107 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) 1108 v += ETHER_VLAN_ENCAP_LEN; 1109 bus_space_write_4(t, br, BE_BRI_RXMAX, v); 1110 bus_space_write_4(t, br, BE_BRI_TXMAX, v); 1111 1112 /* Enable transmitter */ 1113 bus_space_write_4(t, br, 1114 BE_BRI_TXCFG, BE_BR_TXCFG_FIFO | BE_BR_TXCFG_ENABLE); 1115 1116 /* Enable receiver */ 1117 v = bus_space_read_4(t, br, BE_BRI_RXCFG); 1118 v |= BE_BR_RXCFG_FIFO | BE_BR_RXCFG_ENABLE; 1119 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1120 1121 if ((rc = be_ifmedia_upd(ifp)) != 0) 1122 goto out; 1123 1124 ifp->if_flags |= IFF_RUNNING; 1125 ifp->if_flags &= ~IFF_OACTIVE; 1126 1127 callout_reset(&sc->sc_tick_ch, hz, be_tick, sc); 1128 1129 splx(s); 1130 return 0; 1131 out: 1132 splx(s); 1133 return rc; 1134 } 1135 1136 void 1137 be_mcreset(struct be_softc *sc) 1138 { 1139 struct ethercom *ec = &sc->sc_ethercom; 1140 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1141 bus_space_tag_t t = sc->sc_bustag; 1142 bus_space_handle_t br = sc->sc_br; 1143 uint32_t v; 1144 uint32_t crc; 1145 uint16_t hash[4]; 1146 struct ether_multi *enm; 1147 struct ether_multistep step; 1148 1149 if (ifp->if_flags & IFF_PROMISC) { 1150 v = bus_space_read_4(t, br, BE_BRI_RXCFG); 1151 v |= BE_BR_RXCFG_PMISC; 1152 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1153 return; 1154 } 1155 1156 if (ifp->if_flags & IFF_ALLMULTI) { 1157 hash[3] = hash[2] = hash[1] = hash[0] = 0xffff; 1158 goto chipit; 1159 } 1160 1161 hash[3] = hash[2] = hash[1] = hash[0] = 0; 1162 1163 ETHER_FIRST_MULTI(step, ec, enm); 1164 while (enm != NULL) { 1165 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1166 /* 1167 * We must listen to a range of multicast 1168 * addresses. For now, just accept all 1169 * multicasts, rather than trying to set only 1170 * those filter bits needed to match the range. 1171 * (At this time, the only use of address 1172 * ranges is for IP multicast routing, for 1173 * which the range is big enough to require 1174 * all bits set.) 1175 */ 1176 hash[3] = hash[2] = hash[1] = hash[0] = 0xffff; 1177 ifp->if_flags |= IFF_ALLMULTI; 1178 goto chipit; 1179 } 1180 1181 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 1182 /* Just want the 6 most significant bits. */ 1183 crc >>= 26; 1184 1185 hash[crc >> 4] |= 1 << (crc & 0xf); 1186 ETHER_NEXT_MULTI(step, enm); 1187 } 1188 1189 ifp->if_flags &= ~IFF_ALLMULTI; 1190 1191 chipit: 1192 /* Enable the hash filter */ 1193 bus_space_write_4(t, br, BE_BRI_HASHTAB0, hash[0]); 1194 bus_space_write_4(t, br, BE_BRI_HASHTAB1, hash[1]); 1195 bus_space_write_4(t, br, BE_BRI_HASHTAB2, hash[2]); 1196 bus_space_write_4(t, br, BE_BRI_HASHTAB3, hash[3]); 1197 1198 v = bus_space_read_4(t, br, BE_BRI_RXCFG); 1199 v &= ~BE_BR_RXCFG_PMISC; 1200 v |= BE_BR_RXCFG_HENABLE; 1201 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1202 } 1203 1204 /* 1205 * Set the tcvr to an idle state 1206 */ 1207 void 1208 be_mii_sync(struct be_softc *sc) 1209 { 1210 bus_space_tag_t t = sc->sc_bustag; 1211 bus_space_handle_t tr = sc->sc_tr; 1212 int n = 32; 1213 1214 while (n--) { 1215 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, 1216 MGMT_PAL_INT_MDIO | MGMT_PAL_EXT_MDIO | MGMT_PAL_OENAB); 1217 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1218 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, 1219 MGMT_PAL_INT_MDIO | MGMT_PAL_EXT_MDIO | 1220 MGMT_PAL_OENAB | MGMT_PAL_DCLOCK); 1221 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1222 } 1223 } 1224 1225 void 1226 be_pal_gate(struct be_softc *sc, int phy) 1227 { 1228 bus_space_tag_t t = sc->sc_bustag; 1229 bus_space_handle_t tr = sc->sc_tr; 1230 uint32_t v; 1231 1232 be_mii_sync(sc); 1233 1234 v = ~(TCVR_PAL_EXTLBACK | TCVR_PAL_MSENSE | TCVR_PAL_LTENABLE); 1235 if (phy == BE_PHY_INTERNAL) 1236 v &= ~TCVR_PAL_SERIAL; 1237 1238 bus_space_write_4(t, tr, BE_TRI_TCVRPAL, v); 1239 (void)bus_space_read_4(t, tr, BE_TRI_TCVRPAL); 1240 } 1241 1242 static int 1243 be_tcvr_read_bit(struct be_softc *sc, int phy) 1244 { 1245 bus_space_tag_t t = sc->sc_bustag; 1246 bus_space_handle_t tr = sc->sc_tr; 1247 int ret; 1248 1249 if (phy == BE_PHY_INTERNAL) { 1250 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, MGMT_PAL_EXT_MDIO); 1251 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1252 bus_space_write_4(t, tr, 1253 BE_TRI_MGMTPAL, MGMT_PAL_EXT_MDIO | MGMT_PAL_DCLOCK); 1254 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1255 ret = (bus_space_read_4(t, tr, BE_TRI_MGMTPAL) & 1256 MGMT_PAL_INT_MDIO) >> MGMT_PAL_INT_MDIO_SHIFT; 1257 } else { 1258 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, MGMT_PAL_INT_MDIO); 1259 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1260 ret = (bus_space_read_4(t, tr, BE_TRI_MGMTPAL) & 1261 MGMT_PAL_EXT_MDIO) >> MGMT_PAL_EXT_MDIO_SHIFT; 1262 bus_space_write_4(t, tr, 1263 BE_TRI_MGMTPAL, MGMT_PAL_INT_MDIO | MGMT_PAL_DCLOCK); 1264 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1265 } 1266 1267 return ret; 1268 } 1269 1270 static void 1271 be_tcvr_write_bit(struct be_softc *sc, int phy, int bit) 1272 { 1273 bus_space_tag_t t = sc->sc_bustag; 1274 bus_space_handle_t tr = sc->sc_tr; 1275 uint32_t v; 1276 1277 if (phy == BE_PHY_INTERNAL) { 1278 v = ((bit & 1) << MGMT_PAL_INT_MDIO_SHIFT) | 1279 MGMT_PAL_OENAB | MGMT_PAL_EXT_MDIO; 1280 } else { 1281 v = ((bit & 1) << MGMT_PAL_EXT_MDIO_SHIFT) | 1282 MGMT_PAL_OENAB | MGMT_PAL_INT_MDIO; 1283 } 1284 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, v); 1285 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1286 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, v | MGMT_PAL_DCLOCK); 1287 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1288 } 1289 1290 static void 1291 be_mii_sendbits(struct be_softc *sc, int phy, uint32_t data, int nbits) 1292 { 1293 int i; 1294 1295 for (i = 1 << (nbits - 1); i != 0; i >>= 1) { 1296 be_tcvr_write_bit(sc, phy, (data & i) != 0); 1297 } 1298 } 1299 1300 static int 1301 be_mii_readreg(device_t self, int phy, int reg) 1302 { 1303 struct be_softc *sc = device_private(self); 1304 int val = 0, i; 1305 1306 /* 1307 * Read the PHY register by manually driving the MII control lines. 1308 */ 1309 be_mii_sync(sc); 1310 be_mii_sendbits(sc, phy, MII_COMMAND_START, 2); 1311 be_mii_sendbits(sc, phy, MII_COMMAND_READ, 2); 1312 be_mii_sendbits(sc, phy, phy, 5); 1313 be_mii_sendbits(sc, phy, reg, 5); 1314 1315 (void)be_tcvr_read_bit(sc, phy); 1316 (void)be_tcvr_read_bit(sc, phy); 1317 1318 for (i = 15; i >= 0; i--) 1319 val |= (be_tcvr_read_bit(sc, phy) << i); 1320 1321 (void)be_tcvr_read_bit(sc, phy); 1322 (void)be_tcvr_read_bit(sc, phy); 1323 (void)be_tcvr_read_bit(sc, phy); 1324 1325 return val; 1326 } 1327 1328 void 1329 be_mii_writereg(device_t self, int phy, int reg, int val) 1330 { 1331 struct be_softc *sc = device_private(self); 1332 int i; 1333 1334 /* 1335 * Write the PHY register by manually driving the MII control lines. 1336 */ 1337 be_mii_sync(sc); 1338 be_mii_sendbits(sc, phy, MII_COMMAND_START, 2); 1339 be_mii_sendbits(sc, phy, MII_COMMAND_WRITE, 2); 1340 be_mii_sendbits(sc, phy, phy, 5); 1341 be_mii_sendbits(sc, phy, reg, 5); 1342 1343 be_tcvr_write_bit(sc, phy, 1); 1344 be_tcvr_write_bit(sc, phy, 0); 1345 1346 for (i = 15; i >= 0; i--) 1347 be_tcvr_write_bit(sc, phy, (val >> i) & 1); 1348 } 1349 1350 int 1351 be_mii_reset(struct be_softc *sc, int phy) 1352 { 1353 device_t self = sc->sc_dev; 1354 int n; 1355 1356 be_mii_writereg(self, phy, MII_BMCR, BMCR_LOOP | BMCR_PDOWN | BMCR_ISO); 1357 be_mii_writereg(self, phy, MII_BMCR, BMCR_RESET); 1358 1359 for (n = 16; n >= 0; n--) { 1360 int bmcr = be_mii_readreg(self, phy, MII_BMCR); 1361 if ((bmcr & BMCR_RESET) == 0) 1362 break; 1363 DELAY(20); 1364 } 1365 if (n == 0) { 1366 aprint_error_dev(self, "bmcr reset failed\n"); 1367 return EIO; 1368 } 1369 1370 return 0; 1371 } 1372 1373 void 1374 be_tick(void *arg) 1375 { 1376 struct be_softc *sc = arg; 1377 int s = splnet(); 1378 1379 mii_tick(&sc->sc_mii); 1380 (void)be_intphy_service(sc, &sc->sc_mii, MII_TICK); 1381 1382 splx(s); 1383 callout_reset(&sc->sc_tick_ch, hz, be_tick, sc); 1384 } 1385 1386 void 1387 be_mii_statchg(struct ifnet *ifp) 1388 { 1389 struct be_softc *sc = ifp->if_softc; 1390 bus_space_tag_t t = sc->sc_bustag; 1391 bus_space_handle_t br = sc->sc_br; 1392 uint instance; 1393 uint32_t v; 1394 1395 instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media); 1396 #ifdef DIAGNOSTIC 1397 if (instance > 1) 1398 panic("be_mii_statchg: instance %d out of range", instance); 1399 #endif 1400 1401 /* Update duplex mode in TX configuration */ 1402 v = bus_space_read_4(t, br, BE_BRI_TXCFG); 1403 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 1404 v |= BE_BR_TXCFG_FULLDPLX; 1405 else 1406 v &= ~BE_BR_TXCFG_FULLDPLX; 1407 bus_space_write_4(t, br, BE_BRI_TXCFG, v); 1408 1409 /* Change to appropriate gate in transceiver PAL */ 1410 be_pal_gate(sc, sc->sc_phys[instance]); 1411 } 1412 1413 /* 1414 * Get current media settings. 1415 */ 1416 void 1417 be_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1418 { 1419 struct be_softc *sc = ifp->if_softc; 1420 1421 mii_pollstat(&sc->sc_mii); 1422 (void)be_intphy_service(sc, &sc->sc_mii, MII_POLLSTAT); 1423 1424 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1425 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1426 } 1427 1428 /* 1429 * Set media options. 1430 */ 1431 int 1432 be_ifmedia_upd(struct ifnet *ifp) 1433 { 1434 struct be_softc *sc = ifp->if_softc; 1435 int error; 1436 1437 if ((error = mii_mediachg(&sc->sc_mii)) == ENXIO) 1438 error = 0; 1439 else if (error != 0) 1440 return error; 1441 1442 return be_intphy_service(sc, &sc->sc_mii, MII_MEDIACHG); 1443 } 1444 1445 /* 1446 * Service routine for our pseudo-MII internal transceiver. 1447 */ 1448 int 1449 be_intphy_service(struct be_softc *sc, struct mii_data *mii, int cmd) 1450 { 1451 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 1452 device_t self = sc->sc_dev; 1453 int bmcr, bmsr; 1454 int error; 1455 1456 switch (cmd) { 1457 case MII_POLLSTAT: 1458 /* 1459 * If we're not polling our PHY instance, just return. 1460 */ 1461 if (IFM_INST(ife->ifm_media) != sc->sc_mii_inst) 1462 return 0; 1463 1464 break; 1465 1466 case MII_MEDIACHG: 1467 1468 /* 1469 * If the media indicates a different PHY instance, 1470 * isolate ourselves. 1471 */ 1472 if (IFM_INST(ife->ifm_media) != sc->sc_mii_inst) { 1473 bmcr = be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMCR); 1474 be_mii_writereg(self, 1475 BE_PHY_INTERNAL, MII_BMCR, bmcr | BMCR_ISO); 1476 sc->sc_mii_flags &= ~MIIF_HAVELINK; 1477 sc->sc_intphy_curspeed = 0; 1478 return 0; 1479 } 1480 1481 1482 if ((error = be_mii_reset(sc, BE_PHY_INTERNAL)) != 0) 1483 return error; 1484 1485 bmcr = be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMCR); 1486 1487 /* 1488 * Select the new mode and take out of isolation 1489 */ 1490 if (IFM_SUBTYPE(ife->ifm_media) == IFM_100_TX) 1491 bmcr |= BMCR_S100; 1492 else if (IFM_SUBTYPE(ife->ifm_media) == IFM_10_T) 1493 bmcr &= ~BMCR_S100; 1494 else if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) { 1495 if ((sc->sc_mii_flags & MIIF_HAVELINK) != 0) { 1496 bmcr &= ~BMCR_S100; 1497 bmcr |= sc->sc_intphy_curspeed; 1498 } else { 1499 /* Keep isolated until link is up */ 1500 bmcr |= BMCR_ISO; 1501 sc->sc_mii_flags |= MIIF_DOINGAUTO; 1502 } 1503 } 1504 1505 if ((IFM_OPTIONS(ife->ifm_media) & IFM_FDX) != 0) 1506 bmcr |= BMCR_FDX; 1507 else 1508 bmcr &= ~BMCR_FDX; 1509 1510 be_mii_writereg(self, BE_PHY_INTERNAL, MII_BMCR, bmcr); 1511 break; 1512 1513 case MII_TICK: 1514 /* 1515 * If we're not currently selected, just return. 1516 */ 1517 if (IFM_INST(ife->ifm_media) != sc->sc_mii_inst) 1518 return 0; 1519 1520 /* Is the interface even up? */ 1521 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 1522 return 0; 1523 1524 /* Only used for automatic media selection */ 1525 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) 1526 break; 1527 1528 /* 1529 * Check link status; if we don't have a link, try another 1530 * speed. We can't detect duplex mode, so half-duplex is 1531 * what we have to settle for. 1532 */ 1533 1534 /* Read twice in case the register is latched */ 1535 bmsr = 1536 be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMSR) | 1537 be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMSR); 1538 1539 if ((bmsr & BMSR_LINK) != 0) { 1540 /* We have a carrier */ 1541 bmcr = be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMCR); 1542 1543 if ((sc->sc_mii_flags & MIIF_DOINGAUTO) != 0) { 1544 bmcr = be_mii_readreg(self, 1545 BE_PHY_INTERNAL, MII_BMCR); 1546 1547 sc->sc_mii_flags |= MIIF_HAVELINK; 1548 sc->sc_intphy_curspeed = (bmcr & BMCR_S100); 1549 sc->sc_mii_flags &= ~MIIF_DOINGAUTO; 1550 1551 bmcr &= ~BMCR_ISO; 1552 be_mii_writereg(self, 1553 BE_PHY_INTERNAL, MII_BMCR, bmcr); 1554 1555 printf("%s: link up at %s Mbps\n", 1556 device_xname(self), 1557 (bmcr & BMCR_S100) ? "100" : "10"); 1558 } 1559 break; 1560 } 1561 1562 if ((sc->sc_mii_flags & MIIF_DOINGAUTO) == 0) { 1563 sc->sc_mii_flags |= MIIF_DOINGAUTO; 1564 sc->sc_mii_flags &= ~MIIF_HAVELINK; 1565 sc->sc_intphy_curspeed = 0; 1566 printf("%s: link down\n", device_xname(self)); 1567 } 1568 1569 /* Only retry autonegotiation every 5 seconds. */ 1570 if (++sc->sc_mii_ticks < 5) 1571 return 0; 1572 1573 sc->sc_mii_ticks = 0; 1574 bmcr = be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMCR); 1575 /* Just flip the fast speed bit */ 1576 bmcr ^= BMCR_S100; 1577 be_mii_writereg(self, BE_PHY_INTERNAL, MII_BMCR, bmcr); 1578 1579 break; 1580 1581 case MII_DOWN: 1582 /* Isolate this phy */ 1583 bmcr = be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMCR); 1584 be_mii_writereg(self, 1585 BE_PHY_INTERNAL, MII_BMCR, bmcr | BMCR_ISO); 1586 return 0; 1587 } 1588 1589 /* Update the media status. */ 1590 be_intphy_status(sc); 1591 1592 /* Callback if something changed. */ 1593 if (sc->sc_mii_active != mii->mii_media_active || cmd == MII_MEDIACHG) { 1594 (*mii->mii_statchg)(mii->mii_ifp); 1595 sc->sc_mii_active = mii->mii_media_active; 1596 } 1597 return 0; 1598 } 1599 1600 /* 1601 * Determine status of internal transceiver 1602 */ 1603 void 1604 be_intphy_status(struct be_softc *sc) 1605 { 1606 struct mii_data *mii = &sc->sc_mii; 1607 device_t self = sc->sc_dev; 1608 int media_active, media_status; 1609 int bmcr, bmsr; 1610 1611 media_status = IFM_AVALID; 1612 media_active = 0; 1613 1614 /* 1615 * Internal transceiver; do the work here. 1616 */ 1617 bmcr = be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMCR); 1618 1619 switch (bmcr & (BMCR_S100 | BMCR_FDX)) { 1620 case (BMCR_S100 | BMCR_FDX): 1621 media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 1622 break; 1623 case BMCR_S100: 1624 media_active = IFM_ETHER | IFM_100_TX | IFM_HDX; 1625 break; 1626 case BMCR_FDX: 1627 media_active = IFM_ETHER | IFM_10_T | IFM_FDX; 1628 break; 1629 case 0: 1630 media_active = IFM_ETHER | IFM_10_T | IFM_HDX; 1631 break; 1632 } 1633 1634 /* Read twice in case the register is latched */ 1635 bmsr = 1636 be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMSR) | 1637 be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMSR); 1638 if (bmsr & BMSR_LINK) 1639 media_status |= IFM_ACTIVE; 1640 1641 mii->mii_media_status = media_status; 1642 mii->mii_media_active = media_active; 1643 } 1644
Indexes created Sat Oct 25 16:10:12 GMT 2025