be.c revision 1.82
1 /* $NetBSD: be.c,v 1.82 2016/02/09 08:32:12 ozaki-r Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Copyright (c) 1998 Theo de Raadt and Jason L. Wright. 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. The name of the authors may not be used to endorse or promote products 45 * derived from this software without specific prior written permission. 46 * 47 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR 48 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 49 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 50 * IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, 51 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 52 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 53 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 54 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 55 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 56 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 57 */ 58 59 #include <sys/cdefs.h> 60 __KERNEL_RCSID(0, "$NetBSD: be.c,v 1.82 2016/02/09 08:32:12 ozaki-r Exp $"); 61 62 #include "opt_ddb.h" 63 #include "opt_inet.h" 64 65 #include <sys/param.h> 66 #include <sys/systm.h> 67 #include <sys/callout.h> 68 #include <sys/kernel.h> 69 #include <sys/errno.h> 70 #include <sys/ioctl.h> 71 #include <sys/mbuf.h> 72 #include <sys/socket.h> 73 #include <sys/syslog.h> 74 #include <sys/device.h> 75 #include <sys/malloc.h> 76 77 #include <net/if.h> 78 #include <net/if_dl.h> 79 #include <net/if_types.h> 80 #include <net/netisr.h> 81 #include <net/if_media.h> 82 #include <net/if_ether.h> 83 84 #ifdef INET 85 #include <netinet/in.h> 86 #include <netinet/if_inarp.h> 87 #include <netinet/in_systm.h> 88 #include <netinet/in_var.h> 89 #include <netinet/ip.h> 90 #endif 91 92 93 #include <net/bpf.h> 94 #include <net/bpfdesc.h> 95 96 #include <sys/bus.h> 97 #include <sys/intr.h> 98 #include <machine/autoconf.h> 99 100 #include <dev/sbus/sbusvar.h> 101 102 #include <dev/mii/mii.h> 103 #include <dev/mii/miivar.h> 104 105 #include <dev/sbus/qecreg.h> 106 #include <dev/sbus/qecvar.h> 107 #include <dev/sbus/bereg.h> 108 109 struct be_softc { 110 device_t sc_dev; 111 bus_space_tag_t sc_bustag; /* bus & DMA tags */ 112 bus_dma_tag_t sc_dmatag; 113 bus_dmamap_t sc_dmamap; 114 struct ethercom sc_ethercom; 115 /*struct ifmedia sc_ifmedia; -* interface media */ 116 struct mii_data sc_mii; /* MII media control */ 117 #define sc_media sc_mii.mii_media/* shorthand */ 118 int sc_phys[2]; /* MII instance -> phy */ 119 120 struct callout sc_tick_ch; 121 122 /* 123 * Some `mii_softc' items we need to emulate MII operation 124 * for our internal transceiver. 125 */ 126 int sc_mii_inst; /* instance of internal phy */ 127 int sc_mii_active; /* currently active medium */ 128 int sc_mii_ticks; /* tick counter */ 129 int sc_mii_flags; /* phy status flags */ 130 #define MIIF_HAVELINK 0x04000000 131 int sc_intphy_curspeed; /* Established link speed */ 132 133 struct qec_softc *sc_qec; /* QEC parent */ 134 135 bus_space_handle_t sc_qr; /* QEC registers */ 136 bus_space_handle_t sc_br; /* BE registers */ 137 bus_space_handle_t sc_cr; /* channel registers */ 138 bus_space_handle_t sc_tr; /* transceiver registers */ 139 140 u_int sc_rev; 141 142 int sc_channel; /* channel number */ 143 int sc_burst; 144 145 struct qec_ring sc_rb; /* Packet Ring Buffer */ 146 147 /* MAC address */ 148 uint8_t sc_enaddr[ETHER_ADDR_LEN]; 149 #ifdef BEDEBUG 150 int sc_debug; 151 #endif 152 }; 153 154 static int bematch(device_t, cfdata_t, void *); 155 static void beattach(device_t, device_t, void *); 156 157 static int beinit(struct ifnet *); 158 static void bestart(struct ifnet *); 159 static void bestop(struct ifnet *, int); 160 static void bewatchdog(struct ifnet *); 161 static int beioctl(struct ifnet *, u_long, void *); 162 static void bereset(struct be_softc *); 163 static void behwreset(struct be_softc *); 164 165 static int beintr(void *); 166 static int berint(struct be_softc *); 167 static int betint(struct be_softc *); 168 static int beqint(struct be_softc *, uint32_t); 169 static int beeint(struct be_softc *, uint32_t); 170 171 static void be_read(struct be_softc *, int, int); 172 static int be_put(struct be_softc *, int, struct mbuf *); 173 static struct mbuf *be_get(struct be_softc *, int, int); 174 175 static void be_pal_gate(struct be_softc *, int); 176 177 /* ifmedia callbacks */ 178 static void be_ifmedia_sts(struct ifnet *, struct ifmediareq *); 179 static int be_ifmedia_upd(struct ifnet *); 180 181 static void be_mcreset(struct be_softc *); 182 183 /* MII methods & callbacks */ 184 static int be_mii_readreg(device_t, int, int); 185 static void be_mii_writereg(device_t, int, int, int); 186 static void be_mii_statchg(struct ifnet *); 187 188 /* MII helpers */ 189 static void be_mii_sync(struct be_softc *); 190 static void be_mii_sendbits(struct be_softc *, int, uint32_t, int); 191 static int be_mii_reset(struct be_softc *, int); 192 static int be_tcvr_read_bit(struct be_softc *, int); 193 static void be_tcvr_write_bit(struct be_softc *, int, int); 194 195 static void be_tick(void *); 196 #if 0 197 static void be_intphy_auto(struct be_softc *); 198 #endif 199 static void be_intphy_status(struct be_softc *); 200 static int be_intphy_service(struct be_softc *, struct mii_data *, int); 201 202 203 CFATTACH_DECL_NEW(be, sizeof(struct be_softc), 204 bematch, beattach, NULL, NULL); 205 206 int 207 bematch(device_t parent, cfdata_t cf, void *aux) 208 { 209 struct sbus_attach_args *sa = aux; 210 211 return strcmp(cf->cf_name, sa->sa_name) == 0; 212 } 213 214 void 215 beattach(device_t parent, device_t self, void *aux) 216 { 217 struct sbus_attach_args *sa = aux; 218 struct qec_softc *qec = device_private(parent); 219 struct be_softc *sc = device_private(self); 220 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 221 struct mii_data *mii = &sc->sc_mii; 222 struct mii_softc *child; 223 int node = sa->sa_node; 224 bus_dma_tag_t dmatag = sa->sa_dmatag; 225 bus_dma_segment_t seg; 226 bus_size_t size; 227 int instance; 228 int rseg, error; 229 uint32_t v; 230 231 sc->sc_dev = self; 232 233 if (sa->sa_nreg < 3) { 234 printf(": only %d register sets\n", sa->sa_nreg); 235 return; 236 } 237 238 if (bus_space_map(sa->sa_bustag, 239 (bus_addr_t)BUS_ADDR(sa->sa_reg[0].oa_space, sa->sa_reg[0].oa_base), 240 (bus_size_t)sa->sa_reg[0].oa_size, 241 0, &sc->sc_cr) != 0) { 242 printf(": cannot map registers\n"); 243 return; 244 } 245 246 if (bus_space_map(sa->sa_bustag, 247 (bus_addr_t)BUS_ADDR(sa->sa_reg[1].oa_space, sa->sa_reg[1].oa_base), 248 (bus_size_t)sa->sa_reg[1].oa_size, 249 0, &sc->sc_br) != 0) { 250 printf(": cannot map registers\n"); 251 return; 252 } 253 254 if (bus_space_map(sa->sa_bustag, 255 (bus_addr_t)BUS_ADDR(sa->sa_reg[2].oa_space, sa->sa_reg[2].oa_base), 256 (bus_size_t)sa->sa_reg[2].oa_size, 257 0, &sc->sc_tr) != 0) { 258 printf(": cannot map registers\n"); 259 return; 260 } 261 262 sc->sc_bustag = sa->sa_bustag; 263 sc->sc_qec = qec; 264 sc->sc_qr = qec->sc_regs; 265 266 sc->sc_rev = prom_getpropint(node, "board-version", -1); 267 printf(": rev %x,", sc->sc_rev); 268 269 callout_init(&sc->sc_tick_ch, 0); 270 271 sc->sc_channel = prom_getpropint(node, "channel#", -1); 272 if (sc->sc_channel == -1) 273 sc->sc_channel = 0; 274 275 sc->sc_burst = prom_getpropint(node, "burst-sizes", -1); 276 if (sc->sc_burst == -1) 277 sc->sc_burst = qec->sc_burst; 278 279 /* Clamp at parent's burst sizes */ 280 sc->sc_burst &= qec->sc_burst; 281 282 /* Establish interrupt handler */ 283 if (sa->sa_nintr) 284 (void)bus_intr_establish(sa->sa_bustag, sa->sa_pri, IPL_NET, 285 beintr, sc); 286 287 prom_getether(node, sc->sc_enaddr); 288 printf(" address %s\n", ether_sprintf(sc->sc_enaddr)); 289 290 /* 291 * Allocate descriptor ring and buffers. 292 */ 293 294 /* for now, allocate as many bufs as there are ring descriptors */ 295 sc->sc_rb.rb_ntbuf = QEC_XD_RING_MAXSIZE; 296 sc->sc_rb.rb_nrbuf = QEC_XD_RING_MAXSIZE; 297 298 size = 299 QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd) + 300 QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd) + 301 sc->sc_rb.rb_ntbuf * BE_PKT_BUF_SZ + 302 sc->sc_rb.rb_nrbuf * BE_PKT_BUF_SZ; 303 304 /* Get a DMA handle */ 305 if ((error = bus_dmamap_create(dmatag, size, 1, size, 0, 306 BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) { 307 aprint_error_dev(self, "DMA map create error %d\n", error); 308 return; 309 } 310 311 /* Allocate DMA buffer */ 312 if ((error = bus_dmamem_alloc(sa->sa_dmatag, size, 0, 0, 313 &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 314 aprint_error_dev(self, "DMA buffer alloc error %d\n", error); 315 return; 316 } 317 318 /* Map DMA memory in CPU addressable space */ 319 if ((error = bus_dmamem_map(sa->sa_dmatag, &seg, rseg, size, 320 &sc->sc_rb.rb_membase, BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 321 aprint_error_dev(self, "DMA buffer map error %d\n", error); 322 bus_dmamem_free(sa->sa_dmatag, &seg, rseg); 323 return; 324 } 325 326 /* Load the buffer */ 327 if ((error = bus_dmamap_load(dmatag, sc->sc_dmamap, 328 sc->sc_rb.rb_membase, size, NULL, BUS_DMA_NOWAIT)) != 0) { 329 aprint_error_dev(self, "DMA buffer map load error %d\n", error); 330 bus_dmamem_unmap(dmatag, sc->sc_rb.rb_membase, size); 331 bus_dmamem_free(dmatag, &seg, rseg); 332 return; 333 } 334 sc->sc_rb.rb_dmabase = sc->sc_dmamap->dm_segs[0].ds_addr; 335 336 /* 337 * Initialize our media structures and MII info. 338 */ 339 mii->mii_ifp = ifp; 340 mii->mii_readreg = be_mii_readreg; 341 mii->mii_writereg = be_mii_writereg; 342 mii->mii_statchg = be_mii_statchg; 343 344 ifmedia_init(&mii->mii_media, 0, be_ifmedia_upd, be_ifmedia_sts); 345 346 /* 347 * Initialize transceiver and determine which PHY connection to use. 348 */ 349 be_mii_sync(sc); 350 v = bus_space_read_4(sc->sc_bustag, sc->sc_tr, BE_TRI_MGMTPAL); 351 352 instance = 0; 353 354 if ((v & MGMT_PAL_EXT_MDIO) != 0) { 355 356 mii_attach(self, mii, 0xffffffff, BE_PHY_EXTERNAL, 357 MII_OFFSET_ANY, 0); 358 359 child = LIST_FIRST(&mii->mii_phys); 360 if (child == NULL) { 361 /* No PHY attached */ 362 ifmedia_add(&sc->sc_media, 363 IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, instance), 364 0, NULL); 365 ifmedia_set(&sc->sc_media, 366 IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, instance)); 367 } else { 368 /* 369 * Note: we support just one PHY on the external 370 * MII connector. 371 */ 372 #ifdef DIAGNOSTIC 373 if (LIST_NEXT(child, mii_list) != NULL) { 374 aprint_error_dev(self, 375 "spurious MII device %s attached\n", 376 device_xname(child->mii_dev)); 377 } 378 #endif 379 if (child->mii_phy != BE_PHY_EXTERNAL || 380 child->mii_inst > 0) { 381 aprint_error_dev(self, 382 "cannot accommodate MII device %s" 383 " at phy %d, instance %d\n", 384 device_xname(child->mii_dev), 385 child->mii_phy, child->mii_inst); 386 } else { 387 sc->sc_phys[instance] = child->mii_phy; 388 } 389 390 /* 391 * XXX - we can really do the following ONLY if the 392 * phy indeed has the auto negotiation capability!! 393 */ 394 ifmedia_set(&sc->sc_media, 395 IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, instance)); 396 397 /* Mark our current media setting */ 398 be_pal_gate(sc, BE_PHY_EXTERNAL); 399 instance++; 400 } 401 402 } 403 404 if ((v & MGMT_PAL_INT_MDIO) != 0) { 405 /* 406 * The be internal phy looks vaguely like MII hardware, 407 * but not enough to be able to use the MII device 408 * layer. Hence, we have to take care of media selection 409 * ourselves. 410 */ 411 412 sc->sc_mii_inst = instance; 413 sc->sc_phys[instance] = BE_PHY_INTERNAL; 414 415 /* Use `ifm_data' to store BMCR bits */ 416 ifmedia_add(&sc->sc_media, 417 IFM_MAKEWORD(IFM_ETHER, IFM_10_T, 0, instance), 418 0, NULL); 419 ifmedia_add(&sc->sc_media, 420 IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, 0, instance), 421 BMCR_S100, NULL); 422 ifmedia_add(&sc->sc_media, 423 IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, instance), 424 0, NULL); 425 426 printf("on-board transceiver at %s: 10baseT, 100baseTX, auto\n", 427 device_xname(self)); 428 429 be_mii_reset(sc, BE_PHY_INTERNAL); 430 /* Only set default medium here if there's no external PHY */ 431 if (instance == 0) { 432 be_pal_gate(sc, BE_PHY_INTERNAL); 433 ifmedia_set(&sc->sc_media, 434 IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, instance)); 435 } else 436 be_mii_writereg(self, 437 BE_PHY_INTERNAL, MII_BMCR, BMCR_ISO); 438 } 439 440 memcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 441 ifp->if_softc = sc; 442 ifp->if_start = bestart; 443 ifp->if_ioctl = beioctl; 444 ifp->if_watchdog = bewatchdog; 445 ifp->if_init = beinit; 446 ifp->if_stop = bestop; 447 ifp->if_flags = 448 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 449 IFQ_SET_READY(&ifp->if_snd); 450 451 /* claim 802.1q capability */ 452 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 453 454 /* Attach the interface. */ 455 if_attach(ifp); 456 ether_ifattach(ifp, sc->sc_enaddr); 457 } 458 459 460 /* 461 * Routine to copy from mbuf chain to transmit buffer in 462 * network buffer memory. 463 */ 464 static inline int 465 be_put(struct be_softc *sc, int idx, struct mbuf *m) 466 { 467 struct mbuf *n; 468 int len, tlen = 0, boff = 0; 469 uint8_t *bp; 470 471 bp = sc->sc_rb.rb_txbuf + (idx % sc->sc_rb.rb_ntbuf) * BE_PKT_BUF_SZ; 472 473 for (; m; m = n) { 474 len = m->m_len; 475 if (len == 0) { 476 MFREE(m, n); 477 continue; 478 } 479 memcpy(bp + boff, mtod(m, void *), len); 480 boff += len; 481 tlen += len; 482 MFREE(m, n); 483 } 484 return tlen; 485 } 486 487 /* 488 * Pull data off an interface. 489 * Len is the length of data, with local net header stripped. 490 * We copy the data into mbufs. When full cluster sized units are present, 491 * we copy into clusters. 492 */ 493 static inline struct mbuf * 494 be_get(struct be_softc *sc, int idx, int totlen) 495 { 496 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 497 struct mbuf *m; 498 struct mbuf *top, **mp; 499 int len, pad, boff = 0; 500 uint8_t *bp; 501 502 bp = sc->sc_rb.rb_rxbuf + (idx % sc->sc_rb.rb_nrbuf) * BE_PKT_BUF_SZ; 503 504 MGETHDR(m, M_DONTWAIT, MT_DATA); 505 if (m == NULL) 506 return (NULL); 507 m->m_pkthdr.rcvif = ifp; 508 m->m_pkthdr.len = totlen; 509 510 pad = ALIGN(sizeof(struct ether_header)) - sizeof(struct ether_header); 511 m->m_data += pad; 512 len = MHLEN - pad; 513 top = NULL; 514 mp = ⊤ 515 516 while (totlen > 0) { 517 if (top) { 518 MGET(m, M_DONTWAIT, MT_DATA); 519 if (m == NULL) { 520 m_freem(top); 521 return (NULL); 522 } 523 len = MLEN; 524 } 525 if (top && totlen >= MINCLSIZE) { 526 MCLGET(m, M_DONTWAIT); 527 if (m->m_flags & M_EXT) 528 len = MCLBYTES; 529 } 530 m->m_len = len = min(totlen, len); 531 memcpy(mtod(m, void *), bp + boff, len); 532 boff += len; 533 totlen -= len; 534 *mp = m; 535 mp = &m->m_next; 536 } 537 538 return top; 539 } 540 541 /* 542 * Pass a packet to the higher levels. 543 */ 544 static inline void 545 be_read(struct be_softc *sc, int idx, int len) 546 { 547 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 548 struct mbuf *m; 549 550 if (len <= sizeof(struct ether_header) || 551 len > ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN) { 552 #ifdef BEDEBUG 553 if (sc->sc_debug) 554 printf("%s: invalid packet size %d; dropping\n", 555 ifp->if_xname, len); 556 #endif 557 ifp->if_ierrors++; 558 return; 559 } 560 561 /* 562 * Pull packet off interface. 563 */ 564 m = be_get(sc, idx, len); 565 if (m == NULL) { 566 ifp->if_ierrors++; 567 return; 568 } 569 ifp->if_ipackets++; 570 571 /* 572 * Check if there's a BPF listener on this interface. 573 * If so, hand off the raw packet to BPF. 574 */ 575 bpf_mtap(ifp, m); 576 /* Pass the packet up. */ 577 if_percpuq_enqueue(ifp->if_percpuq, m); 578 } 579 580 /* 581 * Start output on interface. 582 * We make two assumptions here: 583 * 1) that the current priority is set to splnet _before_ this code 584 * is called *and* is returned to the appropriate priority after 585 * return 586 * 2) that the IFF_OACTIVE flag is checked before this code is called 587 * (i.e. that the output part of the interface is idle) 588 */ 589 void 590 bestart(struct ifnet *ifp) 591 { 592 struct be_softc *sc = ifp->if_softc; 593 struct qec_xd *txd = sc->sc_rb.rb_txd; 594 struct mbuf *m; 595 unsigned int bix, len; 596 unsigned int ntbuf = sc->sc_rb.rb_ntbuf; 597 598 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 599 return; 600 601 bix = sc->sc_rb.rb_tdhead; 602 603 for (;;) { 604 IFQ_DEQUEUE(&ifp->if_snd, m); 605 if (m == 0) 606 break; 607 608 /* 609 * If BPF is listening on this interface, let it see the 610 * packet before we commit it to the wire. 611 */ 612 bpf_mtap(ifp, m); 613 614 /* 615 * Copy the mbuf chain into the transmit buffer. 616 */ 617 len = be_put(sc, bix, m); 618 619 /* 620 * Initialize transmit registers and start transmission 621 */ 622 txd[bix].xd_flags = QEC_XD_OWN | QEC_XD_SOP | QEC_XD_EOP | 623 (len & QEC_XD_LENGTH); 624 bus_space_write_4(sc->sc_bustag, sc->sc_cr, 625 BE_CRI_CTRL, BE_CR_CTRL_TWAKEUP); 626 627 if (++bix == QEC_XD_RING_MAXSIZE) 628 bix = 0; 629 630 if (++sc->sc_rb.rb_td_nbusy == ntbuf) { 631 ifp->if_flags |= IFF_OACTIVE; 632 break; 633 } 634 } 635 636 sc->sc_rb.rb_tdhead = bix; 637 } 638 639 void 640 bestop(struct ifnet *ifp, int disable) 641 { 642 struct be_softc *sc = ifp->if_softc; 643 644 callout_stop(&sc->sc_tick_ch); 645 646 /* Down the MII. */ 647 mii_down(&sc->sc_mii); 648 (void)be_intphy_service(sc, &sc->sc_mii, MII_DOWN); 649 650 behwreset(sc); 651 } 652 653 void 654 behwreset(struct be_softc *sc) 655 { 656 int n; 657 bus_space_tag_t t = sc->sc_bustag; 658 bus_space_handle_t br = sc->sc_br; 659 660 /* Stop the transmitter */ 661 bus_space_write_4(t, br, BE_BRI_TXCFG, 0); 662 for (n = 32; n > 0; n--) { 663 if (bus_space_read_4(t, br, BE_BRI_TXCFG) == 0) 664 break; 665 DELAY(20); 666 } 667 668 /* Stop the receiver */ 669 bus_space_write_4(t, br, BE_BRI_RXCFG, 0); 670 for (n = 32; n > 0; n--) { 671 if (bus_space_read_4(t, br, BE_BRI_RXCFG) == 0) 672 break; 673 DELAY(20); 674 } 675 } 676 677 /* 678 * Reset interface. 679 */ 680 void 681 bereset(struct be_softc *sc) 682 { 683 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 684 int s; 685 686 s = splnet(); 687 behwreset(sc); 688 if ((sc->sc_ethercom.ec_if.if_flags & IFF_UP) != 0) 689 beinit(ifp); 690 splx(s); 691 } 692 693 void 694 bewatchdog(struct ifnet *ifp) 695 { 696 struct be_softc *sc = ifp->if_softc; 697 698 log(LOG_ERR, "%s: device timeout\n", device_xname(sc->sc_dev)); 699 ++sc->sc_ethercom.ec_if.if_oerrors; 700 701 bereset(sc); 702 } 703 704 int 705 beintr(void *arg) 706 { 707 struct be_softc *sc = arg; 708 bus_space_tag_t t = sc->sc_bustag; 709 uint32_t whyq, whyb, whyc; 710 int r = 0; 711 712 /* Read QEC status, channel status and BE status */ 713 whyq = bus_space_read_4(t, sc->sc_qr, QEC_QRI_STAT); 714 whyc = bus_space_read_4(t, sc->sc_cr, BE_CRI_STAT); 715 whyb = bus_space_read_4(t, sc->sc_br, BE_BRI_STAT); 716 717 if (whyq & QEC_STAT_BM) 718 r |= beeint(sc, whyb); 719 720 if (whyq & QEC_STAT_ER) 721 r |= beqint(sc, whyc); 722 723 if (whyq & QEC_STAT_TX && whyc & BE_CR_STAT_TXIRQ) 724 r |= betint(sc); 725 726 if (whyq & QEC_STAT_RX && whyc & BE_CR_STAT_RXIRQ) 727 r |= berint(sc); 728 729 return r; 730 } 731 732 /* 733 * QEC Interrupt. 734 */ 735 int 736 beqint(struct be_softc *sc, uint32_t why) 737 { 738 device_t self = sc->sc_dev; 739 int r = 0, rst = 0; 740 741 if (why & BE_CR_STAT_TXIRQ) 742 r |= 1; 743 if (why & BE_CR_STAT_RXIRQ) 744 r |= 1; 745 746 if (why & BE_CR_STAT_BERROR) { 747 r |= 1; 748 rst = 1; 749 aprint_error_dev(self, "bigmac error\n"); 750 } 751 752 if (why & BE_CR_STAT_TXDERR) { 753 r |= 1; 754 rst = 1; 755 aprint_error_dev(self, "bogus tx descriptor\n"); 756 } 757 758 if (why & (BE_CR_STAT_TXLERR | BE_CR_STAT_TXPERR | BE_CR_STAT_TXSERR)) { 759 r |= 1; 760 rst = 1; 761 aprint_error_dev(self, "tx DMA error ( "); 762 if (why & BE_CR_STAT_TXLERR) 763 printf("Late "); 764 if (why & BE_CR_STAT_TXPERR) 765 printf("Parity "); 766 if (why & BE_CR_STAT_TXSERR) 767 printf("Generic "); 768 printf(")\n"); 769 } 770 771 if (why & BE_CR_STAT_RXDROP) { 772 r |= 1; 773 rst = 1; 774 aprint_error_dev(self, "out of rx descriptors\n"); 775 } 776 777 if (why & BE_CR_STAT_RXSMALL) { 778 r |= 1; 779 rst = 1; 780 aprint_error_dev(self, "rx descriptor too small\n"); 781 } 782 783 if (why & (BE_CR_STAT_RXLERR | BE_CR_STAT_RXPERR | BE_CR_STAT_RXSERR)) { 784 r |= 1; 785 rst = 1; 786 aprint_error_dev(self, "rx DMA error ( "); 787 if (why & BE_CR_STAT_RXLERR) 788 printf("Late "); 789 if (why & BE_CR_STAT_RXPERR) 790 printf("Parity "); 791 if (why & BE_CR_STAT_RXSERR) 792 printf("Generic "); 793 printf(")\n"); 794 } 795 796 if (!r) { 797 rst = 1; 798 aprint_error_dev(self, "unexpected error interrupt %08x\n", 799 why); 800 } 801 802 if (rst) { 803 printf("%s: resetting\n", device_xname(self)); 804 bereset(sc); 805 } 806 807 return r; 808 } 809 810 /* 811 * Error interrupt. 812 */ 813 int 814 beeint(struct be_softc *sc, uint32_t why) 815 { 816 device_t self = sc->sc_dev; 817 int r = 0, rst = 0; 818 819 if (why & BE_BR_STAT_RFIFOVF) { 820 r |= 1; 821 rst = 1; 822 aprint_error_dev(self, "receive fifo overrun\n"); 823 } 824 if (why & BE_BR_STAT_TFIFO_UND) { 825 r |= 1; 826 rst = 1; 827 aprint_error_dev(self, "transmit fifo underrun\n"); 828 } 829 if (why & BE_BR_STAT_MAXPKTERR) { 830 r |= 1; 831 rst = 1; 832 aprint_error_dev(self, "max packet size error\n"); 833 } 834 835 if (!r) { 836 rst = 1; 837 aprint_error_dev(self, "unexpected error interrupt %08x\n", 838 why); 839 } 840 841 if (rst) { 842 printf("%s: resetting\n", device_xname(self)); 843 bereset(sc); 844 } 845 846 return r; 847 } 848 849 /* 850 * Transmit interrupt. 851 */ 852 int 853 betint(struct be_softc *sc) 854 { 855 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 856 bus_space_tag_t t = sc->sc_bustag; 857 bus_space_handle_t br = sc->sc_br; 858 unsigned int bix, txflags; 859 860 /* 861 * Unload collision counters 862 */ 863 ifp->if_collisions += 864 bus_space_read_4(t, br, BE_BRI_NCCNT) + 865 bus_space_read_4(t, br, BE_BRI_FCCNT) + 866 bus_space_read_4(t, br, BE_BRI_EXCNT) + 867 bus_space_read_4(t, br, BE_BRI_LTCNT); 868 869 /* 870 * the clear the hardware counters 871 */ 872 bus_space_write_4(t, br, BE_BRI_NCCNT, 0); 873 bus_space_write_4(t, br, BE_BRI_FCCNT, 0); 874 bus_space_write_4(t, br, BE_BRI_EXCNT, 0); 875 bus_space_write_4(t, br, BE_BRI_LTCNT, 0); 876 877 bix = sc->sc_rb.rb_tdtail; 878 879 for (;;) { 880 if (sc->sc_rb.rb_td_nbusy <= 0) 881 break; 882 883 txflags = sc->sc_rb.rb_txd[bix].xd_flags; 884 885 if (txflags & QEC_XD_OWN) 886 break; 887 888 ifp->if_flags &= ~IFF_OACTIVE; 889 ifp->if_opackets++; 890 891 if (++bix == QEC_XD_RING_MAXSIZE) 892 bix = 0; 893 894 --sc->sc_rb.rb_td_nbusy; 895 } 896 897 sc->sc_rb.rb_tdtail = bix; 898 899 bestart(ifp); 900 901 if (sc->sc_rb.rb_td_nbusy == 0) 902 ifp->if_timer = 0; 903 904 return 1; 905 } 906 907 /* 908 * Receive interrupt. 909 */ 910 int 911 berint(struct be_softc *sc) 912 { 913 struct qec_xd *xd = sc->sc_rb.rb_rxd; 914 unsigned int bix, len; 915 unsigned int nrbuf = sc->sc_rb.rb_nrbuf; 916 917 bix = sc->sc_rb.rb_rdtail; 918 919 /* 920 * Process all buffers with valid data. 921 */ 922 for (;;) { 923 len = xd[bix].xd_flags; 924 if (len & QEC_XD_OWN) 925 break; 926 927 len &= QEC_XD_LENGTH; 928 be_read(sc, bix, len); 929 930 /* ... */ 931 xd[(bix+nrbuf) % QEC_XD_RING_MAXSIZE].xd_flags = 932 QEC_XD_OWN | (BE_PKT_BUF_SZ & QEC_XD_LENGTH); 933 934 if (++bix == QEC_XD_RING_MAXSIZE) 935 bix = 0; 936 } 937 938 sc->sc_rb.rb_rdtail = bix; 939 940 return 1; 941 } 942 943 int 944 beioctl(struct ifnet *ifp, u_long cmd, void *data) 945 { 946 struct be_softc *sc = ifp->if_softc; 947 struct ifaddr *ifa = data; 948 struct ifreq *ifr = data; 949 int s, error = 0; 950 951 s = splnet(); 952 953 switch (cmd) { 954 case SIOCINITIFADDR: 955 ifp->if_flags |= IFF_UP; 956 beinit(ifp); 957 switch (ifa->ifa_addr->sa_family) { 958 #ifdef INET 959 case AF_INET: 960 arp_ifinit(ifp, ifa); 961 break; 962 #endif /* INET */ 963 default: 964 break; 965 } 966 break; 967 968 case SIOCSIFFLAGS: 969 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 970 break; 971 /* XXX re-use ether_ioctl() */ 972 switch (ifp->if_flags & (IFF_UP|IFF_RUNNING)) { 973 case IFF_RUNNING: 974 /* 975 * If interface is marked down and it is running, then 976 * stop it. 977 */ 978 bestop(ifp, 0); 979 ifp->if_flags &= ~IFF_RUNNING; 980 break; 981 case IFF_UP: 982 /* 983 * If interface is marked up and it is stopped, then 984 * start it. 985 */ 986 beinit(ifp); 987 break; 988 default: 989 /* 990 * Reset the interface to pick up changes in any other 991 * flags that affect hardware registers. 992 */ 993 bestop(ifp, 0); 994 beinit(ifp); 995 break; 996 } 997 #ifdef BEDEBUG 998 if (ifp->if_flags & IFF_DEBUG) 999 sc->sc_debug = 1; 1000 else 1001 sc->sc_debug = 0; 1002 #endif 1003 break; 1004 1005 case SIOCGIFMEDIA: 1006 case SIOCSIFMEDIA: 1007 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd); 1008 break; 1009 default: 1010 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 1011 /* 1012 * Multicast list has changed; set the hardware filter 1013 * accordingly. 1014 */ 1015 if (ifp->if_flags & IFF_RUNNING) 1016 error = beinit(ifp); 1017 else 1018 error = 0; 1019 } 1020 break; 1021 } 1022 splx(s); 1023 return error; 1024 } 1025 1026 1027 int 1028 beinit(struct ifnet *ifp) 1029 { 1030 struct be_softc *sc = ifp->if_softc; 1031 bus_space_tag_t t = sc->sc_bustag; 1032 bus_space_handle_t br = sc->sc_br; 1033 bus_space_handle_t cr = sc->sc_cr; 1034 struct qec_softc *qec = sc->sc_qec; 1035 uint32_t v; 1036 uint32_t qecaddr; 1037 uint8_t *ea; 1038 int rc, s; 1039 1040 s = splnet(); 1041 1042 qec_meminit(&sc->sc_rb, BE_PKT_BUF_SZ); 1043 1044 bestop(ifp, 1); 1045 1046 ea = sc->sc_enaddr; 1047 bus_space_write_4(t, br, BE_BRI_MACADDR0, (ea[0] << 8) | ea[1]); 1048 bus_space_write_4(t, br, BE_BRI_MACADDR1, (ea[2] << 8) | ea[3]); 1049 bus_space_write_4(t, br, BE_BRI_MACADDR2, (ea[4] << 8) | ea[5]); 1050 1051 /* Clear hash table */ 1052 bus_space_write_4(t, br, BE_BRI_HASHTAB0, 0); 1053 bus_space_write_4(t, br, BE_BRI_HASHTAB1, 0); 1054 bus_space_write_4(t, br, BE_BRI_HASHTAB2, 0); 1055 bus_space_write_4(t, br, BE_BRI_HASHTAB3, 0); 1056 1057 /* Re-initialize RX configuration */ 1058 v = BE_BR_RXCFG_FIFO; 1059 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1060 1061 be_mcreset(sc); 1062 1063 bus_space_write_4(t, br, BE_BRI_RANDSEED, 0xbd); 1064 1065 bus_space_write_4(t, br, 1066 BE_BRI_XIFCFG, BE_BR_XCFG_ODENABLE | BE_BR_XCFG_RESV); 1067 1068 bus_space_write_4(t, br, BE_BRI_JSIZE, 4); 1069 1070 /* 1071 * Turn off counter expiration interrupts as well as 1072 * 'gotframe' and 'sentframe' 1073 */ 1074 bus_space_write_4(t, br, BE_BRI_IMASK, 1075 BE_BR_IMASK_GOTFRAME | 1076 BE_BR_IMASK_RCNTEXP | 1077 BE_BR_IMASK_ACNTEXP | 1078 BE_BR_IMASK_CCNTEXP | 1079 BE_BR_IMASK_LCNTEXP | 1080 BE_BR_IMASK_CVCNTEXP | 1081 BE_BR_IMASK_SENTFRAME | 1082 BE_BR_IMASK_NCNTEXP | 1083 BE_BR_IMASK_ECNTEXP | 1084 BE_BR_IMASK_LCCNTEXP | 1085 BE_BR_IMASK_FCNTEXP | 1086 BE_BR_IMASK_DTIMEXP); 1087 1088 /* Channel registers: */ 1089 bus_space_write_4(t, cr, BE_CRI_RXDS, (uint32_t)sc->sc_rb.rb_rxddma); 1090 bus_space_write_4(t, cr, BE_CRI_TXDS, (uint32_t)sc->sc_rb.rb_txddma); 1091 1092 qecaddr = sc->sc_channel * qec->sc_msize; 1093 bus_space_write_4(t, cr, BE_CRI_RXWBUF, qecaddr); 1094 bus_space_write_4(t, cr, BE_CRI_RXRBUF, qecaddr); 1095 bus_space_write_4(t, cr, BE_CRI_TXWBUF, qecaddr + qec->sc_rsize); 1096 bus_space_write_4(t, cr, BE_CRI_TXRBUF, qecaddr + qec->sc_rsize); 1097 1098 bus_space_write_4(t, cr, BE_CRI_RIMASK, 0); 1099 bus_space_write_4(t, cr, BE_CRI_TIMASK, 0); 1100 bus_space_write_4(t, cr, BE_CRI_QMASK, 0); 1101 bus_space_write_4(t, cr, BE_CRI_BMASK, 0); 1102 bus_space_write_4(t, cr, BE_CRI_CCNT, 0); 1103 1104 /* Set max packet length */ 1105 v = ETHER_MAX_LEN; 1106 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) 1107 v += ETHER_VLAN_ENCAP_LEN; 1108 bus_space_write_4(t, br, BE_BRI_RXMAX, v); 1109 bus_space_write_4(t, br, BE_BRI_TXMAX, v); 1110 1111 /* Enable transmitter */ 1112 bus_space_write_4(t, br, 1113 BE_BRI_TXCFG, BE_BR_TXCFG_FIFO | BE_BR_TXCFG_ENABLE); 1114 1115 /* Enable receiver */ 1116 v = bus_space_read_4(t, br, BE_BRI_RXCFG); 1117 v |= BE_BR_RXCFG_FIFO | BE_BR_RXCFG_ENABLE; 1118 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1119 1120 if ((rc = be_ifmedia_upd(ifp)) != 0) 1121 goto out; 1122 1123 ifp->if_flags |= IFF_RUNNING; 1124 ifp->if_flags &= ~IFF_OACTIVE; 1125 1126 callout_reset(&sc->sc_tick_ch, hz, be_tick, sc); 1127 1128 return 0; 1129 out: 1130 splx(s); 1131 return rc; 1132 } 1133 1134 void 1135 be_mcreset(struct be_softc *sc) 1136 { 1137 struct ethercom *ec = &sc->sc_ethercom; 1138 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1139 bus_space_tag_t t = sc->sc_bustag; 1140 bus_space_handle_t br = sc->sc_br; 1141 uint32_t v; 1142 uint32_t crc; 1143 uint16_t hash[4]; 1144 struct ether_multi *enm; 1145 struct ether_multistep step; 1146 1147 if (ifp->if_flags & IFF_PROMISC) { 1148 v = bus_space_read_4(t, br, BE_BRI_RXCFG); 1149 v |= BE_BR_RXCFG_PMISC; 1150 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1151 return; 1152 } 1153 1154 if (ifp->if_flags & IFF_ALLMULTI) { 1155 hash[3] = hash[2] = hash[1] = hash[0] = 0xffff; 1156 goto chipit; 1157 } 1158 1159 hash[3] = hash[2] = hash[1] = hash[0] = 0; 1160 1161 ETHER_FIRST_MULTI(step, ec, enm); 1162 while (enm != NULL) { 1163 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1164 /* 1165 * We must listen to a range of multicast 1166 * addresses. For now, just accept all 1167 * multicasts, rather than trying to set only 1168 * those filter bits needed to match the range. 1169 * (At this time, the only use of address 1170 * ranges is for IP multicast routing, for 1171 * which the range is big enough to require 1172 * all bits set.) 1173 */ 1174 hash[3] = hash[2] = hash[1] = hash[0] = 0xffff; 1175 ifp->if_flags |= IFF_ALLMULTI; 1176 goto chipit; 1177 } 1178 1179 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 1180 /* Just want the 6 most significant bits. */ 1181 crc >>= 26; 1182 1183 hash[crc >> 4] |= 1 << (crc & 0xf); 1184 ETHER_NEXT_MULTI(step, enm); 1185 } 1186 1187 ifp->if_flags &= ~IFF_ALLMULTI; 1188 1189 chipit: 1190 /* Enable the hash filter */ 1191 bus_space_write_4(t, br, BE_BRI_HASHTAB0, hash[0]); 1192 bus_space_write_4(t, br, BE_BRI_HASHTAB1, hash[1]); 1193 bus_space_write_4(t, br, BE_BRI_HASHTAB2, hash[2]); 1194 bus_space_write_4(t, br, BE_BRI_HASHTAB3, hash[3]); 1195 1196 v = bus_space_read_4(t, br, BE_BRI_RXCFG); 1197 v &= ~BE_BR_RXCFG_PMISC; 1198 v |= BE_BR_RXCFG_HENABLE; 1199 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1200 } 1201 1202 /* 1203 * Set the tcvr to an idle state 1204 */ 1205 void 1206 be_mii_sync(struct be_softc *sc) 1207 { 1208 bus_space_tag_t t = sc->sc_bustag; 1209 bus_space_handle_t tr = sc->sc_tr; 1210 int n = 32; 1211 1212 while (n--) { 1213 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, 1214 MGMT_PAL_INT_MDIO | MGMT_PAL_EXT_MDIO | MGMT_PAL_OENAB); 1215 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1216 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, 1217 MGMT_PAL_INT_MDIO | MGMT_PAL_EXT_MDIO | 1218 MGMT_PAL_OENAB | MGMT_PAL_DCLOCK); 1219 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1220 } 1221 } 1222 1223 void 1224 be_pal_gate(struct be_softc *sc, int phy) 1225 { 1226 bus_space_tag_t t = sc->sc_bustag; 1227 bus_space_handle_t tr = sc->sc_tr; 1228 uint32_t v; 1229 1230 be_mii_sync(sc); 1231 1232 v = ~(TCVR_PAL_EXTLBACK | TCVR_PAL_MSENSE | TCVR_PAL_LTENABLE); 1233 if (phy == BE_PHY_INTERNAL) 1234 v &= ~TCVR_PAL_SERIAL; 1235 1236 bus_space_write_4(t, tr, BE_TRI_TCVRPAL, v); 1237 (void)bus_space_read_4(t, tr, BE_TRI_TCVRPAL); 1238 } 1239 1240 static int 1241 be_tcvr_read_bit(struct be_softc *sc, int phy) 1242 { 1243 bus_space_tag_t t = sc->sc_bustag; 1244 bus_space_handle_t tr = sc->sc_tr; 1245 int ret; 1246 1247 if (phy == BE_PHY_INTERNAL) { 1248 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, MGMT_PAL_EXT_MDIO); 1249 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1250 bus_space_write_4(t, tr, 1251 BE_TRI_MGMTPAL, MGMT_PAL_EXT_MDIO | MGMT_PAL_DCLOCK); 1252 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1253 ret = (bus_space_read_4(t, tr, BE_TRI_MGMTPAL) & 1254 MGMT_PAL_INT_MDIO) >> MGMT_PAL_INT_MDIO_SHIFT; 1255 } else { 1256 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, MGMT_PAL_INT_MDIO); 1257 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1258 ret = (bus_space_read_4(t, tr, BE_TRI_MGMTPAL) & 1259 MGMT_PAL_EXT_MDIO) >> MGMT_PAL_EXT_MDIO_SHIFT; 1260 bus_space_write_4(t, tr, 1261 BE_TRI_MGMTPAL, MGMT_PAL_INT_MDIO | MGMT_PAL_DCLOCK); 1262 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1263 } 1264 1265 return ret; 1266 } 1267 1268 static void 1269 be_tcvr_write_bit(struct be_softc *sc, int phy, int bit) 1270 { 1271 bus_space_tag_t t = sc->sc_bustag; 1272 bus_space_handle_t tr = sc->sc_tr; 1273 uint32_t v; 1274 1275 if (phy == BE_PHY_INTERNAL) { 1276 v = ((bit & 1) << MGMT_PAL_INT_MDIO_SHIFT) | 1277 MGMT_PAL_OENAB | MGMT_PAL_EXT_MDIO; 1278 } else { 1279 v = ((bit & 1) << MGMT_PAL_EXT_MDIO_SHIFT) | 1280 MGMT_PAL_OENAB | MGMT_PAL_INT_MDIO; 1281 } 1282 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, v); 1283 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1284 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, v | MGMT_PAL_DCLOCK); 1285 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1286 } 1287 1288 static void 1289 be_mii_sendbits(struct be_softc *sc, int phy, uint32_t data, int nbits) 1290 { 1291 int i; 1292 1293 for (i = 1 << (nbits - 1); i != 0; i >>= 1) { 1294 be_tcvr_write_bit(sc, phy, (data & i) != 0); 1295 } 1296 } 1297 1298 static int 1299 be_mii_readreg(device_t self, int phy, int reg) 1300 { 1301 struct be_softc *sc = device_private(self); 1302 int val = 0, i; 1303 1304 /* 1305 * Read the PHY register by manually driving the MII control lines. 1306 */ 1307 be_mii_sync(sc); 1308 be_mii_sendbits(sc, phy, MII_COMMAND_START, 2); 1309 be_mii_sendbits(sc, phy, MII_COMMAND_READ, 2); 1310 be_mii_sendbits(sc, phy, phy, 5); 1311 be_mii_sendbits(sc, phy, reg, 5); 1312 1313 (void)be_tcvr_read_bit(sc, phy); 1314 (void)be_tcvr_read_bit(sc, phy); 1315 1316 for (i = 15; i >= 0; i--) 1317 val |= (be_tcvr_read_bit(sc, phy) << i); 1318 1319 (void)be_tcvr_read_bit(sc, phy); 1320 (void)be_tcvr_read_bit(sc, phy); 1321 (void)be_tcvr_read_bit(sc, phy); 1322 1323 return val; 1324 } 1325 1326 void 1327 be_mii_writereg(device_t self, int phy, int reg, int val) 1328 { 1329 struct be_softc *sc = device_private(self); 1330 int i; 1331 1332 /* 1333 * Write the PHY register by manually driving the MII control lines. 1334 */ 1335 be_mii_sync(sc); 1336 be_mii_sendbits(sc, phy, MII_COMMAND_START, 2); 1337 be_mii_sendbits(sc, phy, MII_COMMAND_WRITE, 2); 1338 be_mii_sendbits(sc, phy, phy, 5); 1339 be_mii_sendbits(sc, phy, reg, 5); 1340 1341 be_tcvr_write_bit(sc, phy, 1); 1342 be_tcvr_write_bit(sc, phy, 0); 1343 1344 for (i = 15; i >= 0; i--) 1345 be_tcvr_write_bit(sc, phy, (val >> i) & 1); 1346 } 1347 1348 int 1349 be_mii_reset(struct be_softc *sc, int phy) 1350 { 1351 device_t self = sc->sc_dev; 1352 int n; 1353 1354 be_mii_writereg(self, phy, MII_BMCR, BMCR_LOOP | BMCR_PDOWN | BMCR_ISO); 1355 be_mii_writereg(self, phy, MII_BMCR, BMCR_RESET); 1356 1357 for (n = 16; n >= 0; n--) { 1358 int bmcr = be_mii_readreg(self, phy, MII_BMCR); 1359 if ((bmcr & BMCR_RESET) == 0) 1360 break; 1361 DELAY(20); 1362 } 1363 if (n == 0) { 1364 aprint_error_dev(self, "bmcr reset failed\n"); 1365 return EIO; 1366 } 1367 1368 return 0; 1369 } 1370 1371 void 1372 be_tick(void *arg) 1373 { 1374 struct be_softc *sc = arg; 1375 int s = splnet(); 1376 1377 mii_tick(&sc->sc_mii); 1378 (void)be_intphy_service(sc, &sc->sc_mii, MII_TICK); 1379 1380 splx(s); 1381 callout_reset(&sc->sc_tick_ch, hz, be_tick, sc); 1382 } 1383 1384 void 1385 be_mii_statchg(struct ifnet *ifp) 1386 { 1387 struct be_softc *sc = ifp->if_softc; 1388 bus_space_tag_t t = sc->sc_bustag; 1389 bus_space_handle_t br = sc->sc_br; 1390 uint instance; 1391 uint32_t v; 1392 1393 instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media); 1394 #ifdef DIAGNOSTIC 1395 if (instance > 1) 1396 panic("be_mii_statchg: instance %d out of range", instance); 1397 #endif 1398 1399 /* Update duplex mode in TX configuration */ 1400 v = bus_space_read_4(t, br, BE_BRI_TXCFG); 1401 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 1402 v |= BE_BR_TXCFG_FULLDPLX; 1403 else 1404 v &= ~BE_BR_TXCFG_FULLDPLX; 1405 bus_space_write_4(t, br, BE_BRI_TXCFG, v); 1406 1407 /* Change to appropriate gate in transceiver PAL */ 1408 be_pal_gate(sc, sc->sc_phys[instance]); 1409 } 1410 1411 /* 1412 * Get current media settings. 1413 */ 1414 void 1415 be_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1416 { 1417 struct be_softc *sc = ifp->if_softc; 1418 1419 mii_pollstat(&sc->sc_mii); 1420 (void)be_intphy_service(sc, &sc->sc_mii, MII_POLLSTAT); 1421 1422 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1423 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1424 } 1425 1426 /* 1427 * Set media options. 1428 */ 1429 int 1430 be_ifmedia_upd(struct ifnet *ifp) 1431 { 1432 struct be_softc *sc = ifp->if_softc; 1433 int error; 1434 1435 if ((error = mii_mediachg(&sc->sc_mii)) == ENXIO) 1436 error = 0; 1437 else if (error != 0) 1438 return error; 1439 1440 return be_intphy_service(sc, &sc->sc_mii, MII_MEDIACHG); 1441 } 1442 1443 /* 1444 * Service routine for our pseudo-MII internal transceiver. 1445 */ 1446 int 1447 be_intphy_service(struct be_softc *sc, struct mii_data *mii, int cmd) 1448 { 1449 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 1450 device_t self = sc->sc_dev; 1451 int bmcr, bmsr; 1452 int error; 1453 1454 switch (cmd) { 1455 case MII_POLLSTAT: 1456 /* 1457 * If we're not polling our PHY instance, just return. 1458 */ 1459 if (IFM_INST(ife->ifm_media) != sc->sc_mii_inst) 1460 return 0; 1461 1462 break; 1463 1464 case MII_MEDIACHG: 1465 1466 /* 1467 * If the media indicates a different PHY instance, 1468 * isolate ourselves. 1469 */ 1470 if (IFM_INST(ife->ifm_media) != sc->sc_mii_inst) { 1471 bmcr = be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMCR); 1472 be_mii_writereg(self, 1473 BE_PHY_INTERNAL, MII_BMCR, bmcr | BMCR_ISO); 1474 sc->sc_mii_flags &= ~MIIF_HAVELINK; 1475 sc->sc_intphy_curspeed = 0; 1476 return 0; 1477 } 1478 1479 1480 if ((error = be_mii_reset(sc, BE_PHY_INTERNAL)) != 0) 1481 return error; 1482 1483 bmcr = be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMCR); 1484 1485 /* 1486 * Select the new mode and take out of isolation 1487 */ 1488 if (IFM_SUBTYPE(ife->ifm_media) == IFM_100_TX) 1489 bmcr |= BMCR_S100; 1490 else if (IFM_SUBTYPE(ife->ifm_media) == IFM_10_T) 1491 bmcr &= ~BMCR_S100; 1492 else if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) { 1493 if ((sc->sc_mii_flags & MIIF_HAVELINK) != 0) { 1494 bmcr &= ~BMCR_S100; 1495 bmcr |= sc->sc_intphy_curspeed; 1496 } else { 1497 /* Keep isolated until link is up */ 1498 bmcr |= BMCR_ISO; 1499 sc->sc_mii_flags |= MIIF_DOINGAUTO; 1500 } 1501 } 1502 1503 if ((IFM_OPTIONS(ife->ifm_media) & IFM_FDX) != 0) 1504 bmcr |= BMCR_FDX; 1505 else 1506 bmcr &= ~BMCR_FDX; 1507 1508 be_mii_writereg(self, BE_PHY_INTERNAL, MII_BMCR, bmcr); 1509 break; 1510 1511 case MII_TICK: 1512 /* 1513 * If we're not currently selected, just return. 1514 */ 1515 if (IFM_INST(ife->ifm_media) != sc->sc_mii_inst) 1516 return 0; 1517 1518 /* Is the interface even up? */ 1519 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 1520 return 0; 1521 1522 /* Only used for automatic media selection */ 1523 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) 1524 break; 1525 1526 /* 1527 * Check link status; if we don't have a link, try another 1528 * speed. We can't detect duplex mode, so half-duplex is 1529 * what we have to settle for. 1530 */ 1531 1532 /* Read twice in case the register is latched */ 1533 bmsr = 1534 be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMSR) | 1535 be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMSR); 1536 1537 if ((bmsr & BMSR_LINK) != 0) { 1538 /* We have a carrier */ 1539 bmcr = be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMCR); 1540 1541 if ((sc->sc_mii_flags & MIIF_DOINGAUTO) != 0) { 1542 bmcr = be_mii_readreg(self, 1543 BE_PHY_INTERNAL, MII_BMCR); 1544 1545 sc->sc_mii_flags |= MIIF_HAVELINK; 1546 sc->sc_intphy_curspeed = (bmcr & BMCR_S100); 1547 sc->sc_mii_flags &= ~MIIF_DOINGAUTO; 1548 1549 bmcr &= ~BMCR_ISO; 1550 be_mii_writereg(self, 1551 BE_PHY_INTERNAL, MII_BMCR, bmcr); 1552 1553 printf("%s: link up at %s Mbps\n", 1554 device_xname(self), 1555 (bmcr & BMCR_S100) ? "100" : "10"); 1556 } 1557 break; 1558 } 1559 1560 if ((sc->sc_mii_flags & MIIF_DOINGAUTO) == 0) { 1561 sc->sc_mii_flags |= MIIF_DOINGAUTO; 1562 sc->sc_mii_flags &= ~MIIF_HAVELINK; 1563 sc->sc_intphy_curspeed = 0; 1564 printf("%s: link down\n", device_xname(self)); 1565 } 1566 1567 /* Only retry autonegotiation every 5 seconds. */ 1568 if (++sc->sc_mii_ticks < 5) 1569 return 0; 1570 1571 sc->sc_mii_ticks = 0; 1572 bmcr = be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMCR); 1573 /* Just flip the fast speed bit */ 1574 bmcr ^= BMCR_S100; 1575 be_mii_writereg(self, BE_PHY_INTERNAL, MII_BMCR, bmcr); 1576 1577 break; 1578 1579 case MII_DOWN: 1580 /* Isolate this phy */ 1581 bmcr = be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMCR); 1582 be_mii_writereg(self, 1583 BE_PHY_INTERNAL, MII_BMCR, bmcr | BMCR_ISO); 1584 return 0; 1585 } 1586 1587 /* Update the media status. */ 1588 be_intphy_status(sc); 1589 1590 /* Callback if something changed. */ 1591 if (sc->sc_mii_active != mii->mii_media_active || cmd == MII_MEDIACHG) { 1592 (*mii->mii_statchg)(mii->mii_ifp); 1593 sc->sc_mii_active = mii->mii_media_active; 1594 } 1595 return 0; 1596 } 1597 1598 /* 1599 * Determine status of internal transceiver 1600 */ 1601 void 1602 be_intphy_status(struct be_softc *sc) 1603 { 1604 struct mii_data *mii = &sc->sc_mii; 1605 device_t self = sc->sc_dev; 1606 int media_active, media_status; 1607 int bmcr, bmsr; 1608 1609 media_status = IFM_AVALID; 1610 media_active = 0; 1611 1612 /* 1613 * Internal transceiver; do the work here. 1614 */ 1615 bmcr = be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMCR); 1616 1617 switch (bmcr & (BMCR_S100 | BMCR_FDX)) { 1618 case (BMCR_S100 | BMCR_FDX): 1619 media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 1620 break; 1621 case BMCR_S100: 1622 media_active = IFM_ETHER | IFM_100_TX | IFM_HDX; 1623 break; 1624 case BMCR_FDX: 1625 media_active = IFM_ETHER | IFM_10_T | IFM_FDX; 1626 break; 1627 case 0: 1628 media_active = IFM_ETHER | IFM_10_T | IFM_HDX; 1629 break; 1630 } 1631 1632 /* Read twice in case the register is latched */ 1633 bmsr = 1634 be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMSR) | 1635 be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMSR); 1636 if (bmsr & BMSR_LINK) 1637 media_status |= IFM_ACTIVE; 1638 1639 mii->mii_media_status = media_status; 1640 mii->mii_media_active = media_active; 1641 } 1642
Indexes created Tue Sep 30 17:09:57 GMT 2025