be.c revision 1.86
1 /* $NetBSD: be.c,v 1.86 2017/06/25 12:02:59 maxv Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Copyright (c) 1998 Theo de Raadt and Jason L. Wright. 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. The name of the authors may not be used to endorse or promote products 45 * derived from this software without specific prior written permission. 46 * 47 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR 48 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 49 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 50 * IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, 51 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 52 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 53 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 54 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 55 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 56 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 57 */ 58 59 #include <sys/cdefs.h> 60 __KERNEL_RCSID(0, "$NetBSD: be.c,v 1.86 2017/06/25 12:02:59 maxv Exp $"); 61 62 #include "opt_ddb.h" 63 #include "opt_inet.h" 64 65 #include <sys/param.h> 66 #include <sys/systm.h> 67 #include <sys/callout.h> 68 #include <sys/kernel.h> 69 #include <sys/errno.h> 70 #include <sys/ioctl.h> 71 #include <sys/mbuf.h> 72 #include <sys/socket.h> 73 #include <sys/syslog.h> 74 #include <sys/device.h> 75 #include <sys/malloc.h> 76 77 #include <net/if.h> 78 #include <net/if_dl.h> 79 #include <net/if_types.h> 80 #include <net/netisr.h> 81 #include <net/if_media.h> 82 #include <net/if_ether.h> 83 84 #ifdef INET 85 #include <netinet/in.h> 86 #include <netinet/if_inarp.h> 87 #include <netinet/in_systm.h> 88 #include <netinet/in_var.h> 89 #include <netinet/ip.h> 90 #endif 91 92 93 #include <net/bpf.h> 94 #include <net/bpfdesc.h> 95 96 #include <sys/bus.h> 97 #include <sys/intr.h> 98 #include <machine/autoconf.h> 99 100 #include <dev/sbus/sbusvar.h> 101 102 #include <dev/mii/mii.h> 103 #include <dev/mii/miivar.h> 104 105 #include <dev/sbus/qecreg.h> 106 #include <dev/sbus/qecvar.h> 107 #include <dev/sbus/bereg.h> 108 109 struct be_softc { 110 device_t sc_dev; 111 bus_space_tag_t sc_bustag; /* bus & DMA tags */ 112 bus_dma_tag_t sc_dmatag; 113 bus_dmamap_t sc_dmamap; 114 struct ethercom sc_ethercom; 115 /*struct ifmedia sc_ifmedia; -* interface media */ 116 struct mii_data sc_mii; /* MII media control */ 117 #define sc_media sc_mii.mii_media/* shorthand */ 118 int sc_phys[2]; /* MII instance -> phy */ 119 120 struct callout sc_tick_ch; 121 122 /* 123 * Some `mii_softc' items we need to emulate MII operation 124 * for our internal transceiver. 125 */ 126 int sc_mii_inst; /* instance of internal phy */ 127 int sc_mii_active; /* currently active medium */ 128 int sc_mii_ticks; /* tick counter */ 129 int sc_mii_flags; /* phy status flags */ 130 #define MIIF_HAVELINK 0x04000000 131 int sc_intphy_curspeed; /* Established link speed */ 132 133 struct qec_softc *sc_qec; /* QEC parent */ 134 135 bus_space_handle_t sc_qr; /* QEC registers */ 136 bus_space_handle_t sc_br; /* BE registers */ 137 bus_space_handle_t sc_cr; /* channel registers */ 138 bus_space_handle_t sc_tr; /* transceiver registers */ 139 140 u_int sc_rev; 141 142 int sc_channel; /* channel number */ 143 int sc_burst; 144 145 struct qec_ring sc_rb; /* Packet Ring Buffer */ 146 147 /* MAC address */ 148 uint8_t sc_enaddr[ETHER_ADDR_LEN]; 149 #ifdef BEDEBUG 150 int sc_debug; 151 #endif 152 }; 153 154 static int bematch(device_t, cfdata_t, void *); 155 static void beattach(device_t, device_t, void *); 156 157 static int beinit(struct ifnet *); 158 static void bestart(struct ifnet *); 159 static void bestop(struct ifnet *, int); 160 static void bewatchdog(struct ifnet *); 161 static int beioctl(struct ifnet *, u_long, void *); 162 static void bereset(struct be_softc *); 163 static void behwreset(struct be_softc *); 164 165 static int beintr(void *); 166 static int berint(struct be_softc *); 167 static int betint(struct be_softc *); 168 static int beqint(struct be_softc *, uint32_t); 169 static int beeint(struct be_softc *, uint32_t); 170 171 static void be_read(struct be_softc *, int, int); 172 static int be_put(struct be_softc *, int, struct mbuf *); 173 static struct mbuf *be_get(struct be_softc *, int, int); 174 175 static void be_pal_gate(struct be_softc *, int); 176 177 /* ifmedia callbacks */ 178 static void be_ifmedia_sts(struct ifnet *, struct ifmediareq *); 179 static int be_ifmedia_upd(struct ifnet *); 180 181 static void be_mcreset(struct be_softc *); 182 183 /* MII methods & callbacks */ 184 static int be_mii_readreg(device_t, int, int); 185 static void be_mii_writereg(device_t, int, int, int); 186 static void be_mii_statchg(struct ifnet *); 187 188 /* MII helpers */ 189 static void be_mii_sync(struct be_softc *); 190 static void be_mii_sendbits(struct be_softc *, int, uint32_t, int); 191 static int be_mii_reset(struct be_softc *, int); 192 static int be_tcvr_read_bit(struct be_softc *, int); 193 static void be_tcvr_write_bit(struct be_softc *, int, int); 194 195 static void be_tick(void *); 196 #if 0 197 static void be_intphy_auto(struct be_softc *); 198 #endif 199 static void be_intphy_status(struct be_softc *); 200 static int be_intphy_service(struct be_softc *, struct mii_data *, int); 201 202 203 CFATTACH_DECL_NEW(be, sizeof(struct be_softc), 204 bematch, beattach, NULL, NULL); 205 206 int 207 bematch(device_t parent, cfdata_t cf, void *aux) 208 { 209 struct sbus_attach_args *sa = aux; 210 211 return strcmp(cf->cf_name, sa->sa_name) == 0; 212 } 213 214 void 215 beattach(device_t parent, device_t self, void *aux) 216 { 217 struct sbus_attach_args *sa = aux; 218 struct qec_softc *qec = device_private(parent); 219 struct be_softc *sc = device_private(self); 220 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 221 struct mii_data *mii = &sc->sc_mii; 222 struct mii_softc *child; 223 int node = sa->sa_node; 224 bus_dma_tag_t dmatag = sa->sa_dmatag; 225 bus_dma_segment_t seg; 226 bus_size_t size; 227 int instance; 228 int rseg, error; 229 uint32_t v; 230 231 sc->sc_dev = self; 232 233 if (sa->sa_nreg < 3) { 234 printf(": only %d register sets\n", sa->sa_nreg); 235 return; 236 } 237 238 if (bus_space_map(sa->sa_bustag, 239 (bus_addr_t)BUS_ADDR(sa->sa_reg[0].oa_space, sa->sa_reg[0].oa_base), 240 (bus_size_t)sa->sa_reg[0].oa_size, 241 0, &sc->sc_cr) != 0) { 242 printf(": cannot map registers\n"); 243 return; 244 } 245 246 if (bus_space_map(sa->sa_bustag, 247 (bus_addr_t)BUS_ADDR(sa->sa_reg[1].oa_space, sa->sa_reg[1].oa_base), 248 (bus_size_t)sa->sa_reg[1].oa_size, 249 0, &sc->sc_br) != 0) { 250 printf(": cannot map registers\n"); 251 return; 252 } 253 254 if (bus_space_map(sa->sa_bustag, 255 (bus_addr_t)BUS_ADDR(sa->sa_reg[2].oa_space, sa->sa_reg[2].oa_base), 256 (bus_size_t)sa->sa_reg[2].oa_size, 257 0, &sc->sc_tr) != 0) { 258 printf(": cannot map registers\n"); 259 return; 260 } 261 262 sc->sc_bustag = sa->sa_bustag; 263 sc->sc_qec = qec; 264 sc->sc_qr = qec->sc_regs; 265 266 sc->sc_rev = prom_getpropint(node, "board-version", -1); 267 printf(": rev %x,", sc->sc_rev); 268 269 callout_init(&sc->sc_tick_ch, 0); 270 271 sc->sc_channel = prom_getpropint(node, "channel#", -1); 272 if (sc->sc_channel == -1) 273 sc->sc_channel = 0; 274 275 sc->sc_burst = prom_getpropint(node, "burst-sizes", -1); 276 if (sc->sc_burst == -1) 277 sc->sc_burst = qec->sc_burst; 278 279 /* Clamp at parent's burst sizes */ 280 sc->sc_burst &= qec->sc_burst; 281 282 /* Establish interrupt handler */ 283 if (sa->sa_nintr) 284 (void)bus_intr_establish(sa->sa_bustag, sa->sa_pri, IPL_NET, 285 beintr, sc); 286 287 prom_getether(node, sc->sc_enaddr); 288 printf(" address %s\n", ether_sprintf(sc->sc_enaddr)); 289 290 /* 291 * Allocate descriptor ring and buffers. 292 */ 293 294 /* for now, allocate as many bufs as there are ring descriptors */ 295 sc->sc_rb.rb_ntbuf = QEC_XD_RING_MAXSIZE; 296 sc->sc_rb.rb_nrbuf = QEC_XD_RING_MAXSIZE; 297 298 size = 299 QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd) + 300 QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd) + 301 sc->sc_rb.rb_ntbuf * BE_PKT_BUF_SZ + 302 sc->sc_rb.rb_nrbuf * BE_PKT_BUF_SZ; 303 304 /* Get a DMA handle */ 305 if ((error = bus_dmamap_create(dmatag, size, 1, size, 0, 306 BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) { 307 aprint_error_dev(self, "DMA map create error %d\n", error); 308 return; 309 } 310 311 /* Allocate DMA buffer */ 312 if ((error = bus_dmamem_alloc(sa->sa_dmatag, size, 0, 0, 313 &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 314 aprint_error_dev(self, "DMA buffer alloc error %d\n", error); 315 return; 316 } 317 318 /* Map DMA memory in CPU addressable space */ 319 if ((error = bus_dmamem_map(sa->sa_dmatag, &seg, rseg, size, 320 &sc->sc_rb.rb_membase, BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 321 aprint_error_dev(self, "DMA buffer map error %d\n", error); 322 bus_dmamem_free(sa->sa_dmatag, &seg, rseg); 323 return; 324 } 325 326 /* Load the buffer */ 327 if ((error = bus_dmamap_load(dmatag, sc->sc_dmamap, 328 sc->sc_rb.rb_membase, size, NULL, BUS_DMA_NOWAIT)) != 0) { 329 aprint_error_dev(self, "DMA buffer map load error %d\n", error); 330 bus_dmamem_unmap(dmatag, sc->sc_rb.rb_membase, size); 331 bus_dmamem_free(dmatag, &seg, rseg); 332 return; 333 } 334 sc->sc_rb.rb_dmabase = sc->sc_dmamap->dm_segs[0].ds_addr; 335 336 /* 337 * Initialize our media structures and MII info. 338 */ 339 mii->mii_ifp = ifp; 340 mii->mii_readreg = be_mii_readreg; 341 mii->mii_writereg = be_mii_writereg; 342 mii->mii_statchg = be_mii_statchg; 343 344 ifmedia_init(&mii->mii_media, 0, be_ifmedia_upd, be_ifmedia_sts); 345 346 /* 347 * Initialize transceiver and determine which PHY connection to use. 348 */ 349 be_mii_sync(sc); 350 v = bus_space_read_4(sc->sc_bustag, sc->sc_tr, BE_TRI_MGMTPAL); 351 352 instance = 0; 353 354 if ((v & MGMT_PAL_EXT_MDIO) != 0) { 355 356 mii_attach(self, mii, 0xffffffff, BE_PHY_EXTERNAL, 357 MII_OFFSET_ANY, 0); 358 359 child = LIST_FIRST(&mii->mii_phys); 360 if (child == NULL) { 361 /* No PHY attached */ 362 ifmedia_add(&sc->sc_media, 363 IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, instance), 364 0, NULL); 365 ifmedia_set(&sc->sc_media, 366 IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, instance)); 367 } else { 368 /* 369 * Note: we support just one PHY on the external 370 * MII connector. 371 */ 372 #ifdef DIAGNOSTIC 373 if (LIST_NEXT(child, mii_list) != NULL) { 374 aprint_error_dev(self, 375 "spurious MII device %s attached\n", 376 device_xname(child->mii_dev)); 377 } 378 #endif 379 if (child->mii_phy != BE_PHY_EXTERNAL || 380 child->mii_inst > 0) { 381 aprint_error_dev(self, 382 "cannot accommodate MII device %s" 383 " at phy %d, instance %d\n", 384 device_xname(child->mii_dev), 385 child->mii_phy, child->mii_inst); 386 } else { 387 sc->sc_phys[instance] = child->mii_phy; 388 } 389 390 /* 391 * XXX - we can really do the following ONLY if the 392 * phy indeed has the auto negotiation capability!! 393 */ 394 ifmedia_set(&sc->sc_media, 395 IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, instance)); 396 397 /* Mark our current media setting */ 398 be_pal_gate(sc, BE_PHY_EXTERNAL); 399 instance++; 400 } 401 402 } 403 404 if ((v & MGMT_PAL_INT_MDIO) != 0) { 405 /* 406 * The be internal phy looks vaguely like MII hardware, 407 * but not enough to be able to use the MII device 408 * layer. Hence, we have to take care of media selection 409 * ourselves. 410 */ 411 412 sc->sc_mii_inst = instance; 413 sc->sc_phys[instance] = BE_PHY_INTERNAL; 414 415 /* Use `ifm_data' to store BMCR bits */ 416 ifmedia_add(&sc->sc_media, 417 IFM_MAKEWORD(IFM_ETHER, IFM_10_T, 0, instance), 418 0, NULL); 419 ifmedia_add(&sc->sc_media, 420 IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, 0, instance), 421 BMCR_S100, NULL); 422 ifmedia_add(&sc->sc_media, 423 IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, instance), 424 0, NULL); 425 426 printf("on-board transceiver at %s: 10baseT, 100baseTX, auto\n", 427 device_xname(self)); 428 429 be_mii_reset(sc, BE_PHY_INTERNAL); 430 /* Only set default medium here if there's no external PHY */ 431 if (instance == 0) { 432 be_pal_gate(sc, BE_PHY_INTERNAL); 433 ifmedia_set(&sc->sc_media, 434 IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, instance)); 435 } else 436 be_mii_writereg(self, 437 BE_PHY_INTERNAL, MII_BMCR, BMCR_ISO); 438 } 439 440 memcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 441 ifp->if_softc = sc; 442 ifp->if_start = bestart; 443 ifp->if_ioctl = beioctl; 444 ifp->if_watchdog = bewatchdog; 445 ifp->if_init = beinit; 446 ifp->if_stop = bestop; 447 ifp->if_flags = 448 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 449 IFQ_SET_READY(&ifp->if_snd); 450 451 /* claim 802.1q capability */ 452 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 453 454 /* Attach the interface. */ 455 if_attach(ifp); 456 ether_ifattach(ifp, sc->sc_enaddr); 457 } 458 459 460 /* 461 * Routine to copy from mbuf chain to transmit buffer in 462 * network buffer memory. 463 */ 464 static inline int 465 be_put(struct be_softc *sc, int idx, struct mbuf *m) 466 { 467 struct mbuf *n; 468 int len, tlen = 0, boff = 0; 469 uint8_t *bp; 470 471 bp = sc->sc_rb.rb_txbuf + (idx % sc->sc_rb.rb_ntbuf) * BE_PKT_BUF_SZ; 472 473 for (; m; m = n) { 474 len = m->m_len; 475 if (len == 0) { 476 n = m_free(m); 477 continue; 478 } 479 memcpy(bp + boff, mtod(m, void *), len); 480 boff += len; 481 tlen += len; 482 n = m_free(m); 483 } 484 return tlen; 485 } 486 487 /* 488 * Pull data off an interface. 489 * Len is the length of data, with local net header stripped. 490 * We copy the data into mbufs. When full cluster sized units are present, 491 * we copy into clusters. 492 */ 493 static inline struct mbuf * 494 be_get(struct be_softc *sc, int idx, int totlen) 495 { 496 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 497 struct mbuf *m; 498 struct mbuf *top, **mp; 499 int len, pad, boff = 0; 500 uint8_t *bp; 501 502 bp = sc->sc_rb.rb_rxbuf + (idx % sc->sc_rb.rb_nrbuf) * BE_PKT_BUF_SZ; 503 504 MGETHDR(m, M_DONTWAIT, MT_DATA); 505 if (m == NULL) 506 return (NULL); 507 m_set_rcvif(m, ifp); 508 m->m_pkthdr.len = totlen; 509 510 pad = ALIGN(sizeof(struct ether_header)) - sizeof(struct ether_header); 511 m->m_data += pad; 512 len = MHLEN - pad; 513 top = NULL; 514 mp = ⊤ 515 516 while (totlen > 0) { 517 if (top) { 518 MGET(m, M_DONTWAIT, MT_DATA); 519 if (m == NULL) { 520 m_freem(top); 521 return (NULL); 522 } 523 len = MLEN; 524 } 525 if (top && totlen >= MINCLSIZE) { 526 MCLGET(m, M_DONTWAIT); 527 if (m->m_flags & M_EXT) 528 len = MCLBYTES; 529 } 530 m->m_len = len = min(totlen, len); 531 memcpy(mtod(m, void *), bp + boff, len); 532 boff += len; 533 totlen -= len; 534 *mp = m; 535 mp = &m->m_next; 536 } 537 538 return top; 539 } 540 541 /* 542 * Pass a packet to the higher levels. 543 */ 544 static inline void 545 be_read(struct be_softc *sc, int idx, int len) 546 { 547 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 548 struct mbuf *m; 549 550 if (len <= sizeof(struct ether_header) || 551 len > ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN) { 552 #ifdef BEDEBUG 553 if (sc->sc_debug) 554 printf("%s: invalid packet size %d; dropping\n", 555 ifp->if_xname, len); 556 #endif 557 ifp->if_ierrors++; 558 return; 559 } 560 561 /* 562 * Pull packet off interface. 563 */ 564 m = be_get(sc, idx, len); 565 if (m == NULL) { 566 ifp->if_ierrors++; 567 return; 568 } 569 570 /* Pass the packet up. */ 571 if_percpuq_enqueue(ifp->if_percpuq, m); 572 } 573 574 /* 575 * Start output on interface. 576 * We make two assumptions here: 577 * 1) that the current priority is set to splnet _before_ this code 578 * is called *and* is returned to the appropriate priority after 579 * return 580 * 2) that the IFF_OACTIVE flag is checked before this code is called 581 * (i.e. that the output part of the interface is idle) 582 */ 583 void 584 bestart(struct ifnet *ifp) 585 { 586 struct be_softc *sc = ifp->if_softc; 587 struct qec_xd *txd = sc->sc_rb.rb_txd; 588 struct mbuf *m; 589 unsigned int bix, len; 590 unsigned int ntbuf = sc->sc_rb.rb_ntbuf; 591 592 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 593 return; 594 595 bix = sc->sc_rb.rb_tdhead; 596 597 for (;;) { 598 IFQ_DEQUEUE(&ifp->if_snd, m); 599 if (m == 0) 600 break; 601 602 /* 603 * If BPF is listening on this interface, let it see the 604 * packet before we commit it to the wire. 605 */ 606 bpf_mtap(ifp, m); 607 608 /* 609 * Copy the mbuf chain into the transmit buffer. 610 */ 611 len = be_put(sc, bix, m); 612 613 /* 614 * Initialize transmit registers and start transmission 615 */ 616 txd[bix].xd_flags = QEC_XD_OWN | QEC_XD_SOP | QEC_XD_EOP | 617 (len & QEC_XD_LENGTH); 618 bus_space_write_4(sc->sc_bustag, sc->sc_cr, 619 BE_CRI_CTRL, BE_CR_CTRL_TWAKEUP); 620 621 if (++bix == QEC_XD_RING_MAXSIZE) 622 bix = 0; 623 624 if (++sc->sc_rb.rb_td_nbusy == ntbuf) { 625 ifp->if_flags |= IFF_OACTIVE; 626 break; 627 } 628 } 629 630 sc->sc_rb.rb_tdhead = bix; 631 } 632 633 void 634 bestop(struct ifnet *ifp, int disable) 635 { 636 struct be_softc *sc = ifp->if_softc; 637 638 callout_stop(&sc->sc_tick_ch); 639 640 /* Down the MII. */ 641 mii_down(&sc->sc_mii); 642 (void)be_intphy_service(sc, &sc->sc_mii, MII_DOWN); 643 644 behwreset(sc); 645 } 646 647 void 648 behwreset(struct be_softc *sc) 649 { 650 int n; 651 bus_space_tag_t t = sc->sc_bustag; 652 bus_space_handle_t br = sc->sc_br; 653 654 /* Stop the transmitter */ 655 bus_space_write_4(t, br, BE_BRI_TXCFG, 0); 656 for (n = 32; n > 0; n--) { 657 if (bus_space_read_4(t, br, BE_BRI_TXCFG) == 0) 658 break; 659 DELAY(20); 660 } 661 662 /* Stop the receiver */ 663 bus_space_write_4(t, br, BE_BRI_RXCFG, 0); 664 for (n = 32; n > 0; n--) { 665 if (bus_space_read_4(t, br, BE_BRI_RXCFG) == 0) 666 break; 667 DELAY(20); 668 } 669 } 670 671 /* 672 * Reset interface. 673 */ 674 void 675 bereset(struct be_softc *sc) 676 { 677 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 678 int s; 679 680 s = splnet(); 681 behwreset(sc); 682 if ((sc->sc_ethercom.ec_if.if_flags & IFF_UP) != 0) 683 beinit(ifp); 684 splx(s); 685 } 686 687 void 688 bewatchdog(struct ifnet *ifp) 689 { 690 struct be_softc *sc = ifp->if_softc; 691 692 log(LOG_ERR, "%s: device timeout\n", device_xname(sc->sc_dev)); 693 ++sc->sc_ethercom.ec_if.if_oerrors; 694 695 bereset(sc); 696 } 697 698 int 699 beintr(void *arg) 700 { 701 struct be_softc *sc = arg; 702 bus_space_tag_t t = sc->sc_bustag; 703 uint32_t whyq, whyb, whyc; 704 int r = 0; 705 706 /* Read QEC status, channel status and BE status */ 707 whyq = bus_space_read_4(t, sc->sc_qr, QEC_QRI_STAT); 708 whyc = bus_space_read_4(t, sc->sc_cr, BE_CRI_STAT); 709 whyb = bus_space_read_4(t, sc->sc_br, BE_BRI_STAT); 710 711 if (whyq & QEC_STAT_BM) 712 r |= beeint(sc, whyb); 713 714 if (whyq & QEC_STAT_ER) 715 r |= beqint(sc, whyc); 716 717 if (whyq & QEC_STAT_TX && whyc & BE_CR_STAT_TXIRQ) 718 r |= betint(sc); 719 720 if (whyq & QEC_STAT_RX && whyc & BE_CR_STAT_RXIRQ) 721 r |= berint(sc); 722 723 return r; 724 } 725 726 /* 727 * QEC Interrupt. 728 */ 729 int 730 beqint(struct be_softc *sc, uint32_t why) 731 { 732 device_t self = sc->sc_dev; 733 int r = 0, rst = 0; 734 735 if (why & BE_CR_STAT_TXIRQ) 736 r |= 1; 737 if (why & BE_CR_STAT_RXIRQ) 738 r |= 1; 739 740 if (why & BE_CR_STAT_BERROR) { 741 r |= 1; 742 rst = 1; 743 aprint_error_dev(self, "bigmac error\n"); 744 } 745 746 if (why & BE_CR_STAT_TXDERR) { 747 r |= 1; 748 rst = 1; 749 aprint_error_dev(self, "bogus tx descriptor\n"); 750 } 751 752 if (why & (BE_CR_STAT_TXLERR | BE_CR_STAT_TXPERR | BE_CR_STAT_TXSERR)) { 753 r |= 1; 754 rst = 1; 755 aprint_error_dev(self, "tx DMA error ( "); 756 if (why & BE_CR_STAT_TXLERR) 757 printf("Late "); 758 if (why & BE_CR_STAT_TXPERR) 759 printf("Parity "); 760 if (why & BE_CR_STAT_TXSERR) 761 printf("Generic "); 762 printf(")\n"); 763 } 764 765 if (why & BE_CR_STAT_RXDROP) { 766 r |= 1; 767 rst = 1; 768 aprint_error_dev(self, "out of rx descriptors\n"); 769 } 770 771 if (why & BE_CR_STAT_RXSMALL) { 772 r |= 1; 773 rst = 1; 774 aprint_error_dev(self, "rx descriptor too small\n"); 775 } 776 777 if (why & (BE_CR_STAT_RXLERR | BE_CR_STAT_RXPERR | BE_CR_STAT_RXSERR)) { 778 r |= 1; 779 rst = 1; 780 aprint_error_dev(self, "rx DMA error ( "); 781 if (why & BE_CR_STAT_RXLERR) 782 printf("Late "); 783 if (why & BE_CR_STAT_RXPERR) 784 printf("Parity "); 785 if (why & BE_CR_STAT_RXSERR) 786 printf("Generic "); 787 printf(")\n"); 788 } 789 790 if (!r) { 791 rst = 1; 792 aprint_error_dev(self, "unexpected error interrupt %08x\n", 793 why); 794 } 795 796 if (rst) { 797 printf("%s: resetting\n", device_xname(self)); 798 bereset(sc); 799 } 800 801 return r; 802 } 803 804 /* 805 * Error interrupt. 806 */ 807 int 808 beeint(struct be_softc *sc, uint32_t why) 809 { 810 device_t self = sc->sc_dev; 811 int r = 0, rst = 0; 812 813 if (why & BE_BR_STAT_RFIFOVF) { 814 r |= 1; 815 rst = 1; 816 aprint_error_dev(self, "receive fifo overrun\n"); 817 } 818 if (why & BE_BR_STAT_TFIFO_UND) { 819 r |= 1; 820 rst = 1; 821 aprint_error_dev(self, "transmit fifo underrun\n"); 822 } 823 if (why & BE_BR_STAT_MAXPKTERR) { 824 r |= 1; 825 rst = 1; 826 aprint_error_dev(self, "max packet size error\n"); 827 } 828 829 if (!r) { 830 rst = 1; 831 aprint_error_dev(self, "unexpected error interrupt %08x\n", 832 why); 833 } 834 835 if (rst) { 836 printf("%s: resetting\n", device_xname(self)); 837 bereset(sc); 838 } 839 840 return r; 841 } 842 843 /* 844 * Transmit interrupt. 845 */ 846 int 847 betint(struct be_softc *sc) 848 { 849 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 850 bus_space_tag_t t = sc->sc_bustag; 851 bus_space_handle_t br = sc->sc_br; 852 unsigned int bix, txflags; 853 854 /* 855 * Unload collision counters 856 */ 857 ifp->if_collisions += 858 bus_space_read_4(t, br, BE_BRI_NCCNT) + 859 bus_space_read_4(t, br, BE_BRI_FCCNT) + 860 bus_space_read_4(t, br, BE_BRI_EXCNT) + 861 bus_space_read_4(t, br, BE_BRI_LTCNT); 862 863 /* 864 * the clear the hardware counters 865 */ 866 bus_space_write_4(t, br, BE_BRI_NCCNT, 0); 867 bus_space_write_4(t, br, BE_BRI_FCCNT, 0); 868 bus_space_write_4(t, br, BE_BRI_EXCNT, 0); 869 bus_space_write_4(t, br, BE_BRI_LTCNT, 0); 870 871 bix = sc->sc_rb.rb_tdtail; 872 873 for (;;) { 874 if (sc->sc_rb.rb_td_nbusy <= 0) 875 break; 876 877 txflags = sc->sc_rb.rb_txd[bix].xd_flags; 878 879 if (txflags & QEC_XD_OWN) 880 break; 881 882 ifp->if_flags &= ~IFF_OACTIVE; 883 ifp->if_opackets++; 884 885 if (++bix == QEC_XD_RING_MAXSIZE) 886 bix = 0; 887 888 --sc->sc_rb.rb_td_nbusy; 889 } 890 891 sc->sc_rb.rb_tdtail = bix; 892 893 bestart(ifp); 894 895 if (sc->sc_rb.rb_td_nbusy == 0) 896 ifp->if_timer = 0; 897 898 return 1; 899 } 900 901 /* 902 * Receive interrupt. 903 */ 904 int 905 berint(struct be_softc *sc) 906 { 907 struct qec_xd *xd = sc->sc_rb.rb_rxd; 908 unsigned int bix, len; 909 unsigned int nrbuf = sc->sc_rb.rb_nrbuf; 910 911 bix = sc->sc_rb.rb_rdtail; 912 913 /* 914 * Process all buffers with valid data. 915 */ 916 for (;;) { 917 len = xd[bix].xd_flags; 918 if (len & QEC_XD_OWN) 919 break; 920 921 len &= QEC_XD_LENGTH; 922 be_read(sc, bix, len); 923 924 /* ... */ 925 xd[(bix+nrbuf) % QEC_XD_RING_MAXSIZE].xd_flags = 926 QEC_XD_OWN | (BE_PKT_BUF_SZ & QEC_XD_LENGTH); 927 928 if (++bix == QEC_XD_RING_MAXSIZE) 929 bix = 0; 930 } 931 932 sc->sc_rb.rb_rdtail = bix; 933 934 return 1; 935 } 936 937 int 938 beioctl(struct ifnet *ifp, u_long cmd, void *data) 939 { 940 struct be_softc *sc = ifp->if_softc; 941 struct ifaddr *ifa = data; 942 struct ifreq *ifr = data; 943 int s, error = 0; 944 945 s = splnet(); 946 947 switch (cmd) { 948 case SIOCINITIFADDR: 949 ifp->if_flags |= IFF_UP; 950 beinit(ifp); 951 switch (ifa->ifa_addr->sa_family) { 952 #ifdef INET 953 case AF_INET: 954 arp_ifinit(ifp, ifa); 955 break; 956 #endif /* INET */ 957 default: 958 break; 959 } 960 break; 961 962 case SIOCSIFFLAGS: 963 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 964 break; 965 /* XXX re-use ether_ioctl() */ 966 switch (ifp->if_flags & (IFF_UP|IFF_RUNNING)) { 967 case IFF_RUNNING: 968 /* 969 * If interface is marked down and it is running, then 970 * stop it. 971 */ 972 bestop(ifp, 0); 973 ifp->if_flags &= ~IFF_RUNNING; 974 break; 975 case IFF_UP: 976 /* 977 * If interface is marked up and it is stopped, then 978 * start it. 979 */ 980 beinit(ifp); 981 break; 982 default: 983 /* 984 * Reset the interface to pick up changes in any other 985 * flags that affect hardware registers. 986 */ 987 bestop(ifp, 0); 988 beinit(ifp); 989 break; 990 } 991 #ifdef BEDEBUG 992 if (ifp->if_flags & IFF_DEBUG) 993 sc->sc_debug = 1; 994 else 995 sc->sc_debug = 0; 996 #endif 997 break; 998 999 case SIOCGIFMEDIA: 1000 case SIOCSIFMEDIA: 1001 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd); 1002 break; 1003 default: 1004 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 1005 /* 1006 * Multicast list has changed; set the hardware filter 1007 * accordingly. 1008 */ 1009 if (ifp->if_flags & IFF_RUNNING) 1010 error = beinit(ifp); 1011 else 1012 error = 0; 1013 } 1014 break; 1015 } 1016 splx(s); 1017 return error; 1018 } 1019 1020 1021 int 1022 beinit(struct ifnet *ifp) 1023 { 1024 struct be_softc *sc = ifp->if_softc; 1025 bus_space_tag_t t = sc->sc_bustag; 1026 bus_space_handle_t br = sc->sc_br; 1027 bus_space_handle_t cr = sc->sc_cr; 1028 struct qec_softc *qec = sc->sc_qec; 1029 uint32_t v; 1030 uint32_t qecaddr; 1031 uint8_t *ea; 1032 int rc, s; 1033 1034 s = splnet(); 1035 1036 qec_meminit(&sc->sc_rb, BE_PKT_BUF_SZ); 1037 1038 bestop(ifp, 1); 1039 1040 ea = sc->sc_enaddr; 1041 bus_space_write_4(t, br, BE_BRI_MACADDR0, (ea[0] << 8) | ea[1]); 1042 bus_space_write_4(t, br, BE_BRI_MACADDR1, (ea[2] << 8) | ea[3]); 1043 bus_space_write_4(t, br, BE_BRI_MACADDR2, (ea[4] << 8) | ea[5]); 1044 1045 /* Clear hash table */ 1046 bus_space_write_4(t, br, BE_BRI_HASHTAB0, 0); 1047 bus_space_write_4(t, br, BE_BRI_HASHTAB1, 0); 1048 bus_space_write_4(t, br, BE_BRI_HASHTAB2, 0); 1049 bus_space_write_4(t, br, BE_BRI_HASHTAB3, 0); 1050 1051 /* Re-initialize RX configuration */ 1052 v = BE_BR_RXCFG_FIFO; 1053 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1054 1055 be_mcreset(sc); 1056 1057 bus_space_write_4(t, br, BE_BRI_RANDSEED, 0xbd); 1058 1059 bus_space_write_4(t, br, 1060 BE_BRI_XIFCFG, BE_BR_XCFG_ODENABLE | BE_BR_XCFG_RESV); 1061 1062 bus_space_write_4(t, br, BE_BRI_JSIZE, 4); 1063 1064 /* 1065 * Turn off counter expiration interrupts as well as 1066 * 'gotframe' and 'sentframe' 1067 */ 1068 bus_space_write_4(t, br, BE_BRI_IMASK, 1069 BE_BR_IMASK_GOTFRAME | 1070 BE_BR_IMASK_RCNTEXP | 1071 BE_BR_IMASK_ACNTEXP | 1072 BE_BR_IMASK_CCNTEXP | 1073 BE_BR_IMASK_LCNTEXP | 1074 BE_BR_IMASK_CVCNTEXP | 1075 BE_BR_IMASK_SENTFRAME | 1076 BE_BR_IMASK_NCNTEXP | 1077 BE_BR_IMASK_ECNTEXP | 1078 BE_BR_IMASK_LCCNTEXP | 1079 BE_BR_IMASK_FCNTEXP | 1080 BE_BR_IMASK_DTIMEXP); 1081 1082 /* Channel registers: */ 1083 bus_space_write_4(t, cr, BE_CRI_RXDS, (uint32_t)sc->sc_rb.rb_rxddma); 1084 bus_space_write_4(t, cr, BE_CRI_TXDS, (uint32_t)sc->sc_rb.rb_txddma); 1085 1086 qecaddr = sc->sc_channel * qec->sc_msize; 1087 bus_space_write_4(t, cr, BE_CRI_RXWBUF, qecaddr); 1088 bus_space_write_4(t, cr, BE_CRI_RXRBUF, qecaddr); 1089 bus_space_write_4(t, cr, BE_CRI_TXWBUF, qecaddr + qec->sc_rsize); 1090 bus_space_write_4(t, cr, BE_CRI_TXRBUF, qecaddr + qec->sc_rsize); 1091 1092 bus_space_write_4(t, cr, BE_CRI_RIMASK, 0); 1093 bus_space_write_4(t, cr, BE_CRI_TIMASK, 0); 1094 bus_space_write_4(t, cr, BE_CRI_QMASK, 0); 1095 bus_space_write_4(t, cr, BE_CRI_BMASK, 0); 1096 bus_space_write_4(t, cr, BE_CRI_CCNT, 0); 1097 1098 /* Set max packet length */ 1099 v = ETHER_MAX_LEN; 1100 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) 1101 v += ETHER_VLAN_ENCAP_LEN; 1102 bus_space_write_4(t, br, BE_BRI_RXMAX, v); 1103 bus_space_write_4(t, br, BE_BRI_TXMAX, v); 1104 1105 /* Enable transmitter */ 1106 bus_space_write_4(t, br, 1107 BE_BRI_TXCFG, BE_BR_TXCFG_FIFO | BE_BR_TXCFG_ENABLE); 1108 1109 /* Enable receiver */ 1110 v = bus_space_read_4(t, br, BE_BRI_RXCFG); 1111 v |= BE_BR_RXCFG_FIFO | BE_BR_RXCFG_ENABLE; 1112 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1113 1114 if ((rc = be_ifmedia_upd(ifp)) != 0) 1115 goto out; 1116 1117 ifp->if_flags |= IFF_RUNNING; 1118 ifp->if_flags &= ~IFF_OACTIVE; 1119 1120 callout_reset(&sc->sc_tick_ch, hz, be_tick, sc); 1121 1122 splx(s); 1123 return 0; 1124 out: 1125 splx(s); 1126 return rc; 1127 } 1128 1129 void 1130 be_mcreset(struct be_softc *sc) 1131 { 1132 struct ethercom *ec = &sc->sc_ethercom; 1133 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1134 bus_space_tag_t t = sc->sc_bustag; 1135 bus_space_handle_t br = sc->sc_br; 1136 uint32_t v; 1137 uint32_t crc; 1138 uint16_t hash[4]; 1139 struct ether_multi *enm; 1140 struct ether_multistep step; 1141 1142 if (ifp->if_flags & IFF_PROMISC) { 1143 v = bus_space_read_4(t, br, BE_BRI_RXCFG); 1144 v |= BE_BR_RXCFG_PMISC; 1145 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1146 return; 1147 } 1148 1149 if (ifp->if_flags & IFF_ALLMULTI) { 1150 hash[3] = hash[2] = hash[1] = hash[0] = 0xffff; 1151 goto chipit; 1152 } 1153 1154 hash[3] = hash[2] = hash[1] = hash[0] = 0; 1155 1156 ETHER_FIRST_MULTI(step, ec, enm); 1157 while (enm != NULL) { 1158 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1159 /* 1160 * We must listen to a range of multicast 1161 * addresses. For now, just accept all 1162 * multicasts, rather than trying to set only 1163 * those filter bits needed to match the range. 1164 * (At this time, the only use of address 1165 * ranges is for IP multicast routing, for 1166 * which the range is big enough to require 1167 * all bits set.) 1168 */ 1169 hash[3] = hash[2] = hash[1] = hash[0] = 0xffff; 1170 ifp->if_flags |= IFF_ALLMULTI; 1171 goto chipit; 1172 } 1173 1174 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 1175 /* Just want the 6 most significant bits. */ 1176 crc >>= 26; 1177 1178 hash[crc >> 4] |= 1 << (crc & 0xf); 1179 ETHER_NEXT_MULTI(step, enm); 1180 } 1181 1182 ifp->if_flags &= ~IFF_ALLMULTI; 1183 1184 chipit: 1185 /* Enable the hash filter */ 1186 bus_space_write_4(t, br, BE_BRI_HASHTAB0, hash[0]); 1187 bus_space_write_4(t, br, BE_BRI_HASHTAB1, hash[1]); 1188 bus_space_write_4(t, br, BE_BRI_HASHTAB2, hash[2]); 1189 bus_space_write_4(t, br, BE_BRI_HASHTAB3, hash[3]); 1190 1191 v = bus_space_read_4(t, br, BE_BRI_RXCFG); 1192 v &= ~BE_BR_RXCFG_PMISC; 1193 v |= BE_BR_RXCFG_HENABLE; 1194 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1195 } 1196 1197 /* 1198 * Set the tcvr to an idle state 1199 */ 1200 void 1201 be_mii_sync(struct be_softc *sc) 1202 { 1203 bus_space_tag_t t = sc->sc_bustag; 1204 bus_space_handle_t tr = sc->sc_tr; 1205 int n = 32; 1206 1207 while (n--) { 1208 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, 1209 MGMT_PAL_INT_MDIO | MGMT_PAL_EXT_MDIO | MGMT_PAL_OENAB); 1210 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1211 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, 1212 MGMT_PAL_INT_MDIO | MGMT_PAL_EXT_MDIO | 1213 MGMT_PAL_OENAB | MGMT_PAL_DCLOCK); 1214 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1215 } 1216 } 1217 1218 void 1219 be_pal_gate(struct be_softc *sc, int phy) 1220 { 1221 bus_space_tag_t t = sc->sc_bustag; 1222 bus_space_handle_t tr = sc->sc_tr; 1223 uint32_t v; 1224 1225 be_mii_sync(sc); 1226 1227 v = ~(TCVR_PAL_EXTLBACK | TCVR_PAL_MSENSE | TCVR_PAL_LTENABLE); 1228 if (phy == BE_PHY_INTERNAL) 1229 v &= ~TCVR_PAL_SERIAL; 1230 1231 bus_space_write_4(t, tr, BE_TRI_TCVRPAL, v); 1232 (void)bus_space_read_4(t, tr, BE_TRI_TCVRPAL); 1233 } 1234 1235 static int 1236 be_tcvr_read_bit(struct be_softc *sc, int phy) 1237 { 1238 bus_space_tag_t t = sc->sc_bustag; 1239 bus_space_handle_t tr = sc->sc_tr; 1240 int ret; 1241 1242 if (phy == BE_PHY_INTERNAL) { 1243 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, MGMT_PAL_EXT_MDIO); 1244 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1245 bus_space_write_4(t, tr, 1246 BE_TRI_MGMTPAL, MGMT_PAL_EXT_MDIO | MGMT_PAL_DCLOCK); 1247 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1248 ret = (bus_space_read_4(t, tr, BE_TRI_MGMTPAL) & 1249 MGMT_PAL_INT_MDIO) >> MGMT_PAL_INT_MDIO_SHIFT; 1250 } else { 1251 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, MGMT_PAL_INT_MDIO); 1252 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1253 ret = (bus_space_read_4(t, tr, BE_TRI_MGMTPAL) & 1254 MGMT_PAL_EXT_MDIO) >> MGMT_PAL_EXT_MDIO_SHIFT; 1255 bus_space_write_4(t, tr, 1256 BE_TRI_MGMTPAL, MGMT_PAL_INT_MDIO | MGMT_PAL_DCLOCK); 1257 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1258 } 1259 1260 return ret; 1261 } 1262 1263 static void 1264 be_tcvr_write_bit(struct be_softc *sc, int phy, int bit) 1265 { 1266 bus_space_tag_t t = sc->sc_bustag; 1267 bus_space_handle_t tr = sc->sc_tr; 1268 uint32_t v; 1269 1270 if (phy == BE_PHY_INTERNAL) { 1271 v = ((bit & 1) << MGMT_PAL_INT_MDIO_SHIFT) | 1272 MGMT_PAL_OENAB | MGMT_PAL_EXT_MDIO; 1273 } else { 1274 v = ((bit & 1) << MGMT_PAL_EXT_MDIO_SHIFT) | 1275 MGMT_PAL_OENAB | MGMT_PAL_INT_MDIO; 1276 } 1277 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, v); 1278 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1279 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, v | MGMT_PAL_DCLOCK); 1280 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1281 } 1282 1283 static void 1284 be_mii_sendbits(struct be_softc *sc, int phy, uint32_t data, int nbits) 1285 { 1286 int i; 1287 1288 for (i = 1 << (nbits - 1); i != 0; i >>= 1) { 1289 be_tcvr_write_bit(sc, phy, (data & i) != 0); 1290 } 1291 } 1292 1293 static int 1294 be_mii_readreg(device_t self, int phy, int reg) 1295 { 1296 struct be_softc *sc = device_private(self); 1297 int val = 0, i; 1298 1299 /* 1300 * Read the PHY register by manually driving the MII control lines. 1301 */ 1302 be_mii_sync(sc); 1303 be_mii_sendbits(sc, phy, MII_COMMAND_START, 2); 1304 be_mii_sendbits(sc, phy, MII_COMMAND_READ, 2); 1305 be_mii_sendbits(sc, phy, phy, 5); 1306 be_mii_sendbits(sc, phy, reg, 5); 1307 1308 (void)be_tcvr_read_bit(sc, phy); 1309 (void)be_tcvr_read_bit(sc, phy); 1310 1311 for (i = 15; i >= 0; i--) 1312 val |= (be_tcvr_read_bit(sc, phy) << i); 1313 1314 (void)be_tcvr_read_bit(sc, phy); 1315 (void)be_tcvr_read_bit(sc, phy); 1316 (void)be_tcvr_read_bit(sc, phy); 1317 1318 return val; 1319 } 1320 1321 void 1322 be_mii_writereg(device_t self, int phy, int reg, int val) 1323 { 1324 struct be_softc *sc = device_private(self); 1325 int i; 1326 1327 /* 1328 * Write the PHY register by manually driving the MII control lines. 1329 */ 1330 be_mii_sync(sc); 1331 be_mii_sendbits(sc, phy, MII_COMMAND_START, 2); 1332 be_mii_sendbits(sc, phy, MII_COMMAND_WRITE, 2); 1333 be_mii_sendbits(sc, phy, phy, 5); 1334 be_mii_sendbits(sc, phy, reg, 5); 1335 1336 be_tcvr_write_bit(sc, phy, 1); 1337 be_tcvr_write_bit(sc, phy, 0); 1338 1339 for (i = 15; i >= 0; i--) 1340 be_tcvr_write_bit(sc, phy, (val >> i) & 1); 1341 } 1342 1343 int 1344 be_mii_reset(struct be_softc *sc, int phy) 1345 { 1346 device_t self = sc->sc_dev; 1347 int n; 1348 1349 be_mii_writereg(self, phy, MII_BMCR, BMCR_LOOP | BMCR_PDOWN | BMCR_ISO); 1350 be_mii_writereg(self, phy, MII_BMCR, BMCR_RESET); 1351 1352 for (n = 16; n >= 0; n--) { 1353 int bmcr = be_mii_readreg(self, phy, MII_BMCR); 1354 if ((bmcr & BMCR_RESET) == 0) 1355 break; 1356 DELAY(20); 1357 } 1358 if (n == 0) { 1359 aprint_error_dev(self, "bmcr reset failed\n"); 1360 return EIO; 1361 } 1362 1363 return 0; 1364 } 1365 1366 void 1367 be_tick(void *arg) 1368 { 1369 struct be_softc *sc = arg; 1370 int s = splnet(); 1371 1372 mii_tick(&sc->sc_mii); 1373 (void)be_intphy_service(sc, &sc->sc_mii, MII_TICK); 1374 1375 splx(s); 1376 callout_reset(&sc->sc_tick_ch, hz, be_tick, sc); 1377 } 1378 1379 void 1380 be_mii_statchg(struct ifnet *ifp) 1381 { 1382 struct be_softc *sc = ifp->if_softc; 1383 bus_space_tag_t t = sc->sc_bustag; 1384 bus_space_handle_t br = sc->sc_br; 1385 uint instance; 1386 uint32_t v; 1387 1388 instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media); 1389 #ifdef DIAGNOSTIC 1390 if (instance > 1) 1391 panic("be_mii_statchg: instance %d out of range", instance); 1392 #endif 1393 1394 /* Update duplex mode in TX configuration */ 1395 v = bus_space_read_4(t, br, BE_BRI_TXCFG); 1396 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 1397 v |= BE_BR_TXCFG_FULLDPLX; 1398 else 1399 v &= ~BE_BR_TXCFG_FULLDPLX; 1400 bus_space_write_4(t, br, BE_BRI_TXCFG, v); 1401 1402 /* Change to appropriate gate in transceiver PAL */ 1403 be_pal_gate(sc, sc->sc_phys[instance]); 1404 } 1405 1406 /* 1407 * Get current media settings. 1408 */ 1409 void 1410 be_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1411 { 1412 struct be_softc *sc = ifp->if_softc; 1413 1414 mii_pollstat(&sc->sc_mii); 1415 (void)be_intphy_service(sc, &sc->sc_mii, MII_POLLSTAT); 1416 1417 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1418 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1419 } 1420 1421 /* 1422 * Set media options. 1423 */ 1424 int 1425 be_ifmedia_upd(struct ifnet *ifp) 1426 { 1427 struct be_softc *sc = ifp->if_softc; 1428 int error; 1429 1430 if ((error = mii_mediachg(&sc->sc_mii)) == ENXIO) 1431 error = 0; 1432 else if (error != 0) 1433 return error; 1434 1435 return be_intphy_service(sc, &sc->sc_mii, MII_MEDIACHG); 1436 } 1437 1438 /* 1439 * Service routine for our pseudo-MII internal transceiver. 1440 */ 1441 int 1442 be_intphy_service(struct be_softc *sc, struct mii_data *mii, int cmd) 1443 { 1444 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 1445 device_t self = sc->sc_dev; 1446 int bmcr, bmsr; 1447 int error; 1448 1449 switch (cmd) { 1450 case MII_POLLSTAT: 1451 /* 1452 * If we're not polling our PHY instance, just return. 1453 */ 1454 if (IFM_INST(ife->ifm_media) != sc->sc_mii_inst) 1455 return 0; 1456 1457 break; 1458 1459 case MII_MEDIACHG: 1460 1461 /* 1462 * If the media indicates a different PHY instance, 1463 * isolate ourselves. 1464 */ 1465 if (IFM_INST(ife->ifm_media) != sc->sc_mii_inst) { 1466 bmcr = be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMCR); 1467 be_mii_writereg(self, 1468 BE_PHY_INTERNAL, MII_BMCR, bmcr | BMCR_ISO); 1469 sc->sc_mii_flags &= ~MIIF_HAVELINK; 1470 sc->sc_intphy_curspeed = 0; 1471 return 0; 1472 } 1473 1474 1475 if ((error = be_mii_reset(sc, BE_PHY_INTERNAL)) != 0) 1476 return error; 1477 1478 bmcr = be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMCR); 1479 1480 /* 1481 * Select the new mode and take out of isolation 1482 */ 1483 if (IFM_SUBTYPE(ife->ifm_media) == IFM_100_TX) 1484 bmcr |= BMCR_S100; 1485 else if (IFM_SUBTYPE(ife->ifm_media) == IFM_10_T) 1486 bmcr &= ~BMCR_S100; 1487 else if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) { 1488 if ((sc->sc_mii_flags & MIIF_HAVELINK) != 0) { 1489 bmcr &= ~BMCR_S100; 1490 bmcr |= sc->sc_intphy_curspeed; 1491 } else { 1492 /* Keep isolated until link is up */ 1493 bmcr |= BMCR_ISO; 1494 sc->sc_mii_flags |= MIIF_DOINGAUTO; 1495 } 1496 } 1497 1498 if ((IFM_OPTIONS(ife->ifm_media) & IFM_FDX) != 0) 1499 bmcr |= BMCR_FDX; 1500 else 1501 bmcr &= ~BMCR_FDX; 1502 1503 be_mii_writereg(self, BE_PHY_INTERNAL, MII_BMCR, bmcr); 1504 break; 1505 1506 case MII_TICK: 1507 /* 1508 * If we're not currently selected, just return. 1509 */ 1510 if (IFM_INST(ife->ifm_media) != sc->sc_mii_inst) 1511 return 0; 1512 1513 /* Is the interface even up? */ 1514 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 1515 return 0; 1516 1517 /* Only used for automatic media selection */ 1518 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) 1519 break; 1520 1521 /* 1522 * Check link status; if we don't have a link, try another 1523 * speed. We can't detect duplex mode, so half-duplex is 1524 * what we have to settle for. 1525 */ 1526 1527 /* Read twice in case the register is latched */ 1528 bmsr = 1529 be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMSR) | 1530 be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMSR); 1531 1532 if ((bmsr & BMSR_LINK) != 0) { 1533 /* We have a carrier */ 1534 bmcr = be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMCR); 1535 1536 if ((sc->sc_mii_flags & MIIF_DOINGAUTO) != 0) { 1537 bmcr = be_mii_readreg(self, 1538 BE_PHY_INTERNAL, MII_BMCR); 1539 1540 sc->sc_mii_flags |= MIIF_HAVELINK; 1541 sc->sc_intphy_curspeed = (bmcr & BMCR_S100); 1542 sc->sc_mii_flags &= ~MIIF_DOINGAUTO; 1543 1544 bmcr &= ~BMCR_ISO; 1545 be_mii_writereg(self, 1546 BE_PHY_INTERNAL, MII_BMCR, bmcr); 1547 1548 printf("%s: link up at %s Mbps\n", 1549 device_xname(self), 1550 (bmcr & BMCR_S100) ? "100" : "10"); 1551 } 1552 break; 1553 } 1554 1555 if ((sc->sc_mii_flags & MIIF_DOINGAUTO) == 0) { 1556 sc->sc_mii_flags |= MIIF_DOINGAUTO; 1557 sc->sc_mii_flags &= ~MIIF_HAVELINK; 1558 sc->sc_intphy_curspeed = 0; 1559 printf("%s: link down\n", device_xname(self)); 1560 } 1561 1562 /* Only retry autonegotiation every 5 seconds. */ 1563 if (++sc->sc_mii_ticks < 5) 1564 return 0; 1565 1566 sc->sc_mii_ticks = 0; 1567 bmcr = be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMCR); 1568 /* Just flip the fast speed bit */ 1569 bmcr ^= BMCR_S100; 1570 be_mii_writereg(self, BE_PHY_INTERNAL, MII_BMCR, bmcr); 1571 1572 break; 1573 1574 case MII_DOWN: 1575 /* Isolate this phy */ 1576 bmcr = be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMCR); 1577 be_mii_writereg(self, 1578 BE_PHY_INTERNAL, MII_BMCR, bmcr | BMCR_ISO); 1579 return 0; 1580 } 1581 1582 /* Update the media status. */ 1583 be_intphy_status(sc); 1584 1585 /* Callback if something changed. */ 1586 if (sc->sc_mii_active != mii->mii_media_active || cmd == MII_MEDIACHG) { 1587 (*mii->mii_statchg)(mii->mii_ifp); 1588 sc->sc_mii_active = mii->mii_media_active; 1589 } 1590 return 0; 1591 } 1592 1593 /* 1594 * Determine status of internal transceiver 1595 */ 1596 void 1597 be_intphy_status(struct be_softc *sc) 1598 { 1599 struct mii_data *mii = &sc->sc_mii; 1600 device_t self = sc->sc_dev; 1601 int media_active, media_status; 1602 int bmcr, bmsr; 1603 1604 media_status = IFM_AVALID; 1605 media_active = 0; 1606 1607 /* 1608 * Internal transceiver; do the work here. 1609 */ 1610 bmcr = be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMCR); 1611 1612 switch (bmcr & (BMCR_S100 | BMCR_FDX)) { 1613 case (BMCR_S100 | BMCR_FDX): 1614 media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 1615 break; 1616 case BMCR_S100: 1617 media_active = IFM_ETHER | IFM_100_TX | IFM_HDX; 1618 break; 1619 case BMCR_FDX: 1620 media_active = IFM_ETHER | IFM_10_T | IFM_FDX; 1621 break; 1622 case 0: 1623 media_active = IFM_ETHER | IFM_10_T | IFM_HDX; 1624 break; 1625 } 1626 1627 /* Read twice in case the register is latched */ 1628 bmsr = 1629 be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMSR) | 1630 be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMSR); 1631 if (bmsr & BMSR_LINK) 1632 media_status |= IFM_ACTIVE; 1633 1634 mii->mii_media_status = media_status; 1635 mii->mii_media_active = media_active; 1636 } 1637
Indexes created Tue Sep 30 11:09:46 GMT 2025