be.c revision 1.88.2.2
1 /* $NetBSD: be.c,v 1.88.2.2 2020/04/08 14:08:12 martin Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Copyright (c) 1998 Theo de Raadt and Jason L. Wright. 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. The name of the authors may not be used to endorse or promote products 45 * derived from this software without specific prior written permission. 46 * 47 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR 48 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 49 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 50 * IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, 51 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 52 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 53 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 54 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 55 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 56 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 57 */ 58 59 #include <sys/cdefs.h> 60 __KERNEL_RCSID(0, "$NetBSD: be.c,v 1.88.2.2 2020/04/08 14:08:12 martin Exp $"); 61 62 #include "opt_ddb.h" 63 #include "opt_inet.h" 64 65 #include <sys/param.h> 66 #include <sys/systm.h> 67 #include <sys/callout.h> 68 #include <sys/kernel.h> 69 #include <sys/errno.h> 70 #include <sys/ioctl.h> 71 #include <sys/mbuf.h> 72 #include <sys/socket.h> 73 #include <sys/syslog.h> 74 #include <sys/device.h> 75 #include <sys/malloc.h> 76 77 #include <net/if.h> 78 #include <net/if_dl.h> 79 #include <net/if_types.h> 80 #include <net/netisr.h> 81 #include <net/if_media.h> 82 #include <net/if_ether.h> 83 #include <net/bpf.h> 84 85 #ifdef INET 86 #include <netinet/in.h> 87 #include <netinet/if_inarp.h> 88 #include <netinet/in_systm.h> 89 #include <netinet/in_var.h> 90 #include <netinet/ip.h> 91 #endif 92 93 #include <sys/bus.h> 94 #include <sys/intr.h> 95 #include <machine/autoconf.h> 96 97 #include <dev/mii/mii.h> 98 #include <dev/mii/miivar.h> 99 100 #include <dev/sbus/sbusvar.h> 101 #include <dev/sbus/qecreg.h> 102 #include <dev/sbus/qecvar.h> 103 #include <dev/sbus/bereg.h> 104 105 struct be_softc { 106 device_t sc_dev; 107 bus_space_tag_t sc_bustag; /* bus & DMA tags */ 108 bus_dma_tag_t sc_dmatag; 109 bus_dmamap_t sc_dmamap; 110 struct ethercom sc_ethercom; 111 /*struct ifmedia sc_ifmedia; -* interface media */ 112 struct mii_data sc_mii; /* MII media control */ 113 #define sc_media sc_mii.mii_media/* shorthand */ 114 int sc_phys[2]; /* MII instance -> phy */ 115 116 struct callout sc_tick_ch; 117 118 /* 119 * Some `mii_softc' items we need to emulate MII operation 120 * for our internal transceiver. 121 */ 122 int sc_mii_inst; /* instance of internal phy */ 123 int sc_mii_active; /* currently active medium */ 124 int sc_mii_ticks; /* tick counter */ 125 int sc_mii_flags; /* phy status flags */ 126 #define MIIF_HAVELINK 0x04000000 127 int sc_intphy_curspeed; /* Established link speed */ 128 129 struct qec_softc *sc_qec; /* QEC parent */ 130 131 bus_space_handle_t sc_qr; /* QEC registers */ 132 bus_space_handle_t sc_br; /* BE registers */ 133 bus_space_handle_t sc_cr; /* channel registers */ 134 bus_space_handle_t sc_tr; /* transceiver registers */ 135 136 u_int sc_rev; 137 138 int sc_channel; /* channel number */ 139 int sc_burst; 140 141 struct qec_ring sc_rb; /* Packet Ring Buffer */ 142 143 /* MAC address */ 144 uint8_t sc_enaddr[ETHER_ADDR_LEN]; 145 #ifdef BEDEBUG 146 int sc_debug; 147 #endif 148 }; 149 150 static int bematch(device_t, cfdata_t, void *); 151 static void beattach(device_t, device_t, void *); 152 153 static int beinit(struct ifnet *); 154 static void bestart(struct ifnet *); 155 static void bestop(struct ifnet *, int); 156 static void bewatchdog(struct ifnet *); 157 static int beioctl(struct ifnet *, u_long, void *); 158 static void bereset(struct be_softc *); 159 static void behwreset(struct be_softc *); 160 161 static int beintr(void *); 162 static int berint(struct be_softc *); 163 static int betint(struct be_softc *); 164 static int beqint(struct be_softc *, uint32_t); 165 static int beeint(struct be_softc *, uint32_t); 166 167 static void be_read(struct be_softc *, int, int); 168 static int be_put(struct be_softc *, int, struct mbuf *); 169 static struct mbuf *be_get(struct be_softc *, int, int); 170 171 static void be_pal_gate(struct be_softc *, int); 172 173 /* ifmedia callbacks */ 174 static void be_ifmedia_sts(struct ifnet *, struct ifmediareq *); 175 static int be_ifmedia_upd(struct ifnet *); 176 177 static void be_mcreset(struct be_softc *); 178 179 /* MII methods & callbacks */ 180 static int be_mii_readreg(device_t, int, int, uint16_t *); 181 static int be_mii_writereg(device_t, int, int, uint16_t); 182 static void be_mii_statchg(struct ifnet *); 183 184 /* MII helpers */ 185 static void be_mii_sync(struct be_softc *); 186 static void be_mii_sendbits(struct be_softc *, int, uint32_t, int); 187 static int be_mii_reset(struct be_softc *, int); 188 static int be_tcvr_read_bit(struct be_softc *, int); 189 static void be_tcvr_write_bit(struct be_softc *, int, int); 190 191 static void be_tick(void *); 192 #if 0 193 static void be_intphy_auto(struct be_softc *); 194 #endif 195 static void be_intphy_status(struct be_softc *); 196 static int be_intphy_service(struct be_softc *, struct mii_data *, int); 197 198 199 CFATTACH_DECL_NEW(be, sizeof(struct be_softc), 200 bematch, beattach, NULL, NULL); 201 202 int 203 bematch(device_t parent, cfdata_t cf, void *aux) 204 { 205 struct sbus_attach_args *sa = aux; 206 207 return strcmp(cf->cf_name, sa->sa_name) == 0; 208 } 209 210 void 211 beattach(device_t parent, device_t self, void *aux) 212 { 213 struct sbus_attach_args *sa = aux; 214 struct qec_softc *qec = device_private(parent); 215 struct be_softc *sc = device_private(self); 216 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 217 struct mii_data *mii = &sc->sc_mii; 218 struct mii_softc *child; 219 int node = sa->sa_node; 220 bus_dma_tag_t dmatag = sa->sa_dmatag; 221 bus_dma_segment_t seg; 222 bus_size_t size; 223 int instance; 224 int rseg, error; 225 uint32_t v; 226 227 sc->sc_dev = self; 228 229 if (sa->sa_nreg < 3) { 230 printf(": only %d register sets\n", sa->sa_nreg); 231 return; 232 } 233 234 if (bus_space_map(sa->sa_bustag, 235 (bus_addr_t)BUS_ADDR(sa->sa_reg[0].oa_space, sa->sa_reg[0].oa_base), 236 (bus_size_t)sa->sa_reg[0].oa_size, 237 0, &sc->sc_cr) != 0) { 238 printf(": cannot map registers\n"); 239 return; 240 } 241 242 if (bus_space_map(sa->sa_bustag, 243 (bus_addr_t)BUS_ADDR(sa->sa_reg[1].oa_space, sa->sa_reg[1].oa_base), 244 (bus_size_t)sa->sa_reg[1].oa_size, 245 0, &sc->sc_br) != 0) { 246 printf(": cannot map registers\n"); 247 return; 248 } 249 250 if (bus_space_map(sa->sa_bustag, 251 (bus_addr_t)BUS_ADDR(sa->sa_reg[2].oa_space, sa->sa_reg[2].oa_base), 252 (bus_size_t)sa->sa_reg[2].oa_size, 253 0, &sc->sc_tr) != 0) { 254 printf(": cannot map registers\n"); 255 return; 256 } 257 258 sc->sc_bustag = sa->sa_bustag; 259 sc->sc_qec = qec; 260 sc->sc_qr = qec->sc_regs; 261 262 sc->sc_rev = prom_getpropint(node, "board-version", -1); 263 printf(": rev %x,", sc->sc_rev); 264 265 callout_init(&sc->sc_tick_ch, 0); 266 267 sc->sc_channel = prom_getpropint(node, "channel#", -1); 268 if (sc->sc_channel == -1) 269 sc->sc_channel = 0; 270 271 sc->sc_burst = prom_getpropint(node, "burst-sizes", -1); 272 if (sc->sc_burst == -1) 273 sc->sc_burst = qec->sc_burst; 274 275 /* Clamp at parent's burst sizes */ 276 sc->sc_burst &= qec->sc_burst; 277 278 /* Establish interrupt handler */ 279 if (sa->sa_nintr) 280 (void)bus_intr_establish(sa->sa_bustag, sa->sa_pri, IPL_NET, 281 beintr, sc); 282 283 prom_getether(node, sc->sc_enaddr); 284 printf(" address %s\n", ether_sprintf(sc->sc_enaddr)); 285 286 /* 287 * Allocate descriptor ring and buffers. 288 */ 289 290 /* for now, allocate as many bufs as there are ring descriptors */ 291 sc->sc_rb.rb_ntbuf = QEC_XD_RING_MAXSIZE; 292 sc->sc_rb.rb_nrbuf = QEC_XD_RING_MAXSIZE; 293 294 size = 295 QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd) + 296 QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd) + 297 sc->sc_rb.rb_ntbuf * BE_PKT_BUF_SZ + 298 sc->sc_rb.rb_nrbuf * BE_PKT_BUF_SZ; 299 300 /* Get a DMA handle */ 301 if ((error = bus_dmamap_create(dmatag, size, 1, size, 0, 302 BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) { 303 aprint_error_dev(self, "DMA map create error %d\n", error); 304 return; 305 } 306 307 /* Allocate DMA buffer */ 308 if ((error = bus_dmamem_alloc(sa->sa_dmatag, size, 0, 0, 309 &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 310 aprint_error_dev(self, "DMA buffer alloc error %d\n", error); 311 return; 312 } 313 314 /* Map DMA memory in CPU addressable space */ 315 if ((error = bus_dmamem_map(sa->sa_dmatag, &seg, rseg, size, 316 &sc->sc_rb.rb_membase, BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) { 317 aprint_error_dev(self, "DMA buffer map error %d\n", error); 318 bus_dmamem_free(sa->sa_dmatag, &seg, rseg); 319 return; 320 } 321 322 /* Load the buffer */ 323 if ((error = bus_dmamap_load(dmatag, sc->sc_dmamap, 324 sc->sc_rb.rb_membase, size, NULL, BUS_DMA_NOWAIT)) != 0) { 325 aprint_error_dev(self, "DMA buffer map load error %d\n", error); 326 bus_dmamem_unmap(dmatag, sc->sc_rb.rb_membase, size); 327 bus_dmamem_free(dmatag, &seg, rseg); 328 return; 329 } 330 sc->sc_rb.rb_dmabase = sc->sc_dmamap->dm_segs[0].ds_addr; 331 332 /* 333 * Initialize our media structures and MII info. 334 */ 335 mii->mii_ifp = ifp; 336 mii->mii_readreg = be_mii_readreg; 337 mii->mii_writereg = be_mii_writereg; 338 mii->mii_statchg = be_mii_statchg; 339 340 sc->sc_ethercom.ec_mii = mii; 341 ifmedia_init(&mii->mii_media, 0, be_ifmedia_upd, be_ifmedia_sts); 342 343 /* 344 * Initialize transceiver and determine which PHY connection to use. 345 */ 346 be_mii_sync(sc); 347 v = bus_space_read_4(sc->sc_bustag, sc->sc_tr, BE_TRI_MGMTPAL); 348 349 instance = 0; 350 351 if ((v & MGMT_PAL_EXT_MDIO) != 0) { 352 353 mii_attach(self, mii, 0xffffffff, BE_PHY_EXTERNAL, 354 MII_OFFSET_ANY, 0); 355 356 child = LIST_FIRST(&mii->mii_phys); 357 if (child == NULL) { 358 /* No PHY attached */ 359 ifmedia_add(&sc->sc_media, 360 IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, instance), 361 0, NULL); 362 ifmedia_set(&sc->sc_media, 363 IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, instance)); 364 } else { 365 /* 366 * Note: we support just one PHY on the external 367 * MII connector. 368 */ 369 #ifdef DIAGNOSTIC 370 if (LIST_NEXT(child, mii_list) != NULL) { 371 aprint_error_dev(self, 372 "spurious MII device %s attached\n", 373 device_xname(child->mii_dev)); 374 } 375 #endif 376 if (child->mii_phy != BE_PHY_EXTERNAL || 377 child->mii_inst > 0) { 378 aprint_error_dev(self, 379 "cannot accommodate MII device %s" 380 " at phy %d, instance %d\n", 381 device_xname(child->mii_dev), 382 child->mii_phy, child->mii_inst); 383 } else { 384 sc->sc_phys[instance] = child->mii_phy; 385 } 386 387 /* 388 * XXX - we can really do the following ONLY if the 389 * phy indeed has the auto negotiation capability!! 390 */ 391 ifmedia_set(&sc->sc_media, 392 IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, instance)); 393 394 /* Mark our current media setting */ 395 be_pal_gate(sc, BE_PHY_EXTERNAL); 396 instance++; 397 } 398 399 } 400 401 if ((v & MGMT_PAL_INT_MDIO) != 0) { 402 /* 403 * The be internal phy looks vaguely like MII hardware, 404 * but not enough to be able to use the MII device 405 * layer. Hence, we have to take care of media selection 406 * ourselves. 407 */ 408 409 sc->sc_mii_inst = instance; 410 sc->sc_phys[instance] = BE_PHY_INTERNAL; 411 412 /* Use `ifm_data' to store BMCR bits */ 413 ifmedia_add(&sc->sc_media, 414 IFM_MAKEWORD(IFM_ETHER, IFM_10_T, 0, instance), 415 0, NULL); 416 ifmedia_add(&sc->sc_media, 417 IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, 0, instance), 418 BMCR_S100, NULL); 419 ifmedia_add(&sc->sc_media, 420 IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, instance), 421 0, NULL); 422 423 printf("on-board transceiver at %s: 10baseT, 100baseTX, auto\n", 424 device_xname(self)); 425 426 be_mii_reset(sc, BE_PHY_INTERNAL); 427 /* Only set default medium here if there's no external PHY */ 428 if (instance == 0) { 429 be_pal_gate(sc, BE_PHY_INTERNAL); 430 ifmedia_set(&sc->sc_media, 431 IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, instance)); 432 } else 433 be_mii_writereg(self, 434 BE_PHY_INTERNAL, MII_BMCR, BMCR_ISO); 435 } 436 437 memcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 438 ifp->if_softc = sc; 439 ifp->if_start = bestart; 440 ifp->if_ioctl = beioctl; 441 ifp->if_watchdog = bewatchdog; 442 ifp->if_init = beinit; 443 ifp->if_stop = bestop; 444 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 445 IFQ_SET_READY(&ifp->if_snd); 446 447 /* claim 802.1q capability */ 448 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 449 450 /* Attach the interface. */ 451 if_attach(ifp); 452 ether_ifattach(ifp, sc->sc_enaddr); 453 } 454 455 456 /* 457 * Routine to copy from mbuf chain to transmit buffer in 458 * network buffer memory. 459 */ 460 static inline int 461 be_put(struct be_softc *sc, int idx, struct mbuf *m) 462 { 463 struct mbuf *n; 464 int len, tlen = 0, boff = 0; 465 uint8_t *bp; 466 467 bp = sc->sc_rb.rb_txbuf + (idx % sc->sc_rb.rb_ntbuf) * BE_PKT_BUF_SZ; 468 469 for (; m; m = n) { 470 len = m->m_len; 471 if (len == 0) { 472 n = m_free(m); 473 continue; 474 } 475 memcpy(bp + boff, mtod(m, void *), len); 476 boff += len; 477 tlen += len; 478 n = m_free(m); 479 } 480 return tlen; 481 } 482 483 /* 484 * Pull data off an interface. 485 * Len is the length of data, with local net header stripped. 486 * We copy the data into mbufs. When full cluster sized units are present, 487 * we copy into clusters. 488 */ 489 static inline struct mbuf * 490 be_get(struct be_softc *sc, int idx, int totlen) 491 { 492 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 493 struct mbuf *m; 494 struct mbuf *top, **mp; 495 int len, pad, boff = 0; 496 uint8_t *bp; 497 498 bp = sc->sc_rb.rb_rxbuf + (idx % sc->sc_rb.rb_nrbuf) * BE_PKT_BUF_SZ; 499 500 MGETHDR(m, M_DONTWAIT, MT_DATA); 501 if (m == NULL) 502 return (NULL); 503 m_set_rcvif(m, ifp); 504 m->m_pkthdr.len = totlen; 505 506 pad = ALIGN(sizeof(struct ether_header)) - sizeof(struct ether_header); 507 m->m_data += pad; 508 len = MHLEN - pad; 509 top = NULL; 510 mp = ⊤ 511 512 while (totlen > 0) { 513 if (top) { 514 MGET(m, M_DONTWAIT, MT_DATA); 515 if (m == NULL) { 516 m_freem(top); 517 return (NULL); 518 } 519 len = MLEN; 520 } 521 if (top && totlen >= MINCLSIZE) { 522 MCLGET(m, M_DONTWAIT); 523 if (m->m_flags & M_EXT) 524 len = MCLBYTES; 525 } 526 m->m_len = len = uimin(totlen, len); 527 memcpy(mtod(m, void *), bp + boff, len); 528 boff += len; 529 totlen -= len; 530 *mp = m; 531 mp = &m->m_next; 532 } 533 534 return top; 535 } 536 537 /* 538 * Pass a packet to the higher levels. 539 */ 540 static inline void 541 be_read(struct be_softc *sc, int idx, int len) 542 { 543 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 544 struct mbuf *m; 545 546 if (len <= sizeof(struct ether_header) || 547 len > ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN) { 548 #ifdef BEDEBUG 549 if (sc->sc_debug) 550 printf("%s: invalid packet size %d; dropping\n", 551 ifp->if_xname, len); 552 #endif 553 if_statinc(ifp, if_ierrors); 554 return; 555 } 556 557 /* 558 * Pull packet off interface. 559 */ 560 m = be_get(sc, idx, len); 561 if (m == NULL) { 562 if_statinc(ifp, if_ierrors); 563 return; 564 } 565 566 /* Pass the packet up. */ 567 if_percpuq_enqueue(ifp->if_percpuq, m); 568 } 569 570 /* 571 * Start output on interface. 572 * We make an assumption here: 573 * 1) that the current priority is set to splnet _before_ this code 574 * is called *and* is returned to the appropriate priority after 575 * return 576 */ 577 void 578 bestart(struct ifnet *ifp) 579 { 580 struct be_softc *sc = ifp->if_softc; 581 struct qec_xd *txd = sc->sc_rb.rb_txd; 582 struct mbuf *m; 583 unsigned int bix, len; 584 unsigned int ntbuf = sc->sc_rb.rb_ntbuf; 585 586 if ((ifp->if_flags & IFF_RUNNING) != IFF_RUNNING) 587 return; 588 589 bix = sc->sc_rb.rb_tdhead; 590 591 while (sc->sc_rb.rb_td_nbusy < ntbuf) { 592 IFQ_DEQUEUE(&ifp->if_snd, m); 593 if (m == 0) 594 break; 595 596 /* 597 * If BPF is listening on this interface, let it see the 598 * packet before we commit it to the wire. 599 */ 600 bpf_mtap(ifp, m, BPF_D_OUT); 601 602 /* 603 * Copy the mbuf chain into the transmit buffer. 604 */ 605 len = be_put(sc, bix, m); 606 607 /* 608 * Initialize transmit registers and start transmission 609 */ 610 txd[bix].xd_flags = QEC_XD_OWN | QEC_XD_SOP | QEC_XD_EOP | 611 (len & QEC_XD_LENGTH); 612 bus_space_write_4(sc->sc_bustag, sc->sc_cr, 613 BE_CRI_CTRL, BE_CR_CTRL_TWAKEUP); 614 615 if (++bix == QEC_XD_RING_MAXSIZE) 616 bix = 0; 617 618 sc->sc_rb.rb_td_nbusy++; 619 } 620 621 sc->sc_rb.rb_tdhead = bix; 622 } 623 624 void 625 bestop(struct ifnet *ifp, int disable) 626 { 627 struct be_softc *sc = ifp->if_softc; 628 629 callout_stop(&sc->sc_tick_ch); 630 631 /* Down the MII. */ 632 mii_down(&sc->sc_mii); 633 (void)be_intphy_service(sc, &sc->sc_mii, MII_DOWN); 634 635 behwreset(sc); 636 } 637 638 void 639 behwreset(struct be_softc *sc) 640 { 641 int n; 642 bus_space_tag_t t = sc->sc_bustag; 643 bus_space_handle_t br = sc->sc_br; 644 645 /* Stop the transmitter */ 646 bus_space_write_4(t, br, BE_BRI_TXCFG, 0); 647 for (n = 32; n > 0; n--) { 648 if (bus_space_read_4(t, br, BE_BRI_TXCFG) == 0) 649 break; 650 DELAY(20); 651 } 652 653 /* Stop the receiver */ 654 bus_space_write_4(t, br, BE_BRI_RXCFG, 0); 655 for (n = 32; n > 0; n--) { 656 if (bus_space_read_4(t, br, BE_BRI_RXCFG) == 0) 657 break; 658 DELAY(20); 659 } 660 } 661 662 /* 663 * Reset interface. 664 */ 665 void 666 bereset(struct be_softc *sc) 667 { 668 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 669 int s; 670 671 s = splnet(); 672 behwreset(sc); 673 if ((sc->sc_ethercom.ec_if.if_flags & IFF_UP) != 0) 674 beinit(ifp); 675 splx(s); 676 } 677 678 void 679 bewatchdog(struct ifnet *ifp) 680 { 681 struct be_softc *sc = ifp->if_softc; 682 683 log(LOG_ERR, "%s: device timeout\n", device_xname(sc->sc_dev)); 684 if_statinc(ifp, if_oerrors); 685 686 bereset(sc); 687 } 688 689 int 690 beintr(void *arg) 691 { 692 struct be_softc *sc = arg; 693 bus_space_tag_t t = sc->sc_bustag; 694 uint32_t whyq, whyb, whyc; 695 int r = 0; 696 697 /* Read QEC status, channel status and BE status */ 698 whyq = bus_space_read_4(t, sc->sc_qr, QEC_QRI_STAT); 699 whyc = bus_space_read_4(t, sc->sc_cr, BE_CRI_STAT); 700 whyb = bus_space_read_4(t, sc->sc_br, BE_BRI_STAT); 701 702 if (whyq & QEC_STAT_BM) 703 r |= beeint(sc, whyb); 704 705 if (whyq & QEC_STAT_ER) 706 r |= beqint(sc, whyc); 707 708 if (whyq & QEC_STAT_TX && whyc & BE_CR_STAT_TXIRQ) 709 r |= betint(sc); 710 711 if (whyq & QEC_STAT_RX && whyc & BE_CR_STAT_RXIRQ) 712 r |= berint(sc); 713 714 return r; 715 } 716 717 /* 718 * QEC Interrupt. 719 */ 720 int 721 beqint(struct be_softc *sc, uint32_t why) 722 { 723 device_t self = sc->sc_dev; 724 int r = 0, rst = 0; 725 726 if (why & BE_CR_STAT_TXIRQ) 727 r |= 1; 728 if (why & BE_CR_STAT_RXIRQ) 729 r |= 1; 730 731 if (why & BE_CR_STAT_BERROR) { 732 r |= 1; 733 rst = 1; 734 aprint_error_dev(self, "bigmac error\n"); 735 } 736 737 if (why & BE_CR_STAT_TXDERR) { 738 r |= 1; 739 rst = 1; 740 aprint_error_dev(self, "bogus tx descriptor\n"); 741 } 742 743 if (why & (BE_CR_STAT_TXLERR | BE_CR_STAT_TXPERR | BE_CR_STAT_TXSERR)) { 744 r |= 1; 745 rst = 1; 746 aprint_error_dev(self, "tx DMA error ( "); 747 if (why & BE_CR_STAT_TXLERR) 748 printf("Late "); 749 if (why & BE_CR_STAT_TXPERR) 750 printf("Parity "); 751 if (why & BE_CR_STAT_TXSERR) 752 printf("Generic "); 753 printf(")\n"); 754 } 755 756 if (why & BE_CR_STAT_RXDROP) { 757 r |= 1; 758 rst = 1; 759 aprint_error_dev(self, "out of rx descriptors\n"); 760 } 761 762 if (why & BE_CR_STAT_RXSMALL) { 763 r |= 1; 764 rst = 1; 765 aprint_error_dev(self, "rx descriptor too small\n"); 766 } 767 768 if (why & (BE_CR_STAT_RXLERR | BE_CR_STAT_RXPERR | BE_CR_STAT_RXSERR)) { 769 r |= 1; 770 rst = 1; 771 aprint_error_dev(self, "rx DMA error ( "); 772 if (why & BE_CR_STAT_RXLERR) 773 printf("Late "); 774 if (why & BE_CR_STAT_RXPERR) 775 printf("Parity "); 776 if (why & BE_CR_STAT_RXSERR) 777 printf("Generic "); 778 printf(")\n"); 779 } 780 781 if (!r) { 782 rst = 1; 783 aprint_error_dev(self, "unexpected error interrupt %08x\n", 784 why); 785 } 786 787 if (rst) { 788 printf("%s: resetting\n", device_xname(self)); 789 bereset(sc); 790 } 791 792 return r; 793 } 794 795 /* 796 * Error interrupt. 797 */ 798 int 799 beeint(struct be_softc *sc, uint32_t why) 800 { 801 device_t self = sc->sc_dev; 802 int r = 0, rst = 0; 803 804 if (why & BE_BR_STAT_RFIFOVF) { 805 r |= 1; 806 rst = 1; 807 aprint_error_dev(self, "receive fifo overrun\n"); 808 } 809 if (why & BE_BR_STAT_TFIFO_UND) { 810 r |= 1; 811 rst = 1; 812 aprint_error_dev(self, "transmit fifo underrun\n"); 813 } 814 if (why & BE_BR_STAT_MAXPKTERR) { 815 r |= 1; 816 rst = 1; 817 aprint_error_dev(self, "max packet size error\n"); 818 } 819 820 if (!r) { 821 rst = 1; 822 aprint_error_dev(self, "unexpected error interrupt %08x\n", 823 why); 824 } 825 826 if (rst) { 827 printf("%s: resetting\n", device_xname(self)); 828 bereset(sc); 829 } 830 831 return r; 832 } 833 834 /* 835 * Transmit interrupt. 836 */ 837 int 838 betint(struct be_softc *sc) 839 { 840 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 841 bus_space_tag_t t = sc->sc_bustag; 842 bus_space_handle_t br = sc->sc_br; 843 unsigned int bix, txflags; 844 845 /* 846 * Unload collision counters 847 */ 848 if_statadd(ifp, if_collisions, 849 bus_space_read_4(t, br, BE_BRI_NCCNT) + 850 bus_space_read_4(t, br, BE_BRI_FCCNT) + 851 bus_space_read_4(t, br, BE_BRI_EXCNT) + 852 bus_space_read_4(t, br, BE_BRI_LTCNT)); 853 854 /* 855 * the clear the hardware counters 856 */ 857 bus_space_write_4(t, br, BE_BRI_NCCNT, 0); 858 bus_space_write_4(t, br, BE_BRI_FCCNT, 0); 859 bus_space_write_4(t, br, BE_BRI_EXCNT, 0); 860 bus_space_write_4(t, br, BE_BRI_LTCNT, 0); 861 862 bix = sc->sc_rb.rb_tdtail; 863 864 for (;;) { 865 if (sc->sc_rb.rb_td_nbusy <= 0) 866 break; 867 868 txflags = sc->sc_rb.rb_txd[bix].xd_flags; 869 870 if (txflags & QEC_XD_OWN) 871 break; 872 873 if_statinc(ifp, if_opackets); 874 875 if (++bix == QEC_XD_RING_MAXSIZE) 876 bix = 0; 877 878 --sc->sc_rb.rb_td_nbusy; 879 } 880 881 sc->sc_rb.rb_tdtail = bix; 882 883 bestart(ifp); 884 885 if (sc->sc_rb.rb_td_nbusy == 0) 886 ifp->if_timer = 0; 887 888 return 1; 889 } 890 891 /* 892 * Receive interrupt. 893 */ 894 int 895 berint(struct be_softc *sc) 896 { 897 struct qec_xd *xd = sc->sc_rb.rb_rxd; 898 unsigned int bix, len; 899 unsigned int nrbuf = sc->sc_rb.rb_nrbuf; 900 901 bix = sc->sc_rb.rb_rdtail; 902 903 /* 904 * Process all buffers with valid data. 905 */ 906 for (;;) { 907 len = xd[bix].xd_flags; 908 if (len & QEC_XD_OWN) 909 break; 910 911 len &= QEC_XD_LENGTH; 912 be_read(sc, bix, len); 913 914 /* ... */ 915 xd[(bix+nrbuf) % QEC_XD_RING_MAXSIZE].xd_flags = 916 QEC_XD_OWN | (BE_PKT_BUF_SZ & QEC_XD_LENGTH); 917 918 if (++bix == QEC_XD_RING_MAXSIZE) 919 bix = 0; 920 } 921 922 sc->sc_rb.rb_rdtail = bix; 923 924 return 1; 925 } 926 927 int 928 beioctl(struct ifnet *ifp, u_long cmd, void *data) 929 { 930 #ifdef BEDEBUG 931 struct be_softc *sc = ifp->if_softc; 932 #endif 933 struct ifaddr *ifa = data; 934 int s, error = 0; 935 936 s = splnet(); 937 938 switch (cmd) { 939 case SIOCINITIFADDR: 940 ifp->if_flags |= IFF_UP; 941 beinit(ifp); 942 switch (ifa->ifa_addr->sa_family) { 943 #ifdef INET 944 case AF_INET: 945 arp_ifinit(ifp, ifa); 946 break; 947 #endif /* INET */ 948 default: 949 break; 950 } 951 break; 952 953 case SIOCSIFFLAGS: 954 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 955 break; 956 /* XXX re-use ether_ioctl() */ 957 switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { 958 case IFF_RUNNING: 959 /* 960 * If interface is marked down and it is running, then 961 * stop it. 962 */ 963 bestop(ifp, 0); 964 ifp->if_flags &= ~IFF_RUNNING; 965 break; 966 case IFF_UP: 967 /* 968 * If interface is marked up and it is stopped, then 969 * start it. 970 */ 971 beinit(ifp); 972 break; 973 default: 974 /* 975 * Reset the interface to pick up changes in any other 976 * flags that affect hardware registers. 977 */ 978 bestop(ifp, 0); 979 beinit(ifp); 980 break; 981 } 982 #ifdef BEDEBUG 983 if (ifp->if_flags & IFF_DEBUG) 984 sc->sc_debug = 1; 985 else 986 sc->sc_debug = 0; 987 #endif 988 break; 989 990 default: 991 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 992 /* 993 * Multicast list has changed; set the hardware filter 994 * accordingly. 995 */ 996 if (ifp->if_flags & IFF_RUNNING) 997 error = beinit(ifp); 998 else 999 error = 0; 1000 } 1001 break; 1002 } 1003 splx(s); 1004 return error; 1005 } 1006 1007 1008 int 1009 beinit(struct ifnet *ifp) 1010 { 1011 struct be_softc *sc = ifp->if_softc; 1012 bus_space_tag_t t = sc->sc_bustag; 1013 bus_space_handle_t br = sc->sc_br; 1014 bus_space_handle_t cr = sc->sc_cr; 1015 struct qec_softc *qec = sc->sc_qec; 1016 uint32_t v; 1017 uint32_t qecaddr; 1018 uint8_t *ea; 1019 int rc, s; 1020 1021 s = splnet(); 1022 1023 qec_meminit(&sc->sc_rb, BE_PKT_BUF_SZ); 1024 1025 bestop(ifp, 1); 1026 1027 ea = sc->sc_enaddr; 1028 bus_space_write_4(t, br, BE_BRI_MACADDR0, (ea[0] << 8) | ea[1]); 1029 bus_space_write_4(t, br, BE_BRI_MACADDR1, (ea[2] << 8) | ea[3]); 1030 bus_space_write_4(t, br, BE_BRI_MACADDR2, (ea[4] << 8) | ea[5]); 1031 1032 /* Clear hash table */ 1033 bus_space_write_4(t, br, BE_BRI_HASHTAB0, 0); 1034 bus_space_write_4(t, br, BE_BRI_HASHTAB1, 0); 1035 bus_space_write_4(t, br, BE_BRI_HASHTAB2, 0); 1036 bus_space_write_4(t, br, BE_BRI_HASHTAB3, 0); 1037 1038 /* Re-initialize RX configuration */ 1039 v = BE_BR_RXCFG_FIFO; 1040 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1041 1042 be_mcreset(sc); 1043 1044 bus_space_write_4(t, br, BE_BRI_RANDSEED, 0xbd); 1045 1046 bus_space_write_4(t, br, 1047 BE_BRI_XIFCFG, BE_BR_XCFG_ODENABLE | BE_BR_XCFG_RESV); 1048 1049 bus_space_write_4(t, br, BE_BRI_JSIZE, 4); 1050 1051 /* 1052 * Turn off counter expiration interrupts as well as 1053 * 'gotframe' and 'sentframe' 1054 */ 1055 bus_space_write_4(t, br, BE_BRI_IMASK, 1056 BE_BR_IMASK_GOTFRAME | 1057 BE_BR_IMASK_RCNTEXP | 1058 BE_BR_IMASK_ACNTEXP | 1059 BE_BR_IMASK_CCNTEXP | 1060 BE_BR_IMASK_LCNTEXP | 1061 BE_BR_IMASK_CVCNTEXP | 1062 BE_BR_IMASK_SENTFRAME | 1063 BE_BR_IMASK_NCNTEXP | 1064 BE_BR_IMASK_ECNTEXP | 1065 BE_BR_IMASK_LCCNTEXP | 1066 BE_BR_IMASK_FCNTEXP | 1067 BE_BR_IMASK_DTIMEXP); 1068 1069 /* Channel registers: */ 1070 bus_space_write_4(t, cr, BE_CRI_RXDS, (uint32_t)sc->sc_rb.rb_rxddma); 1071 bus_space_write_4(t, cr, BE_CRI_TXDS, (uint32_t)sc->sc_rb.rb_txddma); 1072 1073 qecaddr = sc->sc_channel * qec->sc_msize; 1074 bus_space_write_4(t, cr, BE_CRI_RXWBUF, qecaddr); 1075 bus_space_write_4(t, cr, BE_CRI_RXRBUF, qecaddr); 1076 bus_space_write_4(t, cr, BE_CRI_TXWBUF, qecaddr + qec->sc_rsize); 1077 bus_space_write_4(t, cr, BE_CRI_TXRBUF, qecaddr + qec->sc_rsize); 1078 1079 bus_space_write_4(t, cr, BE_CRI_RIMASK, 0); 1080 bus_space_write_4(t, cr, BE_CRI_TIMASK, 0); 1081 bus_space_write_4(t, cr, BE_CRI_QMASK, 0); 1082 bus_space_write_4(t, cr, BE_CRI_BMASK, 0); 1083 bus_space_write_4(t, cr, BE_CRI_CCNT, 0); 1084 1085 /* Set max packet length */ 1086 v = ETHER_MAX_LEN; 1087 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) 1088 v += ETHER_VLAN_ENCAP_LEN; 1089 bus_space_write_4(t, br, BE_BRI_RXMAX, v); 1090 bus_space_write_4(t, br, BE_BRI_TXMAX, v); 1091 1092 /* Enable transmitter */ 1093 bus_space_write_4(t, br, 1094 BE_BRI_TXCFG, BE_BR_TXCFG_FIFO | BE_BR_TXCFG_ENABLE); 1095 1096 /* Enable receiver */ 1097 v = bus_space_read_4(t, br, BE_BRI_RXCFG); 1098 v |= BE_BR_RXCFG_FIFO | BE_BR_RXCFG_ENABLE; 1099 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1100 1101 if ((rc = be_ifmedia_upd(ifp)) != 0) 1102 goto out; 1103 1104 ifp->if_flags |= IFF_RUNNING; 1105 1106 callout_reset(&sc->sc_tick_ch, hz, be_tick, sc); 1107 1108 splx(s); 1109 return 0; 1110 out: 1111 splx(s); 1112 return rc; 1113 } 1114 1115 void 1116 be_mcreset(struct be_softc *sc) 1117 { 1118 struct ethercom *ec = &sc->sc_ethercom; 1119 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1120 bus_space_tag_t t = sc->sc_bustag; 1121 bus_space_handle_t br = sc->sc_br; 1122 uint32_t v; 1123 uint32_t crc; 1124 uint16_t hash[4]; 1125 struct ether_multi *enm; 1126 struct ether_multistep step; 1127 1128 if (ifp->if_flags & IFF_PROMISC) { 1129 v = bus_space_read_4(t, br, BE_BRI_RXCFG); 1130 v |= BE_BR_RXCFG_PMISC; 1131 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1132 return; 1133 } 1134 1135 if (ifp->if_flags & IFF_ALLMULTI) { 1136 hash[3] = hash[2] = hash[1] = hash[0] = 0xffff; 1137 goto chipit; 1138 } 1139 1140 hash[3] = hash[2] = hash[1] = hash[0] = 0; 1141 1142 ETHER_LOCK(ec); 1143 ETHER_FIRST_MULTI(step, ec, enm); 1144 while (enm != NULL) { 1145 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1146 /* 1147 * We must listen to a range of multicast 1148 * addresses. For now, just accept all 1149 * multicasts, rather than trying to set only 1150 * those filter bits needed to match the range. 1151 * (At this time, the only use of address 1152 * ranges is for IP multicast routing, for 1153 * which the range is big enough to require 1154 * all bits set.) 1155 */ 1156 hash[3] = hash[2] = hash[1] = hash[0] = 0xffff; 1157 ifp->if_flags |= IFF_ALLMULTI; 1158 ETHER_UNLOCK(ec); 1159 goto chipit; 1160 } 1161 1162 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 1163 /* Just want the 6 most significant bits. */ 1164 crc >>= 26; 1165 1166 hash[crc >> 4] |= 1 << (crc & 0xf); 1167 ETHER_NEXT_MULTI(step, enm); 1168 } 1169 ETHER_UNLOCK(ec); 1170 1171 ifp->if_flags &= ~IFF_ALLMULTI; 1172 1173 chipit: 1174 /* Enable the hash filter */ 1175 bus_space_write_4(t, br, BE_BRI_HASHTAB0, hash[0]); 1176 bus_space_write_4(t, br, BE_BRI_HASHTAB1, hash[1]); 1177 bus_space_write_4(t, br, BE_BRI_HASHTAB2, hash[2]); 1178 bus_space_write_4(t, br, BE_BRI_HASHTAB3, hash[3]); 1179 1180 v = bus_space_read_4(t, br, BE_BRI_RXCFG); 1181 v &= ~BE_BR_RXCFG_PMISC; 1182 v |= BE_BR_RXCFG_HENABLE; 1183 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1184 } 1185 1186 /* 1187 * Set the tcvr to an idle state 1188 */ 1189 void 1190 be_mii_sync(struct be_softc *sc) 1191 { 1192 bus_space_tag_t t = sc->sc_bustag; 1193 bus_space_handle_t tr = sc->sc_tr; 1194 int n = 32; 1195 1196 while (n--) { 1197 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, 1198 MGMT_PAL_INT_MDIO | MGMT_PAL_EXT_MDIO | MGMT_PAL_OENAB); 1199 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1200 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, 1201 MGMT_PAL_INT_MDIO | MGMT_PAL_EXT_MDIO | 1202 MGMT_PAL_OENAB | MGMT_PAL_DCLOCK); 1203 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1204 } 1205 } 1206 1207 void 1208 be_pal_gate(struct be_softc *sc, int phy) 1209 { 1210 bus_space_tag_t t = sc->sc_bustag; 1211 bus_space_handle_t tr = sc->sc_tr; 1212 uint32_t v; 1213 1214 be_mii_sync(sc); 1215 1216 v = ~(TCVR_PAL_EXTLBACK | TCVR_PAL_MSENSE | TCVR_PAL_LTENABLE); 1217 if (phy == BE_PHY_INTERNAL) 1218 v &= ~TCVR_PAL_SERIAL; 1219 1220 bus_space_write_4(t, tr, BE_TRI_TCVRPAL, v); 1221 (void)bus_space_read_4(t, tr, BE_TRI_TCVRPAL); 1222 } 1223 1224 static int 1225 be_tcvr_read_bit(struct be_softc *sc, int phy) 1226 { 1227 bus_space_tag_t t = sc->sc_bustag; 1228 bus_space_handle_t tr = sc->sc_tr; 1229 int ret; 1230 1231 if (phy == BE_PHY_INTERNAL) { 1232 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, MGMT_PAL_EXT_MDIO); 1233 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1234 bus_space_write_4(t, tr, 1235 BE_TRI_MGMTPAL, MGMT_PAL_EXT_MDIO | MGMT_PAL_DCLOCK); 1236 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1237 ret = (bus_space_read_4(t, tr, BE_TRI_MGMTPAL) & 1238 MGMT_PAL_INT_MDIO) >> MGMT_PAL_INT_MDIO_SHIFT; 1239 } else { 1240 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, MGMT_PAL_INT_MDIO); 1241 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1242 ret = (bus_space_read_4(t, tr, BE_TRI_MGMTPAL) & 1243 MGMT_PAL_EXT_MDIO) >> MGMT_PAL_EXT_MDIO_SHIFT; 1244 bus_space_write_4(t, tr, 1245 BE_TRI_MGMTPAL, MGMT_PAL_INT_MDIO | MGMT_PAL_DCLOCK); 1246 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1247 } 1248 1249 return ret; 1250 } 1251 1252 static void 1253 be_tcvr_write_bit(struct be_softc *sc, int phy, int bit) 1254 { 1255 bus_space_tag_t t = sc->sc_bustag; 1256 bus_space_handle_t tr = sc->sc_tr; 1257 uint32_t v; 1258 1259 if (phy == BE_PHY_INTERNAL) { 1260 v = ((bit & 1) << MGMT_PAL_INT_MDIO_SHIFT) | 1261 MGMT_PAL_OENAB | MGMT_PAL_EXT_MDIO; 1262 } else { 1263 v = ((bit & 1) << MGMT_PAL_EXT_MDIO_SHIFT) | 1264 MGMT_PAL_OENAB | MGMT_PAL_INT_MDIO; 1265 } 1266 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, v); 1267 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1268 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, v | MGMT_PAL_DCLOCK); 1269 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1270 } 1271 1272 static void 1273 be_mii_sendbits(struct be_softc *sc, int phy, uint32_t data, int nbits) 1274 { 1275 int i; 1276 1277 for (i = 1 << (nbits - 1); i != 0; i >>= 1) { 1278 be_tcvr_write_bit(sc, phy, (data & i) != 0); 1279 } 1280 } 1281 1282 static int 1283 be_mii_readreg(device_t self, int phy, int reg, uint16_t *val) 1284 { 1285 struct be_softc *sc = device_private(self); 1286 int i; 1287 uint16_t data = 0; 1288 1289 /* 1290 * Read the PHY register by manually driving the MII control lines. 1291 */ 1292 be_mii_sync(sc); 1293 be_mii_sendbits(sc, phy, MII_COMMAND_START, 2); 1294 be_mii_sendbits(sc, phy, MII_COMMAND_READ, 2); 1295 be_mii_sendbits(sc, phy, phy, 5); 1296 be_mii_sendbits(sc, phy, reg, 5); 1297 1298 (void)be_tcvr_read_bit(sc, phy); 1299 (void)be_tcvr_read_bit(sc, phy); 1300 1301 for (i = 15; i >= 0; i--) 1302 data |= (be_tcvr_read_bit(sc, phy) << i); 1303 1304 (void)be_tcvr_read_bit(sc, phy); 1305 (void)be_tcvr_read_bit(sc, phy); 1306 (void)be_tcvr_read_bit(sc, phy); 1307 1308 *val = data; 1309 return 0; 1310 } 1311 1312 int 1313 be_mii_writereg(device_t self, int phy, int reg, uint16_t val) 1314 { 1315 struct be_softc *sc = device_private(self); 1316 int i; 1317 1318 /* 1319 * Write the PHY register by manually driving the MII control lines. 1320 */ 1321 be_mii_sync(sc); 1322 be_mii_sendbits(sc, phy, MII_COMMAND_START, 2); 1323 be_mii_sendbits(sc, phy, MII_COMMAND_WRITE, 2); 1324 be_mii_sendbits(sc, phy, phy, 5); 1325 be_mii_sendbits(sc, phy, reg, 5); 1326 1327 be_tcvr_write_bit(sc, phy, 1); 1328 be_tcvr_write_bit(sc, phy, 0); 1329 1330 for (i = 15; i >= 0; i--) 1331 be_tcvr_write_bit(sc, phy, (val >> i) & 1); 1332 1333 return 0; 1334 } 1335 1336 int 1337 be_mii_reset(struct be_softc *sc, int phy) 1338 { 1339 device_t self = sc->sc_dev; 1340 int n; 1341 1342 be_mii_writereg(self, phy, MII_BMCR, BMCR_LOOP | BMCR_PDOWN | BMCR_ISO); 1343 be_mii_writereg(self, phy, MII_BMCR, BMCR_RESET); 1344 1345 for (n = 16; n >= 0; n--) { 1346 uint16_t bmcr; 1347 1348 be_mii_readreg(self, phy, MII_BMCR, &bmcr); 1349 if ((bmcr & BMCR_RESET) == 0) 1350 break; 1351 DELAY(20); 1352 } 1353 if (n == 0) { 1354 aprint_error_dev(self, "bmcr reset failed\n"); 1355 return EIO; 1356 } 1357 1358 return 0; 1359 } 1360 1361 void 1362 be_tick(void *arg) 1363 { 1364 struct be_softc *sc = arg; 1365 int s = splnet(); 1366 1367 mii_tick(&sc->sc_mii); 1368 (void)be_intphy_service(sc, &sc->sc_mii, MII_TICK); 1369 1370 splx(s); 1371 callout_reset(&sc->sc_tick_ch, hz, be_tick, sc); 1372 } 1373 1374 void 1375 be_mii_statchg(struct ifnet *ifp) 1376 { 1377 struct be_softc *sc = ifp->if_softc; 1378 bus_space_tag_t t = sc->sc_bustag; 1379 bus_space_handle_t br = sc->sc_br; 1380 uint instance; 1381 uint32_t v; 1382 1383 instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media); 1384 #ifdef DIAGNOSTIC 1385 if (instance > 1) 1386 panic("be_mii_statchg: instance %d out of range", instance); 1387 #endif 1388 1389 /* Update duplex mode in TX configuration */ 1390 v = bus_space_read_4(t, br, BE_BRI_TXCFG); 1391 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 1392 v |= BE_BR_TXCFG_FULLDPLX; 1393 else 1394 v &= ~BE_BR_TXCFG_FULLDPLX; 1395 bus_space_write_4(t, br, BE_BRI_TXCFG, v); 1396 1397 /* Change to appropriate gate in transceiver PAL */ 1398 be_pal_gate(sc, sc->sc_phys[instance]); 1399 } 1400 1401 /* 1402 * Get current media settings. 1403 */ 1404 void 1405 be_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1406 { 1407 struct be_softc *sc = ifp->if_softc; 1408 1409 mii_pollstat(&sc->sc_mii); 1410 (void)be_intphy_service(sc, &sc->sc_mii, MII_POLLSTAT); 1411 1412 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1413 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1414 } 1415 1416 /* 1417 * Set media options. 1418 */ 1419 int 1420 be_ifmedia_upd(struct ifnet *ifp) 1421 { 1422 struct be_softc *sc = ifp->if_softc; 1423 int error; 1424 1425 if ((error = mii_mediachg(&sc->sc_mii)) == ENXIO) 1426 error = 0; 1427 else if (error != 0) 1428 return error; 1429 1430 return be_intphy_service(sc, &sc->sc_mii, MII_MEDIACHG); 1431 } 1432 1433 /* 1434 * Service routine for our pseudo-MII internal transceiver. 1435 */ 1436 int 1437 be_intphy_service(struct be_softc *sc, struct mii_data *mii, int cmd) 1438 { 1439 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 1440 device_t self = sc->sc_dev; 1441 uint16_t bmcr, bmsr; 1442 int error; 1443 1444 switch (cmd) { 1445 case MII_POLLSTAT: 1446 /* 1447 * If we're not polling our PHY instance, just return. 1448 */ 1449 if (IFM_INST(ife->ifm_media) != sc->sc_mii_inst) 1450 return 0; 1451 1452 break; 1453 1454 case MII_MEDIACHG: 1455 1456 /* 1457 * If the media indicates a different PHY instance, 1458 * isolate ourselves. 1459 */ 1460 if (IFM_INST(ife->ifm_media) != sc->sc_mii_inst) { 1461 be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMCR, &bmcr); 1462 be_mii_writereg(self, 1463 BE_PHY_INTERNAL, MII_BMCR, bmcr | BMCR_ISO); 1464 sc->sc_mii_flags &= ~MIIF_HAVELINK; 1465 sc->sc_intphy_curspeed = 0; 1466 return 0; 1467 } 1468 1469 1470 if ((error = be_mii_reset(sc, BE_PHY_INTERNAL)) != 0) 1471 return error; 1472 1473 be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMCR, &bmcr); 1474 1475 /* 1476 * Select the new mode and take out of isolation 1477 */ 1478 if (IFM_SUBTYPE(ife->ifm_media) == IFM_100_TX) 1479 bmcr |= BMCR_S100; 1480 else if (IFM_SUBTYPE(ife->ifm_media) == IFM_10_T) 1481 bmcr &= ~BMCR_S100; 1482 else if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) { 1483 if ((sc->sc_mii_flags & MIIF_HAVELINK) != 0) { 1484 bmcr &= ~BMCR_S100; 1485 bmcr |= sc->sc_intphy_curspeed; 1486 } else { 1487 /* Keep isolated until link is up */ 1488 bmcr |= BMCR_ISO; 1489 sc->sc_mii_flags |= MIIF_DOINGAUTO; 1490 } 1491 } 1492 1493 if ((IFM_OPTIONS(ife->ifm_media) & IFM_FDX) != 0) 1494 bmcr |= BMCR_FDX; 1495 else 1496 bmcr &= ~BMCR_FDX; 1497 1498 be_mii_writereg(self, BE_PHY_INTERNAL, MII_BMCR, bmcr); 1499 break; 1500 1501 case MII_TICK: 1502 /* 1503 * If we're not currently selected, just return. 1504 */ 1505 if (IFM_INST(ife->ifm_media) != sc->sc_mii_inst) 1506 return 0; 1507 1508 /* Is the interface even up? */ 1509 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 1510 return 0; 1511 1512 /* Only used for automatic media selection */ 1513 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) 1514 break; 1515 1516 /* 1517 * Check link status; if we don't have a link, try another 1518 * speed. We can't detect duplex mode, so half-duplex is 1519 * what we have to settle for. 1520 */ 1521 1522 /* Read twice in case the register is latched */ 1523 be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMSR, &bmsr); 1524 be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMSR, &bmsr); 1525 1526 if ((bmsr & BMSR_LINK) != 0) { 1527 /* We have a carrier */ 1528 be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMCR, &bmcr); 1529 1530 if ((sc->sc_mii_flags & MIIF_DOINGAUTO) != 0) { 1531 be_mii_readreg(self, 1532 BE_PHY_INTERNAL, MII_BMCR, &bmcr); 1533 1534 sc->sc_mii_flags |= MIIF_HAVELINK; 1535 sc->sc_intphy_curspeed = (bmcr & BMCR_S100); 1536 sc->sc_mii_flags &= ~MIIF_DOINGAUTO; 1537 1538 bmcr &= ~BMCR_ISO; 1539 be_mii_writereg(self, 1540 BE_PHY_INTERNAL, MII_BMCR, bmcr); 1541 1542 printf("%s: link up at %s Mbps\n", 1543 device_xname(self), 1544 (bmcr & BMCR_S100) ? "100" : "10"); 1545 } 1546 break; 1547 } 1548 1549 if ((sc->sc_mii_flags & MIIF_DOINGAUTO) == 0) { 1550 sc->sc_mii_flags |= MIIF_DOINGAUTO; 1551 sc->sc_mii_flags &= ~MIIF_HAVELINK; 1552 sc->sc_intphy_curspeed = 0; 1553 printf("%s: link down\n", device_xname(self)); 1554 } 1555 1556 /* Only retry autonegotiation every 5 seconds. */ 1557 if (++sc->sc_mii_ticks < 5) 1558 return 0; 1559 1560 sc->sc_mii_ticks = 0; 1561 be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMCR, &bmcr); 1562 /* Just flip the fast speed bit */ 1563 bmcr ^= BMCR_S100; 1564 be_mii_writereg(self, BE_PHY_INTERNAL, MII_BMCR, bmcr); 1565 1566 break; 1567 1568 case MII_DOWN: 1569 /* Isolate this phy */ 1570 be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMCR, &bmcr); 1571 be_mii_writereg(self, 1572 BE_PHY_INTERNAL, MII_BMCR, bmcr | BMCR_ISO); 1573 return 0; 1574 } 1575 1576 /* Update the media status. */ 1577 be_intphy_status(sc); 1578 1579 /* Callback if something changed. */ 1580 if (sc->sc_mii_active != mii->mii_media_active || cmd == MII_MEDIACHG) { 1581 (*mii->mii_statchg)(mii->mii_ifp); 1582 sc->sc_mii_active = mii->mii_media_active; 1583 } 1584 return 0; 1585 } 1586 1587 /* 1588 * Determine status of internal transceiver 1589 */ 1590 void 1591 be_intphy_status(struct be_softc *sc) 1592 { 1593 struct mii_data *mii = &sc->sc_mii; 1594 device_t self = sc->sc_dev; 1595 int media_active, media_status; 1596 uint16_t bmcr, bmsr; 1597 1598 media_status = IFM_AVALID; 1599 media_active = 0; 1600 1601 /* 1602 * Internal transceiver; do the work here. 1603 */ 1604 be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMCR, &bmcr); 1605 1606 switch (bmcr & (BMCR_S100 | BMCR_FDX)) { 1607 case (BMCR_S100 | BMCR_FDX): 1608 media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 1609 break; 1610 case BMCR_S100: 1611 media_active = IFM_ETHER | IFM_100_TX | IFM_HDX; 1612 break; 1613 case BMCR_FDX: 1614 media_active = IFM_ETHER | IFM_10_T | IFM_FDX; 1615 break; 1616 case 0: 1617 media_active = IFM_ETHER | IFM_10_T | IFM_HDX; 1618 break; 1619 } 1620 1621 /* Read twice in case the register is latched */ 1622 be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMSR, &bmsr); 1623 be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMSR, &bmsr); 1624 if (bmsr & BMSR_LINK) 1625 media_status |= IFM_ACTIVE; 1626 1627 mii->mii_media_status = media_status; 1628 mii->mii_media_active = media_active; 1629 } 1630
Indexes created Sat Oct 25 07:10:08 GMT 2025