be.c revision 1.90
1 /* $NetBSD: be.c,v 1.90 2019/01/22 03:42:28 msaitoh Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Copyright (c) 1998 Theo de Raadt and Jason L. Wright. 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. The name of the authors may not be used to endorse or promote products 45 * derived from this software without specific prior written permission. 46 * 47 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR 48 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 49 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 50 * IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, 51 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 52 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 53 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 54 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 55 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 56 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 57 */ 58 59 #include <sys/cdefs.h> 60 __KERNEL_RCSID(0, "$NetBSD: be.c,v 1.90 2019/01/22 03:42:28 msaitoh Exp $"); 61 62 #include "opt_ddb.h" 63 #include "opt_inet.h" 64 65 #include <sys/param.h> 66 #include <sys/systm.h> 67 #include <sys/callout.h> 68 #include <sys/kernel.h> 69 #include <sys/errno.h> 70 #include <sys/ioctl.h> 71 #include <sys/mbuf.h> 72 #include <sys/socket.h> 73 #include <sys/syslog.h> 74 #include <sys/device.h> 75 #include <sys/malloc.h> 76 77 #include <net/if.h> 78 #include <net/if_dl.h> 79 #include <net/if_types.h> 80 #include <net/netisr.h> 81 #include <net/if_media.h> 82 #include <net/if_ether.h> 83 #include <net/bpf.h> 84 85 #ifdef INET 86 #include <netinet/in.h> 87 #include <netinet/if_inarp.h> 88 #include <netinet/in_systm.h> 89 #include <netinet/in_var.h> 90 #include <netinet/ip.h> 91 #endif 92 93 #include <sys/bus.h> 94 #include <sys/intr.h> 95 #include <machine/autoconf.h> 96 97 #include <dev/sbus/sbusvar.h> 98 99 #include <dev/mii/mii.h> 100 #include <dev/mii/miivar.h> 101 102 #include <dev/sbus/qecreg.h> 103 #include <dev/sbus/qecvar.h> 104 #include <dev/sbus/bereg.h> 105 106 struct be_softc { 107 device_t sc_dev; 108 bus_space_tag_t sc_bustag; /* bus & DMA tags */ 109 bus_dma_tag_t sc_dmatag; 110 bus_dmamap_t sc_dmamap; 111 struct ethercom sc_ethercom; 112 /*struct ifmedia sc_ifmedia; -* interface media */ 113 struct mii_data sc_mii; /* MII media control */ 114 #define sc_media sc_mii.mii_media/* shorthand */ 115 int sc_phys[2]; /* MII instance -> phy */ 116 117 struct callout sc_tick_ch; 118 119 /* 120 * Some `mii_softc' items we need to emulate MII operation 121 * for our internal transceiver. 122 */ 123 int sc_mii_inst; /* instance of internal phy */ 124 int sc_mii_active; /* currently active medium */ 125 int sc_mii_ticks; /* tick counter */ 126 int sc_mii_flags; /* phy status flags */ 127 #define MIIF_HAVELINK 0x04000000 128 int sc_intphy_curspeed; /* Established link speed */ 129 130 struct qec_softc *sc_qec; /* QEC parent */ 131 132 bus_space_handle_t sc_qr; /* QEC registers */ 133 bus_space_handle_t sc_br; /* BE registers */ 134 bus_space_handle_t sc_cr; /* channel registers */ 135 bus_space_handle_t sc_tr; /* transceiver registers */ 136 137 u_int sc_rev; 138 139 int sc_channel; /* channel number */ 140 int sc_burst; 141 142 struct qec_ring sc_rb; /* Packet Ring Buffer */ 143 144 /* MAC address */ 145 uint8_t sc_enaddr[ETHER_ADDR_LEN]; 146 #ifdef BEDEBUG 147 int sc_debug; 148 #endif 149 }; 150 151 static int bematch(device_t, cfdata_t, void *); 152 static void beattach(device_t, device_t, void *); 153 154 static int beinit(struct ifnet *); 155 static void bestart(struct ifnet *); 156 static void bestop(struct ifnet *, int); 157 static void bewatchdog(struct ifnet *); 158 static int beioctl(struct ifnet *, u_long, void *); 159 static void bereset(struct be_softc *); 160 static void behwreset(struct be_softc *); 161 162 static int beintr(void *); 163 static int berint(struct be_softc *); 164 static int betint(struct be_softc *); 165 static int beqint(struct be_softc *, uint32_t); 166 static int beeint(struct be_softc *, uint32_t); 167 168 static void be_read(struct be_softc *, int, int); 169 static int be_put(struct be_softc *, int, struct mbuf *); 170 static struct mbuf *be_get(struct be_softc *, int, int); 171 172 static void be_pal_gate(struct be_softc *, int); 173 174 /* ifmedia callbacks */ 175 static void be_ifmedia_sts(struct ifnet *, struct ifmediareq *); 176 static int be_ifmedia_upd(struct ifnet *); 177 178 static void be_mcreset(struct be_softc *); 179 180 /* MII methods & callbacks */ 181 static int be_mii_readreg(device_t, int, int, uint16_t *); 182 static int be_mii_writereg(device_t, int, int, uint16_t); 183 static void be_mii_statchg(struct ifnet *); 184 185 /* MII helpers */ 186 static void be_mii_sync(struct be_softc *); 187 static void be_mii_sendbits(struct be_softc *, int, uint32_t, int); 188 static int be_mii_reset(struct be_softc *, int); 189 static int be_tcvr_read_bit(struct be_softc *, int); 190 static void be_tcvr_write_bit(struct be_softc *, int, int); 191 192 static void be_tick(void *); 193 #if 0 194 static void be_intphy_auto(struct be_softc *); 195 #endif 196 static void be_intphy_status(struct be_softc *); 197 static int be_intphy_service(struct be_softc *, struct mii_data *, int); 198 199 200 CFATTACH_DECL_NEW(be, sizeof(struct be_softc), 201 bematch, beattach, NULL, NULL); 202 203 int 204 bematch(device_t parent, cfdata_t cf, void *aux) 205 { 206 struct sbus_attach_args *sa = aux; 207 208 return strcmp(cf->cf_name, sa->sa_name) == 0; 209 } 210 211 void 212 beattach(device_t parent, device_t self, void *aux) 213 { 214 struct sbus_attach_args *sa = aux; 215 struct qec_softc *qec = device_private(parent); 216 struct be_softc *sc = device_private(self); 217 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 218 struct mii_data *mii = &sc->sc_mii; 219 struct mii_softc *child; 220 int node = sa->sa_node; 221 bus_dma_tag_t dmatag = sa->sa_dmatag; 222 bus_dma_segment_t seg; 223 bus_size_t size; 224 int instance; 225 int rseg, error; 226 uint32_t v; 227 228 sc->sc_dev = self; 229 230 if (sa->sa_nreg < 3) { 231 printf(": only %d register sets\n", sa->sa_nreg); 232 return; 233 } 234 235 if (bus_space_map(sa->sa_bustag, 236 (bus_addr_t)BUS_ADDR(sa->sa_reg[0].oa_space, sa->sa_reg[0].oa_base), 237 (bus_size_t)sa->sa_reg[0].oa_size, 238 0, &sc->sc_cr) != 0) { 239 printf(": cannot map registers\n"); 240 return; 241 } 242 243 if (bus_space_map(sa->sa_bustag, 244 (bus_addr_t)BUS_ADDR(sa->sa_reg[1].oa_space, sa->sa_reg[1].oa_base), 245 (bus_size_t)sa->sa_reg[1].oa_size, 246 0, &sc->sc_br) != 0) { 247 printf(": cannot map registers\n"); 248 return; 249 } 250 251 if (bus_space_map(sa->sa_bustag, 252 (bus_addr_t)BUS_ADDR(sa->sa_reg[2].oa_space, sa->sa_reg[2].oa_base), 253 (bus_size_t)sa->sa_reg[2].oa_size, 254 0, &sc->sc_tr) != 0) { 255 printf(": cannot map registers\n"); 256 return; 257 } 258 259 sc->sc_bustag = sa->sa_bustag; 260 sc->sc_qec = qec; 261 sc->sc_qr = qec->sc_regs; 262 263 sc->sc_rev = prom_getpropint(node, "board-version", -1); 264 printf(": rev %x,", sc->sc_rev); 265 266 callout_init(&sc->sc_tick_ch, 0); 267 268 sc->sc_channel = prom_getpropint(node, "channel#", -1); 269 if (sc->sc_channel == -1) 270 sc->sc_channel = 0; 271 272 sc->sc_burst = prom_getpropint(node, "burst-sizes", -1); 273 if (sc->sc_burst == -1) 274 sc->sc_burst = qec->sc_burst; 275 276 /* Clamp at parent's burst sizes */ 277 sc->sc_burst &= qec->sc_burst; 278 279 /* Establish interrupt handler */ 280 if (sa->sa_nintr) 281 (void)bus_intr_establish(sa->sa_bustag, sa->sa_pri, IPL_NET, 282 beintr, sc); 283 284 prom_getether(node, sc->sc_enaddr); 285 printf(" address %s\n", ether_sprintf(sc->sc_enaddr)); 286 287 /* 288 * Allocate descriptor ring and buffers. 289 */ 290 291 /* for now, allocate as many bufs as there are ring descriptors */ 292 sc->sc_rb.rb_ntbuf = QEC_XD_RING_MAXSIZE; 293 sc->sc_rb.rb_nrbuf = QEC_XD_RING_MAXSIZE; 294 295 size = 296 QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd) + 297 QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd) + 298 sc->sc_rb.rb_ntbuf * BE_PKT_BUF_SZ + 299 sc->sc_rb.rb_nrbuf * BE_PKT_BUF_SZ; 300 301 /* Get a DMA handle */ 302 if ((error = bus_dmamap_create(dmatag, size, 1, size, 0, 303 BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) { 304 aprint_error_dev(self, "DMA map create error %d\n", error); 305 return; 306 } 307 308 /* Allocate DMA buffer */ 309 if ((error = bus_dmamem_alloc(sa->sa_dmatag, size, 0, 0, 310 &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 311 aprint_error_dev(self, "DMA buffer alloc error %d\n", error); 312 return; 313 } 314 315 /* Map DMA memory in CPU addressable space */ 316 if ((error = bus_dmamem_map(sa->sa_dmatag, &seg, rseg, size, 317 &sc->sc_rb.rb_membase, BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 318 aprint_error_dev(self, "DMA buffer map error %d\n", error); 319 bus_dmamem_free(sa->sa_dmatag, &seg, rseg); 320 return; 321 } 322 323 /* Load the buffer */ 324 if ((error = bus_dmamap_load(dmatag, sc->sc_dmamap, 325 sc->sc_rb.rb_membase, size, NULL, BUS_DMA_NOWAIT)) != 0) { 326 aprint_error_dev(self, "DMA buffer map load error %d\n", error); 327 bus_dmamem_unmap(dmatag, sc->sc_rb.rb_membase, size); 328 bus_dmamem_free(dmatag, &seg, rseg); 329 return; 330 } 331 sc->sc_rb.rb_dmabase = sc->sc_dmamap->dm_segs[0].ds_addr; 332 333 /* 334 * Initialize our media structures and MII info. 335 */ 336 mii->mii_ifp = ifp; 337 mii->mii_readreg = be_mii_readreg; 338 mii->mii_writereg = be_mii_writereg; 339 mii->mii_statchg = be_mii_statchg; 340 341 ifmedia_init(&mii->mii_media, 0, be_ifmedia_upd, be_ifmedia_sts); 342 343 /* 344 * Initialize transceiver and determine which PHY connection to use. 345 */ 346 be_mii_sync(sc); 347 v = bus_space_read_4(sc->sc_bustag, sc->sc_tr, BE_TRI_MGMTPAL); 348 349 instance = 0; 350 351 if ((v & MGMT_PAL_EXT_MDIO) != 0) { 352 353 mii_attach(self, mii, 0xffffffff, BE_PHY_EXTERNAL, 354 MII_OFFSET_ANY, 0); 355 356 child = LIST_FIRST(&mii->mii_phys); 357 if (child == NULL) { 358 /* No PHY attached */ 359 ifmedia_add(&sc->sc_media, 360 IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, instance), 361 0, NULL); 362 ifmedia_set(&sc->sc_media, 363 IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, instance)); 364 } else { 365 /* 366 * Note: we support just one PHY on the external 367 * MII connector. 368 */ 369 #ifdef DIAGNOSTIC 370 if (LIST_NEXT(child, mii_list) != NULL) { 371 aprint_error_dev(self, 372 "spurious MII device %s attached\n", 373 device_xname(child->mii_dev)); 374 } 375 #endif 376 if (child->mii_phy != BE_PHY_EXTERNAL || 377 child->mii_inst > 0) { 378 aprint_error_dev(self, 379 "cannot accommodate MII device %s" 380 " at phy %d, instance %d\n", 381 device_xname(child->mii_dev), 382 child->mii_phy, child->mii_inst); 383 } else { 384 sc->sc_phys[instance] = child->mii_phy; 385 } 386 387 /* 388 * XXX - we can really do the following ONLY if the 389 * phy indeed has the auto negotiation capability!! 390 */ 391 ifmedia_set(&sc->sc_media, 392 IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, instance)); 393 394 /* Mark our current media setting */ 395 be_pal_gate(sc, BE_PHY_EXTERNAL); 396 instance++; 397 } 398 399 } 400 401 if ((v & MGMT_PAL_INT_MDIO) != 0) { 402 /* 403 * The be internal phy looks vaguely like MII hardware, 404 * but not enough to be able to use the MII device 405 * layer. Hence, we have to take care of media selection 406 * ourselves. 407 */ 408 409 sc->sc_mii_inst = instance; 410 sc->sc_phys[instance] = BE_PHY_INTERNAL; 411 412 /* Use `ifm_data' to store BMCR bits */ 413 ifmedia_add(&sc->sc_media, 414 IFM_MAKEWORD(IFM_ETHER, IFM_10_T, 0, instance), 415 0, NULL); 416 ifmedia_add(&sc->sc_media, 417 IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, 0, instance), 418 BMCR_S100, NULL); 419 ifmedia_add(&sc->sc_media, 420 IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, instance), 421 0, NULL); 422 423 printf("on-board transceiver at %s: 10baseT, 100baseTX, auto\n", 424 device_xname(self)); 425 426 be_mii_reset(sc, BE_PHY_INTERNAL); 427 /* Only set default medium here if there's no external PHY */ 428 if (instance == 0) { 429 be_pal_gate(sc, BE_PHY_INTERNAL); 430 ifmedia_set(&sc->sc_media, 431 IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, instance)); 432 } else 433 be_mii_writereg(self, 434 BE_PHY_INTERNAL, MII_BMCR, BMCR_ISO); 435 } 436 437 memcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 438 ifp->if_softc = sc; 439 ifp->if_start = bestart; 440 ifp->if_ioctl = beioctl; 441 ifp->if_watchdog = bewatchdog; 442 ifp->if_init = beinit; 443 ifp->if_stop = bestop; 444 ifp->if_flags = 445 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 446 IFQ_SET_READY(&ifp->if_snd); 447 448 /* claim 802.1q capability */ 449 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 450 451 /* Attach the interface. */ 452 if_attach(ifp); 453 ether_ifattach(ifp, sc->sc_enaddr); 454 } 455 456 457 /* 458 * Routine to copy from mbuf chain to transmit buffer in 459 * network buffer memory. 460 */ 461 static inline int 462 be_put(struct be_softc *sc, int idx, struct mbuf *m) 463 { 464 struct mbuf *n; 465 int len, tlen = 0, boff = 0; 466 uint8_t *bp; 467 468 bp = sc->sc_rb.rb_txbuf + (idx % sc->sc_rb.rb_ntbuf) * BE_PKT_BUF_SZ; 469 470 for (; m; m = n) { 471 len = m->m_len; 472 if (len == 0) { 473 n = m_free(m); 474 continue; 475 } 476 memcpy(bp + boff, mtod(m, void *), len); 477 boff += len; 478 tlen += len; 479 n = m_free(m); 480 } 481 return tlen; 482 } 483 484 /* 485 * Pull data off an interface. 486 * Len is the length of data, with local net header stripped. 487 * We copy the data into mbufs. When full cluster sized units are present, 488 * we copy into clusters. 489 */ 490 static inline struct mbuf * 491 be_get(struct be_softc *sc, int idx, int totlen) 492 { 493 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 494 struct mbuf *m; 495 struct mbuf *top, **mp; 496 int len, pad, boff = 0; 497 uint8_t *bp; 498 499 bp = sc->sc_rb.rb_rxbuf + (idx % sc->sc_rb.rb_nrbuf) * BE_PKT_BUF_SZ; 500 501 MGETHDR(m, M_DONTWAIT, MT_DATA); 502 if (m == NULL) 503 return (NULL); 504 m_set_rcvif(m, ifp); 505 m->m_pkthdr.len = totlen; 506 507 pad = ALIGN(sizeof(struct ether_header)) - sizeof(struct ether_header); 508 m->m_data += pad; 509 len = MHLEN - pad; 510 top = NULL; 511 mp = ⊤ 512 513 while (totlen > 0) { 514 if (top) { 515 MGET(m, M_DONTWAIT, MT_DATA); 516 if (m == NULL) { 517 m_freem(top); 518 return (NULL); 519 } 520 len = MLEN; 521 } 522 if (top && totlen >= MINCLSIZE) { 523 MCLGET(m, M_DONTWAIT); 524 if (m->m_flags & M_EXT) 525 len = MCLBYTES; 526 } 527 m->m_len = len = uimin(totlen, len); 528 memcpy(mtod(m, void *), bp + boff, len); 529 boff += len; 530 totlen -= len; 531 *mp = m; 532 mp = &m->m_next; 533 } 534 535 return top; 536 } 537 538 /* 539 * Pass a packet to the higher levels. 540 */ 541 static inline void 542 be_read(struct be_softc *sc, int idx, int len) 543 { 544 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 545 struct mbuf *m; 546 547 if (len <= sizeof(struct ether_header) || 548 len > ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN) { 549 #ifdef BEDEBUG 550 if (sc->sc_debug) 551 printf("%s: invalid packet size %d; dropping\n", 552 ifp->if_xname, len); 553 #endif 554 ifp->if_ierrors++; 555 return; 556 } 557 558 /* 559 * Pull packet off interface. 560 */ 561 m = be_get(sc, idx, len); 562 if (m == NULL) { 563 ifp->if_ierrors++; 564 return; 565 } 566 567 /* Pass the packet up. */ 568 if_percpuq_enqueue(ifp->if_percpuq, m); 569 } 570 571 /* 572 * Start output on interface. 573 * We make two assumptions here: 574 * 1) that the current priority is set to splnet _before_ this code 575 * is called *and* is returned to the appropriate priority after 576 * return 577 * 2) that the IFF_OACTIVE flag is checked before this code is called 578 * (i.e. that the output part of the interface is idle) 579 */ 580 void 581 bestart(struct ifnet *ifp) 582 { 583 struct be_softc *sc = ifp->if_softc; 584 struct qec_xd *txd = sc->sc_rb.rb_txd; 585 struct mbuf *m; 586 unsigned int bix, len; 587 unsigned int ntbuf = sc->sc_rb.rb_ntbuf; 588 589 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 590 return; 591 592 bix = sc->sc_rb.rb_tdhead; 593 594 for (;;) { 595 IFQ_DEQUEUE(&ifp->if_snd, m); 596 if (m == 0) 597 break; 598 599 /* 600 * If BPF is listening on this interface, let it see the 601 * packet before we commit it to the wire. 602 */ 603 bpf_mtap(ifp, m, BPF_D_OUT); 604 605 /* 606 * Copy the mbuf chain into the transmit buffer. 607 */ 608 len = be_put(sc, bix, m); 609 610 /* 611 * Initialize transmit registers and start transmission 612 */ 613 txd[bix].xd_flags = QEC_XD_OWN | QEC_XD_SOP | QEC_XD_EOP | 614 (len & QEC_XD_LENGTH); 615 bus_space_write_4(sc->sc_bustag, sc->sc_cr, 616 BE_CRI_CTRL, BE_CR_CTRL_TWAKEUP); 617 618 if (++bix == QEC_XD_RING_MAXSIZE) 619 bix = 0; 620 621 if (++sc->sc_rb.rb_td_nbusy == ntbuf) { 622 ifp->if_flags |= IFF_OACTIVE; 623 break; 624 } 625 } 626 627 sc->sc_rb.rb_tdhead = bix; 628 } 629 630 void 631 bestop(struct ifnet *ifp, int disable) 632 { 633 struct be_softc *sc = ifp->if_softc; 634 635 callout_stop(&sc->sc_tick_ch); 636 637 /* Down the MII. */ 638 mii_down(&sc->sc_mii); 639 (void)be_intphy_service(sc, &sc->sc_mii, MII_DOWN); 640 641 behwreset(sc); 642 } 643 644 void 645 behwreset(struct be_softc *sc) 646 { 647 int n; 648 bus_space_tag_t t = sc->sc_bustag; 649 bus_space_handle_t br = sc->sc_br; 650 651 /* Stop the transmitter */ 652 bus_space_write_4(t, br, BE_BRI_TXCFG, 0); 653 for (n = 32; n > 0; n--) { 654 if (bus_space_read_4(t, br, BE_BRI_TXCFG) == 0) 655 break; 656 DELAY(20); 657 } 658 659 /* Stop the receiver */ 660 bus_space_write_4(t, br, BE_BRI_RXCFG, 0); 661 for (n = 32; n > 0; n--) { 662 if (bus_space_read_4(t, br, BE_BRI_RXCFG) == 0) 663 break; 664 DELAY(20); 665 } 666 } 667 668 /* 669 * Reset interface. 670 */ 671 void 672 bereset(struct be_softc *sc) 673 { 674 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 675 int s; 676 677 s = splnet(); 678 behwreset(sc); 679 if ((sc->sc_ethercom.ec_if.if_flags & IFF_UP) != 0) 680 beinit(ifp); 681 splx(s); 682 } 683 684 void 685 bewatchdog(struct ifnet *ifp) 686 { 687 struct be_softc *sc = ifp->if_softc; 688 689 log(LOG_ERR, "%s: device timeout\n", device_xname(sc->sc_dev)); 690 ++sc->sc_ethercom.ec_if.if_oerrors; 691 692 bereset(sc); 693 } 694 695 int 696 beintr(void *arg) 697 { 698 struct be_softc *sc = arg; 699 bus_space_tag_t t = sc->sc_bustag; 700 uint32_t whyq, whyb, whyc; 701 int r = 0; 702 703 /* Read QEC status, channel status and BE status */ 704 whyq = bus_space_read_4(t, sc->sc_qr, QEC_QRI_STAT); 705 whyc = bus_space_read_4(t, sc->sc_cr, BE_CRI_STAT); 706 whyb = bus_space_read_4(t, sc->sc_br, BE_BRI_STAT); 707 708 if (whyq & QEC_STAT_BM) 709 r |= beeint(sc, whyb); 710 711 if (whyq & QEC_STAT_ER) 712 r |= beqint(sc, whyc); 713 714 if (whyq & QEC_STAT_TX && whyc & BE_CR_STAT_TXIRQ) 715 r |= betint(sc); 716 717 if (whyq & QEC_STAT_RX && whyc & BE_CR_STAT_RXIRQ) 718 r |= berint(sc); 719 720 return r; 721 } 722 723 /* 724 * QEC Interrupt. 725 */ 726 int 727 beqint(struct be_softc *sc, uint32_t why) 728 { 729 device_t self = sc->sc_dev; 730 int r = 0, rst = 0; 731 732 if (why & BE_CR_STAT_TXIRQ) 733 r |= 1; 734 if (why & BE_CR_STAT_RXIRQ) 735 r |= 1; 736 737 if (why & BE_CR_STAT_BERROR) { 738 r |= 1; 739 rst = 1; 740 aprint_error_dev(self, "bigmac error\n"); 741 } 742 743 if (why & BE_CR_STAT_TXDERR) { 744 r |= 1; 745 rst = 1; 746 aprint_error_dev(self, "bogus tx descriptor\n"); 747 } 748 749 if (why & (BE_CR_STAT_TXLERR | BE_CR_STAT_TXPERR | BE_CR_STAT_TXSERR)) { 750 r |= 1; 751 rst = 1; 752 aprint_error_dev(self, "tx DMA error ( "); 753 if (why & BE_CR_STAT_TXLERR) 754 printf("Late "); 755 if (why & BE_CR_STAT_TXPERR) 756 printf("Parity "); 757 if (why & BE_CR_STAT_TXSERR) 758 printf("Generic "); 759 printf(")\n"); 760 } 761 762 if (why & BE_CR_STAT_RXDROP) { 763 r |= 1; 764 rst = 1; 765 aprint_error_dev(self, "out of rx descriptors\n"); 766 } 767 768 if (why & BE_CR_STAT_RXSMALL) { 769 r |= 1; 770 rst = 1; 771 aprint_error_dev(self, "rx descriptor too small\n"); 772 } 773 774 if (why & (BE_CR_STAT_RXLERR | BE_CR_STAT_RXPERR | BE_CR_STAT_RXSERR)) { 775 r |= 1; 776 rst = 1; 777 aprint_error_dev(self, "rx DMA error ( "); 778 if (why & BE_CR_STAT_RXLERR) 779 printf("Late "); 780 if (why & BE_CR_STAT_RXPERR) 781 printf("Parity "); 782 if (why & BE_CR_STAT_RXSERR) 783 printf("Generic "); 784 printf(")\n"); 785 } 786 787 if (!r) { 788 rst = 1; 789 aprint_error_dev(self, "unexpected error interrupt %08x\n", 790 why); 791 } 792 793 if (rst) { 794 printf("%s: resetting\n", device_xname(self)); 795 bereset(sc); 796 } 797 798 return r; 799 } 800 801 /* 802 * Error interrupt. 803 */ 804 int 805 beeint(struct be_softc *sc, uint32_t why) 806 { 807 device_t self = sc->sc_dev; 808 int r = 0, rst = 0; 809 810 if (why & BE_BR_STAT_RFIFOVF) { 811 r |= 1; 812 rst = 1; 813 aprint_error_dev(self, "receive fifo overrun\n"); 814 } 815 if (why & BE_BR_STAT_TFIFO_UND) { 816 r |= 1; 817 rst = 1; 818 aprint_error_dev(self, "transmit fifo underrun\n"); 819 } 820 if (why & BE_BR_STAT_MAXPKTERR) { 821 r |= 1; 822 rst = 1; 823 aprint_error_dev(self, "max packet size error\n"); 824 } 825 826 if (!r) { 827 rst = 1; 828 aprint_error_dev(self, "unexpected error interrupt %08x\n", 829 why); 830 } 831 832 if (rst) { 833 printf("%s: resetting\n", device_xname(self)); 834 bereset(sc); 835 } 836 837 return r; 838 } 839 840 /* 841 * Transmit interrupt. 842 */ 843 int 844 betint(struct be_softc *sc) 845 { 846 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 847 bus_space_tag_t t = sc->sc_bustag; 848 bus_space_handle_t br = sc->sc_br; 849 unsigned int bix, txflags; 850 851 /* 852 * Unload collision counters 853 */ 854 ifp->if_collisions += 855 bus_space_read_4(t, br, BE_BRI_NCCNT) + 856 bus_space_read_4(t, br, BE_BRI_FCCNT) + 857 bus_space_read_4(t, br, BE_BRI_EXCNT) + 858 bus_space_read_4(t, br, BE_BRI_LTCNT); 859 860 /* 861 * the clear the hardware counters 862 */ 863 bus_space_write_4(t, br, BE_BRI_NCCNT, 0); 864 bus_space_write_4(t, br, BE_BRI_FCCNT, 0); 865 bus_space_write_4(t, br, BE_BRI_EXCNT, 0); 866 bus_space_write_4(t, br, BE_BRI_LTCNT, 0); 867 868 bix = sc->sc_rb.rb_tdtail; 869 870 for (;;) { 871 if (sc->sc_rb.rb_td_nbusy <= 0) 872 break; 873 874 txflags = sc->sc_rb.rb_txd[bix].xd_flags; 875 876 if (txflags & QEC_XD_OWN) 877 break; 878 879 ifp->if_flags &= ~IFF_OACTIVE; 880 ifp->if_opackets++; 881 882 if (++bix == QEC_XD_RING_MAXSIZE) 883 bix = 0; 884 885 --sc->sc_rb.rb_td_nbusy; 886 } 887 888 sc->sc_rb.rb_tdtail = bix; 889 890 bestart(ifp); 891 892 if (sc->sc_rb.rb_td_nbusy == 0) 893 ifp->if_timer = 0; 894 895 return 1; 896 } 897 898 /* 899 * Receive interrupt. 900 */ 901 int 902 berint(struct be_softc *sc) 903 { 904 struct qec_xd *xd = sc->sc_rb.rb_rxd; 905 unsigned int bix, len; 906 unsigned int nrbuf = sc->sc_rb.rb_nrbuf; 907 908 bix = sc->sc_rb.rb_rdtail; 909 910 /* 911 * Process all buffers with valid data. 912 */ 913 for (;;) { 914 len = xd[bix].xd_flags; 915 if (len & QEC_XD_OWN) 916 break; 917 918 len &= QEC_XD_LENGTH; 919 be_read(sc, bix, len); 920 921 /* ... */ 922 xd[(bix+nrbuf) % QEC_XD_RING_MAXSIZE].xd_flags = 923 QEC_XD_OWN | (BE_PKT_BUF_SZ & QEC_XD_LENGTH); 924 925 if (++bix == QEC_XD_RING_MAXSIZE) 926 bix = 0; 927 } 928 929 sc->sc_rb.rb_rdtail = bix; 930 931 return 1; 932 } 933 934 int 935 beioctl(struct ifnet *ifp, u_long cmd, void *data) 936 { 937 struct be_softc *sc = ifp->if_softc; 938 struct ifaddr *ifa = data; 939 struct ifreq *ifr = data; 940 int s, error = 0; 941 942 s = splnet(); 943 944 switch (cmd) { 945 case SIOCINITIFADDR: 946 ifp->if_flags |= IFF_UP; 947 beinit(ifp); 948 switch (ifa->ifa_addr->sa_family) { 949 #ifdef INET 950 case AF_INET: 951 arp_ifinit(ifp, ifa); 952 break; 953 #endif /* INET */ 954 default: 955 break; 956 } 957 break; 958 959 case SIOCSIFFLAGS: 960 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 961 break; 962 /* XXX re-use ether_ioctl() */ 963 switch (ifp->if_flags & (IFF_UP|IFF_RUNNING)) { 964 case IFF_RUNNING: 965 /* 966 * If interface is marked down and it is running, then 967 * stop it. 968 */ 969 bestop(ifp, 0); 970 ifp->if_flags &= ~IFF_RUNNING; 971 break; 972 case IFF_UP: 973 /* 974 * If interface is marked up and it is stopped, then 975 * start it. 976 */ 977 beinit(ifp); 978 break; 979 default: 980 /* 981 * Reset the interface to pick up changes in any other 982 * flags that affect hardware registers. 983 */ 984 bestop(ifp, 0); 985 beinit(ifp); 986 break; 987 } 988 #ifdef BEDEBUG 989 if (ifp->if_flags & IFF_DEBUG) 990 sc->sc_debug = 1; 991 else 992 sc->sc_debug = 0; 993 #endif 994 break; 995 996 case SIOCGIFMEDIA: 997 case SIOCSIFMEDIA: 998 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd); 999 break; 1000 default: 1001 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 1002 /* 1003 * Multicast list has changed; set the hardware filter 1004 * accordingly. 1005 */ 1006 if (ifp->if_flags & IFF_RUNNING) 1007 error = beinit(ifp); 1008 else 1009 error = 0; 1010 } 1011 break; 1012 } 1013 splx(s); 1014 return error; 1015 } 1016 1017 1018 int 1019 beinit(struct ifnet *ifp) 1020 { 1021 struct be_softc *sc = ifp->if_softc; 1022 bus_space_tag_t t = sc->sc_bustag; 1023 bus_space_handle_t br = sc->sc_br; 1024 bus_space_handle_t cr = sc->sc_cr; 1025 struct qec_softc *qec = sc->sc_qec; 1026 uint32_t v; 1027 uint32_t qecaddr; 1028 uint8_t *ea; 1029 int rc, s; 1030 1031 s = splnet(); 1032 1033 qec_meminit(&sc->sc_rb, BE_PKT_BUF_SZ); 1034 1035 bestop(ifp, 1); 1036 1037 ea = sc->sc_enaddr; 1038 bus_space_write_4(t, br, BE_BRI_MACADDR0, (ea[0] << 8) | ea[1]); 1039 bus_space_write_4(t, br, BE_BRI_MACADDR1, (ea[2] << 8) | ea[3]); 1040 bus_space_write_4(t, br, BE_BRI_MACADDR2, (ea[4] << 8) | ea[5]); 1041 1042 /* Clear hash table */ 1043 bus_space_write_4(t, br, BE_BRI_HASHTAB0, 0); 1044 bus_space_write_4(t, br, BE_BRI_HASHTAB1, 0); 1045 bus_space_write_4(t, br, BE_BRI_HASHTAB2, 0); 1046 bus_space_write_4(t, br, BE_BRI_HASHTAB3, 0); 1047 1048 /* Re-initialize RX configuration */ 1049 v = BE_BR_RXCFG_FIFO; 1050 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1051 1052 be_mcreset(sc); 1053 1054 bus_space_write_4(t, br, BE_BRI_RANDSEED, 0xbd); 1055 1056 bus_space_write_4(t, br, 1057 BE_BRI_XIFCFG, BE_BR_XCFG_ODENABLE | BE_BR_XCFG_RESV); 1058 1059 bus_space_write_4(t, br, BE_BRI_JSIZE, 4); 1060 1061 /* 1062 * Turn off counter expiration interrupts as well as 1063 * 'gotframe' and 'sentframe' 1064 */ 1065 bus_space_write_4(t, br, BE_BRI_IMASK, 1066 BE_BR_IMASK_GOTFRAME | 1067 BE_BR_IMASK_RCNTEXP | 1068 BE_BR_IMASK_ACNTEXP | 1069 BE_BR_IMASK_CCNTEXP | 1070 BE_BR_IMASK_LCNTEXP | 1071 BE_BR_IMASK_CVCNTEXP | 1072 BE_BR_IMASK_SENTFRAME | 1073 BE_BR_IMASK_NCNTEXP | 1074 BE_BR_IMASK_ECNTEXP | 1075 BE_BR_IMASK_LCCNTEXP | 1076 BE_BR_IMASK_FCNTEXP | 1077 BE_BR_IMASK_DTIMEXP); 1078 1079 /* Channel registers: */ 1080 bus_space_write_4(t, cr, BE_CRI_RXDS, (uint32_t)sc->sc_rb.rb_rxddma); 1081 bus_space_write_4(t, cr, BE_CRI_TXDS, (uint32_t)sc->sc_rb.rb_txddma); 1082 1083 qecaddr = sc->sc_channel * qec->sc_msize; 1084 bus_space_write_4(t, cr, BE_CRI_RXWBUF, qecaddr); 1085 bus_space_write_4(t, cr, BE_CRI_RXRBUF, qecaddr); 1086 bus_space_write_4(t, cr, BE_CRI_TXWBUF, qecaddr + qec->sc_rsize); 1087 bus_space_write_4(t, cr, BE_CRI_TXRBUF, qecaddr + qec->sc_rsize); 1088 1089 bus_space_write_4(t, cr, BE_CRI_RIMASK, 0); 1090 bus_space_write_4(t, cr, BE_CRI_TIMASK, 0); 1091 bus_space_write_4(t, cr, BE_CRI_QMASK, 0); 1092 bus_space_write_4(t, cr, BE_CRI_BMASK, 0); 1093 bus_space_write_4(t, cr, BE_CRI_CCNT, 0); 1094 1095 /* Set max packet length */ 1096 v = ETHER_MAX_LEN; 1097 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) 1098 v += ETHER_VLAN_ENCAP_LEN; 1099 bus_space_write_4(t, br, BE_BRI_RXMAX, v); 1100 bus_space_write_4(t, br, BE_BRI_TXMAX, v); 1101 1102 /* Enable transmitter */ 1103 bus_space_write_4(t, br, 1104 BE_BRI_TXCFG, BE_BR_TXCFG_FIFO | BE_BR_TXCFG_ENABLE); 1105 1106 /* Enable receiver */ 1107 v = bus_space_read_4(t, br, BE_BRI_RXCFG); 1108 v |= BE_BR_RXCFG_FIFO | BE_BR_RXCFG_ENABLE; 1109 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1110 1111 if ((rc = be_ifmedia_upd(ifp)) != 0) 1112 goto out; 1113 1114 ifp->if_flags |= IFF_RUNNING; 1115 ifp->if_flags &= ~IFF_OACTIVE; 1116 1117 callout_reset(&sc->sc_tick_ch, hz, be_tick, sc); 1118 1119 splx(s); 1120 return 0; 1121 out: 1122 splx(s); 1123 return rc; 1124 } 1125 1126 void 1127 be_mcreset(struct be_softc *sc) 1128 { 1129 struct ethercom *ec = &sc->sc_ethercom; 1130 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1131 bus_space_tag_t t = sc->sc_bustag; 1132 bus_space_handle_t br = sc->sc_br; 1133 uint32_t v; 1134 uint32_t crc; 1135 uint16_t hash[4]; 1136 struct ether_multi *enm; 1137 struct ether_multistep step; 1138 1139 if (ifp->if_flags & IFF_PROMISC) { 1140 v = bus_space_read_4(t, br, BE_BRI_RXCFG); 1141 v |= BE_BR_RXCFG_PMISC; 1142 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1143 return; 1144 } 1145 1146 if (ifp->if_flags & IFF_ALLMULTI) { 1147 hash[3] = hash[2] = hash[1] = hash[0] = 0xffff; 1148 goto chipit; 1149 } 1150 1151 hash[3] = hash[2] = hash[1] = hash[0] = 0; 1152 1153 ETHER_FIRST_MULTI(step, ec, enm); 1154 while (enm != NULL) { 1155 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1156 /* 1157 * We must listen to a range of multicast 1158 * addresses. For now, just accept all 1159 * multicasts, rather than trying to set only 1160 * those filter bits needed to match the range. 1161 * (At this time, the only use of address 1162 * ranges is for IP multicast routing, for 1163 * which the range is big enough to require 1164 * all bits set.) 1165 */ 1166 hash[3] = hash[2] = hash[1] = hash[0] = 0xffff; 1167 ifp->if_flags |= IFF_ALLMULTI; 1168 goto chipit; 1169 } 1170 1171 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 1172 /* Just want the 6 most significant bits. */ 1173 crc >>= 26; 1174 1175 hash[crc >> 4] |= 1 << (crc & 0xf); 1176 ETHER_NEXT_MULTI(step, enm); 1177 } 1178 1179 ifp->if_flags &= ~IFF_ALLMULTI; 1180 1181 chipit: 1182 /* Enable the hash filter */ 1183 bus_space_write_4(t, br, BE_BRI_HASHTAB0, hash[0]); 1184 bus_space_write_4(t, br, BE_BRI_HASHTAB1, hash[1]); 1185 bus_space_write_4(t, br, BE_BRI_HASHTAB2, hash[2]); 1186 bus_space_write_4(t, br, BE_BRI_HASHTAB3, hash[3]); 1187 1188 v = bus_space_read_4(t, br, BE_BRI_RXCFG); 1189 v &= ~BE_BR_RXCFG_PMISC; 1190 v |= BE_BR_RXCFG_HENABLE; 1191 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1192 } 1193 1194 /* 1195 * Set the tcvr to an idle state 1196 */ 1197 void 1198 be_mii_sync(struct be_softc *sc) 1199 { 1200 bus_space_tag_t t = sc->sc_bustag; 1201 bus_space_handle_t tr = sc->sc_tr; 1202 int n = 32; 1203 1204 while (n--) { 1205 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, 1206 MGMT_PAL_INT_MDIO | MGMT_PAL_EXT_MDIO | MGMT_PAL_OENAB); 1207 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1208 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, 1209 MGMT_PAL_INT_MDIO | MGMT_PAL_EXT_MDIO | 1210 MGMT_PAL_OENAB | MGMT_PAL_DCLOCK); 1211 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1212 } 1213 } 1214 1215 void 1216 be_pal_gate(struct be_softc *sc, int phy) 1217 { 1218 bus_space_tag_t t = sc->sc_bustag; 1219 bus_space_handle_t tr = sc->sc_tr; 1220 uint32_t v; 1221 1222 be_mii_sync(sc); 1223 1224 v = ~(TCVR_PAL_EXTLBACK | TCVR_PAL_MSENSE | TCVR_PAL_LTENABLE); 1225 if (phy == BE_PHY_INTERNAL) 1226 v &= ~TCVR_PAL_SERIAL; 1227 1228 bus_space_write_4(t, tr, BE_TRI_TCVRPAL, v); 1229 (void)bus_space_read_4(t, tr, BE_TRI_TCVRPAL); 1230 } 1231 1232 static int 1233 be_tcvr_read_bit(struct be_softc *sc, int phy) 1234 { 1235 bus_space_tag_t t = sc->sc_bustag; 1236 bus_space_handle_t tr = sc->sc_tr; 1237 int ret; 1238 1239 if (phy == BE_PHY_INTERNAL) { 1240 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, MGMT_PAL_EXT_MDIO); 1241 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1242 bus_space_write_4(t, tr, 1243 BE_TRI_MGMTPAL, MGMT_PAL_EXT_MDIO | MGMT_PAL_DCLOCK); 1244 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1245 ret = (bus_space_read_4(t, tr, BE_TRI_MGMTPAL) & 1246 MGMT_PAL_INT_MDIO) >> MGMT_PAL_INT_MDIO_SHIFT; 1247 } else { 1248 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, MGMT_PAL_INT_MDIO); 1249 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1250 ret = (bus_space_read_4(t, tr, BE_TRI_MGMTPAL) & 1251 MGMT_PAL_EXT_MDIO) >> MGMT_PAL_EXT_MDIO_SHIFT; 1252 bus_space_write_4(t, tr, 1253 BE_TRI_MGMTPAL, MGMT_PAL_INT_MDIO | MGMT_PAL_DCLOCK); 1254 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1255 } 1256 1257 return ret; 1258 } 1259 1260 static void 1261 be_tcvr_write_bit(struct be_softc *sc, int phy, int bit) 1262 { 1263 bus_space_tag_t t = sc->sc_bustag; 1264 bus_space_handle_t tr = sc->sc_tr; 1265 uint32_t v; 1266 1267 if (phy == BE_PHY_INTERNAL) { 1268 v = ((bit & 1) << MGMT_PAL_INT_MDIO_SHIFT) | 1269 MGMT_PAL_OENAB | MGMT_PAL_EXT_MDIO; 1270 } else { 1271 v = ((bit & 1) << MGMT_PAL_EXT_MDIO_SHIFT) | 1272 MGMT_PAL_OENAB | MGMT_PAL_INT_MDIO; 1273 } 1274 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, v); 1275 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1276 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, v | MGMT_PAL_DCLOCK); 1277 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1278 } 1279 1280 static void 1281 be_mii_sendbits(struct be_softc *sc, int phy, uint32_t data, int nbits) 1282 { 1283 int i; 1284 1285 for (i = 1 << (nbits - 1); i != 0; i >>= 1) { 1286 be_tcvr_write_bit(sc, phy, (data & i) != 0); 1287 } 1288 } 1289 1290 static int 1291 be_mii_readreg(device_t self, int phy, int reg, uint16_t *val) 1292 { 1293 struct be_softc *sc = device_private(self); 1294 int i; 1295 uint16_t data = 0; 1296 1297 /* 1298 * Read the PHY register by manually driving the MII control lines. 1299 */ 1300 be_mii_sync(sc); 1301 be_mii_sendbits(sc, phy, MII_COMMAND_START, 2); 1302 be_mii_sendbits(sc, phy, MII_COMMAND_READ, 2); 1303 be_mii_sendbits(sc, phy, phy, 5); 1304 be_mii_sendbits(sc, phy, reg, 5); 1305 1306 (void)be_tcvr_read_bit(sc, phy); 1307 (void)be_tcvr_read_bit(sc, phy); 1308 1309 for (i = 15; i >= 0; i--) 1310 data |= (be_tcvr_read_bit(sc, phy) << i); 1311 1312 (void)be_tcvr_read_bit(sc, phy); 1313 (void)be_tcvr_read_bit(sc, phy); 1314 (void)be_tcvr_read_bit(sc, phy); 1315 1316 *val = data; 1317 return 0; 1318 } 1319 1320 int 1321 be_mii_writereg(device_t self, int phy, int reg, uint16_t val) 1322 { 1323 struct be_softc *sc = device_private(self); 1324 int i; 1325 1326 /* 1327 * Write the PHY register by manually driving the MII control lines. 1328 */ 1329 be_mii_sync(sc); 1330 be_mii_sendbits(sc, phy, MII_COMMAND_START, 2); 1331 be_mii_sendbits(sc, phy, MII_COMMAND_WRITE, 2); 1332 be_mii_sendbits(sc, phy, phy, 5); 1333 be_mii_sendbits(sc, phy, reg, 5); 1334 1335 be_tcvr_write_bit(sc, phy, 1); 1336 be_tcvr_write_bit(sc, phy, 0); 1337 1338 for (i = 15; i >= 0; i--) 1339 be_tcvr_write_bit(sc, phy, (val >> i) & 1); 1340 1341 return 0; 1342 } 1343 1344 int 1345 be_mii_reset(struct be_softc *sc, int phy) 1346 { 1347 device_t self = sc->sc_dev; 1348 int n; 1349 1350 be_mii_writereg(self, phy, MII_BMCR, BMCR_LOOP | BMCR_PDOWN | BMCR_ISO); 1351 be_mii_writereg(self, phy, MII_BMCR, BMCR_RESET); 1352 1353 for (n = 16; n >= 0; n--) { 1354 uint16_t bmcr; 1355 1356 be_mii_readreg(self, phy, MII_BMCR, &bmcr); 1357 if ((bmcr & BMCR_RESET) == 0) 1358 break; 1359 DELAY(20); 1360 } 1361 if (n == 0) { 1362 aprint_error_dev(self, "bmcr reset failed\n"); 1363 return EIO; 1364 } 1365 1366 return 0; 1367 } 1368 1369 void 1370 be_tick(void *arg) 1371 { 1372 struct be_softc *sc = arg; 1373 int s = splnet(); 1374 1375 mii_tick(&sc->sc_mii); 1376 (void)be_intphy_service(sc, &sc->sc_mii, MII_TICK); 1377 1378 splx(s); 1379 callout_reset(&sc->sc_tick_ch, hz, be_tick, sc); 1380 } 1381 1382 void 1383 be_mii_statchg(struct ifnet *ifp) 1384 { 1385 struct be_softc *sc = ifp->if_softc; 1386 bus_space_tag_t t = sc->sc_bustag; 1387 bus_space_handle_t br = sc->sc_br; 1388 uint instance; 1389 uint32_t v; 1390 1391 instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media); 1392 #ifdef DIAGNOSTIC 1393 if (instance > 1) 1394 panic("be_mii_statchg: instance %d out of range", instance); 1395 #endif 1396 1397 /* Update duplex mode in TX configuration */ 1398 v = bus_space_read_4(t, br, BE_BRI_TXCFG); 1399 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 1400 v |= BE_BR_TXCFG_FULLDPLX; 1401 else 1402 v &= ~BE_BR_TXCFG_FULLDPLX; 1403 bus_space_write_4(t, br, BE_BRI_TXCFG, v); 1404 1405 /* Change to appropriate gate in transceiver PAL */ 1406 be_pal_gate(sc, sc->sc_phys[instance]); 1407 } 1408 1409 /* 1410 * Get current media settings. 1411 */ 1412 void 1413 be_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1414 { 1415 struct be_softc *sc = ifp->if_softc; 1416 1417 mii_pollstat(&sc->sc_mii); 1418 (void)be_intphy_service(sc, &sc->sc_mii, MII_POLLSTAT); 1419 1420 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1421 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1422 } 1423 1424 /* 1425 * Set media options. 1426 */ 1427 int 1428 be_ifmedia_upd(struct ifnet *ifp) 1429 { 1430 struct be_softc *sc = ifp->if_softc; 1431 int error; 1432 1433 if ((error = mii_mediachg(&sc->sc_mii)) == ENXIO) 1434 error = 0; 1435 else if (error != 0) 1436 return error; 1437 1438 return be_intphy_service(sc, &sc->sc_mii, MII_MEDIACHG); 1439 } 1440 1441 /* 1442 * Service routine for our pseudo-MII internal transceiver. 1443 */ 1444 int 1445 be_intphy_service(struct be_softc *sc, struct mii_data *mii, int cmd) 1446 { 1447 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 1448 device_t self = sc->sc_dev; 1449 uint16_t bmcr, bmsr; 1450 int error; 1451 1452 switch (cmd) { 1453 case MII_POLLSTAT: 1454 /* 1455 * If we're not polling our PHY instance, just return. 1456 */ 1457 if (IFM_INST(ife->ifm_media) != sc->sc_mii_inst) 1458 return 0; 1459 1460 break; 1461 1462 case MII_MEDIACHG: 1463 1464 /* 1465 * If the media indicates a different PHY instance, 1466 * isolate ourselves. 1467 */ 1468 if (IFM_INST(ife->ifm_media) != sc->sc_mii_inst) { 1469 be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMCR, &bmcr); 1470 be_mii_writereg(self, 1471 BE_PHY_INTERNAL, MII_BMCR, bmcr | BMCR_ISO); 1472 sc->sc_mii_flags &= ~MIIF_HAVELINK; 1473 sc->sc_intphy_curspeed = 0; 1474 return 0; 1475 } 1476 1477 1478 if ((error = be_mii_reset(sc, BE_PHY_INTERNAL)) != 0) 1479 return error; 1480 1481 be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMCR, &bmcr); 1482 1483 /* 1484 * Select the new mode and take out of isolation 1485 */ 1486 if (IFM_SUBTYPE(ife->ifm_media) == IFM_100_TX) 1487 bmcr |= BMCR_S100; 1488 else if (IFM_SUBTYPE(ife->ifm_media) == IFM_10_T) 1489 bmcr &= ~BMCR_S100; 1490 else if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) { 1491 if ((sc->sc_mii_flags & MIIF_HAVELINK) != 0) { 1492 bmcr &= ~BMCR_S100; 1493 bmcr |= sc->sc_intphy_curspeed; 1494 } else { 1495 /* Keep isolated until link is up */ 1496 bmcr |= BMCR_ISO; 1497 sc->sc_mii_flags |= MIIF_DOINGAUTO; 1498 } 1499 } 1500 1501 if ((IFM_OPTIONS(ife->ifm_media) & IFM_FDX) != 0) 1502 bmcr |= BMCR_FDX; 1503 else 1504 bmcr &= ~BMCR_FDX; 1505 1506 be_mii_writereg(self, BE_PHY_INTERNAL, MII_BMCR, bmcr); 1507 break; 1508 1509 case MII_TICK: 1510 /* 1511 * If we're not currently selected, just return. 1512 */ 1513 if (IFM_INST(ife->ifm_media) != sc->sc_mii_inst) 1514 return 0; 1515 1516 /* Is the interface even up? */ 1517 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 1518 return 0; 1519 1520 /* Only used for automatic media selection */ 1521 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) 1522 break; 1523 1524 /* 1525 * Check link status; if we don't have a link, try another 1526 * speed. We can't detect duplex mode, so half-duplex is 1527 * what we have to settle for. 1528 */ 1529 1530 /* Read twice in case the register is latched */ 1531 be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMSR, &bmsr); 1532 be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMSR, &bmsr); 1533 1534 if ((bmsr & BMSR_LINK) != 0) { 1535 /* We have a carrier */ 1536 be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMCR, &bmcr); 1537 1538 if ((sc->sc_mii_flags & MIIF_DOINGAUTO) != 0) { 1539 be_mii_readreg(self, 1540 BE_PHY_INTERNAL, MII_BMCR, &bmcr); 1541 1542 sc->sc_mii_flags |= MIIF_HAVELINK; 1543 sc->sc_intphy_curspeed = (bmcr & BMCR_S100); 1544 sc->sc_mii_flags &= ~MIIF_DOINGAUTO; 1545 1546 bmcr &= ~BMCR_ISO; 1547 be_mii_writereg(self, 1548 BE_PHY_INTERNAL, MII_BMCR, bmcr); 1549 1550 printf("%s: link up at %s Mbps\n", 1551 device_xname(self), 1552 (bmcr & BMCR_S100) ? "100" : "10"); 1553 } 1554 break; 1555 } 1556 1557 if ((sc->sc_mii_flags & MIIF_DOINGAUTO) == 0) { 1558 sc->sc_mii_flags |= MIIF_DOINGAUTO; 1559 sc->sc_mii_flags &= ~MIIF_HAVELINK; 1560 sc->sc_intphy_curspeed = 0; 1561 printf("%s: link down\n", device_xname(self)); 1562 } 1563 1564 /* Only retry autonegotiation every 5 seconds. */ 1565 if (++sc->sc_mii_ticks < 5) 1566 return 0; 1567 1568 sc->sc_mii_ticks = 0; 1569 be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMCR, &bmcr); 1570 /* Just flip the fast speed bit */ 1571 bmcr ^= BMCR_S100; 1572 be_mii_writereg(self, BE_PHY_INTERNAL, MII_BMCR, bmcr); 1573 1574 break; 1575 1576 case MII_DOWN: 1577 /* Isolate this phy */ 1578 be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMCR, &bmcr); 1579 be_mii_writereg(self, 1580 BE_PHY_INTERNAL, MII_BMCR, bmcr | BMCR_ISO); 1581 return 0; 1582 } 1583 1584 /* Update the media status. */ 1585 be_intphy_status(sc); 1586 1587 /* Callback if something changed. */ 1588 if (sc->sc_mii_active != mii->mii_media_active || cmd == MII_MEDIACHG) { 1589 (*mii->mii_statchg)(mii->mii_ifp); 1590 sc->sc_mii_active = mii->mii_media_active; 1591 } 1592 return 0; 1593 } 1594 1595 /* 1596 * Determine status of internal transceiver 1597 */ 1598 void 1599 be_intphy_status(struct be_softc *sc) 1600 { 1601 struct mii_data *mii = &sc->sc_mii; 1602 device_t self = sc->sc_dev; 1603 int media_active, media_status; 1604 uint16_t bmcr, bmsr; 1605 1606 media_status = IFM_AVALID; 1607 media_active = 0; 1608 1609 /* 1610 * Internal transceiver; do the work here. 1611 */ 1612 be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMCR, &bmcr); 1613 1614 switch (bmcr & (BMCR_S100 | BMCR_FDX)) { 1615 case (BMCR_S100 | BMCR_FDX): 1616 media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 1617 break; 1618 case BMCR_S100: 1619 media_active = IFM_ETHER | IFM_100_TX | IFM_HDX; 1620 break; 1621 case BMCR_FDX: 1622 media_active = IFM_ETHER | IFM_10_T | IFM_FDX; 1623 break; 1624 case 0: 1625 media_active = IFM_ETHER | IFM_10_T | IFM_HDX; 1626 break; 1627 } 1628 1629 /* Read twice in case the register is latched */ 1630 be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMSR, &bmsr); 1631 be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMSR, &bmsr); 1632 if (bmsr & BMSR_LINK) 1633 media_status |= IFM_ACTIVE; 1634 1635 mii->mii_media_status = media_status; 1636 mii->mii_media_active = media_active; 1637 } 1638
Indexes created Tue Sep 30 07:10:03 GMT 2025