be.c revision 1.93
1 /* $NetBSD: be.c,v 1.93 2019/05/28 07:41:49 msaitoh Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Copyright (c) 1998 Theo de Raadt and Jason L. Wright. 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. The name of the authors may not be used to endorse or promote products 45 * derived from this software without specific prior written permission. 46 * 47 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR 48 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 49 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 50 * IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, 51 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 52 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 53 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 54 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 55 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 56 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 57 */ 58 59 #include <sys/cdefs.h> 60 __KERNEL_RCSID(0, "$NetBSD: be.c,v 1.93 2019/05/28 07:41:49 msaitoh Exp $"); 61 62 #include "opt_ddb.h" 63 #include "opt_inet.h" 64 65 #include <sys/param.h> 66 #include <sys/systm.h> 67 #include <sys/callout.h> 68 #include <sys/kernel.h> 69 #include <sys/errno.h> 70 #include <sys/ioctl.h> 71 #include <sys/mbuf.h> 72 #include <sys/socket.h> 73 #include <sys/syslog.h> 74 #include <sys/device.h> 75 #include <sys/malloc.h> 76 77 #include <net/if.h> 78 #include <net/if_dl.h> 79 #include <net/if_types.h> 80 #include <net/netisr.h> 81 #include <net/if_media.h> 82 #include <net/if_ether.h> 83 #include <net/bpf.h> 84 85 #ifdef INET 86 #include <netinet/in.h> 87 #include <netinet/if_inarp.h> 88 #include <netinet/in_systm.h> 89 #include <netinet/in_var.h> 90 #include <netinet/ip.h> 91 #endif 92 93 #include <sys/bus.h> 94 #include <sys/intr.h> 95 #include <machine/autoconf.h> 96 97 #include <dev/mii/mii.h> 98 #include <dev/mii/miivar.h> 99 100 #include <dev/sbus/sbusvar.h> 101 #include <dev/sbus/qecreg.h> 102 #include <dev/sbus/qecvar.h> 103 #include <dev/sbus/bereg.h> 104 105 struct be_softc { 106 device_t sc_dev; 107 bus_space_tag_t sc_bustag; /* bus & DMA tags */ 108 bus_dma_tag_t sc_dmatag; 109 bus_dmamap_t sc_dmamap; 110 struct ethercom sc_ethercom; 111 /*struct ifmedia sc_ifmedia; -* interface media */ 112 struct mii_data sc_mii; /* MII media control */ 113 #define sc_media sc_mii.mii_media/* shorthand */ 114 int sc_phys[2]; /* MII instance -> phy */ 115 116 struct callout sc_tick_ch; 117 118 /* 119 * Some `mii_softc' items we need to emulate MII operation 120 * for our internal transceiver. 121 */ 122 int sc_mii_inst; /* instance of internal phy */ 123 int sc_mii_active; /* currently active medium */ 124 int sc_mii_ticks; /* tick counter */ 125 int sc_mii_flags; /* phy status flags */ 126 #define MIIF_HAVELINK 0x04000000 127 int sc_intphy_curspeed; /* Established link speed */ 128 129 struct qec_softc *sc_qec; /* QEC parent */ 130 131 bus_space_handle_t sc_qr; /* QEC registers */ 132 bus_space_handle_t sc_br; /* BE registers */ 133 bus_space_handle_t sc_cr; /* channel registers */ 134 bus_space_handle_t sc_tr; /* transceiver registers */ 135 136 u_int sc_rev; 137 138 int sc_channel; /* channel number */ 139 int sc_burst; 140 141 struct qec_ring sc_rb; /* Packet Ring Buffer */ 142 143 /* MAC address */ 144 uint8_t sc_enaddr[ETHER_ADDR_LEN]; 145 #ifdef BEDEBUG 146 int sc_debug; 147 #endif 148 }; 149 150 static int bematch(device_t, cfdata_t, void *); 151 static void beattach(device_t, device_t, void *); 152 153 static int beinit(struct ifnet *); 154 static void bestart(struct ifnet *); 155 static void bestop(struct ifnet *, int); 156 static void bewatchdog(struct ifnet *); 157 static int beioctl(struct ifnet *, u_long, void *); 158 static void bereset(struct be_softc *); 159 static void behwreset(struct be_softc *); 160 161 static int beintr(void *); 162 static int berint(struct be_softc *); 163 static int betint(struct be_softc *); 164 static int beqint(struct be_softc *, uint32_t); 165 static int beeint(struct be_softc *, uint32_t); 166 167 static void be_read(struct be_softc *, int, int); 168 static int be_put(struct be_softc *, int, struct mbuf *); 169 static struct mbuf *be_get(struct be_softc *, int, int); 170 171 static void be_pal_gate(struct be_softc *, int); 172 173 /* ifmedia callbacks */ 174 static void be_ifmedia_sts(struct ifnet *, struct ifmediareq *); 175 static int be_ifmedia_upd(struct ifnet *); 176 177 static void be_mcreset(struct be_softc *); 178 179 /* MII methods & callbacks */ 180 static int be_mii_readreg(device_t, int, int, uint16_t *); 181 static int be_mii_writereg(device_t, int, int, uint16_t); 182 static void be_mii_statchg(struct ifnet *); 183 184 /* MII helpers */ 185 static void be_mii_sync(struct be_softc *); 186 static void be_mii_sendbits(struct be_softc *, int, uint32_t, int); 187 static int be_mii_reset(struct be_softc *, int); 188 static int be_tcvr_read_bit(struct be_softc *, int); 189 static void be_tcvr_write_bit(struct be_softc *, int, int); 190 191 static void be_tick(void *); 192 #if 0 193 static void be_intphy_auto(struct be_softc *); 194 #endif 195 static void be_intphy_status(struct be_softc *); 196 static int be_intphy_service(struct be_softc *, struct mii_data *, int); 197 198 199 CFATTACH_DECL_NEW(be, sizeof(struct be_softc), 200 bematch, beattach, NULL, NULL); 201 202 int 203 bematch(device_t parent, cfdata_t cf, void *aux) 204 { 205 struct sbus_attach_args *sa = aux; 206 207 return strcmp(cf->cf_name, sa->sa_name) == 0; 208 } 209 210 void 211 beattach(device_t parent, device_t self, void *aux) 212 { 213 struct sbus_attach_args *sa = aux; 214 struct qec_softc *qec = device_private(parent); 215 struct be_softc *sc = device_private(self); 216 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 217 struct mii_data *mii = &sc->sc_mii; 218 struct mii_softc *child; 219 int node = sa->sa_node; 220 bus_dma_tag_t dmatag = sa->sa_dmatag; 221 bus_dma_segment_t seg; 222 bus_size_t size; 223 int instance; 224 int rseg, error; 225 uint32_t v; 226 227 sc->sc_dev = self; 228 229 if (sa->sa_nreg < 3) { 230 printf(": only %d register sets\n", sa->sa_nreg); 231 return; 232 } 233 234 if (bus_space_map(sa->sa_bustag, 235 (bus_addr_t)BUS_ADDR(sa->sa_reg[0].oa_space, sa->sa_reg[0].oa_base), 236 (bus_size_t)sa->sa_reg[0].oa_size, 237 0, &sc->sc_cr) != 0) { 238 printf(": cannot map registers\n"); 239 return; 240 } 241 242 if (bus_space_map(sa->sa_bustag, 243 (bus_addr_t)BUS_ADDR(sa->sa_reg[1].oa_space, sa->sa_reg[1].oa_base), 244 (bus_size_t)sa->sa_reg[1].oa_size, 245 0, &sc->sc_br) != 0) { 246 printf(": cannot map registers\n"); 247 return; 248 } 249 250 if (bus_space_map(sa->sa_bustag, 251 (bus_addr_t)BUS_ADDR(sa->sa_reg[2].oa_space, sa->sa_reg[2].oa_base), 252 (bus_size_t)sa->sa_reg[2].oa_size, 253 0, &sc->sc_tr) != 0) { 254 printf(": cannot map registers\n"); 255 return; 256 } 257 258 sc->sc_bustag = sa->sa_bustag; 259 sc->sc_qec = qec; 260 sc->sc_qr = qec->sc_regs; 261 262 sc->sc_rev = prom_getpropint(node, "board-version", -1); 263 printf(": rev %x,", sc->sc_rev); 264 265 callout_init(&sc->sc_tick_ch, 0); 266 267 sc->sc_channel = prom_getpropint(node, "channel#", -1); 268 if (sc->sc_channel == -1) 269 sc->sc_channel = 0; 270 271 sc->sc_burst = prom_getpropint(node, "burst-sizes", -1); 272 if (sc->sc_burst == -1) 273 sc->sc_burst = qec->sc_burst; 274 275 /* Clamp at parent's burst sizes */ 276 sc->sc_burst &= qec->sc_burst; 277 278 /* Establish interrupt handler */ 279 if (sa->sa_nintr) 280 (void)bus_intr_establish(sa->sa_bustag, sa->sa_pri, IPL_NET, 281 beintr, sc); 282 283 prom_getether(node, sc->sc_enaddr); 284 printf(" address %s\n", ether_sprintf(sc->sc_enaddr)); 285 286 /* 287 * Allocate descriptor ring and buffers. 288 */ 289 290 /* for now, allocate as many bufs as there are ring descriptors */ 291 sc->sc_rb.rb_ntbuf = QEC_XD_RING_MAXSIZE; 292 sc->sc_rb.rb_nrbuf = QEC_XD_RING_MAXSIZE; 293 294 size = 295 QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd) + 296 QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd) + 297 sc->sc_rb.rb_ntbuf * BE_PKT_BUF_SZ + 298 sc->sc_rb.rb_nrbuf * BE_PKT_BUF_SZ; 299 300 /* Get a DMA handle */ 301 if ((error = bus_dmamap_create(dmatag, size, 1, size, 0, 302 BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) { 303 aprint_error_dev(self, "DMA map create error %d\n", error); 304 return; 305 } 306 307 /* Allocate DMA buffer */ 308 if ((error = bus_dmamem_alloc(sa->sa_dmatag, size, 0, 0, 309 &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 310 aprint_error_dev(self, "DMA buffer alloc error %d\n", error); 311 return; 312 } 313 314 /* Map DMA memory in CPU addressable space */ 315 if ((error = bus_dmamem_map(sa->sa_dmatag, &seg, rseg, size, 316 &sc->sc_rb.rb_membase, BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) { 317 aprint_error_dev(self, "DMA buffer map error %d\n", error); 318 bus_dmamem_free(sa->sa_dmatag, &seg, rseg); 319 return; 320 } 321 322 /* Load the buffer */ 323 if ((error = bus_dmamap_load(dmatag, sc->sc_dmamap, 324 sc->sc_rb.rb_membase, size, NULL, BUS_DMA_NOWAIT)) != 0) { 325 aprint_error_dev(self, "DMA buffer map load error %d\n", error); 326 bus_dmamem_unmap(dmatag, sc->sc_rb.rb_membase, size); 327 bus_dmamem_free(dmatag, &seg, rseg); 328 return; 329 } 330 sc->sc_rb.rb_dmabase = sc->sc_dmamap->dm_segs[0].ds_addr; 331 332 /* 333 * Initialize our media structures and MII info. 334 */ 335 mii->mii_ifp = ifp; 336 mii->mii_readreg = be_mii_readreg; 337 mii->mii_writereg = be_mii_writereg; 338 mii->mii_statchg = be_mii_statchg; 339 340 ifmedia_init(&mii->mii_media, 0, be_ifmedia_upd, be_ifmedia_sts); 341 342 /* 343 * Initialize transceiver and determine which PHY connection to use. 344 */ 345 be_mii_sync(sc); 346 v = bus_space_read_4(sc->sc_bustag, sc->sc_tr, BE_TRI_MGMTPAL); 347 348 instance = 0; 349 350 if ((v & MGMT_PAL_EXT_MDIO) != 0) { 351 352 mii_attach(self, mii, 0xffffffff, BE_PHY_EXTERNAL, 353 MII_OFFSET_ANY, 0); 354 355 child = LIST_FIRST(&mii->mii_phys); 356 if (child == NULL) { 357 /* No PHY attached */ 358 ifmedia_add(&sc->sc_media, 359 IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, instance), 360 0, NULL); 361 ifmedia_set(&sc->sc_media, 362 IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, instance)); 363 } else { 364 /* 365 * Note: we support just one PHY on the external 366 * MII connector. 367 */ 368 #ifdef DIAGNOSTIC 369 if (LIST_NEXT(child, mii_list) != NULL) { 370 aprint_error_dev(self, 371 "spurious MII device %s attached\n", 372 device_xname(child->mii_dev)); 373 } 374 #endif 375 if (child->mii_phy != BE_PHY_EXTERNAL || 376 child->mii_inst > 0) { 377 aprint_error_dev(self, 378 "cannot accommodate MII device %s" 379 " at phy %d, instance %d\n", 380 device_xname(child->mii_dev), 381 child->mii_phy, child->mii_inst); 382 } else { 383 sc->sc_phys[instance] = child->mii_phy; 384 } 385 386 /* 387 * XXX - we can really do the following ONLY if the 388 * phy indeed has the auto negotiation capability!! 389 */ 390 ifmedia_set(&sc->sc_media, 391 IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, instance)); 392 393 /* Mark our current media setting */ 394 be_pal_gate(sc, BE_PHY_EXTERNAL); 395 instance++; 396 } 397 398 } 399 400 if ((v & MGMT_PAL_INT_MDIO) != 0) { 401 /* 402 * The be internal phy looks vaguely like MII hardware, 403 * but not enough to be able to use the MII device 404 * layer. Hence, we have to take care of media selection 405 * ourselves. 406 */ 407 408 sc->sc_mii_inst = instance; 409 sc->sc_phys[instance] = BE_PHY_INTERNAL; 410 411 /* Use `ifm_data' to store BMCR bits */ 412 ifmedia_add(&sc->sc_media, 413 IFM_MAKEWORD(IFM_ETHER, IFM_10_T, 0, instance), 414 0, NULL); 415 ifmedia_add(&sc->sc_media, 416 IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, 0, instance), 417 BMCR_S100, NULL); 418 ifmedia_add(&sc->sc_media, 419 IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, instance), 420 0, NULL); 421 422 printf("on-board transceiver at %s: 10baseT, 100baseTX, auto\n", 423 device_xname(self)); 424 425 be_mii_reset(sc, BE_PHY_INTERNAL); 426 /* Only set default medium here if there's no external PHY */ 427 if (instance == 0) { 428 be_pal_gate(sc, BE_PHY_INTERNAL); 429 ifmedia_set(&sc->sc_media, 430 IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, instance)); 431 } else 432 be_mii_writereg(self, 433 BE_PHY_INTERNAL, MII_BMCR, BMCR_ISO); 434 } 435 436 memcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 437 ifp->if_softc = sc; 438 ifp->if_start = bestart; 439 ifp->if_ioctl = beioctl; 440 ifp->if_watchdog = bewatchdog; 441 ifp->if_init = beinit; 442 ifp->if_stop = bestop; 443 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 444 IFQ_SET_READY(&ifp->if_snd); 445 446 /* claim 802.1q capability */ 447 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 448 449 /* Attach the interface. */ 450 if_attach(ifp); 451 ether_ifattach(ifp, sc->sc_enaddr); 452 } 453 454 455 /* 456 * Routine to copy from mbuf chain to transmit buffer in 457 * network buffer memory. 458 */ 459 static inline int 460 be_put(struct be_softc *sc, int idx, struct mbuf *m) 461 { 462 struct mbuf *n; 463 int len, tlen = 0, boff = 0; 464 uint8_t *bp; 465 466 bp = sc->sc_rb.rb_txbuf + (idx % sc->sc_rb.rb_ntbuf) * BE_PKT_BUF_SZ; 467 468 for (; m; m = n) { 469 len = m->m_len; 470 if (len == 0) { 471 n = m_free(m); 472 continue; 473 } 474 memcpy(bp + boff, mtod(m, void *), len); 475 boff += len; 476 tlen += len; 477 n = m_free(m); 478 } 479 return tlen; 480 } 481 482 /* 483 * Pull data off an interface. 484 * Len is the length of data, with local net header stripped. 485 * We copy the data into mbufs. When full cluster sized units are present, 486 * we copy into clusters. 487 */ 488 static inline struct mbuf * 489 be_get(struct be_softc *sc, int idx, int totlen) 490 { 491 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 492 struct mbuf *m; 493 struct mbuf *top, **mp; 494 int len, pad, boff = 0; 495 uint8_t *bp; 496 497 bp = sc->sc_rb.rb_rxbuf + (idx % sc->sc_rb.rb_nrbuf) * BE_PKT_BUF_SZ; 498 499 MGETHDR(m, M_DONTWAIT, MT_DATA); 500 if (m == NULL) 501 return (NULL); 502 m_set_rcvif(m, ifp); 503 m->m_pkthdr.len = totlen; 504 505 pad = ALIGN(sizeof(struct ether_header)) - sizeof(struct ether_header); 506 m->m_data += pad; 507 len = MHLEN - pad; 508 top = NULL; 509 mp = ⊤ 510 511 while (totlen > 0) { 512 if (top) { 513 MGET(m, M_DONTWAIT, MT_DATA); 514 if (m == NULL) { 515 m_freem(top); 516 return (NULL); 517 } 518 len = MLEN; 519 } 520 if (top && totlen >= MINCLSIZE) { 521 MCLGET(m, M_DONTWAIT); 522 if (m->m_flags & M_EXT) 523 len = MCLBYTES; 524 } 525 m->m_len = len = uimin(totlen, len); 526 memcpy(mtod(m, void *), bp + boff, len); 527 boff += len; 528 totlen -= len; 529 *mp = m; 530 mp = &m->m_next; 531 } 532 533 return top; 534 } 535 536 /* 537 * Pass a packet to the higher levels. 538 */ 539 static inline void 540 be_read(struct be_softc *sc, int idx, int len) 541 { 542 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 543 struct mbuf *m; 544 545 if (len <= sizeof(struct ether_header) || 546 len > ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN) { 547 #ifdef BEDEBUG 548 if (sc->sc_debug) 549 printf("%s: invalid packet size %d; dropping\n", 550 ifp->if_xname, len); 551 #endif 552 ifp->if_ierrors++; 553 return; 554 } 555 556 /* 557 * Pull packet off interface. 558 */ 559 m = be_get(sc, idx, len); 560 if (m == NULL) { 561 ifp->if_ierrors++; 562 return; 563 } 564 565 /* Pass the packet up. */ 566 if_percpuq_enqueue(ifp->if_percpuq, m); 567 } 568 569 /* 570 * Start output on interface. 571 * We make two assumptions here: 572 * 1) that the current priority is set to splnet _before_ this code 573 * is called *and* is returned to the appropriate priority after 574 * return 575 * 2) that the IFF_OACTIVE flag is checked before this code is called 576 * (i.e. that the output part of the interface is idle) 577 */ 578 void 579 bestart(struct ifnet *ifp) 580 { 581 struct be_softc *sc = ifp->if_softc; 582 struct qec_xd *txd = sc->sc_rb.rb_txd; 583 struct mbuf *m; 584 unsigned int bix, len; 585 unsigned int ntbuf = sc->sc_rb.rb_ntbuf; 586 587 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 588 return; 589 590 bix = sc->sc_rb.rb_tdhead; 591 592 for (;;) { 593 IFQ_DEQUEUE(&ifp->if_snd, m); 594 if (m == 0) 595 break; 596 597 /* 598 * If BPF is listening on this interface, let it see the 599 * packet before we commit it to the wire. 600 */ 601 bpf_mtap(ifp, m, BPF_D_OUT); 602 603 /* 604 * Copy the mbuf chain into the transmit buffer. 605 */ 606 len = be_put(sc, bix, m); 607 608 /* 609 * Initialize transmit registers and start transmission 610 */ 611 txd[bix].xd_flags = QEC_XD_OWN | QEC_XD_SOP | QEC_XD_EOP | 612 (len & QEC_XD_LENGTH); 613 bus_space_write_4(sc->sc_bustag, sc->sc_cr, 614 BE_CRI_CTRL, BE_CR_CTRL_TWAKEUP); 615 616 if (++bix == QEC_XD_RING_MAXSIZE) 617 bix = 0; 618 619 if (++sc->sc_rb.rb_td_nbusy == ntbuf) { 620 ifp->if_flags |= IFF_OACTIVE; 621 break; 622 } 623 } 624 625 sc->sc_rb.rb_tdhead = bix; 626 } 627 628 void 629 bestop(struct ifnet *ifp, int disable) 630 { 631 struct be_softc *sc = ifp->if_softc; 632 633 callout_stop(&sc->sc_tick_ch); 634 635 /* Down the MII. */ 636 mii_down(&sc->sc_mii); 637 (void)be_intphy_service(sc, &sc->sc_mii, MII_DOWN); 638 639 behwreset(sc); 640 } 641 642 void 643 behwreset(struct be_softc *sc) 644 { 645 int n; 646 bus_space_tag_t t = sc->sc_bustag; 647 bus_space_handle_t br = sc->sc_br; 648 649 /* Stop the transmitter */ 650 bus_space_write_4(t, br, BE_BRI_TXCFG, 0); 651 for (n = 32; n > 0; n--) { 652 if (bus_space_read_4(t, br, BE_BRI_TXCFG) == 0) 653 break; 654 DELAY(20); 655 } 656 657 /* Stop the receiver */ 658 bus_space_write_4(t, br, BE_BRI_RXCFG, 0); 659 for (n = 32; n > 0; n--) { 660 if (bus_space_read_4(t, br, BE_BRI_RXCFG) == 0) 661 break; 662 DELAY(20); 663 } 664 } 665 666 /* 667 * Reset interface. 668 */ 669 void 670 bereset(struct be_softc *sc) 671 { 672 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 673 int s; 674 675 s = splnet(); 676 behwreset(sc); 677 if ((sc->sc_ethercom.ec_if.if_flags & IFF_UP) != 0) 678 beinit(ifp); 679 splx(s); 680 } 681 682 void 683 bewatchdog(struct ifnet *ifp) 684 { 685 struct be_softc *sc = ifp->if_softc; 686 687 log(LOG_ERR, "%s: device timeout\n", device_xname(sc->sc_dev)); 688 ++sc->sc_ethercom.ec_if.if_oerrors; 689 690 bereset(sc); 691 } 692 693 int 694 beintr(void *arg) 695 { 696 struct be_softc *sc = arg; 697 bus_space_tag_t t = sc->sc_bustag; 698 uint32_t whyq, whyb, whyc; 699 int r = 0; 700 701 /* Read QEC status, channel status and BE status */ 702 whyq = bus_space_read_4(t, sc->sc_qr, QEC_QRI_STAT); 703 whyc = bus_space_read_4(t, sc->sc_cr, BE_CRI_STAT); 704 whyb = bus_space_read_4(t, sc->sc_br, BE_BRI_STAT); 705 706 if (whyq & QEC_STAT_BM) 707 r |= beeint(sc, whyb); 708 709 if (whyq & QEC_STAT_ER) 710 r |= beqint(sc, whyc); 711 712 if (whyq & QEC_STAT_TX && whyc & BE_CR_STAT_TXIRQ) 713 r |= betint(sc); 714 715 if (whyq & QEC_STAT_RX && whyc & BE_CR_STAT_RXIRQ) 716 r |= berint(sc); 717 718 return r; 719 } 720 721 /* 722 * QEC Interrupt. 723 */ 724 int 725 beqint(struct be_softc *sc, uint32_t why) 726 { 727 device_t self = sc->sc_dev; 728 int r = 0, rst = 0; 729 730 if (why & BE_CR_STAT_TXIRQ) 731 r |= 1; 732 if (why & BE_CR_STAT_RXIRQ) 733 r |= 1; 734 735 if (why & BE_CR_STAT_BERROR) { 736 r |= 1; 737 rst = 1; 738 aprint_error_dev(self, "bigmac error\n"); 739 } 740 741 if (why & BE_CR_STAT_TXDERR) { 742 r |= 1; 743 rst = 1; 744 aprint_error_dev(self, "bogus tx descriptor\n"); 745 } 746 747 if (why & (BE_CR_STAT_TXLERR | BE_CR_STAT_TXPERR | BE_CR_STAT_TXSERR)) { 748 r |= 1; 749 rst = 1; 750 aprint_error_dev(self, "tx DMA error ( "); 751 if (why & BE_CR_STAT_TXLERR) 752 printf("Late "); 753 if (why & BE_CR_STAT_TXPERR) 754 printf("Parity "); 755 if (why & BE_CR_STAT_TXSERR) 756 printf("Generic "); 757 printf(")\n"); 758 } 759 760 if (why & BE_CR_STAT_RXDROP) { 761 r |= 1; 762 rst = 1; 763 aprint_error_dev(self, "out of rx descriptors\n"); 764 } 765 766 if (why & BE_CR_STAT_RXSMALL) { 767 r |= 1; 768 rst = 1; 769 aprint_error_dev(self, "rx descriptor too small\n"); 770 } 771 772 if (why & (BE_CR_STAT_RXLERR | BE_CR_STAT_RXPERR | BE_CR_STAT_RXSERR)) { 773 r |= 1; 774 rst = 1; 775 aprint_error_dev(self, "rx DMA error ( "); 776 if (why & BE_CR_STAT_RXLERR) 777 printf("Late "); 778 if (why & BE_CR_STAT_RXPERR) 779 printf("Parity "); 780 if (why & BE_CR_STAT_RXSERR) 781 printf("Generic "); 782 printf(")\n"); 783 } 784 785 if (!r) { 786 rst = 1; 787 aprint_error_dev(self, "unexpected error interrupt %08x\n", 788 why); 789 } 790 791 if (rst) { 792 printf("%s: resetting\n", device_xname(self)); 793 bereset(sc); 794 } 795 796 return r; 797 } 798 799 /* 800 * Error interrupt. 801 */ 802 int 803 beeint(struct be_softc *sc, uint32_t why) 804 { 805 device_t self = sc->sc_dev; 806 int r = 0, rst = 0; 807 808 if (why & BE_BR_STAT_RFIFOVF) { 809 r |= 1; 810 rst = 1; 811 aprint_error_dev(self, "receive fifo overrun\n"); 812 } 813 if (why & BE_BR_STAT_TFIFO_UND) { 814 r |= 1; 815 rst = 1; 816 aprint_error_dev(self, "transmit fifo underrun\n"); 817 } 818 if (why & BE_BR_STAT_MAXPKTERR) { 819 r |= 1; 820 rst = 1; 821 aprint_error_dev(self, "max packet size error\n"); 822 } 823 824 if (!r) { 825 rst = 1; 826 aprint_error_dev(self, "unexpected error interrupt %08x\n", 827 why); 828 } 829 830 if (rst) { 831 printf("%s: resetting\n", device_xname(self)); 832 bereset(sc); 833 } 834 835 return r; 836 } 837 838 /* 839 * Transmit interrupt. 840 */ 841 int 842 betint(struct be_softc *sc) 843 { 844 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 845 bus_space_tag_t t = sc->sc_bustag; 846 bus_space_handle_t br = sc->sc_br; 847 unsigned int bix, txflags; 848 849 /* 850 * Unload collision counters 851 */ 852 ifp->if_collisions += 853 bus_space_read_4(t, br, BE_BRI_NCCNT) + 854 bus_space_read_4(t, br, BE_BRI_FCCNT) + 855 bus_space_read_4(t, br, BE_BRI_EXCNT) + 856 bus_space_read_4(t, br, BE_BRI_LTCNT); 857 858 /* 859 * the clear the hardware counters 860 */ 861 bus_space_write_4(t, br, BE_BRI_NCCNT, 0); 862 bus_space_write_4(t, br, BE_BRI_FCCNT, 0); 863 bus_space_write_4(t, br, BE_BRI_EXCNT, 0); 864 bus_space_write_4(t, br, BE_BRI_LTCNT, 0); 865 866 bix = sc->sc_rb.rb_tdtail; 867 868 for (;;) { 869 if (sc->sc_rb.rb_td_nbusy <= 0) 870 break; 871 872 txflags = sc->sc_rb.rb_txd[bix].xd_flags; 873 874 if (txflags & QEC_XD_OWN) 875 break; 876 877 ifp->if_flags &= ~IFF_OACTIVE; 878 ifp->if_opackets++; 879 880 if (++bix == QEC_XD_RING_MAXSIZE) 881 bix = 0; 882 883 --sc->sc_rb.rb_td_nbusy; 884 } 885 886 sc->sc_rb.rb_tdtail = bix; 887 888 bestart(ifp); 889 890 if (sc->sc_rb.rb_td_nbusy == 0) 891 ifp->if_timer = 0; 892 893 return 1; 894 } 895 896 /* 897 * Receive interrupt. 898 */ 899 int 900 berint(struct be_softc *sc) 901 { 902 struct qec_xd *xd = sc->sc_rb.rb_rxd; 903 unsigned int bix, len; 904 unsigned int nrbuf = sc->sc_rb.rb_nrbuf; 905 906 bix = sc->sc_rb.rb_rdtail; 907 908 /* 909 * Process all buffers with valid data. 910 */ 911 for (;;) { 912 len = xd[bix].xd_flags; 913 if (len & QEC_XD_OWN) 914 break; 915 916 len &= QEC_XD_LENGTH; 917 be_read(sc, bix, len); 918 919 /* ... */ 920 xd[(bix+nrbuf) % QEC_XD_RING_MAXSIZE].xd_flags = 921 QEC_XD_OWN | (BE_PKT_BUF_SZ & QEC_XD_LENGTH); 922 923 if (++bix == QEC_XD_RING_MAXSIZE) 924 bix = 0; 925 } 926 927 sc->sc_rb.rb_rdtail = bix; 928 929 return 1; 930 } 931 932 int 933 beioctl(struct ifnet *ifp, u_long cmd, void *data) 934 { 935 struct be_softc *sc = ifp->if_softc; 936 struct ifaddr *ifa = data; 937 struct ifreq *ifr = data; 938 int s, error = 0; 939 940 s = splnet(); 941 942 switch (cmd) { 943 case SIOCINITIFADDR: 944 ifp->if_flags |= IFF_UP; 945 beinit(ifp); 946 switch (ifa->ifa_addr->sa_family) { 947 #ifdef INET 948 case AF_INET: 949 arp_ifinit(ifp, ifa); 950 break; 951 #endif /* INET */ 952 default: 953 break; 954 } 955 break; 956 957 case SIOCSIFFLAGS: 958 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 959 break; 960 /* XXX re-use ether_ioctl() */ 961 switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { 962 case IFF_RUNNING: 963 /* 964 * If interface is marked down and it is running, then 965 * stop it. 966 */ 967 bestop(ifp, 0); 968 ifp->if_flags &= ~IFF_RUNNING; 969 break; 970 case IFF_UP: 971 /* 972 * If interface is marked up and it is stopped, then 973 * start it. 974 */ 975 beinit(ifp); 976 break; 977 default: 978 /* 979 * Reset the interface to pick up changes in any other 980 * flags that affect hardware registers. 981 */ 982 bestop(ifp, 0); 983 beinit(ifp); 984 break; 985 } 986 #ifdef BEDEBUG 987 if (ifp->if_flags & IFF_DEBUG) 988 sc->sc_debug = 1; 989 else 990 sc->sc_debug = 0; 991 #endif 992 break; 993 994 case SIOCGIFMEDIA: 995 case SIOCSIFMEDIA: 996 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd); 997 break; 998 default: 999 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 1000 /* 1001 * Multicast list has changed; set the hardware filter 1002 * accordingly. 1003 */ 1004 if (ifp->if_flags & IFF_RUNNING) 1005 error = beinit(ifp); 1006 else 1007 error = 0; 1008 } 1009 break; 1010 } 1011 splx(s); 1012 return error; 1013 } 1014 1015 1016 int 1017 beinit(struct ifnet *ifp) 1018 { 1019 struct be_softc *sc = ifp->if_softc; 1020 bus_space_tag_t t = sc->sc_bustag; 1021 bus_space_handle_t br = sc->sc_br; 1022 bus_space_handle_t cr = sc->sc_cr; 1023 struct qec_softc *qec = sc->sc_qec; 1024 uint32_t v; 1025 uint32_t qecaddr; 1026 uint8_t *ea; 1027 int rc, s; 1028 1029 s = splnet(); 1030 1031 qec_meminit(&sc->sc_rb, BE_PKT_BUF_SZ); 1032 1033 bestop(ifp, 1); 1034 1035 ea = sc->sc_enaddr; 1036 bus_space_write_4(t, br, BE_BRI_MACADDR0, (ea[0] << 8) | ea[1]); 1037 bus_space_write_4(t, br, BE_BRI_MACADDR1, (ea[2] << 8) | ea[3]); 1038 bus_space_write_4(t, br, BE_BRI_MACADDR2, (ea[4] << 8) | ea[5]); 1039 1040 /* Clear hash table */ 1041 bus_space_write_4(t, br, BE_BRI_HASHTAB0, 0); 1042 bus_space_write_4(t, br, BE_BRI_HASHTAB1, 0); 1043 bus_space_write_4(t, br, BE_BRI_HASHTAB2, 0); 1044 bus_space_write_4(t, br, BE_BRI_HASHTAB3, 0); 1045 1046 /* Re-initialize RX configuration */ 1047 v = BE_BR_RXCFG_FIFO; 1048 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1049 1050 be_mcreset(sc); 1051 1052 bus_space_write_4(t, br, BE_BRI_RANDSEED, 0xbd); 1053 1054 bus_space_write_4(t, br, 1055 BE_BRI_XIFCFG, BE_BR_XCFG_ODENABLE | BE_BR_XCFG_RESV); 1056 1057 bus_space_write_4(t, br, BE_BRI_JSIZE, 4); 1058 1059 /* 1060 * Turn off counter expiration interrupts as well as 1061 * 'gotframe' and 'sentframe' 1062 */ 1063 bus_space_write_4(t, br, BE_BRI_IMASK, 1064 BE_BR_IMASK_GOTFRAME | 1065 BE_BR_IMASK_RCNTEXP | 1066 BE_BR_IMASK_ACNTEXP | 1067 BE_BR_IMASK_CCNTEXP | 1068 BE_BR_IMASK_LCNTEXP | 1069 BE_BR_IMASK_CVCNTEXP | 1070 BE_BR_IMASK_SENTFRAME | 1071 BE_BR_IMASK_NCNTEXP | 1072 BE_BR_IMASK_ECNTEXP | 1073 BE_BR_IMASK_LCCNTEXP | 1074 BE_BR_IMASK_FCNTEXP | 1075 BE_BR_IMASK_DTIMEXP); 1076 1077 /* Channel registers: */ 1078 bus_space_write_4(t, cr, BE_CRI_RXDS, (uint32_t)sc->sc_rb.rb_rxddma); 1079 bus_space_write_4(t, cr, BE_CRI_TXDS, (uint32_t)sc->sc_rb.rb_txddma); 1080 1081 qecaddr = sc->sc_channel * qec->sc_msize; 1082 bus_space_write_4(t, cr, BE_CRI_RXWBUF, qecaddr); 1083 bus_space_write_4(t, cr, BE_CRI_RXRBUF, qecaddr); 1084 bus_space_write_4(t, cr, BE_CRI_TXWBUF, qecaddr + qec->sc_rsize); 1085 bus_space_write_4(t, cr, BE_CRI_TXRBUF, qecaddr + qec->sc_rsize); 1086 1087 bus_space_write_4(t, cr, BE_CRI_RIMASK, 0); 1088 bus_space_write_4(t, cr, BE_CRI_TIMASK, 0); 1089 bus_space_write_4(t, cr, BE_CRI_QMASK, 0); 1090 bus_space_write_4(t, cr, BE_CRI_BMASK, 0); 1091 bus_space_write_4(t, cr, BE_CRI_CCNT, 0); 1092 1093 /* Set max packet length */ 1094 v = ETHER_MAX_LEN; 1095 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) 1096 v += ETHER_VLAN_ENCAP_LEN; 1097 bus_space_write_4(t, br, BE_BRI_RXMAX, v); 1098 bus_space_write_4(t, br, BE_BRI_TXMAX, v); 1099 1100 /* Enable transmitter */ 1101 bus_space_write_4(t, br, 1102 BE_BRI_TXCFG, BE_BR_TXCFG_FIFO | BE_BR_TXCFG_ENABLE); 1103 1104 /* Enable receiver */ 1105 v = bus_space_read_4(t, br, BE_BRI_RXCFG); 1106 v |= BE_BR_RXCFG_FIFO | BE_BR_RXCFG_ENABLE; 1107 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1108 1109 if ((rc = be_ifmedia_upd(ifp)) != 0) 1110 goto out; 1111 1112 ifp->if_flags |= IFF_RUNNING; 1113 ifp->if_flags &= ~IFF_OACTIVE; 1114 1115 callout_reset(&sc->sc_tick_ch, hz, be_tick, sc); 1116 1117 splx(s); 1118 return 0; 1119 out: 1120 splx(s); 1121 return rc; 1122 } 1123 1124 void 1125 be_mcreset(struct be_softc *sc) 1126 { 1127 struct ethercom *ec = &sc->sc_ethercom; 1128 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1129 bus_space_tag_t t = sc->sc_bustag; 1130 bus_space_handle_t br = sc->sc_br; 1131 uint32_t v; 1132 uint32_t crc; 1133 uint16_t hash[4]; 1134 struct ether_multi *enm; 1135 struct ether_multistep step; 1136 1137 if (ifp->if_flags & IFF_PROMISC) { 1138 v = bus_space_read_4(t, br, BE_BRI_RXCFG); 1139 v |= BE_BR_RXCFG_PMISC; 1140 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1141 return; 1142 } 1143 1144 if (ifp->if_flags & IFF_ALLMULTI) { 1145 hash[3] = hash[2] = hash[1] = hash[0] = 0xffff; 1146 goto chipit; 1147 } 1148 1149 hash[3] = hash[2] = hash[1] = hash[0] = 0; 1150 1151 ETHER_LOCK(ec); 1152 ETHER_FIRST_MULTI(step, ec, enm); 1153 while (enm != NULL) { 1154 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1155 /* 1156 * We must listen to a range of multicast 1157 * addresses. For now, just accept all 1158 * multicasts, rather than trying to set only 1159 * those filter bits needed to match the range. 1160 * (At this time, the only use of address 1161 * ranges is for IP multicast routing, for 1162 * which the range is big enough to require 1163 * all bits set.) 1164 */ 1165 hash[3] = hash[2] = hash[1] = hash[0] = 0xffff; 1166 ifp->if_flags |= IFF_ALLMULTI; 1167 ETHER_UNLOCK(ec); 1168 goto chipit; 1169 } 1170 1171 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 1172 /* Just want the 6 most significant bits. */ 1173 crc >>= 26; 1174 1175 hash[crc >> 4] |= 1 << (crc & 0xf); 1176 ETHER_NEXT_MULTI(step, enm); 1177 } 1178 ETHER_UNLOCK(ec); 1179 1180 ifp->if_flags &= ~IFF_ALLMULTI; 1181 1182 chipit: 1183 /* Enable the hash filter */ 1184 bus_space_write_4(t, br, BE_BRI_HASHTAB0, hash[0]); 1185 bus_space_write_4(t, br, BE_BRI_HASHTAB1, hash[1]); 1186 bus_space_write_4(t, br, BE_BRI_HASHTAB2, hash[2]); 1187 bus_space_write_4(t, br, BE_BRI_HASHTAB3, hash[3]); 1188 1189 v = bus_space_read_4(t, br, BE_BRI_RXCFG); 1190 v &= ~BE_BR_RXCFG_PMISC; 1191 v |= BE_BR_RXCFG_HENABLE; 1192 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1193 } 1194 1195 /* 1196 * Set the tcvr to an idle state 1197 */ 1198 void 1199 be_mii_sync(struct be_softc *sc) 1200 { 1201 bus_space_tag_t t = sc->sc_bustag; 1202 bus_space_handle_t tr = sc->sc_tr; 1203 int n = 32; 1204 1205 while (n--) { 1206 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, 1207 MGMT_PAL_INT_MDIO | MGMT_PAL_EXT_MDIO | MGMT_PAL_OENAB); 1208 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1209 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, 1210 MGMT_PAL_INT_MDIO | MGMT_PAL_EXT_MDIO | 1211 MGMT_PAL_OENAB | MGMT_PAL_DCLOCK); 1212 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1213 } 1214 } 1215 1216 void 1217 be_pal_gate(struct be_softc *sc, int phy) 1218 { 1219 bus_space_tag_t t = sc->sc_bustag; 1220 bus_space_handle_t tr = sc->sc_tr; 1221 uint32_t v; 1222 1223 be_mii_sync(sc); 1224 1225 v = ~(TCVR_PAL_EXTLBACK | TCVR_PAL_MSENSE | TCVR_PAL_LTENABLE); 1226 if (phy == BE_PHY_INTERNAL) 1227 v &= ~TCVR_PAL_SERIAL; 1228 1229 bus_space_write_4(t, tr, BE_TRI_TCVRPAL, v); 1230 (void)bus_space_read_4(t, tr, BE_TRI_TCVRPAL); 1231 } 1232 1233 static int 1234 be_tcvr_read_bit(struct be_softc *sc, int phy) 1235 { 1236 bus_space_tag_t t = sc->sc_bustag; 1237 bus_space_handle_t tr = sc->sc_tr; 1238 int ret; 1239 1240 if (phy == BE_PHY_INTERNAL) { 1241 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, MGMT_PAL_EXT_MDIO); 1242 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1243 bus_space_write_4(t, tr, 1244 BE_TRI_MGMTPAL, MGMT_PAL_EXT_MDIO | MGMT_PAL_DCLOCK); 1245 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1246 ret = (bus_space_read_4(t, tr, BE_TRI_MGMTPAL) & 1247 MGMT_PAL_INT_MDIO) >> MGMT_PAL_INT_MDIO_SHIFT; 1248 } else { 1249 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, MGMT_PAL_INT_MDIO); 1250 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1251 ret = (bus_space_read_4(t, tr, BE_TRI_MGMTPAL) & 1252 MGMT_PAL_EXT_MDIO) >> MGMT_PAL_EXT_MDIO_SHIFT; 1253 bus_space_write_4(t, tr, 1254 BE_TRI_MGMTPAL, MGMT_PAL_INT_MDIO | MGMT_PAL_DCLOCK); 1255 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1256 } 1257 1258 return ret; 1259 } 1260 1261 static void 1262 be_tcvr_write_bit(struct be_softc *sc, int phy, int bit) 1263 { 1264 bus_space_tag_t t = sc->sc_bustag; 1265 bus_space_handle_t tr = sc->sc_tr; 1266 uint32_t v; 1267 1268 if (phy == BE_PHY_INTERNAL) { 1269 v = ((bit & 1) << MGMT_PAL_INT_MDIO_SHIFT) | 1270 MGMT_PAL_OENAB | MGMT_PAL_EXT_MDIO; 1271 } else { 1272 v = ((bit & 1) << MGMT_PAL_EXT_MDIO_SHIFT) | 1273 MGMT_PAL_OENAB | MGMT_PAL_INT_MDIO; 1274 } 1275 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, v); 1276 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1277 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, v | MGMT_PAL_DCLOCK); 1278 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1279 } 1280 1281 static void 1282 be_mii_sendbits(struct be_softc *sc, int phy, uint32_t data, int nbits) 1283 { 1284 int i; 1285 1286 for (i = 1 << (nbits - 1); i != 0; i >>= 1) { 1287 be_tcvr_write_bit(sc, phy, (data & i) != 0); 1288 } 1289 } 1290 1291 static int 1292 be_mii_readreg(device_t self, int phy, int reg, uint16_t *val) 1293 { 1294 struct be_softc *sc = device_private(self); 1295 int i; 1296 uint16_t data = 0; 1297 1298 /* 1299 * Read the PHY register by manually driving the MII control lines. 1300 */ 1301 be_mii_sync(sc); 1302 be_mii_sendbits(sc, phy, MII_COMMAND_START, 2); 1303 be_mii_sendbits(sc, phy, MII_COMMAND_READ, 2); 1304 be_mii_sendbits(sc, phy, phy, 5); 1305 be_mii_sendbits(sc, phy, reg, 5); 1306 1307 (void)be_tcvr_read_bit(sc, phy); 1308 (void)be_tcvr_read_bit(sc, phy); 1309 1310 for (i = 15; i >= 0; i--) 1311 data |= (be_tcvr_read_bit(sc, phy) << i); 1312 1313 (void)be_tcvr_read_bit(sc, phy); 1314 (void)be_tcvr_read_bit(sc, phy); 1315 (void)be_tcvr_read_bit(sc, phy); 1316 1317 *val = data; 1318 return 0; 1319 } 1320 1321 int 1322 be_mii_writereg(device_t self, int phy, int reg, uint16_t val) 1323 { 1324 struct be_softc *sc = device_private(self); 1325 int i; 1326 1327 /* 1328 * Write the PHY register by manually driving the MII control lines. 1329 */ 1330 be_mii_sync(sc); 1331 be_mii_sendbits(sc, phy, MII_COMMAND_START, 2); 1332 be_mii_sendbits(sc, phy, MII_COMMAND_WRITE, 2); 1333 be_mii_sendbits(sc, phy, phy, 5); 1334 be_mii_sendbits(sc, phy, reg, 5); 1335 1336 be_tcvr_write_bit(sc, phy, 1); 1337 be_tcvr_write_bit(sc, phy, 0); 1338 1339 for (i = 15; i >= 0; i--) 1340 be_tcvr_write_bit(sc, phy, (val >> i) & 1); 1341 1342 return 0; 1343 } 1344 1345 int 1346 be_mii_reset(struct be_softc *sc, int phy) 1347 { 1348 device_t self = sc->sc_dev; 1349 int n; 1350 1351 be_mii_writereg(self, phy, MII_BMCR, BMCR_LOOP | BMCR_PDOWN | BMCR_ISO); 1352 be_mii_writereg(self, phy, MII_BMCR, BMCR_RESET); 1353 1354 for (n = 16; n >= 0; n--) { 1355 uint16_t bmcr; 1356 1357 be_mii_readreg(self, phy, MII_BMCR, &bmcr); 1358 if ((bmcr & BMCR_RESET) == 0) 1359 break; 1360 DELAY(20); 1361 } 1362 if (n == 0) { 1363 aprint_error_dev(self, "bmcr reset failed\n"); 1364 return EIO; 1365 } 1366 1367 return 0; 1368 } 1369 1370 void 1371 be_tick(void *arg) 1372 { 1373 struct be_softc *sc = arg; 1374 int s = splnet(); 1375 1376 mii_tick(&sc->sc_mii); 1377 (void)be_intphy_service(sc, &sc->sc_mii, MII_TICK); 1378 1379 splx(s); 1380 callout_reset(&sc->sc_tick_ch, hz, be_tick, sc); 1381 } 1382 1383 void 1384 be_mii_statchg(struct ifnet *ifp) 1385 { 1386 struct be_softc *sc = ifp->if_softc; 1387 bus_space_tag_t t = sc->sc_bustag; 1388 bus_space_handle_t br = sc->sc_br; 1389 uint instance; 1390 uint32_t v; 1391 1392 instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media); 1393 #ifdef DIAGNOSTIC 1394 if (instance > 1) 1395 panic("be_mii_statchg: instance %d out of range", instance); 1396 #endif 1397 1398 /* Update duplex mode in TX configuration */ 1399 v = bus_space_read_4(t, br, BE_BRI_TXCFG); 1400 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 1401 v |= BE_BR_TXCFG_FULLDPLX; 1402 else 1403 v &= ~BE_BR_TXCFG_FULLDPLX; 1404 bus_space_write_4(t, br, BE_BRI_TXCFG, v); 1405 1406 /* Change to appropriate gate in transceiver PAL */ 1407 be_pal_gate(sc, sc->sc_phys[instance]); 1408 } 1409 1410 /* 1411 * Get current media settings. 1412 */ 1413 void 1414 be_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1415 { 1416 struct be_softc *sc = ifp->if_softc; 1417 1418 mii_pollstat(&sc->sc_mii); 1419 (void)be_intphy_service(sc, &sc->sc_mii, MII_POLLSTAT); 1420 1421 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1422 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1423 } 1424 1425 /* 1426 * Set media options. 1427 */ 1428 int 1429 be_ifmedia_upd(struct ifnet *ifp) 1430 { 1431 struct be_softc *sc = ifp->if_softc; 1432 int error; 1433 1434 if ((error = mii_mediachg(&sc->sc_mii)) == ENXIO) 1435 error = 0; 1436 else if (error != 0) 1437 return error; 1438 1439 return be_intphy_service(sc, &sc->sc_mii, MII_MEDIACHG); 1440 } 1441 1442 /* 1443 * Service routine for our pseudo-MII internal transceiver. 1444 */ 1445 int 1446 be_intphy_service(struct be_softc *sc, struct mii_data *mii, int cmd) 1447 { 1448 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 1449 device_t self = sc->sc_dev; 1450 uint16_t bmcr, bmsr; 1451 int error; 1452 1453 switch (cmd) { 1454 case MII_POLLSTAT: 1455 /* 1456 * If we're not polling our PHY instance, just return. 1457 */ 1458 if (IFM_INST(ife->ifm_media) != sc->sc_mii_inst) 1459 return 0; 1460 1461 break; 1462 1463 case MII_MEDIACHG: 1464 1465 /* 1466 * If the media indicates a different PHY instance, 1467 * isolate ourselves. 1468 */ 1469 if (IFM_INST(ife->ifm_media) != sc->sc_mii_inst) { 1470 be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMCR, &bmcr); 1471 be_mii_writereg(self, 1472 BE_PHY_INTERNAL, MII_BMCR, bmcr | BMCR_ISO); 1473 sc->sc_mii_flags &= ~MIIF_HAVELINK; 1474 sc->sc_intphy_curspeed = 0; 1475 return 0; 1476 } 1477 1478 1479 if ((error = be_mii_reset(sc, BE_PHY_INTERNAL)) != 0) 1480 return error; 1481 1482 be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMCR, &bmcr); 1483 1484 /* 1485 * Select the new mode and take out of isolation 1486 */ 1487 if (IFM_SUBTYPE(ife->ifm_media) == IFM_100_TX) 1488 bmcr |= BMCR_S100; 1489 else if (IFM_SUBTYPE(ife->ifm_media) == IFM_10_T) 1490 bmcr &= ~BMCR_S100; 1491 else if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) { 1492 if ((sc->sc_mii_flags & MIIF_HAVELINK) != 0) { 1493 bmcr &= ~BMCR_S100; 1494 bmcr |= sc->sc_intphy_curspeed; 1495 } else { 1496 /* Keep isolated until link is up */ 1497 bmcr |= BMCR_ISO; 1498 sc->sc_mii_flags |= MIIF_DOINGAUTO; 1499 } 1500 } 1501 1502 if ((IFM_OPTIONS(ife->ifm_media) & IFM_FDX) != 0) 1503 bmcr |= BMCR_FDX; 1504 else 1505 bmcr &= ~BMCR_FDX; 1506 1507 be_mii_writereg(self, BE_PHY_INTERNAL, MII_BMCR, bmcr); 1508 break; 1509 1510 case MII_TICK: 1511 /* 1512 * If we're not currently selected, just return. 1513 */ 1514 if (IFM_INST(ife->ifm_media) != sc->sc_mii_inst) 1515 return 0; 1516 1517 /* Is the interface even up? */ 1518 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 1519 return 0; 1520 1521 /* Only used for automatic media selection */ 1522 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) 1523 break; 1524 1525 /* 1526 * Check link status; if we don't have a link, try another 1527 * speed. We can't detect duplex mode, so half-duplex is 1528 * what we have to settle for. 1529 */ 1530 1531 /* Read twice in case the register is latched */ 1532 be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMSR, &bmsr); 1533 be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMSR, &bmsr); 1534 1535 if ((bmsr & BMSR_LINK) != 0) { 1536 /* We have a carrier */ 1537 be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMCR, &bmcr); 1538 1539 if ((sc->sc_mii_flags & MIIF_DOINGAUTO) != 0) { 1540 be_mii_readreg(self, 1541 BE_PHY_INTERNAL, MII_BMCR, &bmcr); 1542 1543 sc->sc_mii_flags |= MIIF_HAVELINK; 1544 sc->sc_intphy_curspeed = (bmcr & BMCR_S100); 1545 sc->sc_mii_flags &= ~MIIF_DOINGAUTO; 1546 1547 bmcr &= ~BMCR_ISO; 1548 be_mii_writereg(self, 1549 BE_PHY_INTERNAL, MII_BMCR, bmcr); 1550 1551 printf("%s: link up at %s Mbps\n", 1552 device_xname(self), 1553 (bmcr & BMCR_S100) ? "100" : "10"); 1554 } 1555 break; 1556 } 1557 1558 if ((sc->sc_mii_flags & MIIF_DOINGAUTO) == 0) { 1559 sc->sc_mii_flags |= MIIF_DOINGAUTO; 1560 sc->sc_mii_flags &= ~MIIF_HAVELINK; 1561 sc->sc_intphy_curspeed = 0; 1562 printf("%s: link down\n", device_xname(self)); 1563 } 1564 1565 /* Only retry autonegotiation every 5 seconds. */ 1566 if (++sc->sc_mii_ticks < 5) 1567 return 0; 1568 1569 sc->sc_mii_ticks = 0; 1570 be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMCR, &bmcr); 1571 /* Just flip the fast speed bit */ 1572 bmcr ^= BMCR_S100; 1573 be_mii_writereg(self, BE_PHY_INTERNAL, MII_BMCR, bmcr); 1574 1575 break; 1576 1577 case MII_DOWN: 1578 /* Isolate this phy */ 1579 be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMCR, &bmcr); 1580 be_mii_writereg(self, 1581 BE_PHY_INTERNAL, MII_BMCR, bmcr | BMCR_ISO); 1582 return 0; 1583 } 1584 1585 /* Update the media status. */ 1586 be_intphy_status(sc); 1587 1588 /* Callback if something changed. */ 1589 if (sc->sc_mii_active != mii->mii_media_active || cmd == MII_MEDIACHG) { 1590 (*mii->mii_statchg)(mii->mii_ifp); 1591 sc->sc_mii_active = mii->mii_media_active; 1592 } 1593 return 0; 1594 } 1595 1596 /* 1597 * Determine status of internal transceiver 1598 */ 1599 void 1600 be_intphy_status(struct be_softc *sc) 1601 { 1602 struct mii_data *mii = &sc->sc_mii; 1603 device_t self = sc->sc_dev; 1604 int media_active, media_status; 1605 uint16_t bmcr, bmsr; 1606 1607 media_status = IFM_AVALID; 1608 media_active = 0; 1609 1610 /* 1611 * Internal transceiver; do the work here. 1612 */ 1613 be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMCR, &bmcr); 1614 1615 switch (bmcr & (BMCR_S100 | BMCR_FDX)) { 1616 case (BMCR_S100 | BMCR_FDX): 1617 media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 1618 break; 1619 case BMCR_S100: 1620 media_active = IFM_ETHER | IFM_100_TX | IFM_HDX; 1621 break; 1622 case BMCR_FDX: 1623 media_active = IFM_ETHER | IFM_10_T | IFM_FDX; 1624 break; 1625 case 0: 1626 media_active = IFM_ETHER | IFM_10_T | IFM_HDX; 1627 break; 1628 } 1629 1630 /* Read twice in case the register is latched */ 1631 be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMSR, &bmsr); 1632 be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMSR, &bmsr); 1633 if (bmsr & BMSR_LINK) 1634 media_status |= IFM_ACTIVE; 1635 1636 mii->mii_media_status = media_status; 1637 mii->mii_media_active = media_active; 1638 } 1639
Indexes created Tue Sep 30 20:09:53 GMT 2025