be.c revision 1.94
1 /* $NetBSD: be.c,v 1.94 2019/05/29 10:07:30 msaitoh Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Copyright (c) 1998 Theo de Raadt and Jason L. Wright. 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. The name of the authors may not be used to endorse or promote products 45 * derived from this software without specific prior written permission. 46 * 47 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR 48 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 49 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 50 * IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, 51 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 52 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 53 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 54 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 55 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 56 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 57 */ 58 59 #include <sys/cdefs.h> 60 __KERNEL_RCSID(0, "$NetBSD: be.c,v 1.94 2019/05/29 10:07:30 msaitoh Exp $"); 61 62 #include "opt_ddb.h" 63 #include "opt_inet.h" 64 65 #include <sys/param.h> 66 #include <sys/systm.h> 67 #include <sys/callout.h> 68 #include <sys/kernel.h> 69 #include <sys/errno.h> 70 #include <sys/ioctl.h> 71 #include <sys/mbuf.h> 72 #include <sys/socket.h> 73 #include <sys/syslog.h> 74 #include <sys/device.h> 75 #include <sys/malloc.h> 76 77 #include <net/if.h> 78 #include <net/if_dl.h> 79 #include <net/if_types.h> 80 #include <net/netisr.h> 81 #include <net/if_media.h> 82 #include <net/if_ether.h> 83 #include <net/bpf.h> 84 85 #ifdef INET 86 #include <netinet/in.h> 87 #include <netinet/if_inarp.h> 88 #include <netinet/in_systm.h> 89 #include <netinet/in_var.h> 90 #include <netinet/ip.h> 91 #endif 92 93 #include <sys/bus.h> 94 #include <sys/intr.h> 95 #include <machine/autoconf.h> 96 97 #include <dev/mii/mii.h> 98 #include <dev/mii/miivar.h> 99 100 #include <dev/sbus/sbusvar.h> 101 #include <dev/sbus/qecreg.h> 102 #include <dev/sbus/qecvar.h> 103 #include <dev/sbus/bereg.h> 104 105 struct be_softc { 106 device_t sc_dev; 107 bus_space_tag_t sc_bustag; /* bus & DMA tags */ 108 bus_dma_tag_t sc_dmatag; 109 bus_dmamap_t sc_dmamap; 110 struct ethercom sc_ethercom; 111 /*struct ifmedia sc_ifmedia; -* interface media */ 112 struct mii_data sc_mii; /* MII media control */ 113 #define sc_media sc_mii.mii_media/* shorthand */ 114 int sc_phys[2]; /* MII instance -> phy */ 115 116 struct callout sc_tick_ch; 117 118 /* 119 * Some `mii_softc' items we need to emulate MII operation 120 * for our internal transceiver. 121 */ 122 int sc_mii_inst; /* instance of internal phy */ 123 int sc_mii_active; /* currently active medium */ 124 int sc_mii_ticks; /* tick counter */ 125 int sc_mii_flags; /* phy status flags */ 126 #define MIIF_HAVELINK 0x04000000 127 int sc_intphy_curspeed; /* Established link speed */ 128 129 struct qec_softc *sc_qec; /* QEC parent */ 130 131 bus_space_handle_t sc_qr; /* QEC registers */ 132 bus_space_handle_t sc_br; /* BE registers */ 133 bus_space_handle_t sc_cr; /* channel registers */ 134 bus_space_handle_t sc_tr; /* transceiver registers */ 135 136 u_int sc_rev; 137 138 int sc_channel; /* channel number */ 139 int sc_burst; 140 141 struct qec_ring sc_rb; /* Packet Ring Buffer */ 142 143 /* MAC address */ 144 uint8_t sc_enaddr[ETHER_ADDR_LEN]; 145 #ifdef BEDEBUG 146 int sc_debug; 147 #endif 148 }; 149 150 static int bematch(device_t, cfdata_t, void *); 151 static void beattach(device_t, device_t, void *); 152 153 static int beinit(struct ifnet *); 154 static void bestart(struct ifnet *); 155 static void bestop(struct ifnet *, int); 156 static void bewatchdog(struct ifnet *); 157 static int beioctl(struct ifnet *, u_long, void *); 158 static void bereset(struct be_softc *); 159 static void behwreset(struct be_softc *); 160 161 static int beintr(void *); 162 static int berint(struct be_softc *); 163 static int betint(struct be_softc *); 164 static int beqint(struct be_softc *, uint32_t); 165 static int beeint(struct be_softc *, uint32_t); 166 167 static void be_read(struct be_softc *, int, int); 168 static int be_put(struct be_softc *, int, struct mbuf *); 169 static struct mbuf *be_get(struct be_softc *, int, int); 170 171 static void be_pal_gate(struct be_softc *, int); 172 173 /* ifmedia callbacks */ 174 static void be_ifmedia_sts(struct ifnet *, struct ifmediareq *); 175 static int be_ifmedia_upd(struct ifnet *); 176 177 static void be_mcreset(struct be_softc *); 178 179 /* MII methods & callbacks */ 180 static int be_mii_readreg(device_t, int, int, uint16_t *); 181 static int be_mii_writereg(device_t, int, int, uint16_t); 182 static void be_mii_statchg(struct ifnet *); 183 184 /* MII helpers */ 185 static void be_mii_sync(struct be_softc *); 186 static void be_mii_sendbits(struct be_softc *, int, uint32_t, int); 187 static int be_mii_reset(struct be_softc *, int); 188 static int be_tcvr_read_bit(struct be_softc *, int); 189 static void be_tcvr_write_bit(struct be_softc *, int, int); 190 191 static void be_tick(void *); 192 #if 0 193 static void be_intphy_auto(struct be_softc *); 194 #endif 195 static void be_intphy_status(struct be_softc *); 196 static int be_intphy_service(struct be_softc *, struct mii_data *, int); 197 198 199 CFATTACH_DECL_NEW(be, sizeof(struct be_softc), 200 bematch, beattach, NULL, NULL); 201 202 int 203 bematch(device_t parent, cfdata_t cf, void *aux) 204 { 205 struct sbus_attach_args *sa = aux; 206 207 return strcmp(cf->cf_name, sa->sa_name) == 0; 208 } 209 210 void 211 beattach(device_t parent, device_t self, void *aux) 212 { 213 struct sbus_attach_args *sa = aux; 214 struct qec_softc *qec = device_private(parent); 215 struct be_softc *sc = device_private(self); 216 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 217 struct mii_data *mii = &sc->sc_mii; 218 struct mii_softc *child; 219 int node = sa->sa_node; 220 bus_dma_tag_t dmatag = sa->sa_dmatag; 221 bus_dma_segment_t seg; 222 bus_size_t size; 223 int instance; 224 int rseg, error; 225 uint32_t v; 226 227 sc->sc_dev = self; 228 229 if (sa->sa_nreg < 3) { 230 printf(": only %d register sets\n", sa->sa_nreg); 231 return; 232 } 233 234 if (bus_space_map(sa->sa_bustag, 235 (bus_addr_t)BUS_ADDR(sa->sa_reg[0].oa_space, sa->sa_reg[0].oa_base), 236 (bus_size_t)sa->sa_reg[0].oa_size, 237 0, &sc->sc_cr) != 0) { 238 printf(": cannot map registers\n"); 239 return; 240 } 241 242 if (bus_space_map(sa->sa_bustag, 243 (bus_addr_t)BUS_ADDR(sa->sa_reg[1].oa_space, sa->sa_reg[1].oa_base), 244 (bus_size_t)sa->sa_reg[1].oa_size, 245 0, &sc->sc_br) != 0) { 246 printf(": cannot map registers\n"); 247 return; 248 } 249 250 if (bus_space_map(sa->sa_bustag, 251 (bus_addr_t)BUS_ADDR(sa->sa_reg[2].oa_space, sa->sa_reg[2].oa_base), 252 (bus_size_t)sa->sa_reg[2].oa_size, 253 0, &sc->sc_tr) != 0) { 254 printf(": cannot map registers\n"); 255 return; 256 } 257 258 sc->sc_bustag = sa->sa_bustag; 259 sc->sc_qec = qec; 260 sc->sc_qr = qec->sc_regs; 261 262 sc->sc_rev = prom_getpropint(node, "board-version", -1); 263 printf(": rev %x,", sc->sc_rev); 264 265 callout_init(&sc->sc_tick_ch, 0); 266 267 sc->sc_channel = prom_getpropint(node, "channel#", -1); 268 if (sc->sc_channel == -1) 269 sc->sc_channel = 0; 270 271 sc->sc_burst = prom_getpropint(node, "burst-sizes", -1); 272 if (sc->sc_burst == -1) 273 sc->sc_burst = qec->sc_burst; 274 275 /* Clamp at parent's burst sizes */ 276 sc->sc_burst &= qec->sc_burst; 277 278 /* Establish interrupt handler */ 279 if (sa->sa_nintr) 280 (void)bus_intr_establish(sa->sa_bustag, sa->sa_pri, IPL_NET, 281 beintr, sc); 282 283 prom_getether(node, sc->sc_enaddr); 284 printf(" address %s\n", ether_sprintf(sc->sc_enaddr)); 285 286 /* 287 * Allocate descriptor ring and buffers. 288 */ 289 290 /* for now, allocate as many bufs as there are ring descriptors */ 291 sc->sc_rb.rb_ntbuf = QEC_XD_RING_MAXSIZE; 292 sc->sc_rb.rb_nrbuf = QEC_XD_RING_MAXSIZE; 293 294 size = 295 QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd) + 296 QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd) + 297 sc->sc_rb.rb_ntbuf * BE_PKT_BUF_SZ + 298 sc->sc_rb.rb_nrbuf * BE_PKT_BUF_SZ; 299 300 /* Get a DMA handle */ 301 if ((error = bus_dmamap_create(dmatag, size, 1, size, 0, 302 BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) { 303 aprint_error_dev(self, "DMA map create error %d\n", error); 304 return; 305 } 306 307 /* Allocate DMA buffer */ 308 if ((error = bus_dmamem_alloc(sa->sa_dmatag, size, 0, 0, 309 &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 310 aprint_error_dev(self, "DMA buffer alloc error %d\n", error); 311 return; 312 } 313 314 /* Map DMA memory in CPU addressable space */ 315 if ((error = bus_dmamem_map(sa->sa_dmatag, &seg, rseg, size, 316 &sc->sc_rb.rb_membase, BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) { 317 aprint_error_dev(self, "DMA buffer map error %d\n", error); 318 bus_dmamem_free(sa->sa_dmatag, &seg, rseg); 319 return; 320 } 321 322 /* Load the buffer */ 323 if ((error = bus_dmamap_load(dmatag, sc->sc_dmamap, 324 sc->sc_rb.rb_membase, size, NULL, BUS_DMA_NOWAIT)) != 0) { 325 aprint_error_dev(self, "DMA buffer map load error %d\n", error); 326 bus_dmamem_unmap(dmatag, sc->sc_rb.rb_membase, size); 327 bus_dmamem_free(dmatag, &seg, rseg); 328 return; 329 } 330 sc->sc_rb.rb_dmabase = sc->sc_dmamap->dm_segs[0].ds_addr; 331 332 /* 333 * Initialize our media structures and MII info. 334 */ 335 mii->mii_ifp = ifp; 336 mii->mii_readreg = be_mii_readreg; 337 mii->mii_writereg = be_mii_writereg; 338 mii->mii_statchg = be_mii_statchg; 339 340 sc->sc_ethercom.ec_mii = mii; 341 ifmedia_init(&mii->mii_media, 0, be_ifmedia_upd, be_ifmedia_sts); 342 343 /* 344 * Initialize transceiver and determine which PHY connection to use. 345 */ 346 be_mii_sync(sc); 347 v = bus_space_read_4(sc->sc_bustag, sc->sc_tr, BE_TRI_MGMTPAL); 348 349 instance = 0; 350 351 if ((v & MGMT_PAL_EXT_MDIO) != 0) { 352 353 mii_attach(self, mii, 0xffffffff, BE_PHY_EXTERNAL, 354 MII_OFFSET_ANY, 0); 355 356 child = LIST_FIRST(&mii->mii_phys); 357 if (child == NULL) { 358 /* No PHY attached */ 359 ifmedia_add(&sc->sc_media, 360 IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, instance), 361 0, NULL); 362 ifmedia_set(&sc->sc_media, 363 IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, instance)); 364 } else { 365 /* 366 * Note: we support just one PHY on the external 367 * MII connector. 368 */ 369 #ifdef DIAGNOSTIC 370 if (LIST_NEXT(child, mii_list) != NULL) { 371 aprint_error_dev(self, 372 "spurious MII device %s attached\n", 373 device_xname(child->mii_dev)); 374 } 375 #endif 376 if (child->mii_phy != BE_PHY_EXTERNAL || 377 child->mii_inst > 0) { 378 aprint_error_dev(self, 379 "cannot accommodate MII device %s" 380 " at phy %d, instance %d\n", 381 device_xname(child->mii_dev), 382 child->mii_phy, child->mii_inst); 383 } else { 384 sc->sc_phys[instance] = child->mii_phy; 385 } 386 387 /* 388 * XXX - we can really do the following ONLY if the 389 * phy indeed has the auto negotiation capability!! 390 */ 391 ifmedia_set(&sc->sc_media, 392 IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, instance)); 393 394 /* Mark our current media setting */ 395 be_pal_gate(sc, BE_PHY_EXTERNAL); 396 instance++; 397 } 398 399 } 400 401 if ((v & MGMT_PAL_INT_MDIO) != 0) { 402 /* 403 * The be internal phy looks vaguely like MII hardware, 404 * but not enough to be able to use the MII device 405 * layer. Hence, we have to take care of media selection 406 * ourselves. 407 */ 408 409 sc->sc_mii_inst = instance; 410 sc->sc_phys[instance] = BE_PHY_INTERNAL; 411 412 /* Use `ifm_data' to store BMCR bits */ 413 ifmedia_add(&sc->sc_media, 414 IFM_MAKEWORD(IFM_ETHER, IFM_10_T, 0, instance), 415 0, NULL); 416 ifmedia_add(&sc->sc_media, 417 IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, 0, instance), 418 BMCR_S100, NULL); 419 ifmedia_add(&sc->sc_media, 420 IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, instance), 421 0, NULL); 422 423 printf("on-board transceiver at %s: 10baseT, 100baseTX, auto\n", 424 device_xname(self)); 425 426 be_mii_reset(sc, BE_PHY_INTERNAL); 427 /* Only set default medium here if there's no external PHY */ 428 if (instance == 0) { 429 be_pal_gate(sc, BE_PHY_INTERNAL); 430 ifmedia_set(&sc->sc_media, 431 IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, instance)); 432 } else 433 be_mii_writereg(self, 434 BE_PHY_INTERNAL, MII_BMCR, BMCR_ISO); 435 } 436 437 memcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 438 ifp->if_softc = sc; 439 ifp->if_start = bestart; 440 ifp->if_ioctl = beioctl; 441 ifp->if_watchdog = bewatchdog; 442 ifp->if_init = beinit; 443 ifp->if_stop = bestop; 444 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 445 IFQ_SET_READY(&ifp->if_snd); 446 447 /* claim 802.1q capability */ 448 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 449 450 /* Attach the interface. */ 451 if_attach(ifp); 452 ether_ifattach(ifp, sc->sc_enaddr); 453 } 454 455 456 /* 457 * Routine to copy from mbuf chain to transmit buffer in 458 * network buffer memory. 459 */ 460 static inline int 461 be_put(struct be_softc *sc, int idx, struct mbuf *m) 462 { 463 struct mbuf *n; 464 int len, tlen = 0, boff = 0; 465 uint8_t *bp; 466 467 bp = sc->sc_rb.rb_txbuf + (idx % sc->sc_rb.rb_ntbuf) * BE_PKT_BUF_SZ; 468 469 for (; m; m = n) { 470 len = m->m_len; 471 if (len == 0) { 472 n = m_free(m); 473 continue; 474 } 475 memcpy(bp + boff, mtod(m, void *), len); 476 boff += len; 477 tlen += len; 478 n = m_free(m); 479 } 480 return tlen; 481 } 482 483 /* 484 * Pull data off an interface. 485 * Len is the length of data, with local net header stripped. 486 * We copy the data into mbufs. When full cluster sized units are present, 487 * we copy into clusters. 488 */ 489 static inline struct mbuf * 490 be_get(struct be_softc *sc, int idx, int totlen) 491 { 492 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 493 struct mbuf *m; 494 struct mbuf *top, **mp; 495 int len, pad, boff = 0; 496 uint8_t *bp; 497 498 bp = sc->sc_rb.rb_rxbuf + (idx % sc->sc_rb.rb_nrbuf) * BE_PKT_BUF_SZ; 499 500 MGETHDR(m, M_DONTWAIT, MT_DATA); 501 if (m == NULL) 502 return (NULL); 503 m_set_rcvif(m, ifp); 504 m->m_pkthdr.len = totlen; 505 506 pad = ALIGN(sizeof(struct ether_header)) - sizeof(struct ether_header); 507 m->m_data += pad; 508 len = MHLEN - pad; 509 top = NULL; 510 mp = ⊤ 511 512 while (totlen > 0) { 513 if (top) { 514 MGET(m, M_DONTWAIT, MT_DATA); 515 if (m == NULL) { 516 m_freem(top); 517 return (NULL); 518 } 519 len = MLEN; 520 } 521 if (top && totlen >= MINCLSIZE) { 522 MCLGET(m, M_DONTWAIT); 523 if (m->m_flags & M_EXT) 524 len = MCLBYTES; 525 } 526 m->m_len = len = uimin(totlen, len); 527 memcpy(mtod(m, void *), bp + boff, len); 528 boff += len; 529 totlen -= len; 530 *mp = m; 531 mp = &m->m_next; 532 } 533 534 return top; 535 } 536 537 /* 538 * Pass a packet to the higher levels. 539 */ 540 static inline void 541 be_read(struct be_softc *sc, int idx, int len) 542 { 543 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 544 struct mbuf *m; 545 546 if (len <= sizeof(struct ether_header) || 547 len > ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN) { 548 #ifdef BEDEBUG 549 if (sc->sc_debug) 550 printf("%s: invalid packet size %d; dropping\n", 551 ifp->if_xname, len); 552 #endif 553 ifp->if_ierrors++; 554 return; 555 } 556 557 /* 558 * Pull packet off interface. 559 */ 560 m = be_get(sc, idx, len); 561 if (m == NULL) { 562 ifp->if_ierrors++; 563 return; 564 } 565 566 /* Pass the packet up. */ 567 if_percpuq_enqueue(ifp->if_percpuq, m); 568 } 569 570 /* 571 * Start output on interface. 572 * We make two assumptions here: 573 * 1) that the current priority is set to splnet _before_ this code 574 * is called *and* is returned to the appropriate priority after 575 * return 576 * 2) that the IFF_OACTIVE flag is checked before this code is called 577 * (i.e. that the output part of the interface is idle) 578 */ 579 void 580 bestart(struct ifnet *ifp) 581 { 582 struct be_softc *sc = ifp->if_softc; 583 struct qec_xd *txd = sc->sc_rb.rb_txd; 584 struct mbuf *m; 585 unsigned int bix, len; 586 unsigned int ntbuf = sc->sc_rb.rb_ntbuf; 587 588 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 589 return; 590 591 bix = sc->sc_rb.rb_tdhead; 592 593 for (;;) { 594 IFQ_DEQUEUE(&ifp->if_snd, m); 595 if (m == 0) 596 break; 597 598 /* 599 * If BPF is listening on this interface, let it see the 600 * packet before we commit it to the wire. 601 */ 602 bpf_mtap(ifp, m, BPF_D_OUT); 603 604 /* 605 * Copy the mbuf chain into the transmit buffer. 606 */ 607 len = be_put(sc, bix, m); 608 609 /* 610 * Initialize transmit registers and start transmission 611 */ 612 txd[bix].xd_flags = QEC_XD_OWN | QEC_XD_SOP | QEC_XD_EOP | 613 (len & QEC_XD_LENGTH); 614 bus_space_write_4(sc->sc_bustag, sc->sc_cr, 615 BE_CRI_CTRL, BE_CR_CTRL_TWAKEUP); 616 617 if (++bix == QEC_XD_RING_MAXSIZE) 618 bix = 0; 619 620 if (++sc->sc_rb.rb_td_nbusy == ntbuf) { 621 ifp->if_flags |= IFF_OACTIVE; 622 break; 623 } 624 } 625 626 sc->sc_rb.rb_tdhead = bix; 627 } 628 629 void 630 bestop(struct ifnet *ifp, int disable) 631 { 632 struct be_softc *sc = ifp->if_softc; 633 634 callout_stop(&sc->sc_tick_ch); 635 636 /* Down the MII. */ 637 mii_down(&sc->sc_mii); 638 (void)be_intphy_service(sc, &sc->sc_mii, MII_DOWN); 639 640 behwreset(sc); 641 } 642 643 void 644 behwreset(struct be_softc *sc) 645 { 646 int n; 647 bus_space_tag_t t = sc->sc_bustag; 648 bus_space_handle_t br = sc->sc_br; 649 650 /* Stop the transmitter */ 651 bus_space_write_4(t, br, BE_BRI_TXCFG, 0); 652 for (n = 32; n > 0; n--) { 653 if (bus_space_read_4(t, br, BE_BRI_TXCFG) == 0) 654 break; 655 DELAY(20); 656 } 657 658 /* Stop the receiver */ 659 bus_space_write_4(t, br, BE_BRI_RXCFG, 0); 660 for (n = 32; n > 0; n--) { 661 if (bus_space_read_4(t, br, BE_BRI_RXCFG) == 0) 662 break; 663 DELAY(20); 664 } 665 } 666 667 /* 668 * Reset interface. 669 */ 670 void 671 bereset(struct be_softc *sc) 672 { 673 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 674 int s; 675 676 s = splnet(); 677 behwreset(sc); 678 if ((sc->sc_ethercom.ec_if.if_flags & IFF_UP) != 0) 679 beinit(ifp); 680 splx(s); 681 } 682 683 void 684 bewatchdog(struct ifnet *ifp) 685 { 686 struct be_softc *sc = ifp->if_softc; 687 688 log(LOG_ERR, "%s: device timeout\n", device_xname(sc->sc_dev)); 689 ++sc->sc_ethercom.ec_if.if_oerrors; 690 691 bereset(sc); 692 } 693 694 int 695 beintr(void *arg) 696 { 697 struct be_softc *sc = arg; 698 bus_space_tag_t t = sc->sc_bustag; 699 uint32_t whyq, whyb, whyc; 700 int r = 0; 701 702 /* Read QEC status, channel status and BE status */ 703 whyq = bus_space_read_4(t, sc->sc_qr, QEC_QRI_STAT); 704 whyc = bus_space_read_4(t, sc->sc_cr, BE_CRI_STAT); 705 whyb = bus_space_read_4(t, sc->sc_br, BE_BRI_STAT); 706 707 if (whyq & QEC_STAT_BM) 708 r |= beeint(sc, whyb); 709 710 if (whyq & QEC_STAT_ER) 711 r |= beqint(sc, whyc); 712 713 if (whyq & QEC_STAT_TX && whyc & BE_CR_STAT_TXIRQ) 714 r |= betint(sc); 715 716 if (whyq & QEC_STAT_RX && whyc & BE_CR_STAT_RXIRQ) 717 r |= berint(sc); 718 719 return r; 720 } 721 722 /* 723 * QEC Interrupt. 724 */ 725 int 726 beqint(struct be_softc *sc, uint32_t why) 727 { 728 device_t self = sc->sc_dev; 729 int r = 0, rst = 0; 730 731 if (why & BE_CR_STAT_TXIRQ) 732 r |= 1; 733 if (why & BE_CR_STAT_RXIRQ) 734 r |= 1; 735 736 if (why & BE_CR_STAT_BERROR) { 737 r |= 1; 738 rst = 1; 739 aprint_error_dev(self, "bigmac error\n"); 740 } 741 742 if (why & BE_CR_STAT_TXDERR) { 743 r |= 1; 744 rst = 1; 745 aprint_error_dev(self, "bogus tx descriptor\n"); 746 } 747 748 if (why & (BE_CR_STAT_TXLERR | BE_CR_STAT_TXPERR | BE_CR_STAT_TXSERR)) { 749 r |= 1; 750 rst = 1; 751 aprint_error_dev(self, "tx DMA error ( "); 752 if (why & BE_CR_STAT_TXLERR) 753 printf("Late "); 754 if (why & BE_CR_STAT_TXPERR) 755 printf("Parity "); 756 if (why & BE_CR_STAT_TXSERR) 757 printf("Generic "); 758 printf(")\n"); 759 } 760 761 if (why & BE_CR_STAT_RXDROP) { 762 r |= 1; 763 rst = 1; 764 aprint_error_dev(self, "out of rx descriptors\n"); 765 } 766 767 if (why & BE_CR_STAT_RXSMALL) { 768 r |= 1; 769 rst = 1; 770 aprint_error_dev(self, "rx descriptor too small\n"); 771 } 772 773 if (why & (BE_CR_STAT_RXLERR | BE_CR_STAT_RXPERR | BE_CR_STAT_RXSERR)) { 774 r |= 1; 775 rst = 1; 776 aprint_error_dev(self, "rx DMA error ( "); 777 if (why & BE_CR_STAT_RXLERR) 778 printf("Late "); 779 if (why & BE_CR_STAT_RXPERR) 780 printf("Parity "); 781 if (why & BE_CR_STAT_RXSERR) 782 printf("Generic "); 783 printf(")\n"); 784 } 785 786 if (!r) { 787 rst = 1; 788 aprint_error_dev(self, "unexpected error interrupt %08x\n", 789 why); 790 } 791 792 if (rst) { 793 printf("%s: resetting\n", device_xname(self)); 794 bereset(sc); 795 } 796 797 return r; 798 } 799 800 /* 801 * Error interrupt. 802 */ 803 int 804 beeint(struct be_softc *sc, uint32_t why) 805 { 806 device_t self = sc->sc_dev; 807 int r = 0, rst = 0; 808 809 if (why & BE_BR_STAT_RFIFOVF) { 810 r |= 1; 811 rst = 1; 812 aprint_error_dev(self, "receive fifo overrun\n"); 813 } 814 if (why & BE_BR_STAT_TFIFO_UND) { 815 r |= 1; 816 rst = 1; 817 aprint_error_dev(self, "transmit fifo underrun\n"); 818 } 819 if (why & BE_BR_STAT_MAXPKTERR) { 820 r |= 1; 821 rst = 1; 822 aprint_error_dev(self, "max packet size error\n"); 823 } 824 825 if (!r) { 826 rst = 1; 827 aprint_error_dev(self, "unexpected error interrupt %08x\n", 828 why); 829 } 830 831 if (rst) { 832 printf("%s: resetting\n", device_xname(self)); 833 bereset(sc); 834 } 835 836 return r; 837 } 838 839 /* 840 * Transmit interrupt. 841 */ 842 int 843 betint(struct be_softc *sc) 844 { 845 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 846 bus_space_tag_t t = sc->sc_bustag; 847 bus_space_handle_t br = sc->sc_br; 848 unsigned int bix, txflags; 849 850 /* 851 * Unload collision counters 852 */ 853 ifp->if_collisions += 854 bus_space_read_4(t, br, BE_BRI_NCCNT) + 855 bus_space_read_4(t, br, BE_BRI_FCCNT) + 856 bus_space_read_4(t, br, BE_BRI_EXCNT) + 857 bus_space_read_4(t, br, BE_BRI_LTCNT); 858 859 /* 860 * the clear the hardware counters 861 */ 862 bus_space_write_4(t, br, BE_BRI_NCCNT, 0); 863 bus_space_write_4(t, br, BE_BRI_FCCNT, 0); 864 bus_space_write_4(t, br, BE_BRI_EXCNT, 0); 865 bus_space_write_4(t, br, BE_BRI_LTCNT, 0); 866 867 bix = sc->sc_rb.rb_tdtail; 868 869 for (;;) { 870 if (sc->sc_rb.rb_td_nbusy <= 0) 871 break; 872 873 txflags = sc->sc_rb.rb_txd[bix].xd_flags; 874 875 if (txflags & QEC_XD_OWN) 876 break; 877 878 ifp->if_flags &= ~IFF_OACTIVE; 879 ifp->if_opackets++; 880 881 if (++bix == QEC_XD_RING_MAXSIZE) 882 bix = 0; 883 884 --sc->sc_rb.rb_td_nbusy; 885 } 886 887 sc->sc_rb.rb_tdtail = bix; 888 889 bestart(ifp); 890 891 if (sc->sc_rb.rb_td_nbusy == 0) 892 ifp->if_timer = 0; 893 894 return 1; 895 } 896 897 /* 898 * Receive interrupt. 899 */ 900 int 901 berint(struct be_softc *sc) 902 { 903 struct qec_xd *xd = sc->sc_rb.rb_rxd; 904 unsigned int bix, len; 905 unsigned int nrbuf = sc->sc_rb.rb_nrbuf; 906 907 bix = sc->sc_rb.rb_rdtail; 908 909 /* 910 * Process all buffers with valid data. 911 */ 912 for (;;) { 913 len = xd[bix].xd_flags; 914 if (len & QEC_XD_OWN) 915 break; 916 917 len &= QEC_XD_LENGTH; 918 be_read(sc, bix, len); 919 920 /* ... */ 921 xd[(bix+nrbuf) % QEC_XD_RING_MAXSIZE].xd_flags = 922 QEC_XD_OWN | (BE_PKT_BUF_SZ & QEC_XD_LENGTH); 923 924 if (++bix == QEC_XD_RING_MAXSIZE) 925 bix = 0; 926 } 927 928 sc->sc_rb.rb_rdtail = bix; 929 930 return 1; 931 } 932 933 int 934 beioctl(struct ifnet *ifp, u_long cmd, void *data) 935 { 936 #ifdef BEDEBUG 937 struct be_softc *sc = ifp->if_softc; 938 #endif 939 struct ifaddr *ifa = data; 940 int s, error = 0; 941 942 s = splnet(); 943 944 switch (cmd) { 945 case SIOCINITIFADDR: 946 ifp->if_flags |= IFF_UP; 947 beinit(ifp); 948 switch (ifa->ifa_addr->sa_family) { 949 #ifdef INET 950 case AF_INET: 951 arp_ifinit(ifp, ifa); 952 break; 953 #endif /* INET */ 954 default: 955 break; 956 } 957 break; 958 959 case SIOCSIFFLAGS: 960 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 961 break; 962 /* XXX re-use ether_ioctl() */ 963 switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { 964 case IFF_RUNNING: 965 /* 966 * If interface is marked down and it is running, then 967 * stop it. 968 */ 969 bestop(ifp, 0); 970 ifp->if_flags &= ~IFF_RUNNING; 971 break; 972 case IFF_UP: 973 /* 974 * If interface is marked up and it is stopped, then 975 * start it. 976 */ 977 beinit(ifp); 978 break; 979 default: 980 /* 981 * Reset the interface to pick up changes in any other 982 * flags that affect hardware registers. 983 */ 984 bestop(ifp, 0); 985 beinit(ifp); 986 break; 987 } 988 #ifdef BEDEBUG 989 if (ifp->if_flags & IFF_DEBUG) 990 sc->sc_debug = 1; 991 else 992 sc->sc_debug = 0; 993 #endif 994 break; 995 996 default: 997 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 998 /* 999 * Multicast list has changed; set the hardware filter 1000 * accordingly. 1001 */ 1002 if (ifp->if_flags & IFF_RUNNING) 1003 error = beinit(ifp); 1004 else 1005 error = 0; 1006 } 1007 break; 1008 } 1009 splx(s); 1010 return error; 1011 } 1012 1013 1014 int 1015 beinit(struct ifnet *ifp) 1016 { 1017 struct be_softc *sc = ifp->if_softc; 1018 bus_space_tag_t t = sc->sc_bustag; 1019 bus_space_handle_t br = sc->sc_br; 1020 bus_space_handle_t cr = sc->sc_cr; 1021 struct qec_softc *qec = sc->sc_qec; 1022 uint32_t v; 1023 uint32_t qecaddr; 1024 uint8_t *ea; 1025 int rc, s; 1026 1027 s = splnet(); 1028 1029 qec_meminit(&sc->sc_rb, BE_PKT_BUF_SZ); 1030 1031 bestop(ifp, 1); 1032 1033 ea = sc->sc_enaddr; 1034 bus_space_write_4(t, br, BE_BRI_MACADDR0, (ea[0] << 8) | ea[1]); 1035 bus_space_write_4(t, br, BE_BRI_MACADDR1, (ea[2] << 8) | ea[3]); 1036 bus_space_write_4(t, br, BE_BRI_MACADDR2, (ea[4] << 8) | ea[5]); 1037 1038 /* Clear hash table */ 1039 bus_space_write_4(t, br, BE_BRI_HASHTAB0, 0); 1040 bus_space_write_4(t, br, BE_BRI_HASHTAB1, 0); 1041 bus_space_write_4(t, br, BE_BRI_HASHTAB2, 0); 1042 bus_space_write_4(t, br, BE_BRI_HASHTAB3, 0); 1043 1044 /* Re-initialize RX configuration */ 1045 v = BE_BR_RXCFG_FIFO; 1046 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1047 1048 be_mcreset(sc); 1049 1050 bus_space_write_4(t, br, BE_BRI_RANDSEED, 0xbd); 1051 1052 bus_space_write_4(t, br, 1053 BE_BRI_XIFCFG, BE_BR_XCFG_ODENABLE | BE_BR_XCFG_RESV); 1054 1055 bus_space_write_4(t, br, BE_BRI_JSIZE, 4); 1056 1057 /* 1058 * Turn off counter expiration interrupts as well as 1059 * 'gotframe' and 'sentframe' 1060 */ 1061 bus_space_write_4(t, br, BE_BRI_IMASK, 1062 BE_BR_IMASK_GOTFRAME | 1063 BE_BR_IMASK_RCNTEXP | 1064 BE_BR_IMASK_ACNTEXP | 1065 BE_BR_IMASK_CCNTEXP | 1066 BE_BR_IMASK_LCNTEXP | 1067 BE_BR_IMASK_CVCNTEXP | 1068 BE_BR_IMASK_SENTFRAME | 1069 BE_BR_IMASK_NCNTEXP | 1070 BE_BR_IMASK_ECNTEXP | 1071 BE_BR_IMASK_LCCNTEXP | 1072 BE_BR_IMASK_FCNTEXP | 1073 BE_BR_IMASK_DTIMEXP); 1074 1075 /* Channel registers: */ 1076 bus_space_write_4(t, cr, BE_CRI_RXDS, (uint32_t)sc->sc_rb.rb_rxddma); 1077 bus_space_write_4(t, cr, BE_CRI_TXDS, (uint32_t)sc->sc_rb.rb_txddma); 1078 1079 qecaddr = sc->sc_channel * qec->sc_msize; 1080 bus_space_write_4(t, cr, BE_CRI_RXWBUF, qecaddr); 1081 bus_space_write_4(t, cr, BE_CRI_RXRBUF, qecaddr); 1082 bus_space_write_4(t, cr, BE_CRI_TXWBUF, qecaddr + qec->sc_rsize); 1083 bus_space_write_4(t, cr, BE_CRI_TXRBUF, qecaddr + qec->sc_rsize); 1084 1085 bus_space_write_4(t, cr, BE_CRI_RIMASK, 0); 1086 bus_space_write_4(t, cr, BE_CRI_TIMASK, 0); 1087 bus_space_write_4(t, cr, BE_CRI_QMASK, 0); 1088 bus_space_write_4(t, cr, BE_CRI_BMASK, 0); 1089 bus_space_write_4(t, cr, BE_CRI_CCNT, 0); 1090 1091 /* Set max packet length */ 1092 v = ETHER_MAX_LEN; 1093 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) 1094 v += ETHER_VLAN_ENCAP_LEN; 1095 bus_space_write_4(t, br, BE_BRI_RXMAX, v); 1096 bus_space_write_4(t, br, BE_BRI_TXMAX, v); 1097 1098 /* Enable transmitter */ 1099 bus_space_write_4(t, br, 1100 BE_BRI_TXCFG, BE_BR_TXCFG_FIFO | BE_BR_TXCFG_ENABLE); 1101 1102 /* Enable receiver */ 1103 v = bus_space_read_4(t, br, BE_BRI_RXCFG); 1104 v |= BE_BR_RXCFG_FIFO | BE_BR_RXCFG_ENABLE; 1105 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1106 1107 if ((rc = be_ifmedia_upd(ifp)) != 0) 1108 goto out; 1109 1110 ifp->if_flags |= IFF_RUNNING; 1111 ifp->if_flags &= ~IFF_OACTIVE; 1112 1113 callout_reset(&sc->sc_tick_ch, hz, be_tick, sc); 1114 1115 splx(s); 1116 return 0; 1117 out: 1118 splx(s); 1119 return rc; 1120 } 1121 1122 void 1123 be_mcreset(struct be_softc *sc) 1124 { 1125 struct ethercom *ec = &sc->sc_ethercom; 1126 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1127 bus_space_tag_t t = sc->sc_bustag; 1128 bus_space_handle_t br = sc->sc_br; 1129 uint32_t v; 1130 uint32_t crc; 1131 uint16_t hash[4]; 1132 struct ether_multi *enm; 1133 struct ether_multistep step; 1134 1135 if (ifp->if_flags & IFF_PROMISC) { 1136 v = bus_space_read_4(t, br, BE_BRI_RXCFG); 1137 v |= BE_BR_RXCFG_PMISC; 1138 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1139 return; 1140 } 1141 1142 if (ifp->if_flags & IFF_ALLMULTI) { 1143 hash[3] = hash[2] = hash[1] = hash[0] = 0xffff; 1144 goto chipit; 1145 } 1146 1147 hash[3] = hash[2] = hash[1] = hash[0] = 0; 1148 1149 ETHER_LOCK(ec); 1150 ETHER_FIRST_MULTI(step, ec, enm); 1151 while (enm != NULL) { 1152 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1153 /* 1154 * We must listen to a range of multicast 1155 * addresses. For now, just accept all 1156 * multicasts, rather than trying to set only 1157 * those filter bits needed to match the range. 1158 * (At this time, the only use of address 1159 * ranges is for IP multicast routing, for 1160 * which the range is big enough to require 1161 * all bits set.) 1162 */ 1163 hash[3] = hash[2] = hash[1] = hash[0] = 0xffff; 1164 ifp->if_flags |= IFF_ALLMULTI; 1165 ETHER_UNLOCK(ec); 1166 goto chipit; 1167 } 1168 1169 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 1170 /* Just want the 6 most significant bits. */ 1171 crc >>= 26; 1172 1173 hash[crc >> 4] |= 1 << (crc & 0xf); 1174 ETHER_NEXT_MULTI(step, enm); 1175 } 1176 ETHER_UNLOCK(ec); 1177 1178 ifp->if_flags &= ~IFF_ALLMULTI; 1179 1180 chipit: 1181 /* Enable the hash filter */ 1182 bus_space_write_4(t, br, BE_BRI_HASHTAB0, hash[0]); 1183 bus_space_write_4(t, br, BE_BRI_HASHTAB1, hash[1]); 1184 bus_space_write_4(t, br, BE_BRI_HASHTAB2, hash[2]); 1185 bus_space_write_4(t, br, BE_BRI_HASHTAB3, hash[3]); 1186 1187 v = bus_space_read_4(t, br, BE_BRI_RXCFG); 1188 v &= ~BE_BR_RXCFG_PMISC; 1189 v |= BE_BR_RXCFG_HENABLE; 1190 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1191 } 1192 1193 /* 1194 * Set the tcvr to an idle state 1195 */ 1196 void 1197 be_mii_sync(struct be_softc *sc) 1198 { 1199 bus_space_tag_t t = sc->sc_bustag; 1200 bus_space_handle_t tr = sc->sc_tr; 1201 int n = 32; 1202 1203 while (n--) { 1204 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, 1205 MGMT_PAL_INT_MDIO | MGMT_PAL_EXT_MDIO | MGMT_PAL_OENAB); 1206 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1207 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, 1208 MGMT_PAL_INT_MDIO | MGMT_PAL_EXT_MDIO | 1209 MGMT_PAL_OENAB | MGMT_PAL_DCLOCK); 1210 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1211 } 1212 } 1213 1214 void 1215 be_pal_gate(struct be_softc *sc, int phy) 1216 { 1217 bus_space_tag_t t = sc->sc_bustag; 1218 bus_space_handle_t tr = sc->sc_tr; 1219 uint32_t v; 1220 1221 be_mii_sync(sc); 1222 1223 v = ~(TCVR_PAL_EXTLBACK | TCVR_PAL_MSENSE | TCVR_PAL_LTENABLE); 1224 if (phy == BE_PHY_INTERNAL) 1225 v &= ~TCVR_PAL_SERIAL; 1226 1227 bus_space_write_4(t, tr, BE_TRI_TCVRPAL, v); 1228 (void)bus_space_read_4(t, tr, BE_TRI_TCVRPAL); 1229 } 1230 1231 static int 1232 be_tcvr_read_bit(struct be_softc *sc, int phy) 1233 { 1234 bus_space_tag_t t = sc->sc_bustag; 1235 bus_space_handle_t tr = sc->sc_tr; 1236 int ret; 1237 1238 if (phy == BE_PHY_INTERNAL) { 1239 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, MGMT_PAL_EXT_MDIO); 1240 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1241 bus_space_write_4(t, tr, 1242 BE_TRI_MGMTPAL, MGMT_PAL_EXT_MDIO | MGMT_PAL_DCLOCK); 1243 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1244 ret = (bus_space_read_4(t, tr, BE_TRI_MGMTPAL) & 1245 MGMT_PAL_INT_MDIO) >> MGMT_PAL_INT_MDIO_SHIFT; 1246 } else { 1247 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, MGMT_PAL_INT_MDIO); 1248 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1249 ret = (bus_space_read_4(t, tr, BE_TRI_MGMTPAL) & 1250 MGMT_PAL_EXT_MDIO) >> MGMT_PAL_EXT_MDIO_SHIFT; 1251 bus_space_write_4(t, tr, 1252 BE_TRI_MGMTPAL, MGMT_PAL_INT_MDIO | MGMT_PAL_DCLOCK); 1253 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1254 } 1255 1256 return ret; 1257 } 1258 1259 static void 1260 be_tcvr_write_bit(struct be_softc *sc, int phy, int bit) 1261 { 1262 bus_space_tag_t t = sc->sc_bustag; 1263 bus_space_handle_t tr = sc->sc_tr; 1264 uint32_t v; 1265 1266 if (phy == BE_PHY_INTERNAL) { 1267 v = ((bit & 1) << MGMT_PAL_INT_MDIO_SHIFT) | 1268 MGMT_PAL_OENAB | MGMT_PAL_EXT_MDIO; 1269 } else { 1270 v = ((bit & 1) << MGMT_PAL_EXT_MDIO_SHIFT) | 1271 MGMT_PAL_OENAB | MGMT_PAL_INT_MDIO; 1272 } 1273 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, v); 1274 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1275 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, v | MGMT_PAL_DCLOCK); 1276 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1277 } 1278 1279 static void 1280 be_mii_sendbits(struct be_softc *sc, int phy, uint32_t data, int nbits) 1281 { 1282 int i; 1283 1284 for (i = 1 << (nbits - 1); i != 0; i >>= 1) { 1285 be_tcvr_write_bit(sc, phy, (data & i) != 0); 1286 } 1287 } 1288 1289 static int 1290 be_mii_readreg(device_t self, int phy, int reg, uint16_t *val) 1291 { 1292 struct be_softc *sc = device_private(self); 1293 int i; 1294 uint16_t data = 0; 1295 1296 /* 1297 * Read the PHY register by manually driving the MII control lines. 1298 */ 1299 be_mii_sync(sc); 1300 be_mii_sendbits(sc, phy, MII_COMMAND_START, 2); 1301 be_mii_sendbits(sc, phy, MII_COMMAND_READ, 2); 1302 be_mii_sendbits(sc, phy, phy, 5); 1303 be_mii_sendbits(sc, phy, reg, 5); 1304 1305 (void)be_tcvr_read_bit(sc, phy); 1306 (void)be_tcvr_read_bit(sc, phy); 1307 1308 for (i = 15; i >= 0; i--) 1309 data |= (be_tcvr_read_bit(sc, phy) << i); 1310 1311 (void)be_tcvr_read_bit(sc, phy); 1312 (void)be_tcvr_read_bit(sc, phy); 1313 (void)be_tcvr_read_bit(sc, phy); 1314 1315 *val = data; 1316 return 0; 1317 } 1318 1319 int 1320 be_mii_writereg(device_t self, int phy, int reg, uint16_t val) 1321 { 1322 struct be_softc *sc = device_private(self); 1323 int i; 1324 1325 /* 1326 * Write the PHY register by manually driving the MII control lines. 1327 */ 1328 be_mii_sync(sc); 1329 be_mii_sendbits(sc, phy, MII_COMMAND_START, 2); 1330 be_mii_sendbits(sc, phy, MII_COMMAND_WRITE, 2); 1331 be_mii_sendbits(sc, phy, phy, 5); 1332 be_mii_sendbits(sc, phy, reg, 5); 1333 1334 be_tcvr_write_bit(sc, phy, 1); 1335 be_tcvr_write_bit(sc, phy, 0); 1336 1337 for (i = 15; i >= 0; i--) 1338 be_tcvr_write_bit(sc, phy, (val >> i) & 1); 1339 1340 return 0; 1341 } 1342 1343 int 1344 be_mii_reset(struct be_softc *sc, int phy) 1345 { 1346 device_t self = sc->sc_dev; 1347 int n; 1348 1349 be_mii_writereg(self, phy, MII_BMCR, BMCR_LOOP | BMCR_PDOWN | BMCR_ISO); 1350 be_mii_writereg(self, phy, MII_BMCR, BMCR_RESET); 1351 1352 for (n = 16; n >= 0; n--) { 1353 uint16_t bmcr; 1354 1355 be_mii_readreg(self, phy, MII_BMCR, &bmcr); 1356 if ((bmcr & BMCR_RESET) == 0) 1357 break; 1358 DELAY(20); 1359 } 1360 if (n == 0) { 1361 aprint_error_dev(self, "bmcr reset failed\n"); 1362 return EIO; 1363 } 1364 1365 return 0; 1366 } 1367 1368 void 1369 be_tick(void *arg) 1370 { 1371 struct be_softc *sc = arg; 1372 int s = splnet(); 1373 1374 mii_tick(&sc->sc_mii); 1375 (void)be_intphy_service(sc, &sc->sc_mii, MII_TICK); 1376 1377 splx(s); 1378 callout_reset(&sc->sc_tick_ch, hz, be_tick, sc); 1379 } 1380 1381 void 1382 be_mii_statchg(struct ifnet *ifp) 1383 { 1384 struct be_softc *sc = ifp->if_softc; 1385 bus_space_tag_t t = sc->sc_bustag; 1386 bus_space_handle_t br = sc->sc_br; 1387 uint instance; 1388 uint32_t v; 1389 1390 instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media); 1391 #ifdef DIAGNOSTIC 1392 if (instance > 1) 1393 panic("be_mii_statchg: instance %d out of range", instance); 1394 #endif 1395 1396 /* Update duplex mode in TX configuration */ 1397 v = bus_space_read_4(t, br, BE_BRI_TXCFG); 1398 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 1399 v |= BE_BR_TXCFG_FULLDPLX; 1400 else 1401 v &= ~BE_BR_TXCFG_FULLDPLX; 1402 bus_space_write_4(t, br, BE_BRI_TXCFG, v); 1403 1404 /* Change to appropriate gate in transceiver PAL */ 1405 be_pal_gate(sc, sc->sc_phys[instance]); 1406 } 1407 1408 /* 1409 * Get current media settings. 1410 */ 1411 void 1412 be_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1413 { 1414 struct be_softc *sc = ifp->if_softc; 1415 1416 mii_pollstat(&sc->sc_mii); 1417 (void)be_intphy_service(sc, &sc->sc_mii, MII_POLLSTAT); 1418 1419 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1420 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1421 } 1422 1423 /* 1424 * Set media options. 1425 */ 1426 int 1427 be_ifmedia_upd(struct ifnet *ifp) 1428 { 1429 struct be_softc *sc = ifp->if_softc; 1430 int error; 1431 1432 if ((error = mii_mediachg(&sc->sc_mii)) == ENXIO) 1433 error = 0; 1434 else if (error != 0) 1435 return error; 1436 1437 return be_intphy_service(sc, &sc->sc_mii, MII_MEDIACHG); 1438 } 1439 1440 /* 1441 * Service routine for our pseudo-MII internal transceiver. 1442 */ 1443 int 1444 be_intphy_service(struct be_softc *sc, struct mii_data *mii, int cmd) 1445 { 1446 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 1447 device_t self = sc->sc_dev; 1448 uint16_t bmcr, bmsr; 1449 int error; 1450 1451 switch (cmd) { 1452 case MII_POLLSTAT: 1453 /* 1454 * If we're not polling our PHY instance, just return. 1455 */ 1456 if (IFM_INST(ife->ifm_media) != sc->sc_mii_inst) 1457 return 0; 1458 1459 break; 1460 1461 case MII_MEDIACHG: 1462 1463 /* 1464 * If the media indicates a different PHY instance, 1465 * isolate ourselves. 1466 */ 1467 if (IFM_INST(ife->ifm_media) != sc->sc_mii_inst) { 1468 be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMCR, &bmcr); 1469 be_mii_writereg(self, 1470 BE_PHY_INTERNAL, MII_BMCR, bmcr | BMCR_ISO); 1471 sc->sc_mii_flags &= ~MIIF_HAVELINK; 1472 sc->sc_intphy_curspeed = 0; 1473 return 0; 1474 } 1475 1476 1477 if ((error = be_mii_reset(sc, BE_PHY_INTERNAL)) != 0) 1478 return error; 1479 1480 be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMCR, &bmcr); 1481 1482 /* 1483 * Select the new mode and take out of isolation 1484 */ 1485 if (IFM_SUBTYPE(ife->ifm_media) == IFM_100_TX) 1486 bmcr |= BMCR_S100; 1487 else if (IFM_SUBTYPE(ife->ifm_media) == IFM_10_T) 1488 bmcr &= ~BMCR_S100; 1489 else if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) { 1490 if ((sc->sc_mii_flags & MIIF_HAVELINK) != 0) { 1491 bmcr &= ~BMCR_S100; 1492 bmcr |= sc->sc_intphy_curspeed; 1493 } else { 1494 /* Keep isolated until link is up */ 1495 bmcr |= BMCR_ISO; 1496 sc->sc_mii_flags |= MIIF_DOINGAUTO; 1497 } 1498 } 1499 1500 if ((IFM_OPTIONS(ife->ifm_media) & IFM_FDX) != 0) 1501 bmcr |= BMCR_FDX; 1502 else 1503 bmcr &= ~BMCR_FDX; 1504 1505 be_mii_writereg(self, BE_PHY_INTERNAL, MII_BMCR, bmcr); 1506 break; 1507 1508 case MII_TICK: 1509 /* 1510 * If we're not currently selected, just return. 1511 */ 1512 if (IFM_INST(ife->ifm_media) != sc->sc_mii_inst) 1513 return 0; 1514 1515 /* Is the interface even up? */ 1516 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 1517 return 0; 1518 1519 /* Only used for automatic media selection */ 1520 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) 1521 break; 1522 1523 /* 1524 * Check link status; if we don't have a link, try another 1525 * speed. We can't detect duplex mode, so half-duplex is 1526 * what we have to settle for. 1527 */ 1528 1529 /* Read twice in case the register is latched */ 1530 be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMSR, &bmsr); 1531 be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMSR, &bmsr); 1532 1533 if ((bmsr & BMSR_LINK) != 0) { 1534 /* We have a carrier */ 1535 be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMCR, &bmcr); 1536 1537 if ((sc->sc_mii_flags & MIIF_DOINGAUTO) != 0) { 1538 be_mii_readreg(self, 1539 BE_PHY_INTERNAL, MII_BMCR, &bmcr); 1540 1541 sc->sc_mii_flags |= MIIF_HAVELINK; 1542 sc->sc_intphy_curspeed = (bmcr & BMCR_S100); 1543 sc->sc_mii_flags &= ~MIIF_DOINGAUTO; 1544 1545 bmcr &= ~BMCR_ISO; 1546 be_mii_writereg(self, 1547 BE_PHY_INTERNAL, MII_BMCR, bmcr); 1548 1549 printf("%s: link up at %s Mbps\n", 1550 device_xname(self), 1551 (bmcr & BMCR_S100) ? "100" : "10"); 1552 } 1553 break; 1554 } 1555 1556 if ((sc->sc_mii_flags & MIIF_DOINGAUTO) == 0) { 1557 sc->sc_mii_flags |= MIIF_DOINGAUTO; 1558 sc->sc_mii_flags &= ~MIIF_HAVELINK; 1559 sc->sc_intphy_curspeed = 0; 1560 printf("%s: link down\n", device_xname(self)); 1561 } 1562 1563 /* Only retry autonegotiation every 5 seconds. */ 1564 if (++sc->sc_mii_ticks < 5) 1565 return 0; 1566 1567 sc->sc_mii_ticks = 0; 1568 be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMCR, &bmcr); 1569 /* Just flip the fast speed bit */ 1570 bmcr ^= BMCR_S100; 1571 be_mii_writereg(self, BE_PHY_INTERNAL, MII_BMCR, bmcr); 1572 1573 break; 1574 1575 case MII_DOWN: 1576 /* Isolate this phy */ 1577 be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMCR, &bmcr); 1578 be_mii_writereg(self, 1579 BE_PHY_INTERNAL, MII_BMCR, bmcr | BMCR_ISO); 1580 return 0; 1581 } 1582 1583 /* Update the media status. */ 1584 be_intphy_status(sc); 1585 1586 /* Callback if something changed. */ 1587 if (sc->sc_mii_active != mii->mii_media_active || cmd == MII_MEDIACHG) { 1588 (*mii->mii_statchg)(mii->mii_ifp); 1589 sc->sc_mii_active = mii->mii_media_active; 1590 } 1591 return 0; 1592 } 1593 1594 /* 1595 * Determine status of internal transceiver 1596 */ 1597 void 1598 be_intphy_status(struct be_softc *sc) 1599 { 1600 struct mii_data *mii = &sc->sc_mii; 1601 device_t self = sc->sc_dev; 1602 int media_active, media_status; 1603 uint16_t bmcr, bmsr; 1604 1605 media_status = IFM_AVALID; 1606 media_active = 0; 1607 1608 /* 1609 * Internal transceiver; do the work here. 1610 */ 1611 be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMCR, &bmcr); 1612 1613 switch (bmcr & (BMCR_S100 | BMCR_FDX)) { 1614 case (BMCR_S100 | BMCR_FDX): 1615 media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 1616 break; 1617 case BMCR_S100: 1618 media_active = IFM_ETHER | IFM_100_TX | IFM_HDX; 1619 break; 1620 case BMCR_FDX: 1621 media_active = IFM_ETHER | IFM_10_T | IFM_FDX; 1622 break; 1623 case 0: 1624 media_active = IFM_ETHER | IFM_10_T | IFM_HDX; 1625 break; 1626 } 1627 1628 /* Read twice in case the register is latched */ 1629 be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMSR, &bmsr); 1630 be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMSR, &bmsr); 1631 if (bmsr & BMSR_LINK) 1632 media_status |= IFM_ACTIVE; 1633 1634 mii->mii_media_status = media_status; 1635 mii->mii_media_active = media_active; 1636 } 1637
Indexes created Tue Sep 30 11:09:46 GMT 2025