be.c revision 1.97
1 /* $NetBSD: be.c,v 1.97 2022/09/02 23:48:10 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Copyright (c) 1998 Theo de Raadt and Jason L. Wright. 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. The name of the authors may not be used to endorse or promote products 45 * derived from this software without specific prior written permission. 46 * 47 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR 48 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 49 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 50 * IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, 51 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 52 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 53 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 54 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 55 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 56 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 57 */ 58 59 #include <sys/cdefs.h> 60 __KERNEL_RCSID(0, "$NetBSD: be.c,v 1.97 2022/09/02 23:48:10 thorpej Exp $"); 61 62 #include "opt_ddb.h" 63 #include "opt_inet.h" 64 65 #include <sys/param.h> 66 #include <sys/systm.h> 67 #include <sys/callout.h> 68 #include <sys/kernel.h> 69 #include <sys/errno.h> 70 #include <sys/ioctl.h> 71 #include <sys/mbuf.h> 72 #include <sys/socket.h> 73 #include <sys/syslog.h> 74 #include <sys/device.h> 75 #include <sys/malloc.h> 76 77 #include <net/if.h> 78 #include <net/if_dl.h> 79 #include <net/if_types.h> 80 #include <net/if_media.h> 81 #include <net/if_ether.h> 82 #include <net/bpf.h> 83 84 #ifdef INET 85 #include <netinet/in.h> 86 #include <netinet/if_inarp.h> 87 #include <netinet/in_systm.h> 88 #include <netinet/in_var.h> 89 #include <netinet/ip.h> 90 #endif 91 92 #include <sys/bus.h> 93 #include <sys/intr.h> 94 #include <machine/autoconf.h> 95 96 #include <dev/mii/mii.h> 97 #include <dev/mii/miivar.h> 98 99 #include <dev/sbus/sbusvar.h> 100 #include <dev/sbus/qecreg.h> 101 #include <dev/sbus/qecvar.h> 102 #include <dev/sbus/bereg.h> 103 104 struct be_softc { 105 device_t sc_dev; 106 bus_space_tag_t sc_bustag; /* bus & DMA tags */ 107 bus_dma_tag_t sc_dmatag; 108 bus_dmamap_t sc_dmamap; 109 struct ethercom sc_ethercom; 110 /*struct ifmedia sc_ifmedia; -* interface media */ 111 struct mii_data sc_mii; /* MII media control */ 112 #define sc_media sc_mii.mii_media/* shorthand */ 113 int sc_phys[2]; /* MII instance -> phy */ 114 115 struct callout sc_tick_ch; 116 117 /* 118 * Some `mii_softc' items we need to emulate MII operation 119 * for our internal transceiver. 120 */ 121 int sc_mii_inst; /* instance of internal phy */ 122 int sc_mii_active; /* currently active medium */ 123 int sc_mii_ticks; /* tick counter */ 124 int sc_mii_flags; /* phy status flags */ 125 #define MIIF_HAVELINK 0x04000000 126 int sc_intphy_curspeed; /* Established link speed */ 127 128 struct qec_softc *sc_qec; /* QEC parent */ 129 130 bus_space_handle_t sc_qr; /* QEC registers */ 131 bus_space_handle_t sc_br; /* BE registers */ 132 bus_space_handle_t sc_cr; /* channel registers */ 133 bus_space_handle_t sc_tr; /* transceiver registers */ 134 135 u_int sc_rev; 136 137 int sc_channel; /* channel number */ 138 int sc_burst; 139 140 struct qec_ring sc_rb; /* Packet Ring Buffer */ 141 142 /* MAC address */ 143 uint8_t sc_enaddr[ETHER_ADDR_LEN]; 144 #ifdef BEDEBUG 145 int sc_debug; 146 #endif 147 }; 148 149 static int bematch(device_t, cfdata_t, void *); 150 static void beattach(device_t, device_t, void *); 151 152 static int beinit(struct ifnet *); 153 static void bestart(struct ifnet *); 154 static void bestop(struct ifnet *, int); 155 static void bewatchdog(struct ifnet *); 156 static int beioctl(struct ifnet *, u_long, void *); 157 static void bereset(struct be_softc *); 158 static void behwreset(struct be_softc *); 159 160 static int beintr(void *); 161 static int berint(struct be_softc *); 162 static int betint(struct be_softc *); 163 static int beqint(struct be_softc *, uint32_t); 164 static int beeint(struct be_softc *, uint32_t); 165 166 static void be_read(struct be_softc *, int, int); 167 static int be_put(struct be_softc *, int, struct mbuf *); 168 static struct mbuf *be_get(struct be_softc *, int, int); 169 170 static void be_pal_gate(struct be_softc *, int); 171 172 /* ifmedia callbacks */ 173 static void be_ifmedia_sts(struct ifnet *, struct ifmediareq *); 174 static int be_ifmedia_upd(struct ifnet *); 175 176 static void be_mcreset(struct be_softc *); 177 178 /* MII methods & callbacks */ 179 static int be_mii_readreg(device_t, int, int, uint16_t *); 180 static int be_mii_writereg(device_t, int, int, uint16_t); 181 static void be_mii_statchg(struct ifnet *); 182 183 /* MII helpers */ 184 static void be_mii_sync(struct be_softc *); 185 static void be_mii_sendbits(struct be_softc *, int, uint32_t, int); 186 static int be_mii_reset(struct be_softc *, int); 187 static int be_tcvr_read_bit(struct be_softc *, int); 188 static void be_tcvr_write_bit(struct be_softc *, int, int); 189 190 static void be_tick(void *); 191 #if 0 192 static void be_intphy_auto(struct be_softc *); 193 #endif 194 static void be_intphy_status(struct be_softc *); 195 static int be_intphy_service(struct be_softc *, struct mii_data *, int); 196 197 198 CFATTACH_DECL_NEW(be, sizeof(struct be_softc), 199 bematch, beattach, NULL, NULL); 200 201 int 202 bematch(device_t parent, cfdata_t cf, void *aux) 203 { 204 struct sbus_attach_args *sa = aux; 205 206 return strcmp(cf->cf_name, sa->sa_name) == 0; 207 } 208 209 void 210 beattach(device_t parent, device_t self, void *aux) 211 { 212 struct sbus_attach_args *sa = aux; 213 struct qec_softc *qec = device_private(parent); 214 struct be_softc *sc = device_private(self); 215 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 216 struct mii_data *mii = &sc->sc_mii; 217 struct mii_softc *child; 218 int node = sa->sa_node; 219 bus_dma_tag_t dmatag = sa->sa_dmatag; 220 bus_dma_segment_t seg; 221 bus_size_t size; 222 int instance; 223 int rseg, error; 224 uint32_t v; 225 226 sc->sc_dev = self; 227 228 if (sa->sa_nreg < 3) { 229 printf(": only %d register sets\n", sa->sa_nreg); 230 return; 231 } 232 233 if (bus_space_map(sa->sa_bustag, 234 (bus_addr_t)BUS_ADDR(sa->sa_reg[0].oa_space, sa->sa_reg[0].oa_base), 235 (bus_size_t)sa->sa_reg[0].oa_size, 236 0, &sc->sc_cr) != 0) { 237 printf(": cannot map registers\n"); 238 return; 239 } 240 241 if (bus_space_map(sa->sa_bustag, 242 (bus_addr_t)BUS_ADDR(sa->sa_reg[1].oa_space, sa->sa_reg[1].oa_base), 243 (bus_size_t)sa->sa_reg[1].oa_size, 244 0, &sc->sc_br) != 0) { 245 printf(": cannot map registers\n"); 246 return; 247 } 248 249 if (bus_space_map(sa->sa_bustag, 250 (bus_addr_t)BUS_ADDR(sa->sa_reg[2].oa_space, sa->sa_reg[2].oa_base), 251 (bus_size_t)sa->sa_reg[2].oa_size, 252 0, &sc->sc_tr) != 0) { 253 printf(": cannot map registers\n"); 254 return; 255 } 256 257 sc->sc_bustag = sa->sa_bustag; 258 sc->sc_qec = qec; 259 sc->sc_qr = qec->sc_regs; 260 261 sc->sc_rev = prom_getpropint(node, "board-version", -1); 262 printf(": rev %x,", sc->sc_rev); 263 264 callout_init(&sc->sc_tick_ch, 0); 265 266 sc->sc_channel = prom_getpropint(node, "channel#", -1); 267 if (sc->sc_channel == -1) 268 sc->sc_channel = 0; 269 270 sc->sc_burst = prom_getpropint(node, "burst-sizes", -1); 271 if (sc->sc_burst == -1) 272 sc->sc_burst = qec->sc_burst; 273 274 /* Clamp at parent's burst sizes */ 275 sc->sc_burst &= qec->sc_burst; 276 277 /* Establish interrupt handler */ 278 if (sa->sa_nintr) 279 (void)bus_intr_establish(sa->sa_bustag, sa->sa_pri, IPL_NET, 280 beintr, sc); 281 282 prom_getether(node, sc->sc_enaddr); 283 printf(" address %s\n", ether_sprintf(sc->sc_enaddr)); 284 285 /* 286 * Allocate descriptor ring and buffers. 287 */ 288 289 /* for now, allocate as many bufs as there are ring descriptors */ 290 sc->sc_rb.rb_ntbuf = QEC_XD_RING_MAXSIZE; 291 sc->sc_rb.rb_nrbuf = QEC_XD_RING_MAXSIZE; 292 293 size = 294 QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd) + 295 QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd) + 296 sc->sc_rb.rb_ntbuf * BE_PKT_BUF_SZ + 297 sc->sc_rb.rb_nrbuf * BE_PKT_BUF_SZ; 298 299 /* Get a DMA handle */ 300 if ((error = bus_dmamap_create(dmatag, size, 1, size, 0, 301 BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) { 302 aprint_error_dev(self, "DMA map create error %d\n", error); 303 return; 304 } 305 306 /* Allocate DMA buffer */ 307 if ((error = bus_dmamem_alloc(sa->sa_dmatag, size, 0, 0, 308 &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 309 aprint_error_dev(self, "DMA buffer alloc error %d\n", error); 310 return; 311 } 312 313 /* Map DMA memory in CPU addressable space */ 314 if ((error = bus_dmamem_map(sa->sa_dmatag, &seg, rseg, size, 315 &sc->sc_rb.rb_membase, BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) { 316 aprint_error_dev(self, "DMA buffer map error %d\n", error); 317 bus_dmamem_free(sa->sa_dmatag, &seg, rseg); 318 return; 319 } 320 321 /* Load the buffer */ 322 if ((error = bus_dmamap_load(dmatag, sc->sc_dmamap, 323 sc->sc_rb.rb_membase, size, NULL, BUS_DMA_NOWAIT)) != 0) { 324 aprint_error_dev(self, "DMA buffer map load error %d\n", error); 325 bus_dmamem_unmap(dmatag, sc->sc_rb.rb_membase, size); 326 bus_dmamem_free(dmatag, &seg, rseg); 327 return; 328 } 329 sc->sc_rb.rb_dmabase = sc->sc_dmamap->dm_segs[0].ds_addr; 330 331 /* 332 * Initialize our media structures and MII info. 333 */ 334 mii->mii_ifp = ifp; 335 mii->mii_readreg = be_mii_readreg; 336 mii->mii_writereg = be_mii_writereg; 337 mii->mii_statchg = be_mii_statchg; 338 339 sc->sc_ethercom.ec_mii = mii; 340 ifmedia_init(&mii->mii_media, 0, be_ifmedia_upd, be_ifmedia_sts); 341 342 /* 343 * Initialize transceiver and determine which PHY connection to use. 344 */ 345 be_mii_sync(sc); 346 v = bus_space_read_4(sc->sc_bustag, sc->sc_tr, BE_TRI_MGMTPAL); 347 348 instance = 0; 349 350 if ((v & MGMT_PAL_EXT_MDIO) != 0) { 351 352 mii_attach(self, mii, 0xffffffff, BE_PHY_EXTERNAL, 353 MII_OFFSET_ANY, 0); 354 355 child = LIST_FIRST(&mii->mii_phys); 356 if (child == NULL) { 357 /* No PHY attached */ 358 ifmedia_add(&sc->sc_media, 359 IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, instance), 360 0, NULL); 361 ifmedia_set(&sc->sc_media, 362 IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, instance)); 363 } else { 364 /* 365 * Note: we support just one PHY on the external 366 * MII connector. 367 */ 368 #ifdef DIAGNOSTIC 369 if (LIST_NEXT(child, mii_list) != NULL) { 370 aprint_error_dev(self, 371 "spurious MII device %s attached\n", 372 device_xname(child->mii_dev)); 373 } 374 #endif 375 if (child->mii_phy != BE_PHY_EXTERNAL || 376 child->mii_inst > 0) { 377 aprint_error_dev(self, 378 "cannot accommodate MII device %s" 379 " at phy %d, instance %d\n", 380 device_xname(child->mii_dev), 381 child->mii_phy, child->mii_inst); 382 } else { 383 sc->sc_phys[instance] = child->mii_phy; 384 } 385 386 /* 387 * XXX - we can really do the following ONLY if the 388 * phy indeed has the auto negotiation capability!! 389 */ 390 ifmedia_set(&sc->sc_media, 391 IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, instance)); 392 393 /* Mark our current media setting */ 394 be_pal_gate(sc, BE_PHY_EXTERNAL); 395 instance++; 396 } 397 398 } 399 400 if ((v & MGMT_PAL_INT_MDIO) != 0) { 401 /* 402 * The be internal phy looks vaguely like MII hardware, 403 * but not enough to be able to use the MII device 404 * layer. Hence, we have to take care of media selection 405 * ourselves. 406 */ 407 408 sc->sc_mii_inst = instance; 409 sc->sc_phys[instance] = BE_PHY_INTERNAL; 410 411 /* Use `ifm_data' to store BMCR bits */ 412 ifmedia_add(&sc->sc_media, 413 IFM_MAKEWORD(IFM_ETHER, IFM_10_T, 0, instance), 414 0, NULL); 415 ifmedia_add(&sc->sc_media, 416 IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, 0, instance), 417 BMCR_S100, NULL); 418 ifmedia_add(&sc->sc_media, 419 IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, instance), 420 0, NULL); 421 422 printf("on-board transceiver at %s: 10baseT, 100baseTX, auto\n", 423 device_xname(self)); 424 425 be_mii_reset(sc, BE_PHY_INTERNAL); 426 /* Only set default medium here if there's no external PHY */ 427 if (instance == 0) { 428 be_pal_gate(sc, BE_PHY_INTERNAL); 429 ifmedia_set(&sc->sc_media, 430 IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, instance)); 431 } else 432 be_mii_writereg(self, 433 BE_PHY_INTERNAL, MII_BMCR, BMCR_ISO); 434 } 435 436 memcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 437 ifp->if_softc = sc; 438 ifp->if_start = bestart; 439 ifp->if_ioctl = beioctl; 440 ifp->if_watchdog = bewatchdog; 441 ifp->if_init = beinit; 442 ifp->if_stop = bestop; 443 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 444 IFQ_SET_READY(&ifp->if_snd); 445 446 /* claim 802.1q capability */ 447 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 448 449 /* Attach the interface. */ 450 if_attach(ifp); 451 ether_ifattach(ifp, sc->sc_enaddr); 452 } 453 454 455 /* 456 * Routine to copy from mbuf chain to transmit buffer in 457 * network buffer memory. 458 */ 459 static inline int 460 be_put(struct be_softc *sc, int idx, struct mbuf *m) 461 { 462 struct mbuf *n; 463 int len, tlen = 0, boff = 0; 464 uint8_t *bp; 465 466 bp = sc->sc_rb.rb_txbuf + (idx % sc->sc_rb.rb_ntbuf) * BE_PKT_BUF_SZ; 467 468 for (; m; m = n) { 469 len = m->m_len; 470 if (len == 0) { 471 n = m_free(m); 472 continue; 473 } 474 memcpy(bp + boff, mtod(m, void *), len); 475 boff += len; 476 tlen += len; 477 n = m_free(m); 478 } 479 return tlen; 480 } 481 482 /* 483 * Pull data off an interface. 484 * Len is the length of data, with local net header stripped. 485 * We copy the data into mbufs. When full cluster sized units are present, 486 * we copy into clusters. 487 */ 488 static inline struct mbuf * 489 be_get(struct be_softc *sc, int idx, int totlen) 490 { 491 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 492 struct mbuf *m; 493 struct mbuf *top, **mp; 494 int len, pad, boff = 0; 495 uint8_t *bp; 496 497 bp = sc->sc_rb.rb_rxbuf + (idx % sc->sc_rb.rb_nrbuf) * BE_PKT_BUF_SZ; 498 499 MGETHDR(m, M_DONTWAIT, MT_DATA); 500 if (m == NULL) 501 return (NULL); 502 m_set_rcvif(m, ifp); 503 m->m_pkthdr.len = totlen; 504 505 pad = ALIGN(sizeof(struct ether_header)) - sizeof(struct ether_header); 506 m->m_data += pad; 507 len = MHLEN - pad; 508 top = NULL; 509 mp = ⊤ 510 511 while (totlen > 0) { 512 if (top) { 513 MGET(m, M_DONTWAIT, MT_DATA); 514 if (m == NULL) { 515 m_freem(top); 516 return (NULL); 517 } 518 len = MLEN; 519 } 520 if (top && totlen >= MINCLSIZE) { 521 MCLGET(m, M_DONTWAIT); 522 if (m->m_flags & M_EXT) 523 len = MCLBYTES; 524 } 525 m->m_len = len = uimin(totlen, len); 526 memcpy(mtod(m, void *), bp + boff, len); 527 boff += len; 528 totlen -= len; 529 *mp = m; 530 mp = &m->m_next; 531 } 532 533 return top; 534 } 535 536 /* 537 * Pass a packet to the higher levels. 538 */ 539 static inline void 540 be_read(struct be_softc *sc, int idx, int len) 541 { 542 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 543 struct mbuf *m; 544 545 if (len <= sizeof(struct ether_header) || 546 len > ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN) { 547 #ifdef BEDEBUG 548 if (sc->sc_debug) 549 printf("%s: invalid packet size %d; dropping\n", 550 ifp->if_xname, len); 551 #endif 552 if_statinc(ifp, if_ierrors); 553 return; 554 } 555 556 /* 557 * Pull packet off interface. 558 */ 559 m = be_get(sc, idx, len); 560 if (m == NULL) { 561 if_statinc(ifp, if_ierrors); 562 return; 563 } 564 565 /* Pass the packet up. */ 566 if_percpuq_enqueue(ifp->if_percpuq, m); 567 } 568 569 /* 570 * Start output on interface. 571 * We make an assumption here: 572 * 1) that the current priority is set to splnet _before_ this code 573 * is called *and* is returned to the appropriate priority after 574 * return 575 */ 576 void 577 bestart(struct ifnet *ifp) 578 { 579 struct be_softc *sc = ifp->if_softc; 580 struct qec_xd *txd = sc->sc_rb.rb_txd; 581 struct mbuf *m; 582 unsigned int bix, len; 583 unsigned int ntbuf = sc->sc_rb.rb_ntbuf; 584 585 if ((ifp->if_flags & IFF_RUNNING) != IFF_RUNNING) 586 return; 587 588 bix = sc->sc_rb.rb_tdhead; 589 590 while (sc->sc_rb.rb_td_nbusy < ntbuf) { 591 IFQ_DEQUEUE(&ifp->if_snd, m); 592 if (m == 0) 593 break; 594 595 /* 596 * If BPF is listening on this interface, let it see the 597 * packet before we commit it to the wire. 598 */ 599 bpf_mtap(ifp, m, BPF_D_OUT); 600 601 /* 602 * Copy the mbuf chain into the transmit buffer. 603 */ 604 len = be_put(sc, bix, m); 605 606 /* 607 * Initialize transmit registers and start transmission 608 */ 609 txd[bix].xd_flags = QEC_XD_OWN | QEC_XD_SOP | QEC_XD_EOP | 610 (len & QEC_XD_LENGTH); 611 bus_space_write_4(sc->sc_bustag, sc->sc_cr, 612 BE_CRI_CTRL, BE_CR_CTRL_TWAKEUP); 613 614 if (++bix == QEC_XD_RING_MAXSIZE) 615 bix = 0; 616 617 sc->sc_rb.rb_td_nbusy++; 618 } 619 620 sc->sc_rb.rb_tdhead = bix; 621 } 622 623 void 624 bestop(struct ifnet *ifp, int disable) 625 { 626 struct be_softc *sc = ifp->if_softc; 627 628 callout_stop(&sc->sc_tick_ch); 629 630 /* Down the MII. */ 631 mii_down(&sc->sc_mii); 632 (void)be_intphy_service(sc, &sc->sc_mii, MII_DOWN); 633 634 behwreset(sc); 635 } 636 637 void 638 behwreset(struct be_softc *sc) 639 { 640 int n; 641 bus_space_tag_t t = sc->sc_bustag; 642 bus_space_handle_t br = sc->sc_br; 643 644 /* Stop the transmitter */ 645 bus_space_write_4(t, br, BE_BRI_TXCFG, 0); 646 for (n = 32; n > 0; n--) { 647 if (bus_space_read_4(t, br, BE_BRI_TXCFG) == 0) 648 break; 649 DELAY(20); 650 } 651 652 /* Stop the receiver */ 653 bus_space_write_4(t, br, BE_BRI_RXCFG, 0); 654 for (n = 32; n > 0; n--) { 655 if (bus_space_read_4(t, br, BE_BRI_RXCFG) == 0) 656 break; 657 DELAY(20); 658 } 659 } 660 661 /* 662 * Reset interface. 663 */ 664 void 665 bereset(struct be_softc *sc) 666 { 667 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 668 int s; 669 670 s = splnet(); 671 behwreset(sc); 672 if ((sc->sc_ethercom.ec_if.if_flags & IFF_UP) != 0) 673 beinit(ifp); 674 splx(s); 675 } 676 677 void 678 bewatchdog(struct ifnet *ifp) 679 { 680 struct be_softc *sc = ifp->if_softc; 681 682 log(LOG_ERR, "%s: device timeout\n", device_xname(sc->sc_dev)); 683 if_statinc(ifp, if_oerrors); 684 685 bereset(sc); 686 } 687 688 int 689 beintr(void *arg) 690 { 691 struct be_softc *sc = arg; 692 bus_space_tag_t t = sc->sc_bustag; 693 uint32_t whyq, whyb, whyc; 694 int r = 0; 695 696 /* Read QEC status, channel status and BE status */ 697 whyq = bus_space_read_4(t, sc->sc_qr, QEC_QRI_STAT); 698 whyc = bus_space_read_4(t, sc->sc_cr, BE_CRI_STAT); 699 whyb = bus_space_read_4(t, sc->sc_br, BE_BRI_STAT); 700 701 if (whyq & QEC_STAT_BM) 702 r |= beeint(sc, whyb); 703 704 if (whyq & QEC_STAT_ER) 705 r |= beqint(sc, whyc); 706 707 if (whyq & QEC_STAT_TX && whyc & BE_CR_STAT_TXIRQ) 708 r |= betint(sc); 709 710 if (whyq & QEC_STAT_RX && whyc & BE_CR_STAT_RXIRQ) 711 r |= berint(sc); 712 713 return r; 714 } 715 716 /* 717 * QEC Interrupt. 718 */ 719 int 720 beqint(struct be_softc *sc, uint32_t why) 721 { 722 device_t self = sc->sc_dev; 723 int r = 0, rst = 0; 724 725 if (why & BE_CR_STAT_TXIRQ) 726 r |= 1; 727 if (why & BE_CR_STAT_RXIRQ) 728 r |= 1; 729 730 if (why & BE_CR_STAT_BERROR) { 731 r |= 1; 732 rst = 1; 733 aprint_error_dev(self, "bigmac error\n"); 734 } 735 736 if (why & BE_CR_STAT_TXDERR) { 737 r |= 1; 738 rst = 1; 739 aprint_error_dev(self, "bogus tx descriptor\n"); 740 } 741 742 if (why & (BE_CR_STAT_TXLERR | BE_CR_STAT_TXPERR | BE_CR_STAT_TXSERR)) { 743 r |= 1; 744 rst = 1; 745 aprint_error_dev(self, "tx DMA error ( "); 746 if (why & BE_CR_STAT_TXLERR) 747 printf("Late "); 748 if (why & BE_CR_STAT_TXPERR) 749 printf("Parity "); 750 if (why & BE_CR_STAT_TXSERR) 751 printf("Generic "); 752 printf(")\n"); 753 } 754 755 if (why & BE_CR_STAT_RXDROP) { 756 r |= 1; 757 rst = 1; 758 aprint_error_dev(self, "out of rx descriptors\n"); 759 } 760 761 if (why & BE_CR_STAT_RXSMALL) { 762 r |= 1; 763 rst = 1; 764 aprint_error_dev(self, "rx descriptor too small\n"); 765 } 766 767 if (why & (BE_CR_STAT_RXLERR | BE_CR_STAT_RXPERR | BE_CR_STAT_RXSERR)) { 768 r |= 1; 769 rst = 1; 770 aprint_error_dev(self, "rx DMA error ( "); 771 if (why & BE_CR_STAT_RXLERR) 772 printf("Late "); 773 if (why & BE_CR_STAT_RXPERR) 774 printf("Parity "); 775 if (why & BE_CR_STAT_RXSERR) 776 printf("Generic "); 777 printf(")\n"); 778 } 779 780 if (!r) { 781 rst = 1; 782 aprint_error_dev(self, "unexpected error interrupt %08x\n", 783 why); 784 } 785 786 if (rst) { 787 printf("%s: resetting\n", device_xname(self)); 788 bereset(sc); 789 } 790 791 return r; 792 } 793 794 /* 795 * Error interrupt. 796 */ 797 int 798 beeint(struct be_softc *sc, uint32_t why) 799 { 800 device_t self = sc->sc_dev; 801 int r = 0, rst = 0; 802 803 if (why & BE_BR_STAT_RFIFOVF) { 804 r |= 1; 805 rst = 1; 806 aprint_error_dev(self, "receive fifo overrun\n"); 807 } 808 if (why & BE_BR_STAT_TFIFO_UND) { 809 r |= 1; 810 rst = 1; 811 aprint_error_dev(self, "transmit fifo underrun\n"); 812 } 813 if (why & BE_BR_STAT_MAXPKTERR) { 814 r |= 1; 815 rst = 1; 816 aprint_error_dev(self, "max packet size error\n"); 817 } 818 819 if (!r) { 820 rst = 1; 821 aprint_error_dev(self, "unexpected error interrupt %08x\n", 822 why); 823 } 824 825 if (rst) { 826 printf("%s: resetting\n", device_xname(self)); 827 bereset(sc); 828 } 829 830 return r; 831 } 832 833 /* 834 * Transmit interrupt. 835 */ 836 int 837 betint(struct be_softc *sc) 838 { 839 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 840 bus_space_tag_t t = sc->sc_bustag; 841 bus_space_handle_t br = sc->sc_br; 842 unsigned int bix, txflags; 843 844 /* 845 * Unload collision counters 846 */ 847 if_statadd(ifp, if_collisions, 848 bus_space_read_4(t, br, BE_BRI_NCCNT) + 849 bus_space_read_4(t, br, BE_BRI_FCCNT) + 850 bus_space_read_4(t, br, BE_BRI_EXCNT) + 851 bus_space_read_4(t, br, BE_BRI_LTCNT)); 852 853 /* 854 * the clear the hardware counters 855 */ 856 bus_space_write_4(t, br, BE_BRI_NCCNT, 0); 857 bus_space_write_4(t, br, BE_BRI_FCCNT, 0); 858 bus_space_write_4(t, br, BE_BRI_EXCNT, 0); 859 bus_space_write_4(t, br, BE_BRI_LTCNT, 0); 860 861 bix = sc->sc_rb.rb_tdtail; 862 863 for (;;) { 864 if (sc->sc_rb.rb_td_nbusy <= 0) 865 break; 866 867 txflags = sc->sc_rb.rb_txd[bix].xd_flags; 868 869 if (txflags & QEC_XD_OWN) 870 break; 871 872 if_statinc(ifp, if_opackets); 873 874 if (++bix == QEC_XD_RING_MAXSIZE) 875 bix = 0; 876 877 --sc->sc_rb.rb_td_nbusy; 878 } 879 880 sc->sc_rb.rb_tdtail = bix; 881 882 bestart(ifp); 883 884 if (sc->sc_rb.rb_td_nbusy == 0) 885 ifp->if_timer = 0; 886 887 return 1; 888 } 889 890 /* 891 * Receive interrupt. 892 */ 893 int 894 berint(struct be_softc *sc) 895 { 896 struct qec_xd *xd = sc->sc_rb.rb_rxd; 897 unsigned int bix, len; 898 unsigned int nrbuf = sc->sc_rb.rb_nrbuf; 899 900 bix = sc->sc_rb.rb_rdtail; 901 902 /* 903 * Process all buffers with valid data. 904 */ 905 for (;;) { 906 len = xd[bix].xd_flags; 907 if (len & QEC_XD_OWN) 908 break; 909 910 len &= QEC_XD_LENGTH; 911 be_read(sc, bix, len); 912 913 /* ... */ 914 xd[(bix+nrbuf) % QEC_XD_RING_MAXSIZE].xd_flags = 915 QEC_XD_OWN | (BE_PKT_BUF_SZ & QEC_XD_LENGTH); 916 917 if (++bix == QEC_XD_RING_MAXSIZE) 918 bix = 0; 919 } 920 921 sc->sc_rb.rb_rdtail = bix; 922 923 return 1; 924 } 925 926 int 927 beioctl(struct ifnet *ifp, u_long cmd, void *data) 928 { 929 #ifdef BEDEBUG 930 struct be_softc *sc = ifp->if_softc; 931 #endif 932 struct ifaddr *ifa = data; 933 int s, error = 0; 934 935 s = splnet(); 936 937 switch (cmd) { 938 case SIOCINITIFADDR: 939 ifp->if_flags |= IFF_UP; 940 beinit(ifp); 941 switch (ifa->ifa_addr->sa_family) { 942 #ifdef INET 943 case AF_INET: 944 arp_ifinit(ifp, ifa); 945 break; 946 #endif /* INET */ 947 default: 948 break; 949 } 950 break; 951 952 case SIOCSIFFLAGS: 953 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 954 break; 955 /* XXX re-use ether_ioctl() */ 956 switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { 957 case IFF_RUNNING: 958 /* 959 * If interface is marked down and it is running, then 960 * stop it. 961 */ 962 bestop(ifp, 0); 963 ifp->if_flags &= ~IFF_RUNNING; 964 break; 965 case IFF_UP: 966 /* 967 * If interface is marked up and it is stopped, then 968 * start it. 969 */ 970 beinit(ifp); 971 break; 972 default: 973 /* 974 * Reset the interface to pick up changes in any other 975 * flags that affect hardware registers. 976 */ 977 bestop(ifp, 0); 978 beinit(ifp); 979 break; 980 } 981 #ifdef BEDEBUG 982 if (ifp->if_flags & IFF_DEBUG) 983 sc->sc_debug = 1; 984 else 985 sc->sc_debug = 0; 986 #endif 987 break; 988 989 default: 990 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 991 /* 992 * Multicast list has changed; set the hardware filter 993 * accordingly. 994 */ 995 if (ifp->if_flags & IFF_RUNNING) 996 error = beinit(ifp); 997 else 998 error = 0; 999 } 1000 break; 1001 } 1002 splx(s); 1003 return error; 1004 } 1005 1006 1007 int 1008 beinit(struct ifnet *ifp) 1009 { 1010 struct be_softc *sc = ifp->if_softc; 1011 bus_space_tag_t t = sc->sc_bustag; 1012 bus_space_handle_t br = sc->sc_br; 1013 bus_space_handle_t cr = sc->sc_cr; 1014 struct qec_softc *qec = sc->sc_qec; 1015 uint32_t v; 1016 uint32_t qecaddr; 1017 uint8_t *ea; 1018 int rc, s; 1019 1020 s = splnet(); 1021 1022 qec_meminit(&sc->sc_rb, BE_PKT_BUF_SZ); 1023 1024 bestop(ifp, 1); 1025 1026 ea = sc->sc_enaddr; 1027 bus_space_write_4(t, br, BE_BRI_MACADDR0, (ea[0] << 8) | ea[1]); 1028 bus_space_write_4(t, br, BE_BRI_MACADDR1, (ea[2] << 8) | ea[3]); 1029 bus_space_write_4(t, br, BE_BRI_MACADDR2, (ea[4] << 8) | ea[5]); 1030 1031 /* Clear hash table */ 1032 bus_space_write_4(t, br, BE_BRI_HASHTAB0, 0); 1033 bus_space_write_4(t, br, BE_BRI_HASHTAB1, 0); 1034 bus_space_write_4(t, br, BE_BRI_HASHTAB2, 0); 1035 bus_space_write_4(t, br, BE_BRI_HASHTAB3, 0); 1036 1037 /* Re-initialize RX configuration */ 1038 v = BE_BR_RXCFG_FIFO; 1039 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1040 1041 be_mcreset(sc); 1042 1043 bus_space_write_4(t, br, BE_BRI_RANDSEED, 0xbd); 1044 1045 bus_space_write_4(t, br, 1046 BE_BRI_XIFCFG, BE_BR_XCFG_ODENABLE | BE_BR_XCFG_RESV); 1047 1048 bus_space_write_4(t, br, BE_BRI_JSIZE, 4); 1049 1050 /* 1051 * Turn off counter expiration interrupts as well as 1052 * 'gotframe' and 'sentframe' 1053 */ 1054 bus_space_write_4(t, br, BE_BRI_IMASK, 1055 BE_BR_IMASK_GOTFRAME | 1056 BE_BR_IMASK_RCNTEXP | 1057 BE_BR_IMASK_ACNTEXP | 1058 BE_BR_IMASK_CCNTEXP | 1059 BE_BR_IMASK_LCNTEXP | 1060 BE_BR_IMASK_CVCNTEXP | 1061 BE_BR_IMASK_SENTFRAME | 1062 BE_BR_IMASK_NCNTEXP | 1063 BE_BR_IMASK_ECNTEXP | 1064 BE_BR_IMASK_LCCNTEXP | 1065 BE_BR_IMASK_FCNTEXP | 1066 BE_BR_IMASK_DTIMEXP); 1067 1068 /* Channel registers: */ 1069 bus_space_write_4(t, cr, BE_CRI_RXDS, (uint32_t)sc->sc_rb.rb_rxddma); 1070 bus_space_write_4(t, cr, BE_CRI_TXDS, (uint32_t)sc->sc_rb.rb_txddma); 1071 1072 qecaddr = sc->sc_channel * qec->sc_msize; 1073 bus_space_write_4(t, cr, BE_CRI_RXWBUF, qecaddr); 1074 bus_space_write_4(t, cr, BE_CRI_RXRBUF, qecaddr); 1075 bus_space_write_4(t, cr, BE_CRI_TXWBUF, qecaddr + qec->sc_rsize); 1076 bus_space_write_4(t, cr, BE_CRI_TXRBUF, qecaddr + qec->sc_rsize); 1077 1078 bus_space_write_4(t, cr, BE_CRI_RIMASK, 0); 1079 bus_space_write_4(t, cr, BE_CRI_TIMASK, 0); 1080 bus_space_write_4(t, cr, BE_CRI_QMASK, 0); 1081 bus_space_write_4(t, cr, BE_CRI_BMASK, 0); 1082 bus_space_write_4(t, cr, BE_CRI_CCNT, 0); 1083 1084 /* Set max packet length */ 1085 v = ETHER_MAX_LEN; 1086 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) 1087 v += ETHER_VLAN_ENCAP_LEN; 1088 bus_space_write_4(t, br, BE_BRI_RXMAX, v); 1089 bus_space_write_4(t, br, BE_BRI_TXMAX, v); 1090 1091 /* Enable transmitter */ 1092 bus_space_write_4(t, br, 1093 BE_BRI_TXCFG, BE_BR_TXCFG_FIFO | BE_BR_TXCFG_ENABLE); 1094 1095 /* Enable receiver */ 1096 v = bus_space_read_4(t, br, BE_BRI_RXCFG); 1097 v |= BE_BR_RXCFG_FIFO | BE_BR_RXCFG_ENABLE; 1098 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1099 1100 if ((rc = be_ifmedia_upd(ifp)) != 0) 1101 goto out; 1102 1103 ifp->if_flags |= IFF_RUNNING; 1104 1105 callout_reset(&sc->sc_tick_ch, hz, be_tick, sc); 1106 1107 splx(s); 1108 return 0; 1109 out: 1110 splx(s); 1111 return rc; 1112 } 1113 1114 void 1115 be_mcreset(struct be_softc *sc) 1116 { 1117 struct ethercom *ec = &sc->sc_ethercom; 1118 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1119 bus_space_tag_t t = sc->sc_bustag; 1120 bus_space_handle_t br = sc->sc_br; 1121 uint32_t v; 1122 uint32_t crc; 1123 uint16_t hash[4]; 1124 struct ether_multi *enm; 1125 struct ether_multistep step; 1126 1127 if (ifp->if_flags & IFF_PROMISC) { 1128 v = bus_space_read_4(t, br, BE_BRI_RXCFG); 1129 v |= BE_BR_RXCFG_PMISC; 1130 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1131 return; 1132 } 1133 1134 if (ifp->if_flags & IFF_ALLMULTI) { 1135 hash[3] = hash[2] = hash[1] = hash[0] = 0xffff; 1136 goto chipit; 1137 } 1138 1139 hash[3] = hash[2] = hash[1] = hash[0] = 0; 1140 1141 ETHER_LOCK(ec); 1142 ETHER_FIRST_MULTI(step, ec, enm); 1143 while (enm != NULL) { 1144 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1145 /* 1146 * We must listen to a range of multicast 1147 * addresses. For now, just accept all 1148 * multicasts, rather than trying to set only 1149 * those filter bits needed to match the range. 1150 * (At this time, the only use of address 1151 * ranges is for IP multicast routing, for 1152 * which the range is big enough to require 1153 * all bits set.) 1154 */ 1155 hash[3] = hash[2] = hash[1] = hash[0] = 0xffff; 1156 ifp->if_flags |= IFF_ALLMULTI; 1157 ETHER_UNLOCK(ec); 1158 goto chipit; 1159 } 1160 1161 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 1162 /* Just want the 6 most significant bits. */ 1163 crc >>= 26; 1164 1165 hash[crc >> 4] |= 1 << (crc & 0xf); 1166 ETHER_NEXT_MULTI(step, enm); 1167 } 1168 ETHER_UNLOCK(ec); 1169 1170 ifp->if_flags &= ~IFF_ALLMULTI; 1171 1172 chipit: 1173 /* Enable the hash filter */ 1174 bus_space_write_4(t, br, BE_BRI_HASHTAB0, hash[0]); 1175 bus_space_write_4(t, br, BE_BRI_HASHTAB1, hash[1]); 1176 bus_space_write_4(t, br, BE_BRI_HASHTAB2, hash[2]); 1177 bus_space_write_4(t, br, BE_BRI_HASHTAB3, hash[3]); 1178 1179 v = bus_space_read_4(t, br, BE_BRI_RXCFG); 1180 v &= ~BE_BR_RXCFG_PMISC; 1181 v |= BE_BR_RXCFG_HENABLE; 1182 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1183 } 1184 1185 /* 1186 * Set the tcvr to an idle state 1187 */ 1188 void 1189 be_mii_sync(struct be_softc *sc) 1190 { 1191 bus_space_tag_t t = sc->sc_bustag; 1192 bus_space_handle_t tr = sc->sc_tr; 1193 int n = 32; 1194 1195 while (n--) { 1196 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, 1197 MGMT_PAL_INT_MDIO | MGMT_PAL_EXT_MDIO | MGMT_PAL_OENAB); 1198 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1199 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, 1200 MGMT_PAL_INT_MDIO | MGMT_PAL_EXT_MDIO | 1201 MGMT_PAL_OENAB | MGMT_PAL_DCLOCK); 1202 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1203 } 1204 } 1205 1206 void 1207 be_pal_gate(struct be_softc *sc, int phy) 1208 { 1209 bus_space_tag_t t = sc->sc_bustag; 1210 bus_space_handle_t tr = sc->sc_tr; 1211 uint32_t v; 1212 1213 be_mii_sync(sc); 1214 1215 v = ~(TCVR_PAL_EXTLBACK | TCVR_PAL_MSENSE | TCVR_PAL_LTENABLE); 1216 if (phy == BE_PHY_INTERNAL) 1217 v &= ~TCVR_PAL_SERIAL; 1218 1219 bus_space_write_4(t, tr, BE_TRI_TCVRPAL, v); 1220 (void)bus_space_read_4(t, tr, BE_TRI_TCVRPAL); 1221 } 1222 1223 static int 1224 be_tcvr_read_bit(struct be_softc *sc, int phy) 1225 { 1226 bus_space_tag_t t = sc->sc_bustag; 1227 bus_space_handle_t tr = sc->sc_tr; 1228 int ret; 1229 1230 if (phy == BE_PHY_INTERNAL) { 1231 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, MGMT_PAL_EXT_MDIO); 1232 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1233 bus_space_write_4(t, tr, 1234 BE_TRI_MGMTPAL, MGMT_PAL_EXT_MDIO | MGMT_PAL_DCLOCK); 1235 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1236 ret = (bus_space_read_4(t, tr, BE_TRI_MGMTPAL) & 1237 MGMT_PAL_INT_MDIO) >> MGMT_PAL_INT_MDIO_SHIFT; 1238 } else { 1239 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, MGMT_PAL_INT_MDIO); 1240 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1241 ret = (bus_space_read_4(t, tr, BE_TRI_MGMTPAL) & 1242 MGMT_PAL_EXT_MDIO) >> MGMT_PAL_EXT_MDIO_SHIFT; 1243 bus_space_write_4(t, tr, 1244 BE_TRI_MGMTPAL, MGMT_PAL_INT_MDIO | MGMT_PAL_DCLOCK); 1245 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1246 } 1247 1248 return ret; 1249 } 1250 1251 static void 1252 be_tcvr_write_bit(struct be_softc *sc, int phy, int bit) 1253 { 1254 bus_space_tag_t t = sc->sc_bustag; 1255 bus_space_handle_t tr = sc->sc_tr; 1256 uint32_t v; 1257 1258 if (phy == BE_PHY_INTERNAL) { 1259 v = ((bit & 1) << MGMT_PAL_INT_MDIO_SHIFT) | 1260 MGMT_PAL_OENAB | MGMT_PAL_EXT_MDIO; 1261 } else { 1262 v = ((bit & 1) << MGMT_PAL_EXT_MDIO_SHIFT) | 1263 MGMT_PAL_OENAB | MGMT_PAL_INT_MDIO; 1264 } 1265 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, v); 1266 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1267 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, v | MGMT_PAL_DCLOCK); 1268 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1269 } 1270 1271 static void 1272 be_mii_sendbits(struct be_softc *sc, int phy, uint32_t data, int nbits) 1273 { 1274 int i; 1275 1276 for (i = 1 << (nbits - 1); i != 0; i >>= 1) { 1277 be_tcvr_write_bit(sc, phy, (data & i) != 0); 1278 } 1279 } 1280 1281 static int 1282 be_mii_readreg(device_t self, int phy, int reg, uint16_t *val) 1283 { 1284 struct be_softc *sc = device_private(self); 1285 int i; 1286 uint16_t data = 0; 1287 1288 /* 1289 * Read the PHY register by manually driving the MII control lines. 1290 */ 1291 be_mii_sync(sc); 1292 be_mii_sendbits(sc, phy, MII_COMMAND_START, 2); 1293 be_mii_sendbits(sc, phy, MII_COMMAND_READ, 2); 1294 be_mii_sendbits(sc, phy, phy, 5); 1295 be_mii_sendbits(sc, phy, reg, 5); 1296 1297 (void)be_tcvr_read_bit(sc, phy); 1298 (void)be_tcvr_read_bit(sc, phy); 1299 1300 for (i = 15; i >= 0; i--) 1301 data |= (be_tcvr_read_bit(sc, phy) << i); 1302 1303 (void)be_tcvr_read_bit(sc, phy); 1304 (void)be_tcvr_read_bit(sc, phy); 1305 (void)be_tcvr_read_bit(sc, phy); 1306 1307 *val = data; 1308 return 0; 1309 } 1310 1311 int 1312 be_mii_writereg(device_t self, int phy, int reg, uint16_t val) 1313 { 1314 struct be_softc *sc = device_private(self); 1315 int i; 1316 1317 /* 1318 * Write the PHY register by manually driving the MII control lines. 1319 */ 1320 be_mii_sync(sc); 1321 be_mii_sendbits(sc, phy, MII_COMMAND_START, 2); 1322 be_mii_sendbits(sc, phy, MII_COMMAND_WRITE, 2); 1323 be_mii_sendbits(sc, phy, phy, 5); 1324 be_mii_sendbits(sc, phy, reg, 5); 1325 1326 be_tcvr_write_bit(sc, phy, 1); 1327 be_tcvr_write_bit(sc, phy, 0); 1328 1329 for (i = 15; i >= 0; i--) 1330 be_tcvr_write_bit(sc, phy, (val >> i) & 1); 1331 1332 return 0; 1333 } 1334 1335 int 1336 be_mii_reset(struct be_softc *sc, int phy) 1337 { 1338 device_t self = sc->sc_dev; 1339 int n; 1340 1341 be_mii_writereg(self, phy, MII_BMCR, BMCR_LOOP | BMCR_PDOWN | BMCR_ISO); 1342 be_mii_writereg(self, phy, MII_BMCR, BMCR_RESET); 1343 1344 for (n = 16; n >= 0; n--) { 1345 uint16_t bmcr; 1346 1347 be_mii_readreg(self, phy, MII_BMCR, &bmcr); 1348 if ((bmcr & BMCR_RESET) == 0) 1349 break; 1350 DELAY(20); 1351 } 1352 if (n == 0) { 1353 aprint_error_dev(self, "bmcr reset failed\n"); 1354 return EIO; 1355 } 1356 1357 return 0; 1358 } 1359 1360 void 1361 be_tick(void *arg) 1362 { 1363 struct be_softc *sc = arg; 1364 int s = splnet(); 1365 1366 mii_tick(&sc->sc_mii); 1367 (void)be_intphy_service(sc, &sc->sc_mii, MII_TICK); 1368 1369 splx(s); 1370 callout_reset(&sc->sc_tick_ch, hz, be_tick, sc); 1371 } 1372 1373 void 1374 be_mii_statchg(struct ifnet *ifp) 1375 { 1376 struct be_softc *sc = ifp->if_softc; 1377 bus_space_tag_t t = sc->sc_bustag; 1378 bus_space_handle_t br = sc->sc_br; 1379 uint instance; 1380 uint32_t v; 1381 1382 instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media); 1383 #ifdef DIAGNOSTIC 1384 if (instance > 1) 1385 panic("be_mii_statchg: instance %d out of range", instance); 1386 #endif 1387 1388 /* Update duplex mode in TX configuration */ 1389 v = bus_space_read_4(t, br, BE_BRI_TXCFG); 1390 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 1391 v |= BE_BR_TXCFG_FULLDPLX; 1392 else 1393 v &= ~BE_BR_TXCFG_FULLDPLX; 1394 bus_space_write_4(t, br, BE_BRI_TXCFG, v); 1395 1396 /* Change to appropriate gate in transceiver PAL */ 1397 be_pal_gate(sc, sc->sc_phys[instance]); 1398 } 1399 1400 /* 1401 * Get current media settings. 1402 */ 1403 void 1404 be_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1405 { 1406 struct be_softc *sc = ifp->if_softc; 1407 1408 mii_pollstat(&sc->sc_mii); 1409 (void)be_intphy_service(sc, &sc->sc_mii, MII_POLLSTAT); 1410 1411 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1412 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1413 } 1414 1415 /* 1416 * Set media options. 1417 */ 1418 int 1419 be_ifmedia_upd(struct ifnet *ifp) 1420 { 1421 struct be_softc *sc = ifp->if_softc; 1422 int error; 1423 1424 if ((error = mii_mediachg(&sc->sc_mii)) == ENXIO) 1425 error = 0; 1426 else if (error != 0) 1427 return error; 1428 1429 return be_intphy_service(sc, &sc->sc_mii, MII_MEDIACHG); 1430 } 1431 1432 /* 1433 * Service routine for our pseudo-MII internal transceiver. 1434 */ 1435 int 1436 be_intphy_service(struct be_softc *sc, struct mii_data *mii, int cmd) 1437 { 1438 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 1439 device_t self = sc->sc_dev; 1440 uint16_t bmcr, bmsr; 1441 int error; 1442 1443 switch (cmd) { 1444 case MII_POLLSTAT: 1445 /* 1446 * If we're not polling our PHY instance, just return. 1447 */ 1448 if (IFM_INST(ife->ifm_media) != sc->sc_mii_inst) 1449 return 0; 1450 1451 break; 1452 1453 case MII_MEDIACHG: 1454 1455 /* 1456 * If the media indicates a different PHY instance, 1457 * isolate ourselves. 1458 */ 1459 if (IFM_INST(ife->ifm_media) != sc->sc_mii_inst) { 1460 be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMCR, &bmcr); 1461 be_mii_writereg(self, 1462 BE_PHY_INTERNAL, MII_BMCR, bmcr | BMCR_ISO); 1463 sc->sc_mii_flags &= ~MIIF_HAVELINK; 1464 sc->sc_intphy_curspeed = 0; 1465 return 0; 1466 } 1467 1468 1469 if ((error = be_mii_reset(sc, BE_PHY_INTERNAL)) != 0) 1470 return error; 1471 1472 be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMCR, &bmcr); 1473 1474 /* 1475 * Select the new mode and take out of isolation 1476 */ 1477 if (IFM_SUBTYPE(ife->ifm_media) == IFM_100_TX) 1478 bmcr |= BMCR_S100; 1479 else if (IFM_SUBTYPE(ife->ifm_media) == IFM_10_T) 1480 bmcr &= ~BMCR_S100; 1481 else if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) { 1482 if ((sc->sc_mii_flags & MIIF_HAVELINK) != 0) { 1483 bmcr &= ~BMCR_S100; 1484 bmcr |= sc->sc_intphy_curspeed; 1485 } else { 1486 /* Keep isolated until link is up */ 1487 bmcr |= BMCR_ISO; 1488 sc->sc_mii_flags |= MIIF_DOINGAUTO; 1489 } 1490 } 1491 1492 if ((IFM_OPTIONS(ife->ifm_media) & IFM_FDX) != 0) 1493 bmcr |= BMCR_FDX; 1494 else 1495 bmcr &= ~BMCR_FDX; 1496 1497 be_mii_writereg(self, BE_PHY_INTERNAL, MII_BMCR, bmcr); 1498 break; 1499 1500 case MII_TICK: 1501 /* 1502 * If we're not currently selected, just return. 1503 */ 1504 if (IFM_INST(ife->ifm_media) != sc->sc_mii_inst) 1505 return 0; 1506 1507 /* Is the interface even up? */ 1508 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 1509 return 0; 1510 1511 /* Only used for automatic media selection */ 1512 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) 1513 break; 1514 1515 /* 1516 * Check link status; if we don't have a link, try another 1517 * speed. We can't detect duplex mode, so half-duplex is 1518 * what we have to settle for. 1519 */ 1520 1521 /* Read twice in case the register is latched */ 1522 be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMSR, &bmsr); 1523 be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMSR, &bmsr); 1524 1525 if ((bmsr & BMSR_LINK) != 0) { 1526 /* We have a carrier */ 1527 be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMCR, &bmcr); 1528 1529 if ((sc->sc_mii_flags & MIIF_DOINGAUTO) != 0) { 1530 be_mii_readreg(self, 1531 BE_PHY_INTERNAL, MII_BMCR, &bmcr); 1532 1533 sc->sc_mii_flags |= MIIF_HAVELINK; 1534 sc->sc_intphy_curspeed = (bmcr & BMCR_S100); 1535 sc->sc_mii_flags &= ~MIIF_DOINGAUTO; 1536 1537 bmcr &= ~BMCR_ISO; 1538 be_mii_writereg(self, 1539 BE_PHY_INTERNAL, MII_BMCR, bmcr); 1540 1541 printf("%s: link up at %s Mbps\n", 1542 device_xname(self), 1543 (bmcr & BMCR_S100) ? "100" : "10"); 1544 } 1545 break; 1546 } 1547 1548 if ((sc->sc_mii_flags & MIIF_DOINGAUTO) == 0) { 1549 sc->sc_mii_flags |= MIIF_DOINGAUTO; 1550 sc->sc_mii_flags &= ~MIIF_HAVELINK; 1551 sc->sc_intphy_curspeed = 0; 1552 printf("%s: link down\n", device_xname(self)); 1553 } 1554 1555 /* Only retry autonegotiation every 5 seconds. */ 1556 if (++sc->sc_mii_ticks < 5) 1557 return 0; 1558 1559 sc->sc_mii_ticks = 0; 1560 be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMCR, &bmcr); 1561 /* Just flip the fast speed bit */ 1562 bmcr ^= BMCR_S100; 1563 be_mii_writereg(self, BE_PHY_INTERNAL, MII_BMCR, bmcr); 1564 1565 break; 1566 1567 case MII_DOWN: 1568 /* Isolate this phy */ 1569 be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMCR, &bmcr); 1570 be_mii_writereg(self, 1571 BE_PHY_INTERNAL, MII_BMCR, bmcr | BMCR_ISO); 1572 return 0; 1573 } 1574 1575 /* Update the media status. */ 1576 be_intphy_status(sc); 1577 1578 /* Callback if something changed. */ 1579 if (sc->sc_mii_active != mii->mii_media_active || cmd == MII_MEDIACHG) { 1580 (*mii->mii_statchg)(mii->mii_ifp); 1581 sc->sc_mii_active = mii->mii_media_active; 1582 } 1583 return 0; 1584 } 1585 1586 /* 1587 * Determine status of internal transceiver 1588 */ 1589 void 1590 be_intphy_status(struct be_softc *sc) 1591 { 1592 struct mii_data *mii = &sc->sc_mii; 1593 device_t self = sc->sc_dev; 1594 int media_active, media_status; 1595 uint16_t bmcr, bmsr; 1596 1597 media_status = IFM_AVALID; 1598 media_active = 0; 1599 1600 /* 1601 * Internal transceiver; do the work here. 1602 */ 1603 be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMCR, &bmcr); 1604 1605 switch (bmcr & (BMCR_S100 | BMCR_FDX)) { 1606 case (BMCR_S100 | BMCR_FDX): 1607 media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 1608 break; 1609 case BMCR_S100: 1610 media_active = IFM_ETHER | IFM_100_TX | IFM_HDX; 1611 break; 1612 case BMCR_FDX: 1613 media_active = IFM_ETHER | IFM_10_T | IFM_FDX; 1614 break; 1615 case 0: 1616 media_active = IFM_ETHER | IFM_10_T | IFM_HDX; 1617 break; 1618 } 1619 1620 /* Read twice in case the register is latched */ 1621 be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMSR, &bmsr); 1622 be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMSR, &bmsr); 1623 if (bmsr & BMSR_LINK) 1624 media_status |= IFM_ACTIVE; 1625 1626 mii->mii_media_status = media_status; 1627 mii->mii_media_active = media_active; 1628 } 1629
Indexes created Sat Oct 25 07:10:08 GMT 2025