bpp.c revision 1.2
1 /* $NetBSD: bpp.c,v 1.2 1999/02/28 17:01:49 pk Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <sys/param.h> 40 #include <sys/ioctl.h> 41 #include <sys/fcntl.h> 42 #include <sys/systm.h> 43 #include <sys/kernel.h> 44 #include <sys/vnode.h> 45 #include <sys/poll.h> 46 #include <sys/select.h> 47 #include <sys/malloc.h> 48 #include <sys/proc.h> 49 #include <sys/signalvar.h> 50 #include <sys/conf.h> 51 #include <sys/errno.h> 52 #include <sys/device.h> 53 54 #include <machine/conf.h> 55 #include <machine/bus.h> 56 #include <machine/autoconf.h> 57 58 #include <dev/ic/lsi64854reg.h> 59 #include <dev/ic/lsi64854var.h> 60 61 #include <dev/sbus/sbusvar.h> 62 #include <dev/sbus/bppreg.h> 63 64 #define splbpp() spltty() /* XXX */ 65 66 #if 0 67 struct bpp_param { 68 int bpp_dss; /* data setup to strobe */ 69 int bpp_dsw; /* data strobe width */ 70 int bpp_outputpins; /* Select/Autofeed/Init pins */ 71 int bpp_inputpins; /* Error/Select/Paperout pins */ 72 }; 73 #endif 74 75 struct hwstate { 76 u_int16_t hw_hcr; /* Hardware config register */ 77 u_int16_t hw_ocr; /* Operation config register */ 78 u_int8_t hw_tcr; /* Transfer Control register */ 79 u_int8_t hw_or; /* Output register */ 80 u_int16_t hw_irq; /* IRQ; polarity bits only */ 81 }; 82 83 struct bpp_softc { 84 struct lsi64854_softc sc_lsi64854; /* base device */ 85 struct sbusdev sc_sd; /* sbus device */ 86 87 size_t sc_bufsz; /* temp buffer */ 88 caddr_t sc_buf; 89 90 int sc_error; /* bottom-half error */ 91 int sc_flags; 92 #define BPP_OPEN 0x01 /* Device is open */ 93 #define BPP_XCLUDE 0x02 /* Exclusive-open mode */ 94 #define BPP_ASYNC 0x04 /* Asynchronous I/O mode */ 95 #define BPP_LOCKED 0x08 /* DMA in progress */ 96 #define BPP_WANT 0x10 /* Waiting for DMA */ 97 98 struct selinfo sc_rsel; 99 struct selinfo sc_wsel; 100 struct proc *sc_asyncproc; /* Process to notify if async */ 101 102 /* Hardware state */ 103 struct hwstate sc_hwdefault; 104 struct hwstate sc_hwcurrent; 105 }; 106 107 static int bppmatch __P((struct device *, struct cfdata *, void *)); 108 static void bppattach __P((struct device *, struct device *, void *)); 109 static int bppintr __P((void *)); 110 static void bpp_setparams __P((struct bpp_softc *, struct hwstate *)); 111 112 struct cfattach bpp_ca = { 113 sizeof(struct bpp_softc), bppmatch, bppattach 114 }; 115 116 extern struct cfdriver bpp_cd; 117 #define BPPUNIT(dev) (minor(dev)) 118 119 120 int 121 bppmatch(parent, cf, aux) 122 struct device *parent; 123 struct cfdata *cf; 124 void *aux; 125 { 126 struct sbus_attach_args *sa = aux; 127 128 return (strcmp("SUNW,bpp", sa->sa_name) == 0); 129 } 130 131 void 132 bppattach(parent, self, aux) 133 struct device *parent, *self; 134 void *aux; 135 { 136 struct sbus_attach_args *sa = aux; 137 struct bpp_softc *dsc = (void *)self; 138 struct lsi64854_softc *sc = &dsc->sc_lsi64854; 139 int burst, sbusburst; 140 int node; 141 142 sc->sc_bustag = sa->sa_bustag; 143 sc->sc_dmatag = sa->sa_dmatag; 144 node = sa->sa_node; 145 146 /* Map device registers */ 147 if (bus_space_map2(sa->sa_bustag, 148 sa->sa_slot, 149 sa->sa_offset, 150 sa->sa_size, 151 BUS_SPACE_MAP_LINEAR, 152 0, &sc->sc_regs) != 0) { 153 printf("%s: cannot map registers\n", self->dv_xname); 154 return; 155 } 156 157 /* 158 * Get transfer burst size from PROM and plug it into the 159 * controller registers. This is needed on the Sun4m; do 160 * others need it too? 161 */ 162 sbusburst = ((struct sbus_softc *)parent)->sc_burst; 163 if (sbusburst == 0) 164 sbusburst = SBUS_BURST_32 - 1; /* 1->16 */ 165 166 burst = getpropint(node, "burst-sizes", -1); 167 if (burst == -1) 168 /* take SBus burst sizes */ 169 burst = sbusburst; 170 171 /* Clamp at parent's burst sizes */ 172 burst &= sbusburst; 173 sc->sc_burst = (burst & SBUS_BURST_32) ? 32 : 174 (burst & SBUS_BURST_16) ? 16 : 0; 175 176 /* Join the Sbus device family */ 177 dsc->sc_sd.sd_reset = (void *)0; 178 sbus_establish(&dsc->sc_sd, self); 179 180 /* Initialize the DMA channel */ 181 sc->sc_channel = L64854_CHANNEL_PP; 182 lsi64854_attach(sc); 183 184 sc->sc_intrchain = bppintr; 185 sc->sc_intrchainarg = dsc; 186 (void)bus_intr_establish(sa->sa_bustag, sa->sa_pri, 0, 187 lsi64854_pp_intr, sc); 188 189 /* Allocate buffer XXX - should actually use dmamap_uio() */ 190 dsc->sc_bufsz = 1024; 191 dsc->sc_buf = malloc(dsc->sc_bufsz, M_DEVBUF, M_NOWAIT); 192 193 /* XXX read default state */ 194 { 195 bus_space_handle_t h = sc->sc_regs; 196 struct hwstate *hw = &dsc->sc_hwdefault; 197 hw->hw_hcr = bus_space_read_2(sc->sc_bustag, h, L64854_REG_HCR); 198 hw->hw_ocr = bus_space_read_2(sc->sc_bustag, h, L64854_REG_OCR); 199 hw->hw_tcr = bus_space_read_1(sc->sc_bustag, h, L64854_REG_TCR); 200 hw->hw_or = bus_space_read_1(sc->sc_bustag, h, L64854_REG_OR); 201 } 202 } 203 204 void 205 bpp_setparams(sc, hw) 206 struct bpp_softc *sc; 207 struct hwstate *hw; 208 { 209 u_int16_t irq; 210 bus_space_tag_t t = sc->sc_lsi64854.sc_bustag; 211 bus_space_handle_t h = sc->sc_lsi64854.sc_regs; 212 213 bus_space_write_2(t, h, L64854_REG_HCR, hw->hw_hcr); 214 bus_space_write_2(t, h, L64854_REG_OCR, hw->hw_ocr); 215 bus_space_write_1(t, h, L64854_REG_TCR, hw->hw_tcr); 216 bus_space_write_1(t, h, L64854_REG_OR, hw->hw_or); 217 218 /* Only change IRP settings in interrupt status register */ 219 irq = bus_space_read_2(t, h, L64854_REG_ICR); 220 irq &= ~BPP_ALLIRP; 221 irq |= (hw->hw_irq & BPP_ALLIRP); 222 bus_space_write_2(t, h, L64854_REG_ICR, irq); 223 } 224 225 int 226 bppopen(dev, flags, mode, p) 227 dev_t dev; 228 int flags, mode; 229 struct proc *p; 230 { 231 int unit = BPPUNIT(dev); 232 struct bpp_softc *sc; 233 struct lsi64854_softc *lsi; 234 u_int16_t irq; 235 int s; 236 237 if (unit >= bpp_cd.cd_ndevs) 238 return (ENXIO); 239 sc = bpp_cd.cd_devs[unit]; 240 241 if ((sc->sc_flags & (BPP_OPEN|BPP_XCLUDE)) == (BPP_OPEN|BPP_XCLUDE)) 242 return (EBUSY); 243 244 lsi = &sc->sc_lsi64854; 245 246 /* Set default parameters */ 247 sc->sc_hwcurrent = sc->sc_hwdefault; 248 s = splbpp(); 249 bpp_setparams(sc, &sc->sc_hwdefault); 250 splx(s); 251 252 /* Enable interrupts */ 253 irq = BPP_ALLEN; 254 irq |= sc->sc_hwdefault.hw_irq; 255 bus_space_write_2(lsi->sc_bustag, lsi->sc_regs, L64854_REG_ICR, irq); 256 return (0); 257 } 258 259 int 260 bppclose(dev, flags, mode, p) 261 dev_t dev; 262 int flags, mode; 263 struct proc *p; 264 { 265 struct bpp_softc *sc = bpp_cd.cd_devs[BPPUNIT(dev)]; 266 struct lsi64854_softc *lsi = &sc->sc_lsi64854; 267 u_int16_t irq; 268 269 /* Turn off all interrupt enables */ 270 irq = sc->sc_hwdefault.hw_irq | BPP_ALLIRQ; 271 irq &= ~BPP_ALLEN; 272 bus_space_write_2(lsi->sc_bustag, lsi->sc_regs, L64854_REG_ICR, irq); 273 274 sc->sc_asyncproc = NULL; 275 sc->sc_flags = 0; 276 return (0); 277 } 278 279 int 280 bppread(dev, uio, flags) 281 dev_t dev; 282 struct uio *uio; 283 int flags; 284 { 285 286 return (ENXIO); 287 } 288 289 int 290 bppwrite(dev, uio, flags) 291 dev_t dev; 292 struct uio *uio; 293 int flags; 294 { 295 struct bpp_softc *sc = bpp_cd.cd_devs[BPPUNIT(dev)]; 296 struct lsi64854_softc *lsi = &sc->sc_lsi64854; 297 int error = 0; 298 int s; 299 300 /* 301 * Wait until the DMA engibe is free. 302 */ 303 s = splbpp(); 304 while ((sc->sc_flags & BPP_LOCKED) != 0) { 305 if ((flags & IO_NDELAY) != 0) { 306 splx(s); 307 return (EWOULDBLOCK); 308 } 309 310 sc->sc_flags |= BPP_WANT; 311 error = tsleep(sc->sc_buf, PZERO|PCATCH, "bppwrite", 0); 312 if (error != 0) { 313 splx(s); 314 return (error); 315 } 316 } 317 sc->sc_flags |= BPP_LOCKED; 318 splx(s); 319 320 /* 321 * Move data from user space into our private buffer 322 * and start DMA. 323 */ 324 while (uio->uio_resid > 0) { 325 caddr_t bp = sc->sc_buf; 326 size_t len = min(sc->sc_bufsz, uio->uio_resid); 327 328 if ((error = uiomove(bp, len, uio)) != 0) 329 break; 330 331 while (len > 0) { 332 u_int8_t tcr; 333 size_t size = len; 334 DMA_SETUP(lsi, &bp, &len, 0, &size); 335 336 /* Clear direction control bit */ 337 tcr = bus_space_read_1(lsi->sc_bustag, lsi->sc_regs, 338 L64854_REG_TCR); 339 tcr &= ~BPP_TCR_DIR; 340 bus_space_write_1(lsi->sc_bustag, lsi->sc_regs, 341 L64854_REG_TCR, tcr); 342 343 /* Enable DMA */ 344 DMA_GO(lsi); 345 error = tsleep(sc, PZERO|PCATCH, "bppdma", 0); 346 if (error != 0) 347 goto out; 348 349 /* Bail out if bottom half reported an error */ 350 if ((error = sc->sc_error) != 0) 351 goto out; 352 } 353 } 354 355 out: 356 s = splbpp(); 357 sc->sc_flags &= ~BPP_LOCKED; 358 if ((sc->sc_flags & BPP_WANT) != 0) { 359 sc->sc_flags &= ~BPP_WANT; 360 wakeup(sc->sc_buf); 361 } 362 splx(s); 363 return (error); 364 } 365 366 /* move to header: */ 367 #define BPPIOCSPARAM _IOW('P', 0x1, struct hwstate) 368 #define BPPIOCGPARAM _IOR('P', 0x2, struct hwstate) 369 370 int 371 bppioctl(dev, cmd, data, flag, p) 372 dev_t dev; 373 u_long cmd; 374 caddr_t data; 375 int flag; 376 struct proc *p; 377 { 378 struct bpp_softc *sc = bpp_cd.cd_devs[BPPUNIT(dev)]; 379 struct hwstate *hw, *chw; 380 int error = 0; 381 int s; 382 383 switch(cmd) { 384 case BPPIOCSPARAM: 385 chw = &sc->sc_hwcurrent; 386 hw = (struct hwstate *)data; 387 388 /* 389 * Extract and store user-settable bits. 390 */ 391 #define _bpp_set(reg,mask) do { \ 392 chw->reg &= ~(mask); \ 393 chw->reg |= (hw->reg & (mask)); \ 394 } while (0) 395 _bpp_set(hw_hcr, BPP_HCR_DSS_MASK|BPP_HCR_DSW_MASK); 396 _bpp_set(hw_ocr, BPP_OCR_USER); 397 _bpp_set(hw_tcr, BPP_TCR_USER); 398 _bpp_set(hw_or, BPP_OR_USER); 399 _bpp_set(hw_irq, BPP_IRQ_USER); 400 #undef _bpp_set 401 402 /* Apply settings */ 403 s = splbpp(); 404 bpp_setparams(sc, chw); 405 splx(s); 406 break; 407 case BPPIOCGPARAM: 408 *((struct hwstate *)data) = sc->sc_hwcurrent; 409 break; 410 case TIOCEXCL: 411 s = splbpp(); 412 sc->sc_flags |= BPP_XCLUDE; 413 splx(s); 414 break; 415 case TIOCNXCL: 416 s = splbpp(); 417 sc->sc_flags &= ~BPP_XCLUDE; 418 splx(s); 419 break; 420 case FIOASYNC: 421 s = splbpp(); 422 if (*(int *)data) { 423 if (sc->sc_asyncproc != NULL) 424 error = EBUSY; 425 else 426 sc->sc_asyncproc = p; 427 } else 428 sc->sc_asyncproc = NULL; 429 splx(s); 430 break; 431 default: 432 break; 433 } 434 435 return (error); 436 } 437 438 int 439 bpppoll(dev, events, p) 440 dev_t dev; 441 int events; 442 struct proc *p; 443 { 444 struct bpp_softc *sc = bpp_cd.cd_devs[BPPUNIT(dev)]; 445 int revents = 0; 446 447 if (events & (POLLIN | POLLRDNORM)) { 448 /* read is not yet implemented */ 449 } 450 451 if (events & (POLLOUT | POLLWRNORM)) { 452 if ((sc->sc_flags & BPP_LOCKED) == 0) 453 revents |= (POLLOUT | POLLWRNORM); 454 } 455 456 if (revents == 0) { 457 if (events & (POLLIN | POLLRDNORM)) 458 selrecord(p, &sc->sc_rsel); 459 if (events & (POLLOUT | POLLWRNORM)) 460 selrecord(p, &sc->sc_wsel); 461 } 462 463 return (revents); 464 } 465 466 int 467 bppintr(arg) 468 void *arg; 469 { 470 struct bpp_softc *sc = arg; 471 struct lsi64854_softc *lsi = &sc->sc_lsi64854; 472 u_int16_t irq; 473 474 irq = bus_space_read_2(lsi->sc_bustag, lsi->sc_regs, L64854_REG_ICR); 475 /* Ack all interrupts */ 476 bus_space_write_2(lsi->sc_bustag, lsi->sc_regs, L64854_REG_ICR, 477 irq | BPP_ALLIRQ); 478 479 /* Did our device interrupt? */ 480 if ((irq & BPP_ALLIRQ) == 0) 481 return (0); 482 483 if ((sc->sc_flags & BPP_LOCKED) != 0) 484 wakeup(sc); 485 else if ((sc->sc_flags & BPP_WANT) != 0) { 486 sc->sc_flags &= ~BPP_WANT; 487 wakeup(sc->sc_buf); 488 } else { 489 selwakeup(&sc->sc_wsel); 490 if (sc->sc_asyncproc != NULL) 491 psignal(sc->sc_asyncproc, SIGIO); 492 } 493 return (1); 494 } 495
Indexes created Wed Sep 24 05:09:52 GMT 2025