bpp.c revision 1.24.4.7
1 /* $NetBSD: bpp.c,v 1.24.4.7 2008/03/17 09:15:27 yamt Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <sys/cdefs.h> 40 __KERNEL_RCSID(0, "$NetBSD: bpp.c,v 1.24.4.7 2008/03/17 09:15:27 yamt Exp $"); 41 42 #include <sys/param.h> 43 #include <sys/ioctl.h> 44 #include <sys/fcntl.h> 45 #include <sys/systm.h> 46 #include <sys/kernel.h> 47 #include <sys/vnode.h> 48 #include <sys/poll.h> 49 #include <sys/select.h> 50 #include <sys/malloc.h> 51 #include <sys/proc.h> 52 #include <sys/signalvar.h> 53 #include <sys/conf.h> 54 #include <sys/errno.h> 55 #include <sys/device.h> 56 57 #include <sys/bus.h> 58 #include <sys/intr.h> 59 #include <machine/autoconf.h> 60 61 #include <dev/ic/lsi64854reg.h> 62 #include <dev/ic/lsi64854var.h> 63 64 #include <dev/sbus/sbusvar.h> 65 #include <dev/sbus/bppreg.h> 66 67 #define splbpp() spltty() /* XXX */ 68 69 #ifdef DEBUG 70 #define DPRINTF(x) do { if (bppdebug) printf x ; } while (0) 71 int bppdebug = 1; 72 #else 73 #define DPRINTF(x) 74 #endif 75 76 #if 0 77 struct bpp_param { 78 int bpp_dss; /* data setup to strobe */ 79 int bpp_dsw; /* data strobe width */ 80 int bpp_outputpins; /* Select/Autofeed/Init pins */ 81 int bpp_inputpins; /* Error/Select/Paperout pins */ 82 }; 83 #endif 84 85 struct hwstate { 86 u_int16_t hw_hcr; /* Hardware config register */ 87 u_int16_t hw_ocr; /* Operation config register */ 88 u_int8_t hw_tcr; /* Transfer Control register */ 89 u_int8_t hw_or; /* Output register */ 90 u_int16_t hw_irq; /* IRQ; polarity bits only */ 91 }; 92 93 struct bpp_softc { 94 struct lsi64854_softc sc_lsi64854; /* base device */ 95 struct sbusdev sc_sd; /* sbus device */ 96 97 size_t sc_bufsz; /* temp buffer */ 98 void * sc_buf; 99 100 int sc_error; /* bottom-half error */ 101 int sc_flags; 102 #define BPP_OPEN 0x01 /* Device is open */ 103 #define BPP_XCLUDE 0x02 /* Exclusive-open mode */ 104 #define BPP_ASYNC 0x04 /* Asynchronous I/O mode */ 105 #define BPP_LOCKED 0x08 /* DMA in progress */ 106 #define BPP_WANT 0x10 /* Waiting for DMA */ 107 108 struct selinfo sc_rsel; 109 struct selinfo sc_wsel; 110 struct proc *sc_asyncproc; /* Process to notify if async */ 111 112 /* Hardware state */ 113 struct hwstate sc_hwdefault; 114 struct hwstate sc_hwcurrent; 115 }; 116 117 static int bppmatch(struct device *, struct cfdata *, void *); 118 static void bppattach(struct device *, struct device *, void *); 119 static int bppintr (void *); 120 static void bpp_setparams(struct bpp_softc *, struct hwstate *); 121 122 CFATTACH_DECL(bpp, sizeof(struct bpp_softc), 123 bppmatch, bppattach, NULL, NULL); 124 125 extern struct cfdriver bpp_cd; 126 127 dev_type_open(bppopen); 128 dev_type_close(bppclose); 129 dev_type_write(bppwrite); 130 dev_type_ioctl(bppioctl); 131 dev_type_poll(bpppoll); 132 dev_type_kqfilter(bppkqfilter); 133 134 const struct cdevsw bpp_cdevsw = { 135 bppopen, bppclose, noread, bppwrite, bppioctl, 136 nostop, notty, bpppoll, nommap, bppkqfilter, D_TTY 137 }; 138 139 #define BPPUNIT(dev) (minor(dev)) 140 141 142 int 143 bppmatch(parent, cf, aux) 144 struct device *parent; 145 struct cfdata *cf; 146 void *aux; 147 { 148 struct sbus_attach_args *sa = aux; 149 150 return (strcmp("SUNW,bpp", sa->sa_name) == 0); 151 } 152 153 void 154 bppattach(parent, self, aux) 155 struct device *parent, *self; 156 void *aux; 157 { 158 struct sbus_attach_args *sa = aux; 159 struct bpp_softc *dsc = (void *)self; 160 struct lsi64854_softc *sc = &dsc->sc_lsi64854; 161 int burst, sbusburst; 162 int node; 163 164 selinit(&dsc->sc_rsel); 165 selinit(&dsc->sc_wsel); 166 167 sc->sc_bustag = sa->sa_bustag; 168 sc->sc_dmatag = sa->sa_dmatag; 169 node = sa->sa_node; 170 171 /* Map device registers */ 172 if (sbus_bus_map(sa->sa_bustag, 173 sa->sa_slot, sa->sa_offset, sa->sa_size, 174 0, &sc->sc_regs) != 0) { 175 printf("%s: cannot map registers\n", self->dv_xname); 176 return; 177 } 178 179 /* 180 * Get transfer burst size from PROM and plug it into the 181 * controller registers. This is needed on the Sun4m; do 182 * others need it too? 183 */ 184 sbusburst = ((struct sbus_softc *)parent)->sc_burst; 185 if (sbusburst == 0) 186 sbusburst = SBUS_BURST_32 - 1; /* 1->16 */ 187 188 burst = prom_getpropint(node, "burst-sizes", -1); 189 if (burst == -1) 190 /* take SBus burst sizes */ 191 burst = sbusburst; 192 193 /* Clamp at parent's burst sizes */ 194 burst &= sbusburst; 195 sc->sc_burst = (burst & SBUS_BURST_32) ? 32 : 196 (burst & SBUS_BURST_16) ? 16 : 0; 197 198 /* Join the Sbus device family */ 199 dsc->sc_sd.sd_reset = (void *)0; 200 sbus_establish(&dsc->sc_sd, self); 201 202 /* Initialize the DMA channel */ 203 sc->sc_channel = L64854_CHANNEL_PP; 204 lsi64854_attach(sc); 205 206 /* Establish interrupt handler */ 207 if (sa->sa_nintr) { 208 sc->sc_intrchain = bppintr; 209 sc->sc_intrchainarg = dsc; 210 (void)bus_intr_establish(sa->sa_bustag, sa->sa_pri, IPL_TTY, 211 bppintr, sc); 212 } 213 214 /* Allocate buffer XXX - should actually use dmamap_uio() */ 215 dsc->sc_bufsz = 1024; 216 dsc->sc_buf = malloc(dsc->sc_bufsz, M_DEVBUF, M_NOWAIT); 217 218 /* XXX read default state */ 219 { 220 bus_space_handle_t h = sc->sc_regs; 221 struct hwstate *hw = &dsc->sc_hwdefault; 222 int ack_rate = sa->sa_frequency/1000000; 223 224 hw->hw_hcr = bus_space_read_2(sc->sc_bustag, h, L64854_REG_HCR); 225 hw->hw_ocr = bus_space_read_2(sc->sc_bustag, h, L64854_REG_OCR); 226 hw->hw_tcr = bus_space_read_1(sc->sc_bustag, h, L64854_REG_TCR); 227 hw->hw_or = bus_space_read_1(sc->sc_bustag, h, L64854_REG_OR); 228 229 DPRINTF(("bpp: hcr %x ocr %x tcr %x or %x\n", 230 hw->hw_hcr, hw->hw_ocr, hw->hw_tcr, hw->hw_or)); 231 /* Set these to sane values */ 232 hw->hw_hcr = ((ack_rate<<BPP_HCR_DSS_SHFT)&BPP_HCR_DSS_MASK) 233 | ((ack_rate<<BPP_HCR_DSW_SHFT)&BPP_HCR_DSW_MASK); 234 hw->hw_ocr |= BPP_OCR_ACK_OP; 235 } 236 } 237 238 void 239 bpp_setparams(sc, hw) 240 struct bpp_softc *sc; 241 struct hwstate *hw; 242 { 243 u_int16_t irq; 244 bus_space_tag_t t = sc->sc_lsi64854.sc_bustag; 245 bus_space_handle_t h = sc->sc_lsi64854.sc_regs; 246 247 bus_space_write_2(t, h, L64854_REG_HCR, hw->hw_hcr); 248 bus_space_write_2(t, h, L64854_REG_OCR, hw->hw_ocr); 249 bus_space_write_1(t, h, L64854_REG_TCR, hw->hw_tcr); 250 bus_space_write_1(t, h, L64854_REG_OR, hw->hw_or); 251 252 /* Only change IRP settings in interrupt status register */ 253 irq = bus_space_read_2(t, h, L64854_REG_ICR); 254 irq &= ~BPP_ALLIRP; 255 irq |= (hw->hw_irq & BPP_ALLIRP); 256 bus_space_write_2(t, h, L64854_REG_ICR, irq); 257 DPRINTF(("bpp_setparams: hcr %x ocr %x tcr %x or %x, irq %x\n", 258 hw->hw_hcr, hw->hw_ocr, hw->hw_tcr, hw->hw_or, irq)); 259 } 260 261 int 262 bppopen(dev, flags, mode, l) 263 dev_t dev; 264 int flags, mode; 265 struct lwp *l; 266 { 267 int unit = BPPUNIT(dev); 268 struct bpp_softc *sc; 269 struct lsi64854_softc *lsi; 270 u_int16_t irq; 271 int s; 272 273 if (unit >= bpp_cd.cd_ndevs) 274 return (ENXIO); 275 sc = bpp_cd.cd_devs[unit]; 276 277 if ((sc->sc_flags & (BPP_OPEN|BPP_XCLUDE)) == (BPP_OPEN|BPP_XCLUDE)) 278 return (EBUSY); 279 280 lsi = &sc->sc_lsi64854; 281 282 /* Set default parameters */ 283 sc->sc_hwcurrent = sc->sc_hwdefault; 284 s = splbpp(); 285 bpp_setparams(sc, &sc->sc_hwdefault); 286 splx(s); 287 288 /* Enable interrupts */ 289 irq = BPP_ERR_IRQ_EN; 290 irq |= sc->sc_hwdefault.hw_irq; 291 bus_space_write_2(lsi->sc_bustag, lsi->sc_regs, L64854_REG_ICR, irq); 292 return (0); 293 } 294 295 int 296 bppclose(dev, flags, mode, l) 297 dev_t dev; 298 int flags, mode; 299 struct lwp *l; 300 { 301 struct bpp_softc *sc = bpp_cd.cd_devs[BPPUNIT(dev)]; 302 struct lsi64854_softc *lsi = &sc->sc_lsi64854; 303 u_int16_t irq; 304 305 /* Turn off all interrupt enables */ 306 irq = sc->sc_hwdefault.hw_irq | BPP_ALLIRQ; 307 irq &= ~BPP_ALLEN; 308 bus_space_write_2(lsi->sc_bustag, lsi->sc_regs, L64854_REG_ICR, irq); 309 310 sc->sc_asyncproc = NULL; 311 sc->sc_flags = 0; 312 return (0); 313 } 314 315 int 316 bppwrite(dev, uio, flags) 317 dev_t dev; 318 struct uio *uio; 319 int flags; 320 { 321 struct bpp_softc *sc = bpp_cd.cd_devs[BPPUNIT(dev)]; 322 struct lsi64854_softc *lsi = &sc->sc_lsi64854; 323 int error = 0; 324 int s; 325 326 /* 327 * Wait until the DMA engine is free. 328 */ 329 s = splbpp(); 330 while ((sc->sc_flags & BPP_LOCKED) != 0) { 331 if ((flags & IO_NDELAY) != 0) { 332 splx(s); 333 return (EWOULDBLOCK); 334 } 335 336 sc->sc_flags |= BPP_WANT; 337 error = tsleep(sc->sc_buf, PZERO|PCATCH, "bppwrite", 0); 338 if (error != 0) { 339 splx(s); 340 return (error); 341 } 342 } 343 sc->sc_flags |= BPP_LOCKED; 344 splx(s); 345 346 /* 347 * Move data from user space into our private buffer 348 * and start DMA. 349 */ 350 while (uio->uio_resid > 0) { 351 void *bp = sc->sc_buf; 352 size_t len = min(sc->sc_bufsz, uio->uio_resid); 353 354 if ((error = uiomove(bp, len, uio)) != 0) 355 break; 356 357 while (len > 0) { 358 u_int8_t tcr; 359 size_t size = len; 360 DMA_SETUP(lsi, &bp, &len, 0, &size); 361 362 #ifdef DEBUG 363 if (bppdebug) { 364 int i; 365 unsigned char *b = bp; 366 printf("bpp: writing %ld : ", len); 367 for (i=0; i<len; i++) printf("%c(0x%x)", b[i], 368 b[i]); 369 printf("\n"); 370 } 371 #endif 372 373 /* Clear direction control bit */ 374 tcr = bus_space_read_1(lsi->sc_bustag, lsi->sc_regs, 375 L64854_REG_TCR); 376 tcr &= ~BPP_TCR_DIR; 377 bus_space_write_1(lsi->sc_bustag, lsi->sc_regs, 378 L64854_REG_TCR, tcr); 379 380 /* Enable DMA */ 381 s = splbpp(); 382 DMA_GO(lsi); 383 error = tsleep(sc, PZERO|PCATCH, "bppdma", 0); 384 splx(s); 385 if (error != 0) 386 goto out; 387 388 /* Bail out if bottom half reported an error */ 389 if ((error = sc->sc_error) != 0) 390 goto out; 391 392 /* 393 * lsi64854_pp_intr() does this part. 394 * 395 * len -= size; 396 */ 397 } 398 } 399 400 out: 401 DPRINTF(("bpp done %x\n", error)); 402 s = splbpp(); 403 sc->sc_flags &= ~BPP_LOCKED; 404 if ((sc->sc_flags & BPP_WANT) != 0) { 405 sc->sc_flags &= ~BPP_WANT; 406 wakeup(sc->sc_buf); 407 } 408 splx(s); 409 return (error); 410 } 411 412 /* move to header: */ 413 #define BPPIOCSPARAM _IOW('P', 0x1, struct hwstate) 414 #define BPPIOCGPARAM _IOR('P', 0x2, struct hwstate) 415 416 int 417 bppioctl(dev, cmd, data, flag, l) 418 dev_t dev; 419 u_long cmd; 420 void * data; 421 int flag; 422 struct lwp *l; 423 { 424 struct bpp_softc *sc = bpp_cd.cd_devs[BPPUNIT(dev)]; 425 struct proc *p = l->l_proc; 426 struct hwstate *hw, *chw; 427 int error = 0; 428 int s; 429 430 switch(cmd) { 431 case BPPIOCSPARAM: 432 chw = &sc->sc_hwcurrent; 433 hw = (struct hwstate *)data; 434 435 /* 436 * Extract and store user-settable bits. 437 */ 438 #define _bpp_set(reg,mask) do { \ 439 chw->reg &= ~(mask); \ 440 chw->reg |= (hw->reg & (mask)); \ 441 } while (0) 442 _bpp_set(hw_hcr, BPP_HCR_DSS_MASK|BPP_HCR_DSW_MASK); 443 _bpp_set(hw_ocr, BPP_OCR_USER); 444 _bpp_set(hw_tcr, BPP_TCR_USER); 445 _bpp_set(hw_or, BPP_OR_USER); 446 _bpp_set(hw_irq, BPP_IRQ_USER); 447 #undef _bpp_set 448 449 /* Apply settings */ 450 s = splbpp(); 451 bpp_setparams(sc, chw); 452 splx(s); 453 break; 454 case BPPIOCGPARAM: 455 *((struct hwstate *)data) = sc->sc_hwcurrent; 456 break; 457 case TIOCEXCL: 458 s = splbpp(); 459 sc->sc_flags |= BPP_XCLUDE; 460 splx(s); 461 break; 462 case TIOCNXCL: 463 s = splbpp(); 464 sc->sc_flags &= ~BPP_XCLUDE; 465 splx(s); 466 break; 467 case FIOASYNC: 468 s = splbpp(); 469 if (*(int *)data) { 470 if (sc->sc_asyncproc != NULL) 471 error = EBUSY; 472 else 473 sc->sc_asyncproc = p; 474 } else 475 sc->sc_asyncproc = NULL; 476 splx(s); 477 break; 478 default: 479 break; 480 } 481 482 return (error); 483 } 484 485 int 486 bpppoll(dev, events, l) 487 dev_t dev; 488 int events; 489 struct lwp *l; 490 { 491 struct bpp_softc *sc = bpp_cd.cd_devs[BPPUNIT(dev)]; 492 int revents = 0; 493 494 if (events & (POLLIN | POLLRDNORM)) { 495 /* read is not yet implemented */ 496 } 497 498 if (events & (POLLOUT | POLLWRNORM)) { 499 if ((sc->sc_flags & BPP_LOCKED) == 0) 500 revents |= (POLLOUT | POLLWRNORM); 501 } 502 503 if (revents == 0) { 504 if (events & (POLLIN | POLLRDNORM)) 505 selrecord(l, &sc->sc_rsel); 506 if (events & (POLLOUT | POLLWRNORM)) 507 selrecord(l, &sc->sc_wsel); 508 } 509 510 return (revents); 511 } 512 513 static void 514 filt_bpprdetach(struct knote *kn) 515 { 516 struct bpp_softc *sc = kn->kn_hook; 517 int s; 518 519 s = splbpp(); 520 SLIST_REMOVE(&sc->sc_rsel.sel_klist, kn, knote, kn_selnext); 521 splx(s); 522 } 523 524 static int 525 filt_bppread(struct knote *kn, long hint) 526 { 527 /* XXX Read not yet implemented. */ 528 return (0); 529 } 530 531 static const struct filterops bppread_filtops = 532 { 1, NULL, filt_bpprdetach, filt_bppread }; 533 534 static void 535 filt_bppwdetach(struct knote *kn) 536 { 537 struct bpp_softc *sc = kn->kn_hook; 538 int s; 539 540 s = splbpp(); 541 SLIST_REMOVE(&sc->sc_wsel.sel_klist, kn, knote, kn_selnext); 542 splx(s); 543 } 544 545 static int 546 filt_bpfwrite(struct knote *kn, long hint) 547 { 548 struct bpp_softc *sc = kn->kn_hook; 549 550 if (sc->sc_flags & BPP_LOCKED) 551 return (0); 552 553 kn->kn_data = 0; /* XXXLUKEM (thorpej): what to put here? */ 554 return (1); 555 } 556 557 static const struct filterops bppwrite_filtops = 558 { 1, NULL, filt_bppwdetach, filt_bpfwrite }; 559 560 int 561 bppkqfilter(dev_t dev, struct knote *kn) 562 { 563 struct bpp_softc *sc = bpp_cd.cd_devs[BPPUNIT(dev)]; 564 struct klist *klist; 565 int s; 566 567 switch (kn->kn_filter) { 568 case EVFILT_READ: 569 klist = &sc->sc_rsel.sel_klist; 570 kn->kn_fop = &bppread_filtops; 571 break; 572 573 case EVFILT_WRITE: 574 klist = &sc->sc_wsel.sel_klist; 575 kn->kn_fop = &bppwrite_filtops; 576 break; 577 578 default: 579 return (EINVAL); 580 } 581 582 kn->kn_hook = sc; 583 584 s = splbpp(); 585 SLIST_INSERT_HEAD(klist, kn, kn_selnext); 586 splx(s); 587 588 return (0); 589 } 590 591 int 592 bppintr(arg) 593 void *arg; 594 { 595 struct bpp_softc *sc = arg; 596 struct lsi64854_softc *lsi = &sc->sc_lsi64854; 597 u_int16_t irq; 598 599 /* First handle any possible DMA interrupts */ 600 if (lsi64854_pp_intr((void *)lsi) == -1) 601 sc->sc_error = 1; 602 603 irq = bus_space_read_2(lsi->sc_bustag, lsi->sc_regs, L64854_REG_ICR); 604 /* Ack all interrupts */ 605 bus_space_write_2(lsi->sc_bustag, lsi->sc_regs, L64854_REG_ICR, 606 irq | BPP_ALLIRQ); 607 608 DPRINTF(("bpp_intr: %x\n", irq)); 609 /* Did our device interrupt? */ 610 if ((irq & BPP_ALLIRQ) == 0) 611 return (0); 612 613 if ((sc->sc_flags & BPP_LOCKED) != 0) 614 wakeup(sc); 615 else if ((sc->sc_flags & BPP_WANT) != 0) { 616 sc->sc_flags &= ~BPP_WANT; 617 wakeup(sc->sc_buf); 618 } else { 619 selnotify(&sc->sc_wsel, 0, 0); 620 if (sc->sc_asyncproc != NULL) { 621 mutex_enter(&proclist_mutex); 622 psignal(sc->sc_asyncproc, SIGIO); 623 mutex_exit(&proclist_mutex); 624 } 625 } 626 return (1); 627 } 628
Indexes created Thu Oct 02 14:10:14 GMT 2025