bpp.c revision 1.29.16.2
1 /* $NetBSD: bpp.c,v 1.29.16.2 2008/01/09 01:54:27 matt Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <sys/cdefs.h> 40 __KERNEL_RCSID(0, "$NetBSD: bpp.c,v 1.29.16.2 2008/01/09 01:54:27 matt Exp $"); 41 42 #include <sys/param.h> 43 #include <sys/ioctl.h> 44 #include <sys/fcntl.h> 45 #include <sys/systm.h> 46 #include <sys/kernel.h> 47 #include <sys/vnode.h> 48 #include <sys/poll.h> 49 #include <sys/select.h> 50 #include <sys/malloc.h> 51 #include <sys/proc.h> 52 #include <sys/signalvar.h> 53 #include <sys/conf.h> 54 #include <sys/errno.h> 55 #include <sys/device.h> 56 57 #include <sys/bus.h> 58 #include <sys/intr.h> 59 #include <machine/autoconf.h> 60 61 #include <dev/ic/lsi64854reg.h> 62 #include <dev/ic/lsi64854var.h> 63 64 #include <dev/sbus/sbusvar.h> 65 #include <dev/sbus/bppreg.h> 66 67 #define splbpp() spltty() /* XXX */ 68 69 #ifdef DEBUG 70 #define DPRINTF(x) do { if (bppdebug) printf x ; } while (0) 71 int bppdebug = 1; 72 #else 73 #define DPRINTF(x) 74 #endif 75 76 #if 0 77 struct bpp_param { 78 int bpp_dss; /* data setup to strobe */ 79 int bpp_dsw; /* data strobe width */ 80 int bpp_outputpins; /* Select/Autofeed/Init pins */ 81 int bpp_inputpins; /* Error/Select/Paperout pins */ 82 }; 83 #endif 84 85 struct hwstate { 86 u_int16_t hw_hcr; /* Hardware config register */ 87 u_int16_t hw_ocr; /* Operation config register */ 88 u_int8_t hw_tcr; /* Transfer Control register */ 89 u_int8_t hw_or; /* Output register */ 90 u_int16_t hw_irq; /* IRQ; polarity bits only */ 91 }; 92 93 struct bpp_softc { 94 struct lsi64854_softc sc_lsi64854; /* base device */ 95 struct sbusdev sc_sd; /* sbus device */ 96 97 size_t sc_bufsz; /* temp buffer */ 98 void * sc_buf; 99 100 int sc_error; /* bottom-half error */ 101 int sc_flags; 102 #define BPP_OPEN 0x01 /* Device is open */ 103 #define BPP_XCLUDE 0x02 /* Exclusive-open mode */ 104 #define BPP_ASYNC 0x04 /* Asynchronous I/O mode */ 105 #define BPP_LOCKED 0x08 /* DMA in progress */ 106 #define BPP_WANT 0x10 /* Waiting for DMA */ 107 108 struct selinfo sc_rsel; 109 struct selinfo sc_wsel; 110 struct proc *sc_asyncproc; /* Process to notify if async */ 111 112 /* Hardware state */ 113 struct hwstate sc_hwdefault; 114 struct hwstate sc_hwcurrent; 115 }; 116 117 static int bppmatch(struct device *, struct cfdata *, void *); 118 static void bppattach(struct device *, struct device *, void *); 119 static int bppintr (void *); 120 static void bpp_setparams(struct bpp_softc *, struct hwstate *); 121 122 CFATTACH_DECL(bpp, sizeof(struct bpp_softc), 123 bppmatch, bppattach, NULL, NULL); 124 125 extern struct cfdriver bpp_cd; 126 127 dev_type_open(bppopen); 128 dev_type_close(bppclose); 129 dev_type_write(bppwrite); 130 dev_type_ioctl(bppioctl); 131 dev_type_poll(bpppoll); 132 dev_type_kqfilter(bppkqfilter); 133 134 const struct cdevsw bpp_cdevsw = { 135 bppopen, bppclose, noread, bppwrite, bppioctl, 136 nostop, notty, bpppoll, nommap, bppkqfilter, D_TTY 137 }; 138 139 #define BPPUNIT(dev) (minor(dev)) 140 141 142 int 143 bppmatch(parent, cf, aux) 144 struct device *parent; 145 struct cfdata *cf; 146 void *aux; 147 { 148 struct sbus_attach_args *sa = aux; 149 150 return (strcmp("SUNW,bpp", sa->sa_name) == 0); 151 } 152 153 void 154 bppattach(parent, self, aux) 155 struct device *parent, *self; 156 void *aux; 157 { 158 struct sbus_attach_args *sa = aux; 159 struct bpp_softc *dsc = (void *)self; 160 struct lsi64854_softc *sc = &dsc->sc_lsi64854; 161 int burst, sbusburst; 162 int node; 163 164 sc->sc_bustag = sa->sa_bustag; 165 sc->sc_dmatag = sa->sa_dmatag; 166 node = sa->sa_node; 167 168 /* Map device registers */ 169 if (sbus_bus_map(sa->sa_bustag, 170 sa->sa_slot, sa->sa_offset, sa->sa_size, 171 0, &sc->sc_regs) != 0) { 172 printf("%s: cannot map registers\n", self->dv_xname); 173 return; 174 } 175 176 /* 177 * Get transfer burst size from PROM and plug it into the 178 * controller registers. This is needed on the Sun4m; do 179 * others need it too? 180 */ 181 sbusburst = ((struct sbus_softc *)parent)->sc_burst; 182 if (sbusburst == 0) 183 sbusburst = SBUS_BURST_32 - 1; /* 1->16 */ 184 185 burst = prom_getpropint(node, "burst-sizes", -1); 186 if (burst == -1) 187 /* take SBus burst sizes */ 188 burst = sbusburst; 189 190 /* Clamp at parent's burst sizes */ 191 burst &= sbusburst; 192 sc->sc_burst = (burst & SBUS_BURST_32) ? 32 : 193 (burst & SBUS_BURST_16) ? 16 : 0; 194 195 /* Join the Sbus device family */ 196 dsc->sc_sd.sd_reset = (void *)0; 197 sbus_establish(&dsc->sc_sd, self); 198 199 /* Initialize the DMA channel */ 200 sc->sc_channel = L64854_CHANNEL_PP; 201 lsi64854_attach(sc); 202 203 /* Establish interrupt handler */ 204 if (sa->sa_nintr) { 205 sc->sc_intrchain = bppintr; 206 sc->sc_intrchainarg = dsc; 207 (void)bus_intr_establish(sa->sa_bustag, sa->sa_pri, IPL_TTY, 208 bppintr, sc); 209 } 210 211 /* Allocate buffer XXX - should actually use dmamap_uio() */ 212 dsc->sc_bufsz = 1024; 213 dsc->sc_buf = malloc(dsc->sc_bufsz, M_DEVBUF, M_NOWAIT); 214 215 /* XXX read default state */ 216 { 217 bus_space_handle_t h = sc->sc_regs; 218 struct hwstate *hw = &dsc->sc_hwdefault; 219 int ack_rate = sa->sa_frequency/1000000; 220 221 hw->hw_hcr = bus_space_read_2(sc->sc_bustag, h, L64854_REG_HCR); 222 hw->hw_ocr = bus_space_read_2(sc->sc_bustag, h, L64854_REG_OCR); 223 hw->hw_tcr = bus_space_read_1(sc->sc_bustag, h, L64854_REG_TCR); 224 hw->hw_or = bus_space_read_1(sc->sc_bustag, h, L64854_REG_OR); 225 226 DPRINTF(("bpp: hcr %x ocr %x tcr %x or %x\n", 227 hw->hw_hcr, hw->hw_ocr, hw->hw_tcr, hw->hw_or)); 228 /* Set these to sane values */ 229 hw->hw_hcr = ((ack_rate<<BPP_HCR_DSS_SHFT)&BPP_HCR_DSS_MASK) 230 | ((ack_rate<<BPP_HCR_DSW_SHFT)&BPP_HCR_DSW_MASK); 231 hw->hw_ocr |= BPP_OCR_ACK_OP; 232 } 233 } 234 235 void 236 bpp_setparams(sc, hw) 237 struct bpp_softc *sc; 238 struct hwstate *hw; 239 { 240 u_int16_t irq; 241 bus_space_tag_t t = sc->sc_lsi64854.sc_bustag; 242 bus_space_handle_t h = sc->sc_lsi64854.sc_regs; 243 244 bus_space_write_2(t, h, L64854_REG_HCR, hw->hw_hcr); 245 bus_space_write_2(t, h, L64854_REG_OCR, hw->hw_ocr); 246 bus_space_write_1(t, h, L64854_REG_TCR, hw->hw_tcr); 247 bus_space_write_1(t, h, L64854_REG_OR, hw->hw_or); 248 249 /* Only change IRP settings in interrupt status register */ 250 irq = bus_space_read_2(t, h, L64854_REG_ICR); 251 irq &= ~BPP_ALLIRP; 252 irq |= (hw->hw_irq & BPP_ALLIRP); 253 bus_space_write_2(t, h, L64854_REG_ICR, irq); 254 DPRINTF(("bpp_setparams: hcr %x ocr %x tcr %x or %x, irq %x\n", 255 hw->hw_hcr, hw->hw_ocr, hw->hw_tcr, hw->hw_or, irq)); 256 } 257 258 int 259 bppopen(dev, flags, mode, l) 260 dev_t dev; 261 int flags, mode; 262 struct lwp *l; 263 { 264 int unit = BPPUNIT(dev); 265 struct bpp_softc *sc; 266 struct lsi64854_softc *lsi; 267 u_int16_t irq; 268 int s; 269 270 if (unit >= bpp_cd.cd_ndevs) 271 return (ENXIO); 272 sc = bpp_cd.cd_devs[unit]; 273 274 if ((sc->sc_flags & (BPP_OPEN|BPP_XCLUDE)) == (BPP_OPEN|BPP_XCLUDE)) 275 return (EBUSY); 276 277 lsi = &sc->sc_lsi64854; 278 279 /* Set default parameters */ 280 sc->sc_hwcurrent = sc->sc_hwdefault; 281 s = splbpp(); 282 bpp_setparams(sc, &sc->sc_hwdefault); 283 splx(s); 284 285 /* Enable interrupts */ 286 irq = BPP_ERR_IRQ_EN; 287 irq |= sc->sc_hwdefault.hw_irq; 288 bus_space_write_2(lsi->sc_bustag, lsi->sc_regs, L64854_REG_ICR, irq); 289 return (0); 290 } 291 292 int 293 bppclose(dev, flags, mode, l) 294 dev_t dev; 295 int flags, mode; 296 struct lwp *l; 297 { 298 struct bpp_softc *sc = bpp_cd.cd_devs[BPPUNIT(dev)]; 299 struct lsi64854_softc *lsi = &sc->sc_lsi64854; 300 u_int16_t irq; 301 302 /* Turn off all interrupt enables */ 303 irq = sc->sc_hwdefault.hw_irq | BPP_ALLIRQ; 304 irq &= ~BPP_ALLEN; 305 bus_space_write_2(lsi->sc_bustag, lsi->sc_regs, L64854_REG_ICR, irq); 306 307 sc->sc_asyncproc = NULL; 308 sc->sc_flags = 0; 309 return (0); 310 } 311 312 int 313 bppwrite(dev, uio, flags) 314 dev_t dev; 315 struct uio *uio; 316 int flags; 317 { 318 struct bpp_softc *sc = bpp_cd.cd_devs[BPPUNIT(dev)]; 319 struct lsi64854_softc *lsi = &sc->sc_lsi64854; 320 int error = 0; 321 int s; 322 323 /* 324 * Wait until the DMA engine is free. 325 */ 326 s = splbpp(); 327 while ((sc->sc_flags & BPP_LOCKED) != 0) { 328 if ((flags & IO_NDELAY) != 0) { 329 splx(s); 330 return (EWOULDBLOCK); 331 } 332 333 sc->sc_flags |= BPP_WANT; 334 error = tsleep(sc->sc_buf, PZERO|PCATCH, "bppwrite", 0); 335 if (error != 0) { 336 splx(s); 337 return (error); 338 } 339 } 340 sc->sc_flags |= BPP_LOCKED; 341 splx(s); 342 343 /* 344 * Move data from user space into our private buffer 345 * and start DMA. 346 */ 347 while (uio->uio_resid > 0) { 348 void *bp = sc->sc_buf; 349 size_t len = min(sc->sc_bufsz, uio->uio_resid); 350 351 if ((error = uiomove(bp, len, uio)) != 0) 352 break; 353 354 while (len > 0) { 355 u_int8_t tcr; 356 size_t size = len; 357 DMA_SETUP(lsi, &bp, &len, 0, &size); 358 359 #ifdef DEBUG 360 if (bppdebug) { 361 int i; 362 unsigned char *b = bp; 363 printf("bpp: writing %ld : ", len); 364 for (i=0; i<len; i++) printf("%c(0x%x)", b[i], 365 b[i]); 366 printf("\n"); 367 } 368 #endif 369 370 /* Clear direction control bit */ 371 tcr = bus_space_read_1(lsi->sc_bustag, lsi->sc_regs, 372 L64854_REG_TCR); 373 tcr &= ~BPP_TCR_DIR; 374 bus_space_write_1(lsi->sc_bustag, lsi->sc_regs, 375 L64854_REG_TCR, tcr); 376 377 /* Enable DMA */ 378 s = splbpp(); 379 DMA_GO(lsi); 380 error = tsleep(sc, PZERO|PCATCH, "bppdma", 0); 381 splx(s); 382 if (error != 0) 383 goto out; 384 385 /* Bail out if bottom half reported an error */ 386 if ((error = sc->sc_error) != 0) 387 goto out; 388 389 /* 390 * lsi64854_pp_intr() does this part. 391 * 392 * len -= size; 393 */ 394 } 395 } 396 397 out: 398 DPRINTF(("bpp done %x\n", error)); 399 s = splbpp(); 400 sc->sc_flags &= ~BPP_LOCKED; 401 if ((sc->sc_flags & BPP_WANT) != 0) { 402 sc->sc_flags &= ~BPP_WANT; 403 wakeup(sc->sc_buf); 404 } 405 splx(s); 406 return (error); 407 } 408 409 /* move to header: */ 410 #define BPPIOCSPARAM _IOW('P', 0x1, struct hwstate) 411 #define BPPIOCGPARAM _IOR('P', 0x2, struct hwstate) 412 413 int 414 bppioctl(dev, cmd, data, flag, l) 415 dev_t dev; 416 u_long cmd; 417 void * data; 418 int flag; 419 struct lwp *l; 420 { 421 struct bpp_softc *sc = bpp_cd.cd_devs[BPPUNIT(dev)]; 422 struct proc *p = l->l_proc; 423 struct hwstate *hw, *chw; 424 int error = 0; 425 int s; 426 427 switch(cmd) { 428 case BPPIOCSPARAM: 429 chw = &sc->sc_hwcurrent; 430 hw = (struct hwstate *)data; 431 432 /* 433 * Extract and store user-settable bits. 434 */ 435 #define _bpp_set(reg,mask) do { \ 436 chw->reg &= ~(mask); \ 437 chw->reg |= (hw->reg & (mask)); \ 438 } while (0) 439 _bpp_set(hw_hcr, BPP_HCR_DSS_MASK|BPP_HCR_DSW_MASK); 440 _bpp_set(hw_ocr, BPP_OCR_USER); 441 _bpp_set(hw_tcr, BPP_TCR_USER); 442 _bpp_set(hw_or, BPP_OR_USER); 443 _bpp_set(hw_irq, BPP_IRQ_USER); 444 #undef _bpp_set 445 446 /* Apply settings */ 447 s = splbpp(); 448 bpp_setparams(sc, chw); 449 splx(s); 450 break; 451 case BPPIOCGPARAM: 452 *((struct hwstate *)data) = sc->sc_hwcurrent; 453 break; 454 case TIOCEXCL: 455 s = splbpp(); 456 sc->sc_flags |= BPP_XCLUDE; 457 splx(s); 458 break; 459 case TIOCNXCL: 460 s = splbpp(); 461 sc->sc_flags &= ~BPP_XCLUDE; 462 splx(s); 463 break; 464 case FIOASYNC: 465 s = splbpp(); 466 if (*(int *)data) { 467 if (sc->sc_asyncproc != NULL) 468 error = EBUSY; 469 else 470 sc->sc_asyncproc = p; 471 } else 472 sc->sc_asyncproc = NULL; 473 splx(s); 474 break; 475 default: 476 break; 477 } 478 479 return (error); 480 } 481 482 int 483 bpppoll(dev, events, l) 484 dev_t dev; 485 int events; 486 struct lwp *l; 487 { 488 struct bpp_softc *sc = bpp_cd.cd_devs[BPPUNIT(dev)]; 489 int revents = 0; 490 491 if (events & (POLLIN | POLLRDNORM)) { 492 /* read is not yet implemented */ 493 } 494 495 if (events & (POLLOUT | POLLWRNORM)) { 496 if ((sc->sc_flags & BPP_LOCKED) == 0) 497 revents |= (POLLOUT | POLLWRNORM); 498 } 499 500 if (revents == 0) { 501 if (events & (POLLIN | POLLRDNORM)) 502 selrecord(l, &sc->sc_rsel); 503 if (events & (POLLOUT | POLLWRNORM)) 504 selrecord(l, &sc->sc_wsel); 505 } 506 507 return (revents); 508 } 509 510 static void 511 filt_bpprdetach(struct knote *kn) 512 { 513 struct bpp_softc *sc = kn->kn_hook; 514 int s; 515 516 s = splbpp(); 517 SLIST_REMOVE(&sc->sc_rsel.sel_klist, kn, knote, kn_selnext); 518 splx(s); 519 } 520 521 static int 522 filt_bppread(struct knote *kn, long hint) 523 { 524 /* XXX Read not yet implemented. */ 525 return (0); 526 } 527 528 static const struct filterops bppread_filtops = 529 { 1, NULL, filt_bpprdetach, filt_bppread }; 530 531 static void 532 filt_bppwdetach(struct knote *kn) 533 { 534 struct bpp_softc *sc = kn->kn_hook; 535 int s; 536 537 s = splbpp(); 538 SLIST_REMOVE(&sc->sc_wsel.sel_klist, kn, knote, kn_selnext); 539 splx(s); 540 } 541 542 static int 543 filt_bpfwrite(struct knote *kn, long hint) 544 { 545 struct bpp_softc *sc = kn->kn_hook; 546 547 if (sc->sc_flags & BPP_LOCKED) 548 return (0); 549 550 kn->kn_data = 0; /* XXXLUKEM (thorpej): what to put here? */ 551 return (1); 552 } 553 554 static const struct filterops bppwrite_filtops = 555 { 1, NULL, filt_bppwdetach, filt_bpfwrite }; 556 557 int 558 bppkqfilter(dev_t dev, struct knote *kn) 559 { 560 struct bpp_softc *sc = bpp_cd.cd_devs[BPPUNIT(dev)]; 561 struct klist *klist; 562 int s; 563 564 switch (kn->kn_filter) { 565 case EVFILT_READ: 566 klist = &sc->sc_rsel.sel_klist; 567 kn->kn_fop = &bppread_filtops; 568 break; 569 570 case EVFILT_WRITE: 571 klist = &sc->sc_wsel.sel_klist; 572 kn->kn_fop = &bppwrite_filtops; 573 break; 574 575 default: 576 return (EINVAL); 577 } 578 579 kn->kn_hook = sc; 580 581 s = splbpp(); 582 SLIST_INSERT_HEAD(klist, kn, kn_selnext); 583 splx(s); 584 585 return (0); 586 } 587 588 int 589 bppintr(arg) 590 void *arg; 591 { 592 struct bpp_softc *sc = arg; 593 struct lsi64854_softc *lsi = &sc->sc_lsi64854; 594 u_int16_t irq; 595 596 /* First handle any possible DMA interrupts */ 597 if (lsi64854_pp_intr((void *)lsi) == -1) 598 sc->sc_error = 1; 599 600 irq = bus_space_read_2(lsi->sc_bustag, lsi->sc_regs, L64854_REG_ICR); 601 /* Ack all interrupts */ 602 bus_space_write_2(lsi->sc_bustag, lsi->sc_regs, L64854_REG_ICR, 603 irq | BPP_ALLIRQ); 604 605 DPRINTF(("bpp_intr: %x\n", irq)); 606 /* Did our device interrupt? */ 607 if ((irq & BPP_ALLIRQ) == 0) 608 return (0); 609 610 if ((sc->sc_flags & BPP_LOCKED) != 0) 611 wakeup(sc); 612 else if ((sc->sc_flags & BPP_WANT) != 0) { 613 sc->sc_flags &= ~BPP_WANT; 614 wakeup(sc->sc_buf); 615 } else { 616 selnotify(&sc->sc_wsel, 0); 617 if (sc->sc_asyncproc != NULL) { 618 mutex_enter(&proclist_mutex); 619 psignal(sc->sc_asyncproc, SIGIO); 620 mutex_exit(&proclist_mutex); 621 } 622 } 623 return (1); 624 } 625
Indexes created Thu Oct 02 14:10:14 GMT 2025