bpp.c revision 1.3.2.1
1 /* $NetBSD: bpp.c,v 1.3.2.1 2000/06/22 17:08:06 minoura Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <sys/param.h> 40 #include <sys/ioctl.h> 41 #include <sys/fcntl.h> 42 #include <sys/systm.h> 43 #include <sys/kernel.h> 44 #include <sys/vnode.h> 45 #include <sys/poll.h> 46 #include <sys/select.h> 47 #include <sys/malloc.h> 48 #include <sys/proc.h> 49 #include <sys/signalvar.h> 50 #include <sys/conf.h> 51 #include <sys/errno.h> 52 #include <sys/device.h> 53 54 #include <machine/conf.h> 55 #include <machine/bus.h> 56 #include <machine/autoconf.h> 57 58 #include <dev/ic/lsi64854reg.h> 59 #include <dev/ic/lsi64854var.h> 60 61 #include <dev/sbus/sbusvar.h> 62 #include <dev/sbus/bppreg.h> 63 64 #define splbpp() spltty() /* XXX */ 65 66 #if 0 67 struct bpp_param { 68 int bpp_dss; /* data setup to strobe */ 69 int bpp_dsw; /* data strobe width */ 70 int bpp_outputpins; /* Select/Autofeed/Init pins */ 71 int bpp_inputpins; /* Error/Select/Paperout pins */ 72 }; 73 #endif 74 75 struct hwstate { 76 u_int16_t hw_hcr; /* Hardware config register */ 77 u_int16_t hw_ocr; /* Operation config register */ 78 u_int8_t hw_tcr; /* Transfer Control register */ 79 u_int8_t hw_or; /* Output register */ 80 u_int16_t hw_irq; /* IRQ; polarity bits only */ 81 }; 82 83 struct bpp_softc { 84 struct lsi64854_softc sc_lsi64854; /* base device */ 85 struct sbusdev sc_sd; /* sbus device */ 86 87 size_t sc_bufsz; /* temp buffer */ 88 caddr_t sc_buf; 89 90 int sc_error; /* bottom-half error */ 91 int sc_flags; 92 #define BPP_OPEN 0x01 /* Device is open */ 93 #define BPP_XCLUDE 0x02 /* Exclusive-open mode */ 94 #define BPP_ASYNC 0x04 /* Asynchronous I/O mode */ 95 #define BPP_LOCKED 0x08 /* DMA in progress */ 96 #define BPP_WANT 0x10 /* Waiting for DMA */ 97 98 struct selinfo sc_rsel; 99 struct selinfo sc_wsel; 100 struct proc *sc_asyncproc; /* Process to notify if async */ 101 102 /* Hardware state */ 103 struct hwstate sc_hwdefault; 104 struct hwstate sc_hwcurrent; 105 }; 106 107 static int bppmatch __P((struct device *, struct cfdata *, void *)); 108 static void bppattach __P((struct device *, struct device *, void *)); 109 static int bppintr __P((void *)); 110 static void bpp_setparams __P((struct bpp_softc *, struct hwstate *)); 111 112 struct cfattach bpp_ca = { 113 sizeof(struct bpp_softc), bppmatch, bppattach 114 }; 115 116 extern struct cfdriver bpp_cd; 117 #define BPPUNIT(dev) (minor(dev)) 118 119 120 int 121 bppmatch(parent, cf, aux) 122 struct device *parent; 123 struct cfdata *cf; 124 void *aux; 125 { 126 struct sbus_attach_args *sa = aux; 127 128 return (strcmp("SUNW,bpp", sa->sa_name) == 0); 129 } 130 131 void 132 bppattach(parent, self, aux) 133 struct device *parent, *self; 134 void *aux; 135 { 136 struct sbus_attach_args *sa = aux; 137 struct bpp_softc *dsc = (void *)self; 138 struct lsi64854_softc *sc = &dsc->sc_lsi64854; 139 int burst, sbusburst; 140 int node; 141 142 sc->sc_bustag = sa->sa_bustag; 143 sc->sc_dmatag = sa->sa_dmatag; 144 node = sa->sa_node; 145 146 /* Map device registers */ 147 if (bus_space_map2(sa->sa_bustag, 148 sa->sa_slot, 149 sa->sa_offset, 150 sa->sa_size, 151 BUS_SPACE_MAP_LINEAR, 152 0, &sc->sc_regs) != 0) { 153 printf("%s: cannot map registers\n", self->dv_xname); 154 return; 155 } 156 157 /* 158 * Get transfer burst size from PROM and plug it into the 159 * controller registers. This is needed on the Sun4m; do 160 * others need it too? 161 */ 162 sbusburst = ((struct sbus_softc *)parent)->sc_burst; 163 if (sbusburst == 0) 164 sbusburst = SBUS_BURST_32 - 1; /* 1->16 */ 165 166 burst = getpropint(node, "burst-sizes", -1); 167 if (burst == -1) 168 /* take SBus burst sizes */ 169 burst = sbusburst; 170 171 /* Clamp at parent's burst sizes */ 172 burst &= sbusburst; 173 sc->sc_burst = (burst & SBUS_BURST_32) ? 32 : 174 (burst & SBUS_BURST_16) ? 16 : 0; 175 176 /* Join the Sbus device family */ 177 dsc->sc_sd.sd_reset = (void *)0; 178 sbus_establish(&dsc->sc_sd, self); 179 180 /* Initialize the DMA channel */ 181 sc->sc_channel = L64854_CHANNEL_PP; 182 lsi64854_attach(sc); 183 184 /* Establish interrupt handler */ 185 if (sa->sa_nintr) { 186 sc->sc_intrchain = bppintr; 187 sc->sc_intrchainarg = dsc; 188 (void)bus_intr_establish(sa->sa_bustag, sa->sa_pri, 0, 189 lsi64854_pp_intr, sc); 190 } 191 192 /* Allocate buffer XXX - should actually use dmamap_uio() */ 193 dsc->sc_bufsz = 1024; 194 dsc->sc_buf = malloc(dsc->sc_bufsz, M_DEVBUF, M_NOWAIT); 195 196 /* XXX read default state */ 197 { 198 bus_space_handle_t h = sc->sc_regs; 199 struct hwstate *hw = &dsc->sc_hwdefault; 200 hw->hw_hcr = bus_space_read_2(sc->sc_bustag, h, L64854_REG_HCR); 201 hw->hw_ocr = bus_space_read_2(sc->sc_bustag, h, L64854_REG_OCR); 202 hw->hw_tcr = bus_space_read_1(sc->sc_bustag, h, L64854_REG_TCR); 203 hw->hw_or = bus_space_read_1(sc->sc_bustag, h, L64854_REG_OR); 204 } 205 } 206 207 void 208 bpp_setparams(sc, hw) 209 struct bpp_softc *sc; 210 struct hwstate *hw; 211 { 212 u_int16_t irq; 213 bus_space_tag_t t = sc->sc_lsi64854.sc_bustag; 214 bus_space_handle_t h = sc->sc_lsi64854.sc_regs; 215 216 bus_space_write_2(t, h, L64854_REG_HCR, hw->hw_hcr); 217 bus_space_write_2(t, h, L64854_REG_OCR, hw->hw_ocr); 218 bus_space_write_1(t, h, L64854_REG_TCR, hw->hw_tcr); 219 bus_space_write_1(t, h, L64854_REG_OR, hw->hw_or); 220 221 /* Only change IRP settings in interrupt status register */ 222 irq = bus_space_read_2(t, h, L64854_REG_ICR); 223 irq &= ~BPP_ALLIRP; 224 irq |= (hw->hw_irq & BPP_ALLIRP); 225 bus_space_write_2(t, h, L64854_REG_ICR, irq); 226 } 227 228 int 229 bppopen(dev, flags, mode, p) 230 dev_t dev; 231 int flags, mode; 232 struct proc *p; 233 { 234 int unit = BPPUNIT(dev); 235 struct bpp_softc *sc; 236 struct lsi64854_softc *lsi; 237 u_int16_t irq; 238 int s; 239 240 if (unit >= bpp_cd.cd_ndevs) 241 return (ENXIO); 242 sc = bpp_cd.cd_devs[unit]; 243 244 if ((sc->sc_flags & (BPP_OPEN|BPP_XCLUDE)) == (BPP_OPEN|BPP_XCLUDE)) 245 return (EBUSY); 246 247 lsi = &sc->sc_lsi64854; 248 249 /* Set default parameters */ 250 sc->sc_hwcurrent = sc->sc_hwdefault; 251 s = splbpp(); 252 bpp_setparams(sc, &sc->sc_hwdefault); 253 splx(s); 254 255 /* Enable interrupts */ 256 irq = BPP_ALLEN; 257 irq |= sc->sc_hwdefault.hw_irq; 258 bus_space_write_2(lsi->sc_bustag, lsi->sc_regs, L64854_REG_ICR, irq); 259 return (0); 260 } 261 262 int 263 bppclose(dev, flags, mode, p) 264 dev_t dev; 265 int flags, mode; 266 struct proc *p; 267 { 268 struct bpp_softc *sc = bpp_cd.cd_devs[BPPUNIT(dev)]; 269 struct lsi64854_softc *lsi = &sc->sc_lsi64854; 270 u_int16_t irq; 271 272 /* Turn off all interrupt enables */ 273 irq = sc->sc_hwdefault.hw_irq | BPP_ALLIRQ; 274 irq &= ~BPP_ALLEN; 275 bus_space_write_2(lsi->sc_bustag, lsi->sc_regs, L64854_REG_ICR, irq); 276 277 sc->sc_asyncproc = NULL; 278 sc->sc_flags = 0; 279 return (0); 280 } 281 282 int 283 bppread(dev, uio, flags) 284 dev_t dev; 285 struct uio *uio; 286 int flags; 287 { 288 289 return (ENXIO); 290 } 291 292 int 293 bppwrite(dev, uio, flags) 294 dev_t dev; 295 struct uio *uio; 296 int flags; 297 { 298 struct bpp_softc *sc = bpp_cd.cd_devs[BPPUNIT(dev)]; 299 struct lsi64854_softc *lsi = &sc->sc_lsi64854; 300 int error = 0; 301 int s; 302 303 /* 304 * Wait until the DMA engine is free. 305 */ 306 s = splbpp(); 307 while ((sc->sc_flags & BPP_LOCKED) != 0) { 308 if ((flags & IO_NDELAY) != 0) { 309 splx(s); 310 return (EWOULDBLOCK); 311 } 312 313 sc->sc_flags |= BPP_WANT; 314 error = tsleep(sc->sc_buf, PZERO|PCATCH, "bppwrite", 0); 315 if (error != 0) { 316 splx(s); 317 return (error); 318 } 319 } 320 sc->sc_flags |= BPP_LOCKED; 321 splx(s); 322 323 /* 324 * Move data from user space into our private buffer 325 * and start DMA. 326 */ 327 while (uio->uio_resid > 0) { 328 caddr_t bp = sc->sc_buf; 329 size_t len = min(sc->sc_bufsz, uio->uio_resid); 330 331 if ((error = uiomove(bp, len, uio)) != 0) 332 break; 333 334 while (len > 0) { 335 u_int8_t tcr; 336 size_t size = len; 337 DMA_SETUP(lsi, &bp, &len, 0, &size); 338 339 /* Clear direction control bit */ 340 tcr = bus_space_read_1(lsi->sc_bustag, lsi->sc_regs, 341 L64854_REG_TCR); 342 tcr &= ~BPP_TCR_DIR; 343 bus_space_write_1(lsi->sc_bustag, lsi->sc_regs, 344 L64854_REG_TCR, tcr); 345 346 /* Enable DMA */ 347 s = splbpp(); 348 DMA_GO(lsi); 349 error = tsleep(sc, PZERO|PCATCH, "bppdma", 0); 350 splx(s); 351 if (error != 0) 352 goto out; 353 354 /* Bail out if bottom half reported an error */ 355 if ((error = sc->sc_error) != 0) 356 goto out; 357 358 len -= size; 359 } 360 } 361 362 out: 363 s = splbpp(); 364 sc->sc_flags &= ~BPP_LOCKED; 365 if ((sc->sc_flags & BPP_WANT) != 0) { 366 sc->sc_flags &= ~BPP_WANT; 367 wakeup(sc->sc_buf); 368 } 369 splx(s); 370 return (error); 371 } 372 373 /* move to header: */ 374 #define BPPIOCSPARAM _IOW('P', 0x1, struct hwstate) 375 #define BPPIOCGPARAM _IOR('P', 0x2, struct hwstate) 376 377 int 378 bppioctl(dev, cmd, data, flag, p) 379 dev_t dev; 380 u_long cmd; 381 caddr_t data; 382 int flag; 383 struct proc *p; 384 { 385 struct bpp_softc *sc = bpp_cd.cd_devs[BPPUNIT(dev)]; 386 struct hwstate *hw, *chw; 387 int error = 0; 388 int s; 389 390 switch(cmd) { 391 case BPPIOCSPARAM: 392 chw = &sc->sc_hwcurrent; 393 hw = (struct hwstate *)data; 394 395 /* 396 * Extract and store user-settable bits. 397 */ 398 #define _bpp_set(reg,mask) do { \ 399 chw->reg &= ~(mask); \ 400 chw->reg |= (hw->reg & (mask)); \ 401 } while (0) 402 _bpp_set(hw_hcr, BPP_HCR_DSS_MASK|BPP_HCR_DSW_MASK); 403 _bpp_set(hw_ocr, BPP_OCR_USER); 404 _bpp_set(hw_tcr, BPP_TCR_USER); 405 _bpp_set(hw_or, BPP_OR_USER); 406 _bpp_set(hw_irq, BPP_IRQ_USER); 407 #undef _bpp_set 408 409 /* Apply settings */ 410 s = splbpp(); 411 bpp_setparams(sc, chw); 412 splx(s); 413 break; 414 case BPPIOCGPARAM: 415 *((struct hwstate *)data) = sc->sc_hwcurrent; 416 break; 417 case TIOCEXCL: 418 s = splbpp(); 419 sc->sc_flags |= BPP_XCLUDE; 420 splx(s); 421 break; 422 case TIOCNXCL: 423 s = splbpp(); 424 sc->sc_flags &= ~BPP_XCLUDE; 425 splx(s); 426 break; 427 case FIOASYNC: 428 s = splbpp(); 429 if (*(int *)data) { 430 if (sc->sc_asyncproc != NULL) 431 error = EBUSY; 432 else 433 sc->sc_asyncproc = p; 434 } else 435 sc->sc_asyncproc = NULL; 436 splx(s); 437 break; 438 default: 439 break; 440 } 441 442 return (error); 443 } 444 445 int 446 bpppoll(dev, events, p) 447 dev_t dev; 448 int events; 449 struct proc *p; 450 { 451 struct bpp_softc *sc = bpp_cd.cd_devs[BPPUNIT(dev)]; 452 int revents = 0; 453 454 if (events & (POLLIN | POLLRDNORM)) { 455 /* read is not yet implemented */ 456 } 457 458 if (events & (POLLOUT | POLLWRNORM)) { 459 if ((sc->sc_flags & BPP_LOCKED) == 0) 460 revents |= (POLLOUT | POLLWRNORM); 461 } 462 463 if (revents == 0) { 464 if (events & (POLLIN | POLLRDNORM)) 465 selrecord(p, &sc->sc_rsel); 466 if (events & (POLLOUT | POLLWRNORM)) 467 selrecord(p, &sc->sc_wsel); 468 } 469 470 return (revents); 471 } 472 473 int 474 bppintr(arg) 475 void *arg; 476 { 477 struct bpp_softc *sc = arg; 478 struct lsi64854_softc *lsi = &sc->sc_lsi64854; 479 u_int16_t irq; 480 481 irq = bus_space_read_2(lsi->sc_bustag, lsi->sc_regs, L64854_REG_ICR); 482 /* Ack all interrupts */ 483 bus_space_write_2(lsi->sc_bustag, lsi->sc_regs, L64854_REG_ICR, 484 irq | BPP_ALLIRQ); 485 486 /* Did our device interrupt? */ 487 if ((irq & BPP_ALLIRQ) == 0) 488 return (0); 489 490 if ((sc->sc_flags & BPP_LOCKED) != 0) 491 wakeup(sc); 492 else if ((sc->sc_flags & BPP_WANT) != 0) { 493 sc->sc_flags &= ~BPP_WANT; 494 wakeup(sc->sc_buf); 495 } else { 496 selwakeup(&sc->sc_wsel); 497 if (sc->sc_asyncproc != NULL) 498 psignal(sc->sc_asyncproc, SIGIO); 499 } 500 return (1); 501 } 502
Indexes created Thu Oct 02 14:10:14 GMT 2025