bpp.c revision 1.38
1 /* $NetBSD: bpp.c,v 1.38 2008/04/28 20:23:57 martin Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: bpp.c,v 1.38 2008/04/28 20:23:57 martin Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/ioctl.h> 37 #include <sys/fcntl.h> 38 #include <sys/systm.h> 39 #include <sys/kernel.h> 40 #include <sys/vnode.h> 41 #include <sys/poll.h> 42 #include <sys/select.h> 43 #include <sys/malloc.h> 44 #include <sys/proc.h> 45 #include <sys/signalvar.h> 46 #include <sys/conf.h> 47 #include <sys/errno.h> 48 #include <sys/device.h> 49 #include <sys/bus.h> 50 #include <sys/intr.h> 51 52 #include <machine/autoconf.h> 53 54 #include <dev/ic/lsi64854reg.h> 55 #include <dev/ic/lsi64854var.h> 56 57 #include <dev/sbus/sbusvar.h> 58 #include <dev/sbus/bppreg.h> 59 60 #include "ioconf.h" 61 62 #define splbpp() spltty() /* XXX */ 63 64 #ifdef DEBUG 65 #define DPRINTF(x) do { if (bppdebug) printf x ; } while (0) 66 int bppdebug = 1; 67 #else 68 #define DPRINTF(x) 69 #endif 70 71 #if 0 72 struct bpp_param { 73 int bpp_dss; /* data setup to strobe */ 74 int bpp_dsw; /* data strobe width */ 75 int bpp_outputpins; /* Select/Autofeed/Init pins */ 76 int bpp_inputpins; /* Error/Select/Paperout pins */ 77 }; 78 #endif 79 80 struct hwstate { 81 uint16_t hw_hcr; /* Hardware config register */ 82 uint16_t hw_ocr; /* Operation config register */ 83 uint8_t hw_tcr; /* Transfer Control register */ 84 uint8_t hw_or; /* Output register */ 85 uint16_t hw_irq; /* IRQ; polarity bits only */ 86 }; 87 88 struct bpp_softc { 89 struct lsi64854_softc sc_lsi64854; /* base device */ 90 struct sbusdev sc_sd; /* sbus device */ 91 92 size_t sc_bufsz; /* temp buffer */ 93 uint8_t *sc_buf; 94 95 int sc_error; /* bottom-half error */ 96 int sc_flags; 97 #define BPP_OPEN 0x01 /* Device is open */ 98 #define BPP_XCLUDE 0x02 /* Exclusive-open mode */ 99 #define BPP_ASYNC 0x04 /* Asynchronous I/O mode */ 100 #define BPP_LOCKED 0x08 /* DMA in progress */ 101 #define BPP_WANT 0x10 /* Waiting for DMA */ 102 103 struct selinfo sc_rsel; 104 struct selinfo sc_wsel; 105 struct proc *sc_asyncproc; /* Process to notify if async */ 106 void *sc_sih; 107 108 /* Hardware state */ 109 struct hwstate sc_hwdefault; 110 struct hwstate sc_hwcurrent; 111 }; 112 113 static int bppmatch(device_t, cfdata_t, void *); 114 static void bppattach(device_t, device_t, void *); 115 static int bppintr(void *); 116 static void bppsoftintr(void *); 117 static void bpp_setparams(struct bpp_softc *, struct hwstate *); 118 119 CFATTACH_DECL_NEW(bpp, sizeof(struct bpp_softc), 120 bppmatch, bppattach, NULL, NULL); 121 122 dev_type_open(bppopen); 123 dev_type_close(bppclose); 124 dev_type_write(bppwrite); 125 dev_type_ioctl(bppioctl); 126 dev_type_poll(bpppoll); 127 dev_type_kqfilter(bppkqfilter); 128 129 const struct cdevsw bpp_cdevsw = { 130 bppopen, bppclose, noread, bppwrite, bppioctl, 131 nostop, notty, bpppoll, nommap, bppkqfilter, D_TTY 132 }; 133 134 #define BPPUNIT(dev) (minor(dev)) 135 136 137 int 138 bppmatch(device_t parent, cfdata_t cf, void *aux) 139 { 140 struct sbus_attach_args *sa = aux; 141 142 return strcmp("SUNW,bpp", sa->sa_name) == 0; 143 } 144 145 void 146 bppattach(device_t parent, device_t self, void *aux) 147 { 148 struct bpp_softc *dsc = device_private(self); 149 struct lsi64854_softc *sc = &dsc->sc_lsi64854; 150 struct sbus_softc *sbsc = device_private(parent); 151 struct sbus_attach_args *sa = aux; 152 int burst, sbusburst; 153 int node; 154 155 sc->sc_dev = self; 156 157 selinit(&dsc->sc_rsel); 158 selinit(&dsc->sc_wsel); 159 dsc->sc_sih = softint_establish(SOFTINT_CLOCK, bppsoftintr, dsc); 160 161 sc->sc_bustag = sa->sa_bustag; 162 sc->sc_dmatag = sa->sa_dmatag; 163 node = sa->sa_node; 164 165 /* Map device registers */ 166 if (sbus_bus_map(sa->sa_bustag, 167 sa->sa_slot, sa->sa_offset, sa->sa_size, 168 0, &sc->sc_regs) != 0) { 169 aprint_error(": cannot map registers\n"); 170 return; 171 } 172 173 /* 174 * Get transfer burst size from PROM and plug it into the 175 * controller registers. This is needed on the Sun4m; do 176 * others need it too? 177 */ 178 sbusburst = sbsc->sc_burst; 179 if (sbusburst == 0) 180 sbusburst = SBUS_BURST_32 - 1; /* 1->16 */ 181 182 burst = prom_getpropint(node, "burst-sizes", -1); 183 if (burst == -1) 184 /* take SBus burst sizes */ 185 burst = sbusburst; 186 187 /* Clamp at parent's burst sizes */ 188 burst &= sbusburst; 189 sc->sc_burst = (burst & SBUS_BURST_32) ? 32 : 190 (burst & SBUS_BURST_16) ? 16 : 0; 191 192 /* Join the Sbus device family */ 193 dsc->sc_sd.sd_reset = NULL; 194 sbus_establish(&dsc->sc_sd, self); 195 196 /* Initialize the DMA channel */ 197 sc->sc_channel = L64854_CHANNEL_PP; 198 lsi64854_attach(sc); 199 200 /* Establish interrupt handler */ 201 if (sa->sa_nintr) { 202 sc->sc_intrchain = bppintr; 203 sc->sc_intrchainarg = dsc; 204 (void)bus_intr_establish(sa->sa_bustag, sa->sa_pri, IPL_TTY, 205 bppintr, sc); 206 } 207 208 /* Allocate buffer XXX - should actually use dmamap_uio() */ 209 dsc->sc_bufsz = 1024; 210 dsc->sc_buf = malloc(dsc->sc_bufsz, M_DEVBUF, M_NOWAIT); 211 212 /* XXX read default state */ 213 { 214 bus_space_handle_t h = sc->sc_regs; 215 struct hwstate *hw = &dsc->sc_hwdefault; 216 int ack_rate = sa->sa_frequency / 1000000; 217 218 hw->hw_hcr = bus_space_read_2(sc->sc_bustag, h, L64854_REG_HCR); 219 hw->hw_ocr = bus_space_read_2(sc->sc_bustag, h, L64854_REG_OCR); 220 hw->hw_tcr = bus_space_read_1(sc->sc_bustag, h, L64854_REG_TCR); 221 hw->hw_or = bus_space_read_1(sc->sc_bustag, h, L64854_REG_OR); 222 223 DPRINTF(("bpp: hcr %x ocr %x tcr %x or %x\n", 224 hw->hw_hcr, hw->hw_ocr, hw->hw_tcr, hw->hw_or)); 225 /* Set these to sane values */ 226 hw->hw_hcr = ((ack_rate<<BPP_HCR_DSS_SHFT)&BPP_HCR_DSS_MASK) 227 | ((ack_rate<<BPP_HCR_DSW_SHFT)&BPP_HCR_DSW_MASK); 228 hw->hw_ocr |= BPP_OCR_ACK_OP; 229 } 230 } 231 232 void 233 bpp_setparams(struct bpp_softc *sc, struct hwstate *hw) 234 { 235 uint16_t irq; 236 bus_space_tag_t t = sc->sc_lsi64854.sc_bustag; 237 bus_space_handle_t h = sc->sc_lsi64854.sc_regs; 238 239 bus_space_write_2(t, h, L64854_REG_HCR, hw->hw_hcr); 240 bus_space_write_2(t, h, L64854_REG_OCR, hw->hw_ocr); 241 bus_space_write_1(t, h, L64854_REG_TCR, hw->hw_tcr); 242 bus_space_write_1(t, h, L64854_REG_OR, hw->hw_or); 243 244 /* Only change IRP settings in interrupt status register */ 245 irq = bus_space_read_2(t, h, L64854_REG_ICR); 246 irq &= ~BPP_ALLIRP; 247 irq |= (hw->hw_irq & BPP_ALLIRP); 248 bus_space_write_2(t, h, L64854_REG_ICR, irq); 249 DPRINTF(("bpp_setparams: hcr %x ocr %x tcr %x or %x, irq %x\n", 250 hw->hw_hcr, hw->hw_ocr, hw->hw_tcr, hw->hw_or, irq)); 251 } 252 253 int 254 bppopen(dev_t dev, int flags, int mode, struct lwp *l) 255 { 256 int unit = BPPUNIT(dev); 257 struct bpp_softc *sc; 258 struct lsi64854_softc *lsi; 259 uint16_t irq; 260 int s; 261 262 if (unit >= bpp_cd.cd_ndevs) 263 return ENXIO; 264 sc = device_lookup_private(&bpp_cd, unit); 265 266 if ((sc->sc_flags & (BPP_OPEN|BPP_XCLUDE)) == (BPP_OPEN|BPP_XCLUDE)) 267 return EBUSY; 268 269 lsi = &sc->sc_lsi64854; 270 271 /* Set default parameters */ 272 sc->sc_hwcurrent = sc->sc_hwdefault; 273 s = splbpp(); 274 bpp_setparams(sc, &sc->sc_hwdefault); 275 splx(s); 276 277 /* Enable interrupts */ 278 irq = BPP_ERR_IRQ_EN; 279 irq |= sc->sc_hwdefault.hw_irq; 280 bus_space_write_2(lsi->sc_bustag, lsi->sc_regs, L64854_REG_ICR, irq); 281 return 0; 282 } 283 284 int 285 bppclose(dev_t dev, int flags, int mode, struct lwp *l) 286 { 287 struct bpp_softc *sc; 288 struct lsi64854_softc *lsi; 289 uint16_t irq; 290 291 sc = device_lookup_private(&bpp_cd, BPPUNIT(dev)); 292 lsi = &sc->sc_lsi64854; 293 294 /* Turn off all interrupt enables */ 295 irq = sc->sc_hwdefault.hw_irq | BPP_ALLIRQ; 296 irq &= ~BPP_ALLEN; 297 bus_space_write_2(lsi->sc_bustag, lsi->sc_regs, L64854_REG_ICR, irq); 298 299 mutex_enter(proc_lock); 300 sc->sc_asyncproc = NULL; 301 mutex_exit(proc_lock); 302 sc->sc_flags = 0; 303 return 0; 304 } 305 306 int 307 bppwrite(dev_t dev, struct uio *uio, int flags) 308 { 309 struct bpp_softc *sc; 310 struct lsi64854_softc *lsi; 311 int error = 0; 312 int s; 313 314 sc = device_lookup_private(&bpp_cd, BPPUNIT(dev)); 315 lsi = &sc->sc_lsi64854; 316 317 /* 318 * Wait until the DMA engine is free. 319 */ 320 s = splbpp(); 321 while ((sc->sc_flags & BPP_LOCKED) != 0) { 322 if ((flags & IO_NDELAY) != 0) { 323 splx(s); 324 return EWOULDBLOCK; 325 } 326 327 sc->sc_flags |= BPP_WANT; 328 error = tsleep(sc->sc_buf, PZERO|PCATCH, "bppwrite", 0); 329 if (error != 0) { 330 splx(s); 331 return error; 332 } 333 } 334 sc->sc_flags |= BPP_LOCKED; 335 splx(s); 336 337 /* 338 * Move data from user space into our private buffer 339 * and start DMA. 340 */ 341 while (uio->uio_resid > 0) { 342 uint8_t *bp = sc->sc_buf; 343 size_t len = min(sc->sc_bufsz, uio->uio_resid); 344 345 if ((error = uiomove(bp, len, uio)) != 0) 346 break; 347 348 while (len > 0) { 349 uint8_t tcr; 350 size_t size = len; 351 DMA_SETUP(lsi, &bp, &len, 0, &size); 352 353 #ifdef DEBUG 354 if (bppdebug) { 355 int i; 356 uint8_t *b = bp; 357 printf("bpp: writing %ld : ", len); 358 for (i = 0; i < len; i++) 359 printf("%c(0x%x)", b[i], b[i]); 360 printf("\n"); 361 } 362 #endif 363 364 /* Clear direction control bit */ 365 tcr = bus_space_read_1(lsi->sc_bustag, lsi->sc_regs, 366 L64854_REG_TCR); 367 tcr &= ~BPP_TCR_DIR; 368 bus_space_write_1(lsi->sc_bustag, lsi->sc_regs, 369 L64854_REG_TCR, tcr); 370 371 /* Enable DMA */ 372 s = splbpp(); 373 DMA_GO(lsi); 374 error = tsleep(sc, PZERO|PCATCH, "bppdma", 0); 375 splx(s); 376 if (error != 0) 377 goto out; 378 379 /* Bail out if bottom half reported an error */ 380 if ((error = sc->sc_error) != 0) 381 goto out; 382 383 /* 384 * lsi64854_pp_intr() does this part. 385 * 386 * len -= size; 387 */ 388 } 389 } 390 391 out: 392 DPRINTF(("bpp done %x\n", error)); 393 s = splbpp(); 394 sc->sc_flags &= ~BPP_LOCKED; 395 if ((sc->sc_flags & BPP_WANT) != 0) { 396 sc->sc_flags &= ~BPP_WANT; 397 wakeup(sc->sc_buf); 398 } 399 splx(s); 400 return error; 401 } 402 403 /* move to header: */ 404 #define BPPIOCSPARAM _IOW('P', 0x1, struct hwstate) 405 #define BPPIOCGPARAM _IOR('P', 0x2, struct hwstate) 406 407 int 408 bppioctl(dev_t dev, u_long cmd, void *data, int flag, struct lwp *l) 409 { 410 struct bpp_softc *sc; 411 struct proc *p = l->l_proc; 412 struct hwstate *hw, *chw; 413 int error = 0; 414 int s; 415 416 sc = device_lookup_private(&bpp_cd, BPPUNIT(dev)); 417 418 switch(cmd) { 419 case BPPIOCSPARAM: 420 chw = &sc->sc_hwcurrent; 421 hw = (struct hwstate *)data; 422 423 /* 424 * Extract and store user-settable bits. 425 */ 426 #define _bpp_set(reg,mask) do { \ 427 chw->reg &= ~(mask); \ 428 chw->reg |= (hw->reg & (mask)); \ 429 } while (/* CONSTCOND */ 0) 430 _bpp_set(hw_hcr, BPP_HCR_DSS_MASK|BPP_HCR_DSW_MASK); 431 _bpp_set(hw_ocr, BPP_OCR_USER); 432 _bpp_set(hw_tcr, BPP_TCR_USER); 433 _bpp_set(hw_or, BPP_OR_USER); 434 _bpp_set(hw_irq, BPP_IRQ_USER); 435 #undef _bpp_set 436 437 /* Apply settings */ 438 s = splbpp(); 439 bpp_setparams(sc, chw); 440 splx(s); 441 break; 442 case BPPIOCGPARAM: 443 *((struct hwstate *)data) = sc->sc_hwcurrent; 444 break; 445 case TIOCEXCL: 446 s = splbpp(); 447 sc->sc_flags |= BPP_XCLUDE; 448 splx(s); 449 break; 450 case TIOCNXCL: 451 s = splbpp(); 452 sc->sc_flags &= ~BPP_XCLUDE; 453 splx(s); 454 break; 455 case FIOASYNC: 456 mutex_enter(proc_lock); 457 if (*(int *)data) { 458 if (sc->sc_asyncproc != NULL) 459 error = EBUSY; 460 else 461 sc->sc_asyncproc = p; 462 } else 463 sc->sc_asyncproc = NULL; 464 mutex_exit(proc_lock); 465 break; 466 default: 467 break; 468 } 469 470 return error; 471 } 472 473 int 474 bpppoll(dev_t dev, int events, struct lwp *l) 475 { 476 struct bpp_softc *sc; 477 int revents = 0; 478 479 sc = device_lookup_private(&bpp_cd, BPPUNIT(dev)); 480 481 if (events & (POLLIN | POLLRDNORM)) { 482 /* read is not yet implemented */ 483 } 484 485 if (events & (POLLOUT | POLLWRNORM)) { 486 if ((sc->sc_flags & BPP_LOCKED) == 0) 487 revents |= (POLLOUT | POLLWRNORM); 488 } 489 490 if (revents == 0) { 491 if (events & (POLLIN | POLLRDNORM)) 492 selrecord(l, &sc->sc_rsel); 493 if (events & (POLLOUT | POLLWRNORM)) 494 selrecord(l, &sc->sc_wsel); 495 } 496 497 return revents; 498 } 499 500 static void 501 filt_bpprdetach(struct knote *kn) 502 { 503 struct bpp_softc *sc = kn->kn_hook; 504 int s; 505 506 s = splbpp(); 507 SLIST_REMOVE(&sc->sc_rsel.sel_klist, kn, knote, kn_selnext); 508 splx(s); 509 } 510 511 static int 512 filt_bppread(struct knote *kn, long hint) 513 { 514 /* XXX Read not yet implemented. */ 515 return 0; 516 } 517 518 static const struct filterops bppread_filtops = 519 { 1, NULL, filt_bpprdetach, filt_bppread }; 520 521 static void 522 filt_bppwdetach(struct knote *kn) 523 { 524 struct bpp_softc *sc = kn->kn_hook; 525 int s; 526 527 s = splbpp(); 528 SLIST_REMOVE(&sc->sc_wsel.sel_klist, kn, knote, kn_selnext); 529 splx(s); 530 } 531 532 static int 533 filt_bpfwrite(struct knote *kn, long hint) 534 { 535 struct bpp_softc *sc = kn->kn_hook; 536 537 if (sc->sc_flags & BPP_LOCKED) 538 return 0; 539 540 kn->kn_data = 0; /* XXXLUKEM (thorpej): what to put here? */ 541 return 1; 542 } 543 544 static const struct filterops bppwrite_filtops = 545 { 1, NULL, filt_bppwdetach, filt_bpfwrite }; 546 547 int 548 bppkqfilter(dev_t dev, struct knote *kn) 549 { 550 struct bpp_softc *sc; 551 struct klist *klist; 552 int s; 553 554 sc = device_lookup_private(&bpp_cd, BPPUNIT(dev)); 555 556 switch (kn->kn_filter) { 557 case EVFILT_READ: 558 klist = &sc->sc_rsel.sel_klist; 559 kn->kn_fop = &bppread_filtops; 560 break; 561 562 case EVFILT_WRITE: 563 klist = &sc->sc_wsel.sel_klist; 564 kn->kn_fop = &bppwrite_filtops; 565 break; 566 567 default: 568 return EINVAL; 569 } 570 571 kn->kn_hook = sc; 572 573 s = splbpp(); 574 SLIST_INSERT_HEAD(klist, kn, kn_selnext); 575 splx(s); 576 577 return 0; 578 } 579 580 int 581 bppintr(void *arg) 582 { 583 struct bpp_softc *sc = arg; 584 struct lsi64854_softc *lsi = &sc->sc_lsi64854; 585 uint16_t irq; 586 587 /* First handle any possible DMA interrupts */ 588 if (lsi64854_pp_intr((void *)lsi) == -1) 589 sc->sc_error = 1; 590 591 irq = bus_space_read_2(lsi->sc_bustag, lsi->sc_regs, L64854_REG_ICR); 592 /* Ack all interrupts */ 593 bus_space_write_2(lsi->sc_bustag, lsi->sc_regs, L64854_REG_ICR, 594 irq | BPP_ALLIRQ); 595 596 DPRINTF(("%s: %x\n", __func__, irq)); 597 /* Did our device interrupt? */ 598 if ((irq & BPP_ALLIRQ) == 0) 599 return 0; 600 601 if ((sc->sc_flags & BPP_LOCKED) != 0) 602 wakeup(sc); 603 else if ((sc->sc_flags & BPP_WANT) != 0) { 604 sc->sc_flags &= ~BPP_WANT; 605 wakeup(sc->sc_buf); 606 } else { 607 selnotify(&sc->sc_wsel, 0, 0); 608 if (sc->sc_asyncproc != NULL) 609 softint_schedule(sc->sc_sih); 610 } 611 return 1; 612 } 613 614 static void 615 bppsoftintr(void *cookie) 616 { 617 struct bpp_softc *sc = cookie; 618 619 mutex_enter(proc_lock); 620 if (sc->sc_asyncproc) 621 psignal(sc->sc_asyncproc, SIGIO); 622 mutex_exit(proc_lock); 623 } 624
Indexes created Thu Oct 02 14:10:14 GMT 2025