bpp.c revision 1.40
1 /* $NetBSD: bpp.c,v 1.40 2014/03/16 05:20:29 dholland Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: bpp.c,v 1.40 2014/03/16 05:20:29 dholland Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/ioctl.h> 37 #include <sys/fcntl.h> 38 #include <sys/systm.h> 39 #include <sys/kernel.h> 40 #include <sys/vnode.h> 41 #include <sys/poll.h> 42 #include <sys/select.h> 43 #include <sys/malloc.h> 44 #include <sys/proc.h> 45 #include <sys/signalvar.h> 46 #include <sys/conf.h> 47 #include <sys/errno.h> 48 #include <sys/device.h> 49 #include <sys/bus.h> 50 #include <sys/intr.h> 51 52 #include <machine/autoconf.h> 53 54 #include <dev/ic/lsi64854reg.h> 55 #include <dev/ic/lsi64854var.h> 56 57 #include <dev/sbus/sbusvar.h> 58 #include <dev/sbus/bppreg.h> 59 60 #include "ioconf.h" 61 62 #define splbpp() spltty() /* XXX */ 63 64 #ifdef DEBUG 65 #define DPRINTF(x) do { if (bppdebug) printf x ; } while (0) 66 int bppdebug = 1; 67 #else 68 #define DPRINTF(x) 69 #endif 70 71 #if 0 72 struct bpp_param { 73 int bpp_dss; /* data setup to strobe */ 74 int bpp_dsw; /* data strobe width */ 75 int bpp_outputpins; /* Select/Autofeed/Init pins */ 76 int bpp_inputpins; /* Error/Select/Paperout pins */ 77 }; 78 #endif 79 80 struct hwstate { 81 uint16_t hw_hcr; /* Hardware config register */ 82 uint16_t hw_ocr; /* Operation config register */ 83 uint8_t hw_tcr; /* Transfer Control register */ 84 uint8_t hw_or; /* Output register */ 85 uint16_t hw_irq; /* IRQ; polarity bits only */ 86 }; 87 88 struct bpp_softc { 89 struct lsi64854_softc sc_lsi64854; /* base device */ 90 91 size_t sc_bufsz; /* temp buffer */ 92 uint8_t *sc_buf; 93 94 int sc_error; /* bottom-half error */ 95 int sc_flags; 96 #define BPP_OPEN 0x01 /* Device is open */ 97 #define BPP_XCLUDE 0x02 /* Exclusive-open mode */ 98 #define BPP_ASYNC 0x04 /* Asynchronous I/O mode */ 99 #define BPP_LOCKED 0x08 /* DMA in progress */ 100 #define BPP_WANT 0x10 /* Waiting for DMA */ 101 102 struct selinfo sc_rsel; 103 struct selinfo sc_wsel; 104 struct proc *sc_asyncproc; /* Process to notify if async */ 105 void *sc_sih; 106 107 /* Hardware state */ 108 struct hwstate sc_hwdefault; 109 struct hwstate sc_hwcurrent; 110 }; 111 112 static int bppmatch(device_t, cfdata_t, void *); 113 static void bppattach(device_t, device_t, void *); 114 static int bppintr(void *); 115 static void bppsoftintr(void *); 116 static void bpp_setparams(struct bpp_softc *, struct hwstate *); 117 118 CFATTACH_DECL_NEW(bpp, sizeof(struct bpp_softc), 119 bppmatch, bppattach, NULL, NULL); 120 121 dev_type_open(bppopen); 122 dev_type_close(bppclose); 123 dev_type_write(bppwrite); 124 dev_type_ioctl(bppioctl); 125 dev_type_poll(bpppoll); 126 dev_type_kqfilter(bppkqfilter); 127 128 const struct cdevsw bpp_cdevsw = { 129 .d_open = bppopen, 130 .d_close = bppclose, 131 .d_read = noread, 132 .d_write = bppwrite, 133 .d_ioctl = bppioctl, 134 .d_stop = nostop, 135 .d_tty = notty, 136 .d_poll = bpppoll, 137 .d_mmap = nommap, 138 .d_kqfilter = bppkqfilter, 139 .d_flag = D_TTY 140 }; 141 142 #define BPPUNIT(dev) (minor(dev)) 143 144 145 int 146 bppmatch(device_t parent, cfdata_t cf, void *aux) 147 { 148 struct sbus_attach_args *sa = aux; 149 150 return strcmp("SUNW,bpp", sa->sa_name) == 0; 151 } 152 153 void 154 bppattach(device_t parent, device_t self, void *aux) 155 { 156 struct bpp_softc *dsc = device_private(self); 157 struct lsi64854_softc *sc = &dsc->sc_lsi64854; 158 struct sbus_softc *sbsc = device_private(parent); 159 struct sbus_attach_args *sa = aux; 160 int burst, sbusburst; 161 int node; 162 163 sc->sc_dev = self; 164 165 selinit(&dsc->sc_rsel); 166 selinit(&dsc->sc_wsel); 167 dsc->sc_sih = softint_establish(SOFTINT_CLOCK, bppsoftintr, dsc); 168 169 sc->sc_bustag = sa->sa_bustag; 170 sc->sc_dmatag = sa->sa_dmatag; 171 node = sa->sa_node; 172 173 /* Map device registers */ 174 if (sbus_bus_map(sa->sa_bustag, 175 sa->sa_slot, sa->sa_offset, sa->sa_size, 176 0, &sc->sc_regs) != 0) { 177 aprint_error(": cannot map registers\n"); 178 return; 179 } 180 181 /* 182 * Get transfer burst size from PROM and plug it into the 183 * controller registers. This is needed on the Sun4m; do 184 * others need it too? 185 */ 186 sbusburst = sbsc->sc_burst; 187 if (sbusburst == 0) 188 sbusburst = SBUS_BURST_32 - 1; /* 1->16 */ 189 190 burst = prom_getpropint(node, "burst-sizes", -1); 191 if (burst == -1) 192 /* take SBus burst sizes */ 193 burst = sbusburst; 194 195 /* Clamp at parent's burst sizes */ 196 burst &= sbusburst; 197 sc->sc_burst = (burst & SBUS_BURST_32) ? 32 : 198 (burst & SBUS_BURST_16) ? 16 : 0; 199 200 /* Initialize the DMA channel */ 201 sc->sc_channel = L64854_CHANNEL_PP; 202 lsi64854_attach(sc); 203 204 /* Establish interrupt handler */ 205 if (sa->sa_nintr) { 206 sc->sc_intrchain = bppintr; 207 sc->sc_intrchainarg = dsc; 208 (void)bus_intr_establish(sa->sa_bustag, sa->sa_pri, IPL_TTY, 209 bppintr, sc); 210 } 211 212 /* Allocate buffer XXX - should actually use dmamap_uio() */ 213 dsc->sc_bufsz = 1024; 214 dsc->sc_buf = malloc(dsc->sc_bufsz, M_DEVBUF, M_NOWAIT); 215 216 /* XXX read default state */ 217 { 218 bus_space_handle_t h = sc->sc_regs; 219 struct hwstate *hw = &dsc->sc_hwdefault; 220 int ack_rate = sa->sa_frequency / 1000000; 221 222 hw->hw_hcr = bus_space_read_2(sc->sc_bustag, h, L64854_REG_HCR); 223 hw->hw_ocr = bus_space_read_2(sc->sc_bustag, h, L64854_REG_OCR); 224 hw->hw_tcr = bus_space_read_1(sc->sc_bustag, h, L64854_REG_TCR); 225 hw->hw_or = bus_space_read_1(sc->sc_bustag, h, L64854_REG_OR); 226 227 DPRINTF(("bpp: hcr %x ocr %x tcr %x or %x\n", 228 hw->hw_hcr, hw->hw_ocr, hw->hw_tcr, hw->hw_or)); 229 /* Set these to sane values */ 230 hw->hw_hcr = ((ack_rate<<BPP_HCR_DSS_SHFT)&BPP_HCR_DSS_MASK) 231 | ((ack_rate<<BPP_HCR_DSW_SHFT)&BPP_HCR_DSW_MASK); 232 hw->hw_ocr |= BPP_OCR_ACK_OP; 233 } 234 } 235 236 void 237 bpp_setparams(struct bpp_softc *sc, struct hwstate *hw) 238 { 239 uint16_t irq; 240 bus_space_tag_t t = sc->sc_lsi64854.sc_bustag; 241 bus_space_handle_t h = sc->sc_lsi64854.sc_regs; 242 243 bus_space_write_2(t, h, L64854_REG_HCR, hw->hw_hcr); 244 bus_space_write_2(t, h, L64854_REG_OCR, hw->hw_ocr); 245 bus_space_write_1(t, h, L64854_REG_TCR, hw->hw_tcr); 246 bus_space_write_1(t, h, L64854_REG_OR, hw->hw_or); 247 248 /* Only change IRP settings in interrupt status register */ 249 irq = bus_space_read_2(t, h, L64854_REG_ICR); 250 irq &= ~BPP_ALLIRP; 251 irq |= (hw->hw_irq & BPP_ALLIRP); 252 bus_space_write_2(t, h, L64854_REG_ICR, irq); 253 DPRINTF(("bpp_setparams: hcr %x ocr %x tcr %x or %x, irq %x\n", 254 hw->hw_hcr, hw->hw_ocr, hw->hw_tcr, hw->hw_or, irq)); 255 } 256 257 int 258 bppopen(dev_t dev, int flags, int mode, struct lwp *l) 259 { 260 int unit = BPPUNIT(dev); 261 struct bpp_softc *sc; 262 struct lsi64854_softc *lsi; 263 uint16_t irq; 264 int s; 265 266 if (unit >= bpp_cd.cd_ndevs) 267 return ENXIO; 268 sc = device_lookup_private(&bpp_cd, unit); 269 270 if ((sc->sc_flags & (BPP_OPEN|BPP_XCLUDE)) == (BPP_OPEN|BPP_XCLUDE)) 271 return EBUSY; 272 273 lsi = &sc->sc_lsi64854; 274 275 /* Set default parameters */ 276 sc->sc_hwcurrent = sc->sc_hwdefault; 277 s = splbpp(); 278 bpp_setparams(sc, &sc->sc_hwdefault); 279 splx(s); 280 281 /* Enable interrupts */ 282 irq = BPP_ERR_IRQ_EN; 283 irq |= sc->sc_hwdefault.hw_irq; 284 bus_space_write_2(lsi->sc_bustag, lsi->sc_regs, L64854_REG_ICR, irq); 285 return 0; 286 } 287 288 int 289 bppclose(dev_t dev, int flags, int mode, struct lwp *l) 290 { 291 struct bpp_softc *sc; 292 struct lsi64854_softc *lsi; 293 uint16_t irq; 294 295 sc = device_lookup_private(&bpp_cd, BPPUNIT(dev)); 296 lsi = &sc->sc_lsi64854; 297 298 /* Turn off all interrupt enables */ 299 irq = sc->sc_hwdefault.hw_irq | BPP_ALLIRQ; 300 irq &= ~BPP_ALLEN; 301 bus_space_write_2(lsi->sc_bustag, lsi->sc_regs, L64854_REG_ICR, irq); 302 303 mutex_enter(proc_lock); 304 sc->sc_asyncproc = NULL; 305 mutex_exit(proc_lock); 306 sc->sc_flags = 0; 307 return 0; 308 } 309 310 int 311 bppwrite(dev_t dev, struct uio *uio, int flags) 312 { 313 struct bpp_softc *sc; 314 struct lsi64854_softc *lsi; 315 int error = 0; 316 int s; 317 318 sc = device_lookup_private(&bpp_cd, BPPUNIT(dev)); 319 lsi = &sc->sc_lsi64854; 320 321 /* 322 * Wait until the DMA engine is free. 323 */ 324 s = splbpp(); 325 while ((sc->sc_flags & BPP_LOCKED) != 0) { 326 if ((flags & IO_NDELAY) != 0) { 327 splx(s); 328 return EWOULDBLOCK; 329 } 330 331 sc->sc_flags |= BPP_WANT; 332 error = tsleep(sc->sc_buf, PZERO|PCATCH, "bppwrite", 0); 333 if (error != 0) { 334 splx(s); 335 return error; 336 } 337 } 338 sc->sc_flags |= BPP_LOCKED; 339 splx(s); 340 341 /* 342 * Move data from user space into our private buffer 343 * and start DMA. 344 */ 345 while (uio->uio_resid > 0) { 346 uint8_t *bp = sc->sc_buf; 347 size_t len = min(sc->sc_bufsz, uio->uio_resid); 348 349 if ((error = uiomove(bp, len, uio)) != 0) 350 break; 351 352 while (len > 0) { 353 uint8_t tcr; 354 size_t size = len; 355 DMA_SETUP(lsi, &bp, &len, 0, &size); 356 357 #ifdef DEBUG 358 if (bppdebug) { 359 int i; 360 uint8_t *b = bp; 361 printf("bpp: writing %ld : ", len); 362 for (i = 0; i < len; i++) 363 printf("%c(0x%x)", b[i], b[i]); 364 printf("\n"); 365 } 366 #endif 367 368 /* Clear direction control bit */ 369 tcr = bus_space_read_1(lsi->sc_bustag, lsi->sc_regs, 370 L64854_REG_TCR); 371 tcr &= ~BPP_TCR_DIR; 372 bus_space_write_1(lsi->sc_bustag, lsi->sc_regs, 373 L64854_REG_TCR, tcr); 374 375 /* Enable DMA */ 376 s = splbpp(); 377 DMA_GO(lsi); 378 error = tsleep(sc, PZERO|PCATCH, "bppdma", 0); 379 splx(s); 380 if (error != 0) 381 goto out; 382 383 /* Bail out if bottom half reported an error */ 384 if ((error = sc->sc_error) != 0) 385 goto out; 386 387 /* 388 * lsi64854_pp_intr() does this part. 389 * 390 * len -= size; 391 */ 392 } 393 } 394 395 out: 396 DPRINTF(("bpp done %x\n", error)); 397 s = splbpp(); 398 sc->sc_flags &= ~BPP_LOCKED; 399 if ((sc->sc_flags & BPP_WANT) != 0) { 400 sc->sc_flags &= ~BPP_WANT; 401 wakeup(sc->sc_buf); 402 } 403 splx(s); 404 return error; 405 } 406 407 /* move to header: */ 408 #define BPPIOCSPARAM _IOW('P', 0x1, struct hwstate) 409 #define BPPIOCGPARAM _IOR('P', 0x2, struct hwstate) 410 411 int 412 bppioctl(dev_t dev, u_long cmd, void *data, int flag, struct lwp *l) 413 { 414 struct bpp_softc *sc; 415 struct proc *p = l->l_proc; 416 struct hwstate *hw, *chw; 417 int error = 0; 418 int s; 419 420 sc = device_lookup_private(&bpp_cd, BPPUNIT(dev)); 421 422 switch(cmd) { 423 case BPPIOCSPARAM: 424 chw = &sc->sc_hwcurrent; 425 hw = (struct hwstate *)data; 426 427 /* 428 * Extract and store user-settable bits. 429 */ 430 #define _bpp_set(reg,mask) do { \ 431 chw->reg &= ~(mask); \ 432 chw->reg |= (hw->reg & (mask)); \ 433 } while (/* CONSTCOND */ 0) 434 _bpp_set(hw_hcr, BPP_HCR_DSS_MASK|BPP_HCR_DSW_MASK); 435 _bpp_set(hw_ocr, BPP_OCR_USER); 436 _bpp_set(hw_tcr, BPP_TCR_USER); 437 _bpp_set(hw_or, BPP_OR_USER); 438 _bpp_set(hw_irq, BPP_IRQ_USER); 439 #undef _bpp_set 440 441 /* Apply settings */ 442 s = splbpp(); 443 bpp_setparams(sc, chw); 444 splx(s); 445 break; 446 case BPPIOCGPARAM: 447 *((struct hwstate *)data) = sc->sc_hwcurrent; 448 break; 449 case TIOCEXCL: 450 s = splbpp(); 451 sc->sc_flags |= BPP_XCLUDE; 452 splx(s); 453 break; 454 case TIOCNXCL: 455 s = splbpp(); 456 sc->sc_flags &= ~BPP_XCLUDE; 457 splx(s); 458 break; 459 case FIOASYNC: 460 mutex_enter(proc_lock); 461 if (*(int *)data) { 462 if (sc->sc_asyncproc != NULL) 463 error = EBUSY; 464 else 465 sc->sc_asyncproc = p; 466 } else 467 sc->sc_asyncproc = NULL; 468 mutex_exit(proc_lock); 469 break; 470 default: 471 break; 472 } 473 474 return error; 475 } 476 477 int 478 bpppoll(dev_t dev, int events, struct lwp *l) 479 { 480 struct bpp_softc *sc; 481 int revents = 0; 482 483 sc = device_lookup_private(&bpp_cd, BPPUNIT(dev)); 484 485 if (events & (POLLIN | POLLRDNORM)) { 486 /* read is not yet implemented */ 487 } 488 489 if (events & (POLLOUT | POLLWRNORM)) { 490 if ((sc->sc_flags & BPP_LOCKED) == 0) 491 revents |= (POLLOUT | POLLWRNORM); 492 } 493 494 if (revents == 0) { 495 if (events & (POLLIN | POLLRDNORM)) 496 selrecord(l, &sc->sc_rsel); 497 if (events & (POLLOUT | POLLWRNORM)) 498 selrecord(l, &sc->sc_wsel); 499 } 500 501 return revents; 502 } 503 504 static void 505 filt_bpprdetach(struct knote *kn) 506 { 507 struct bpp_softc *sc = kn->kn_hook; 508 int s; 509 510 s = splbpp(); 511 SLIST_REMOVE(&sc->sc_rsel.sel_klist, kn, knote, kn_selnext); 512 splx(s); 513 } 514 515 static int 516 filt_bppread(struct knote *kn, long hint) 517 { 518 /* XXX Read not yet implemented. */ 519 return 0; 520 } 521 522 static const struct filterops bppread_filtops = 523 { 1, NULL, filt_bpprdetach, filt_bppread }; 524 525 static void 526 filt_bppwdetach(struct knote *kn) 527 { 528 struct bpp_softc *sc = kn->kn_hook; 529 int s; 530 531 s = splbpp(); 532 SLIST_REMOVE(&sc->sc_wsel.sel_klist, kn, knote, kn_selnext); 533 splx(s); 534 } 535 536 static int 537 filt_bpfwrite(struct knote *kn, long hint) 538 { 539 struct bpp_softc *sc = kn->kn_hook; 540 541 if (sc->sc_flags & BPP_LOCKED) 542 return 0; 543 544 kn->kn_data = 0; /* XXXLUKEM (thorpej): what to put here? */ 545 return 1; 546 } 547 548 static const struct filterops bppwrite_filtops = 549 { 1, NULL, filt_bppwdetach, filt_bpfwrite }; 550 551 int 552 bppkqfilter(dev_t dev, struct knote *kn) 553 { 554 struct bpp_softc *sc; 555 struct klist *klist; 556 int s; 557 558 sc = device_lookup_private(&bpp_cd, BPPUNIT(dev)); 559 560 switch (kn->kn_filter) { 561 case EVFILT_READ: 562 klist = &sc->sc_rsel.sel_klist; 563 kn->kn_fop = &bppread_filtops; 564 break; 565 566 case EVFILT_WRITE: 567 klist = &sc->sc_wsel.sel_klist; 568 kn->kn_fop = &bppwrite_filtops; 569 break; 570 571 default: 572 return EINVAL; 573 } 574 575 kn->kn_hook = sc; 576 577 s = splbpp(); 578 SLIST_INSERT_HEAD(klist, kn, kn_selnext); 579 splx(s); 580 581 return 0; 582 } 583 584 int 585 bppintr(void *arg) 586 { 587 struct bpp_softc *sc = arg; 588 struct lsi64854_softc *lsi = &sc->sc_lsi64854; 589 uint16_t irq; 590 591 /* First handle any possible DMA interrupts */ 592 if (lsi64854_pp_intr((void *)lsi) == -1) 593 sc->sc_error = 1; 594 595 irq = bus_space_read_2(lsi->sc_bustag, lsi->sc_regs, L64854_REG_ICR); 596 /* Ack all interrupts */ 597 bus_space_write_2(lsi->sc_bustag, lsi->sc_regs, L64854_REG_ICR, 598 irq | BPP_ALLIRQ); 599 600 DPRINTF(("%s: %x\n", __func__, irq)); 601 /* Did our device interrupt? */ 602 if ((irq & BPP_ALLIRQ) == 0) 603 return 0; 604 605 if ((sc->sc_flags & BPP_LOCKED) != 0) 606 wakeup(sc); 607 else if ((sc->sc_flags & BPP_WANT) != 0) { 608 sc->sc_flags &= ~BPP_WANT; 609 wakeup(sc->sc_buf); 610 } else { 611 selnotify(&sc->sc_wsel, 0, 0); 612 if (sc->sc_asyncproc != NULL) 613 softint_schedule(sc->sc_sih); 614 } 615 return 1; 616 } 617 618 static void 619 bppsoftintr(void *cookie) 620 { 621 struct bpp_softc *sc = cookie; 622 623 mutex_enter(proc_lock); 624 if (sc->sc_asyncproc) 625 psignal(sc->sc_asyncproc, SIGIO); 626 mutex_exit(proc_lock); 627 } 628
Indexes created Wed Sep 24 02:09:48 GMT 2025