bpp.c revision 1.8.2.2
1 /* $NetBSD: bpp.c,v 1.8.2.2 2001/11/14 19:15:56 nathanw Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <sys/cdefs.h> 40 __KERNEL_RCSID(0, "$NetBSD: bpp.c,v 1.8.2.2 2001/11/14 19:15:56 nathanw Exp $"); 41 42 #include <sys/param.h> 43 #include <sys/ioctl.h> 44 #include <sys/fcntl.h> 45 #include <sys/systm.h> 46 #include <sys/kernel.h> 47 #include <sys/vnode.h> 48 #include <sys/poll.h> 49 #include <sys/select.h> 50 #include <sys/malloc.h> 51 #include <sys/proc.h> 52 #include <sys/signalvar.h> 53 #include <sys/conf.h> 54 #include <sys/errno.h> 55 #include <sys/device.h> 56 57 #include <machine/bus.h> 58 #include <machine/intr.h> 59 #include <machine/autoconf.h> 60 #include <machine/conf.h> 61 62 #include <dev/ic/lsi64854reg.h> 63 #include <dev/ic/lsi64854var.h> 64 65 #include <dev/sbus/sbusvar.h> 66 #include <dev/sbus/bppreg.h> 67 68 #define splbpp() spltty() /* XXX */ 69 70 #ifdef DEBUG 71 #define DPRINTF(x) do { if (bppdebug) printf x ; } while (0) 72 int bppdebug = 1; 73 #else 74 #define DPRINTF(x) 75 #endif 76 77 #if 0 78 struct bpp_param { 79 int bpp_dss; /* data setup to strobe */ 80 int bpp_dsw; /* data strobe width */ 81 int bpp_outputpins; /* Select/Autofeed/Init pins */ 82 int bpp_inputpins; /* Error/Select/Paperout pins */ 83 }; 84 #endif 85 86 struct hwstate { 87 u_int16_t hw_hcr; /* Hardware config register */ 88 u_int16_t hw_ocr; /* Operation config register */ 89 u_int8_t hw_tcr; /* Transfer Control register */ 90 u_int8_t hw_or; /* Output register */ 91 u_int16_t hw_irq; /* IRQ; polarity bits only */ 92 }; 93 94 struct bpp_softc { 95 struct lsi64854_softc sc_lsi64854; /* base device */ 96 struct sbusdev sc_sd; /* sbus device */ 97 98 size_t sc_bufsz; /* temp buffer */ 99 caddr_t sc_buf; 100 101 int sc_error; /* bottom-half error */ 102 int sc_flags; 103 #define BPP_OPEN 0x01 /* Device is open */ 104 #define BPP_XCLUDE 0x02 /* Exclusive-open mode */ 105 #define BPP_ASYNC 0x04 /* Asynchronous I/O mode */ 106 #define BPP_LOCKED 0x08 /* DMA in progress */ 107 #define BPP_WANT 0x10 /* Waiting for DMA */ 108 109 struct selinfo sc_rsel; 110 struct selinfo sc_wsel; 111 struct proc *sc_asyncproc; /* Process to notify if async */ 112 113 /* Hardware state */ 114 struct hwstate sc_hwdefault; 115 struct hwstate sc_hwcurrent; 116 }; 117 118 static int bppmatch __P((struct device *, struct cfdata *, void *)); 119 static void bppattach __P((struct device *, struct device *, void *)); 120 static int bppintr __P((void *)); 121 static void bpp_setparams __P((struct bpp_softc *, struct hwstate *)); 122 123 struct cfattach bpp_ca = { 124 sizeof(struct bpp_softc), bppmatch, bppattach 125 }; 126 127 extern struct cfdriver bpp_cd; 128 #define BPPUNIT(dev) (minor(dev)) 129 130 131 int 132 bppmatch(parent, cf, aux) 133 struct device *parent; 134 struct cfdata *cf; 135 void *aux; 136 { 137 struct sbus_attach_args *sa = aux; 138 139 return (strcmp("SUNW,bpp", sa->sa_name) == 0); 140 } 141 142 void 143 bppattach(parent, self, aux) 144 struct device *parent, *self; 145 void *aux; 146 { 147 struct sbus_attach_args *sa = aux; 148 struct bpp_softc *dsc = (void *)self; 149 struct lsi64854_softc *sc = &dsc->sc_lsi64854; 150 int burst, sbusburst; 151 int node; 152 153 sc->sc_bustag = sa->sa_bustag; 154 sc->sc_dmatag = sa->sa_dmatag; 155 node = sa->sa_node; 156 157 /* Map device registers */ 158 if (bus_space_map2(sa->sa_bustag, 159 sa->sa_slot, 160 sa->sa_offset, 161 sa->sa_size, 162 BUS_SPACE_MAP_LINEAR, 163 0, &sc->sc_regs) != 0) { 164 printf("%s: cannot map registers\n", self->dv_xname); 165 return; 166 } 167 168 /* 169 * Get transfer burst size from PROM and plug it into the 170 * controller registers. This is needed on the Sun4m; do 171 * others need it too? 172 */ 173 sbusburst = ((struct sbus_softc *)parent)->sc_burst; 174 if (sbusburst == 0) 175 sbusburst = SBUS_BURST_32 - 1; /* 1->16 */ 176 177 burst = PROM_getpropint(node, "burst-sizes", -1); 178 if (burst == -1) 179 /* take SBus burst sizes */ 180 burst = sbusburst; 181 182 /* Clamp at parent's burst sizes */ 183 burst &= sbusburst; 184 sc->sc_burst = (burst & SBUS_BURST_32) ? 32 : 185 (burst & SBUS_BURST_16) ? 16 : 0; 186 187 /* Join the Sbus device family */ 188 dsc->sc_sd.sd_reset = (void *)0; 189 sbus_establish(&dsc->sc_sd, self); 190 191 /* Initialize the DMA channel */ 192 sc->sc_channel = L64854_CHANNEL_PP; 193 lsi64854_attach(sc); 194 195 /* Establish interrupt handler */ 196 if (sa->sa_nintr) { 197 sc->sc_intrchain = bppintr; 198 sc->sc_intrchainarg = dsc; 199 (void)bus_intr_establish(sa->sa_bustag, sa->sa_pri, IPL_TTY, 0, 200 bppintr, sc); 201 } 202 203 /* Allocate buffer XXX - should actually use dmamap_uio() */ 204 dsc->sc_bufsz = 1024; 205 dsc->sc_buf = malloc(dsc->sc_bufsz, M_DEVBUF, M_NOWAIT); 206 207 /* XXX read default state */ 208 { 209 bus_space_handle_t h = sc->sc_regs; 210 struct hwstate *hw = &dsc->sc_hwdefault; 211 int ack_rate = sa->sa_frequency/1000000; 212 213 hw->hw_hcr = bus_space_read_2(sc->sc_bustag, h, L64854_REG_HCR); 214 hw->hw_ocr = bus_space_read_2(sc->sc_bustag, h, L64854_REG_OCR); 215 hw->hw_tcr = bus_space_read_1(sc->sc_bustag, h, L64854_REG_TCR); 216 hw->hw_or = bus_space_read_1(sc->sc_bustag, h, L64854_REG_OR); 217 218 DPRINTF(("bpp: hcr %x ocr %x tcr %x or %x\n", 219 hw->hw_hcr, hw->hw_ocr, hw->hw_tcr, hw->hw_or)); 220 /* Set these to sane values */ 221 hw->hw_hcr = ((ack_rate<<BPP_HCR_DSS_SHFT)&BPP_HCR_DSS_MASK) 222 | ((ack_rate<<BPP_HCR_DSW_SHFT)&BPP_HCR_DSW_MASK); 223 hw->hw_ocr |= BPP_OCR_ACK_OP; 224 } 225 } 226 227 void 228 bpp_setparams(sc, hw) 229 struct bpp_softc *sc; 230 struct hwstate *hw; 231 { 232 u_int16_t irq; 233 bus_space_tag_t t = sc->sc_lsi64854.sc_bustag; 234 bus_space_handle_t h = sc->sc_lsi64854.sc_regs; 235 236 bus_space_write_2(t, h, L64854_REG_HCR, hw->hw_hcr); 237 bus_space_write_2(t, h, L64854_REG_OCR, hw->hw_ocr); 238 bus_space_write_1(t, h, L64854_REG_TCR, hw->hw_tcr); 239 bus_space_write_1(t, h, L64854_REG_OR, hw->hw_or); 240 241 /* Only change IRP settings in interrupt status register */ 242 irq = bus_space_read_2(t, h, L64854_REG_ICR); 243 irq &= ~BPP_ALLIRP; 244 irq |= (hw->hw_irq & BPP_ALLIRP); 245 bus_space_write_2(t, h, L64854_REG_ICR, irq); 246 DPRINTF(("bpp_setparams: hcr %x ocr %x tcr %x or %x, irq %x\n", 247 hw->hw_hcr, hw->hw_ocr, hw->hw_tcr, hw->hw_or, irq)); 248 } 249 250 int 251 bppopen(dev, flags, mode, p) 252 dev_t dev; 253 int flags, mode; 254 struct proc *p; 255 { 256 int unit = BPPUNIT(dev); 257 struct bpp_softc *sc; 258 struct lsi64854_softc *lsi; 259 u_int16_t irq; 260 int s; 261 262 if (unit >= bpp_cd.cd_ndevs) 263 return (ENXIO); 264 sc = bpp_cd.cd_devs[unit]; 265 266 if ((sc->sc_flags & (BPP_OPEN|BPP_XCLUDE)) == (BPP_OPEN|BPP_XCLUDE)) 267 return (EBUSY); 268 269 lsi = &sc->sc_lsi64854; 270 271 /* Set default parameters */ 272 sc->sc_hwcurrent = sc->sc_hwdefault; 273 s = splbpp(); 274 bpp_setparams(sc, &sc->sc_hwdefault); 275 splx(s); 276 277 /* Enable interrupts */ 278 irq = BPP_ERR_IRQ_EN; 279 irq |= sc->sc_hwdefault.hw_irq; 280 bus_space_write_2(lsi->sc_bustag, lsi->sc_regs, L64854_REG_ICR, irq); 281 return (0); 282 } 283 284 int 285 bppclose(dev, flags, mode, p) 286 dev_t dev; 287 int flags, mode; 288 struct proc *p; 289 { 290 struct bpp_softc *sc = bpp_cd.cd_devs[BPPUNIT(dev)]; 291 struct lsi64854_softc *lsi = &sc->sc_lsi64854; 292 u_int16_t irq; 293 294 /* Turn off all interrupt enables */ 295 irq = sc->sc_hwdefault.hw_irq | BPP_ALLIRQ; 296 irq &= ~BPP_ALLEN; 297 bus_space_write_2(lsi->sc_bustag, lsi->sc_regs, L64854_REG_ICR, irq); 298 299 sc->sc_asyncproc = NULL; 300 sc->sc_flags = 0; 301 return (0); 302 } 303 304 int 305 bppread(dev, uio, flags) 306 dev_t dev; 307 struct uio *uio; 308 int flags; 309 { 310 311 return (ENXIO); 312 } 313 314 int 315 bppwrite(dev, uio, flags) 316 dev_t dev; 317 struct uio *uio; 318 int flags; 319 { 320 struct bpp_softc *sc = bpp_cd.cd_devs[BPPUNIT(dev)]; 321 struct lsi64854_softc *lsi = &sc->sc_lsi64854; 322 int error = 0; 323 int s; 324 325 /* 326 * Wait until the DMA engine is free. 327 */ 328 s = splbpp(); 329 while ((sc->sc_flags & BPP_LOCKED) != 0) { 330 if ((flags & IO_NDELAY) != 0) { 331 splx(s); 332 return (EWOULDBLOCK); 333 } 334 335 sc->sc_flags |= BPP_WANT; 336 error = tsleep(sc->sc_buf, PZERO|PCATCH, "bppwrite", 0); 337 if (error != 0) { 338 splx(s); 339 return (error); 340 } 341 } 342 sc->sc_flags |= BPP_LOCKED; 343 splx(s); 344 345 /* 346 * Move data from user space into our private buffer 347 * and start DMA. 348 */ 349 while (uio->uio_resid > 0) { 350 caddr_t bp = sc->sc_buf; 351 size_t len = min(sc->sc_bufsz, uio->uio_resid); 352 353 if ((error = uiomove(bp, len, uio)) != 0) 354 break; 355 356 while (len > 0) { 357 u_int8_t tcr; 358 size_t size = len; 359 DMA_SETUP(lsi, &bp, &len, 0, &size); 360 361 #ifdef DEBUG 362 if (bppdebug) { 363 int i; 364 printf("bpp: writing %ld : ", len); 365 for (i=0; i<len; i++) printf("%c(0x%x)", bp[i], bp[i]); 366 printf("\n"); 367 } 368 #endif 369 370 /* Clear direction control bit */ 371 tcr = bus_space_read_1(lsi->sc_bustag, lsi->sc_regs, 372 L64854_REG_TCR); 373 tcr &= ~BPP_TCR_DIR; 374 bus_space_write_1(lsi->sc_bustag, lsi->sc_regs, 375 L64854_REG_TCR, tcr); 376 377 /* Enable DMA */ 378 s = splbpp(); 379 DMA_GO(lsi); 380 error = tsleep(sc, PZERO|PCATCH, "bppdma", 0); 381 splx(s); 382 if (error != 0) 383 goto out; 384 385 /* Bail out if bottom half reported an error */ 386 if ((error = sc->sc_error) != 0) 387 goto out; 388 389 /* 390 * lsi64854_pp_intr() does this part. 391 * 392 * len -= size; 393 */ 394 } 395 } 396 397 out: 398 DPRINTF(("bpp done %x\n", error)); 399 s = splbpp(); 400 sc->sc_flags &= ~BPP_LOCKED; 401 if ((sc->sc_flags & BPP_WANT) != 0) { 402 sc->sc_flags &= ~BPP_WANT; 403 wakeup(sc->sc_buf); 404 } 405 splx(s); 406 return (error); 407 } 408 409 /* move to header: */ 410 #define BPPIOCSPARAM _IOW('P', 0x1, struct hwstate) 411 #define BPPIOCGPARAM _IOR('P', 0x2, struct hwstate) 412 413 int 414 bppioctl(dev, cmd, data, flag, p) 415 dev_t dev; 416 u_long cmd; 417 caddr_t data; 418 int flag; 419 struct proc *p; 420 { 421 struct bpp_softc *sc = bpp_cd.cd_devs[BPPUNIT(dev)]; 422 struct hwstate *hw, *chw; 423 int error = 0; 424 int s; 425 426 switch(cmd) { 427 case BPPIOCSPARAM: 428 chw = &sc->sc_hwcurrent; 429 hw = (struct hwstate *)data; 430 431 /* 432 * Extract and store user-settable bits. 433 */ 434 #define _bpp_set(reg,mask) do { \ 435 chw->reg &= ~(mask); \ 436 chw->reg |= (hw->reg & (mask)); \ 437 } while (0) 438 _bpp_set(hw_hcr, BPP_HCR_DSS_MASK|BPP_HCR_DSW_MASK); 439 _bpp_set(hw_ocr, BPP_OCR_USER); 440 _bpp_set(hw_tcr, BPP_TCR_USER); 441 _bpp_set(hw_or, BPP_OR_USER); 442 _bpp_set(hw_irq, BPP_IRQ_USER); 443 #undef _bpp_set 444 445 /* Apply settings */ 446 s = splbpp(); 447 bpp_setparams(sc, chw); 448 splx(s); 449 break; 450 case BPPIOCGPARAM: 451 *((struct hwstate *)data) = sc->sc_hwcurrent; 452 break; 453 case TIOCEXCL: 454 s = splbpp(); 455 sc->sc_flags |= BPP_XCLUDE; 456 splx(s); 457 break; 458 case TIOCNXCL: 459 s = splbpp(); 460 sc->sc_flags &= ~BPP_XCLUDE; 461 splx(s); 462 break; 463 case FIOASYNC: 464 s = splbpp(); 465 if (*(int *)data) { 466 if (sc->sc_asyncproc != NULL) 467 error = EBUSY; 468 else 469 sc->sc_asyncproc = p; 470 } else 471 sc->sc_asyncproc = NULL; 472 splx(s); 473 break; 474 default: 475 break; 476 } 477 478 return (error); 479 } 480 481 int 482 bpppoll(dev, events, p) 483 dev_t dev; 484 int events; 485 struct proc *p; 486 { 487 struct bpp_softc *sc = bpp_cd.cd_devs[BPPUNIT(dev)]; 488 int revents = 0; 489 490 if (events & (POLLIN | POLLRDNORM)) { 491 /* read is not yet implemented */ 492 } 493 494 if (events & (POLLOUT | POLLWRNORM)) { 495 if ((sc->sc_flags & BPP_LOCKED) == 0) 496 revents |= (POLLOUT | POLLWRNORM); 497 } 498 499 if (revents == 0) { 500 if (events & (POLLIN | POLLRDNORM)) 501 selrecord(p, &sc->sc_rsel); 502 if (events & (POLLOUT | POLLWRNORM)) 503 selrecord(p, &sc->sc_wsel); 504 } 505 506 return (revents); 507 } 508 509 int 510 bppintr(arg) 511 void *arg; 512 { 513 struct bpp_softc *sc = arg; 514 struct lsi64854_softc *lsi = &sc->sc_lsi64854; 515 u_int16_t irq; 516 517 /* First handle any possible DMA interrupts */ 518 if (lsi64854_pp_intr((void *)lsi) == -1) 519 sc->sc_error = 1; 520 521 irq = bus_space_read_2(lsi->sc_bustag, lsi->sc_regs, L64854_REG_ICR); 522 /* Ack all interrupts */ 523 bus_space_write_2(lsi->sc_bustag, lsi->sc_regs, L64854_REG_ICR, 524 irq | BPP_ALLIRQ); 525 526 DPRINTF(("bpp_intr: %x\n", irq)); 527 /* Did our device interrupt? */ 528 if ((irq & BPP_ALLIRQ) == 0) 529 return (0); 530 531 if ((sc->sc_flags & BPP_LOCKED) != 0) 532 wakeup(sc); 533 else if ((sc->sc_flags & BPP_WANT) != 0) { 534 sc->sc_flags &= ~BPP_WANT; 535 wakeup(sc->sc_buf); 536 } else { 537 selwakeup(&sc->sc_wsel); 538 if (sc->sc_asyncproc != NULL) 539 psignal(sc->sc_asyncproc, SIGIO); 540 } 541 return (1); 542 } 543
Indexes created Thu Oct 02 14:10:14 GMT 2025