bpp.c revision 1.8.2.5
1 /* $NetBSD: bpp.c,v 1.8.2.5 2002/10/18 02:44:02 nathanw Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <sys/cdefs.h> 40 __KERNEL_RCSID(0, "$NetBSD: bpp.c,v 1.8.2.5 2002/10/18 02:44:02 nathanw Exp $"); 41 42 #include <sys/param.h> 43 #include <sys/ioctl.h> 44 #include <sys/fcntl.h> 45 #include <sys/systm.h> 46 #include <sys/kernel.h> 47 #include <sys/vnode.h> 48 #include <sys/poll.h> 49 #include <sys/select.h> 50 #include <sys/malloc.h> 51 #include <sys/proc.h> 52 #include <sys/signalvar.h> 53 #include <sys/conf.h> 54 #include <sys/errno.h> 55 #include <sys/device.h> 56 57 #include <machine/bus.h> 58 #include <machine/intr.h> 59 #include <machine/autoconf.h> 60 61 #include <dev/ic/lsi64854reg.h> 62 #include <dev/ic/lsi64854var.h> 63 64 #include <dev/sbus/sbusvar.h> 65 #include <dev/sbus/bppreg.h> 66 67 #define splbpp() spltty() /* XXX */ 68 69 #ifdef DEBUG 70 #define DPRINTF(x) do { if (bppdebug) printf x ; } while (0) 71 int bppdebug = 1; 72 #else 73 #define DPRINTF(x) 74 #endif 75 76 #if 0 77 struct bpp_param { 78 int bpp_dss; /* data setup to strobe */ 79 int bpp_dsw; /* data strobe width */ 80 int bpp_outputpins; /* Select/Autofeed/Init pins */ 81 int bpp_inputpins; /* Error/Select/Paperout pins */ 82 }; 83 #endif 84 85 struct hwstate { 86 u_int16_t hw_hcr; /* Hardware config register */ 87 u_int16_t hw_ocr; /* Operation config register */ 88 u_int8_t hw_tcr; /* Transfer Control register */ 89 u_int8_t hw_or; /* Output register */ 90 u_int16_t hw_irq; /* IRQ; polarity bits only */ 91 }; 92 93 struct bpp_softc { 94 struct lsi64854_softc sc_lsi64854; /* base device */ 95 struct sbusdev sc_sd; /* sbus device */ 96 97 size_t sc_bufsz; /* temp buffer */ 98 caddr_t sc_buf; 99 100 int sc_error; /* bottom-half error */ 101 int sc_flags; 102 #define BPP_OPEN 0x01 /* Device is open */ 103 #define BPP_XCLUDE 0x02 /* Exclusive-open mode */ 104 #define BPP_ASYNC 0x04 /* Asynchronous I/O mode */ 105 #define BPP_LOCKED 0x08 /* DMA in progress */ 106 #define BPP_WANT 0x10 /* Waiting for DMA */ 107 108 struct selinfo sc_rsel; 109 struct selinfo sc_wsel; 110 struct proc *sc_asyncproc; /* Process to notify if async */ 111 112 /* Hardware state */ 113 struct hwstate sc_hwdefault; 114 struct hwstate sc_hwcurrent; 115 }; 116 117 static int bppmatch __P((struct device *, struct cfdata *, void *)); 118 static void bppattach __P((struct device *, struct device *, void *)); 119 static int bppintr __P((void *)); 120 static void bpp_setparams __P((struct bpp_softc *, struct hwstate *)); 121 122 CFATTACH_DECL(bpp, sizeof(struct bpp_softc), 123 bppmatch, bppattach, NULL, NULL); 124 125 extern struct cfdriver bpp_cd; 126 127 dev_type_open(bppopen); 128 dev_type_close(bppclose); 129 dev_type_write(bppwrite); 130 dev_type_ioctl(bppioctl); 131 dev_type_poll(bpppoll); 132 133 const struct cdevsw bpp_cdevsw = { 134 bppopen, bppclose, noread, bppwrite, bppioctl, 135 nostop, notty, bpppoll, nommap, 136 }; 137 138 #define BPPUNIT(dev) (minor(dev)) 139 140 141 int 142 bppmatch(parent, cf, aux) 143 struct device *parent; 144 struct cfdata *cf; 145 void *aux; 146 { 147 struct sbus_attach_args *sa = aux; 148 149 return (strcmp("SUNW,bpp", sa->sa_name) == 0); 150 } 151 152 void 153 bppattach(parent, self, aux) 154 struct device *parent, *self; 155 void *aux; 156 { 157 struct sbus_attach_args *sa = aux; 158 struct bpp_softc *dsc = (void *)self; 159 struct lsi64854_softc *sc = &dsc->sc_lsi64854; 160 int burst, sbusburst; 161 int node; 162 163 sc->sc_bustag = sa->sa_bustag; 164 sc->sc_dmatag = sa->sa_dmatag; 165 node = sa->sa_node; 166 167 /* Map device registers */ 168 if (sbus_bus_map(sa->sa_bustag, 169 sa->sa_slot, sa->sa_offset, sa->sa_size, 170 0, &sc->sc_regs) != 0) { 171 printf("%s: cannot map registers\n", self->dv_xname); 172 return; 173 } 174 175 /* 176 * Get transfer burst size from PROM and plug it into the 177 * controller registers. This is needed on the Sun4m; do 178 * others need it too? 179 */ 180 sbusburst = ((struct sbus_softc *)parent)->sc_burst; 181 if (sbusburst == 0) 182 sbusburst = SBUS_BURST_32 - 1; /* 1->16 */ 183 184 burst = PROM_getpropint(node, "burst-sizes", -1); 185 if (burst == -1) 186 /* take SBus burst sizes */ 187 burst = sbusburst; 188 189 /* Clamp at parent's burst sizes */ 190 burst &= sbusburst; 191 sc->sc_burst = (burst & SBUS_BURST_32) ? 32 : 192 (burst & SBUS_BURST_16) ? 16 : 0; 193 194 /* Join the Sbus device family */ 195 dsc->sc_sd.sd_reset = (void *)0; 196 sbus_establish(&dsc->sc_sd, self); 197 198 /* Initialize the DMA channel */ 199 sc->sc_channel = L64854_CHANNEL_PP; 200 lsi64854_attach(sc); 201 202 /* Establish interrupt handler */ 203 if (sa->sa_nintr) { 204 sc->sc_intrchain = bppintr; 205 sc->sc_intrchainarg = dsc; 206 (void)bus_intr_establish(sa->sa_bustag, sa->sa_pri, IPL_TTY, 0, 207 bppintr, sc); 208 } 209 210 /* Allocate buffer XXX - should actually use dmamap_uio() */ 211 dsc->sc_bufsz = 1024; 212 dsc->sc_buf = malloc(dsc->sc_bufsz, M_DEVBUF, M_NOWAIT); 213 214 /* XXX read default state */ 215 { 216 bus_space_handle_t h = sc->sc_regs; 217 struct hwstate *hw = &dsc->sc_hwdefault; 218 int ack_rate = sa->sa_frequency/1000000; 219 220 hw->hw_hcr = bus_space_read_2(sc->sc_bustag, h, L64854_REG_HCR); 221 hw->hw_ocr = bus_space_read_2(sc->sc_bustag, h, L64854_REG_OCR); 222 hw->hw_tcr = bus_space_read_1(sc->sc_bustag, h, L64854_REG_TCR); 223 hw->hw_or = bus_space_read_1(sc->sc_bustag, h, L64854_REG_OR); 224 225 DPRINTF(("bpp: hcr %x ocr %x tcr %x or %x\n", 226 hw->hw_hcr, hw->hw_ocr, hw->hw_tcr, hw->hw_or)); 227 /* Set these to sane values */ 228 hw->hw_hcr = ((ack_rate<<BPP_HCR_DSS_SHFT)&BPP_HCR_DSS_MASK) 229 | ((ack_rate<<BPP_HCR_DSW_SHFT)&BPP_HCR_DSW_MASK); 230 hw->hw_ocr |= BPP_OCR_ACK_OP; 231 } 232 } 233 234 void 235 bpp_setparams(sc, hw) 236 struct bpp_softc *sc; 237 struct hwstate *hw; 238 { 239 u_int16_t irq; 240 bus_space_tag_t t = sc->sc_lsi64854.sc_bustag; 241 bus_space_handle_t h = sc->sc_lsi64854.sc_regs; 242 243 bus_space_write_2(t, h, L64854_REG_HCR, hw->hw_hcr); 244 bus_space_write_2(t, h, L64854_REG_OCR, hw->hw_ocr); 245 bus_space_write_1(t, h, L64854_REG_TCR, hw->hw_tcr); 246 bus_space_write_1(t, h, L64854_REG_OR, hw->hw_or); 247 248 /* Only change IRP settings in interrupt status register */ 249 irq = bus_space_read_2(t, h, L64854_REG_ICR); 250 irq &= ~BPP_ALLIRP; 251 irq |= (hw->hw_irq & BPP_ALLIRP); 252 bus_space_write_2(t, h, L64854_REG_ICR, irq); 253 DPRINTF(("bpp_setparams: hcr %x ocr %x tcr %x or %x, irq %x\n", 254 hw->hw_hcr, hw->hw_ocr, hw->hw_tcr, hw->hw_or, irq)); 255 } 256 257 int 258 bppopen(dev, flags, mode, p) 259 dev_t dev; 260 int flags, mode; 261 struct proc *p; 262 { 263 int unit = BPPUNIT(dev); 264 struct bpp_softc *sc; 265 struct lsi64854_softc *lsi; 266 u_int16_t irq; 267 int s; 268 269 if (unit >= bpp_cd.cd_ndevs) 270 return (ENXIO); 271 sc = bpp_cd.cd_devs[unit]; 272 273 if ((sc->sc_flags & (BPP_OPEN|BPP_XCLUDE)) == (BPP_OPEN|BPP_XCLUDE)) 274 return (EBUSY); 275 276 lsi = &sc->sc_lsi64854; 277 278 /* Set default parameters */ 279 sc->sc_hwcurrent = sc->sc_hwdefault; 280 s = splbpp(); 281 bpp_setparams(sc, &sc->sc_hwdefault); 282 splx(s); 283 284 /* Enable interrupts */ 285 irq = BPP_ERR_IRQ_EN; 286 irq |= sc->sc_hwdefault.hw_irq; 287 bus_space_write_2(lsi->sc_bustag, lsi->sc_regs, L64854_REG_ICR, irq); 288 return (0); 289 } 290 291 int 292 bppclose(dev, flags, mode, p) 293 dev_t dev; 294 int flags, mode; 295 struct proc *p; 296 { 297 struct bpp_softc *sc = bpp_cd.cd_devs[BPPUNIT(dev)]; 298 struct lsi64854_softc *lsi = &sc->sc_lsi64854; 299 u_int16_t irq; 300 301 /* Turn off all interrupt enables */ 302 irq = sc->sc_hwdefault.hw_irq | BPP_ALLIRQ; 303 irq &= ~BPP_ALLEN; 304 bus_space_write_2(lsi->sc_bustag, lsi->sc_regs, L64854_REG_ICR, irq); 305 306 sc->sc_asyncproc = NULL; 307 sc->sc_flags = 0; 308 return (0); 309 } 310 311 int 312 bppwrite(dev, uio, flags) 313 dev_t dev; 314 struct uio *uio; 315 int flags; 316 { 317 struct bpp_softc *sc = bpp_cd.cd_devs[BPPUNIT(dev)]; 318 struct lsi64854_softc *lsi = &sc->sc_lsi64854; 319 int error = 0; 320 int s; 321 322 /* 323 * Wait until the DMA engine is free. 324 */ 325 s = splbpp(); 326 while ((sc->sc_flags & BPP_LOCKED) != 0) { 327 if ((flags & IO_NDELAY) != 0) { 328 splx(s); 329 return (EWOULDBLOCK); 330 } 331 332 sc->sc_flags |= BPP_WANT; 333 error = tsleep(sc->sc_buf, PZERO|PCATCH, "bppwrite", 0); 334 if (error != 0) { 335 splx(s); 336 return (error); 337 } 338 } 339 sc->sc_flags |= BPP_LOCKED; 340 splx(s); 341 342 /* 343 * Move data from user space into our private buffer 344 * and start DMA. 345 */ 346 while (uio->uio_resid > 0) { 347 caddr_t bp = sc->sc_buf; 348 size_t len = min(sc->sc_bufsz, uio->uio_resid); 349 350 if ((error = uiomove(bp, len, uio)) != 0) 351 break; 352 353 while (len > 0) { 354 u_int8_t tcr; 355 size_t size = len; 356 DMA_SETUP(lsi, &bp, &len, 0, &size); 357 358 #ifdef DEBUG 359 if (bppdebug) { 360 int i; 361 printf("bpp: writing %ld : ", len); 362 for (i=0; i<len; i++) printf("%c(0x%x)", bp[i], bp[i]); 363 printf("\n"); 364 } 365 #endif 366 367 /* Clear direction control bit */ 368 tcr = bus_space_read_1(lsi->sc_bustag, lsi->sc_regs, 369 L64854_REG_TCR); 370 tcr &= ~BPP_TCR_DIR; 371 bus_space_write_1(lsi->sc_bustag, lsi->sc_regs, 372 L64854_REG_TCR, tcr); 373 374 /* Enable DMA */ 375 s = splbpp(); 376 DMA_GO(lsi); 377 error = tsleep(sc, PZERO|PCATCH, "bppdma", 0); 378 splx(s); 379 if (error != 0) 380 goto out; 381 382 /* Bail out if bottom half reported an error */ 383 if ((error = sc->sc_error) != 0) 384 goto out; 385 386 /* 387 * lsi64854_pp_intr() does this part. 388 * 389 * len -= size; 390 */ 391 } 392 } 393 394 out: 395 DPRINTF(("bpp done %x\n", error)); 396 s = splbpp(); 397 sc->sc_flags &= ~BPP_LOCKED; 398 if ((sc->sc_flags & BPP_WANT) != 0) { 399 sc->sc_flags &= ~BPP_WANT; 400 wakeup(sc->sc_buf); 401 } 402 splx(s); 403 return (error); 404 } 405 406 /* move to header: */ 407 #define BPPIOCSPARAM _IOW('P', 0x1, struct hwstate) 408 #define BPPIOCGPARAM _IOR('P', 0x2, struct hwstate) 409 410 int 411 bppioctl(dev, cmd, data, flag, p) 412 dev_t dev; 413 u_long cmd; 414 caddr_t data; 415 int flag; 416 struct proc *p; 417 { 418 struct bpp_softc *sc = bpp_cd.cd_devs[BPPUNIT(dev)]; 419 struct hwstate *hw, *chw; 420 int error = 0; 421 int s; 422 423 switch(cmd) { 424 case BPPIOCSPARAM: 425 chw = &sc->sc_hwcurrent; 426 hw = (struct hwstate *)data; 427 428 /* 429 * Extract and store user-settable bits. 430 */ 431 #define _bpp_set(reg,mask) do { \ 432 chw->reg &= ~(mask); \ 433 chw->reg |= (hw->reg & (mask)); \ 434 } while (0) 435 _bpp_set(hw_hcr, BPP_HCR_DSS_MASK|BPP_HCR_DSW_MASK); 436 _bpp_set(hw_ocr, BPP_OCR_USER); 437 _bpp_set(hw_tcr, BPP_TCR_USER); 438 _bpp_set(hw_or, BPP_OR_USER); 439 _bpp_set(hw_irq, BPP_IRQ_USER); 440 #undef _bpp_set 441 442 /* Apply settings */ 443 s = splbpp(); 444 bpp_setparams(sc, chw); 445 splx(s); 446 break; 447 case BPPIOCGPARAM: 448 *((struct hwstate *)data) = sc->sc_hwcurrent; 449 break; 450 case TIOCEXCL: 451 s = splbpp(); 452 sc->sc_flags |= BPP_XCLUDE; 453 splx(s); 454 break; 455 case TIOCNXCL: 456 s = splbpp(); 457 sc->sc_flags &= ~BPP_XCLUDE; 458 splx(s); 459 break; 460 case FIOASYNC: 461 s = splbpp(); 462 if (*(int *)data) { 463 if (sc->sc_asyncproc != NULL) 464 error = EBUSY; 465 else 466 sc->sc_asyncproc = p; 467 } else 468 sc->sc_asyncproc = NULL; 469 splx(s); 470 break; 471 default: 472 break; 473 } 474 475 return (error); 476 } 477 478 int 479 bpppoll(dev, events, p) 480 dev_t dev; 481 int events; 482 struct proc *p; 483 { 484 struct bpp_softc *sc = bpp_cd.cd_devs[BPPUNIT(dev)]; 485 int revents = 0; 486 487 if (events & (POLLIN | POLLRDNORM)) { 488 /* read is not yet implemented */ 489 } 490 491 if (events & (POLLOUT | POLLWRNORM)) { 492 if ((sc->sc_flags & BPP_LOCKED) == 0) 493 revents |= (POLLOUT | POLLWRNORM); 494 } 495 496 if (revents == 0) { 497 if (events & (POLLIN | POLLRDNORM)) 498 selrecord(p, &sc->sc_rsel); 499 if (events & (POLLOUT | POLLWRNORM)) 500 selrecord(p, &sc->sc_wsel); 501 } 502 503 return (revents); 504 } 505 506 int 507 bppintr(arg) 508 void *arg; 509 { 510 struct bpp_softc *sc = arg; 511 struct lsi64854_softc *lsi = &sc->sc_lsi64854; 512 u_int16_t irq; 513 514 /* First handle any possible DMA interrupts */ 515 if (lsi64854_pp_intr((void *)lsi) == -1) 516 sc->sc_error = 1; 517 518 irq = bus_space_read_2(lsi->sc_bustag, lsi->sc_regs, L64854_REG_ICR); 519 /* Ack all interrupts */ 520 bus_space_write_2(lsi->sc_bustag, lsi->sc_regs, L64854_REG_ICR, 521 irq | BPP_ALLIRQ); 522 523 DPRINTF(("bpp_intr: %x\n", irq)); 524 /* Did our device interrupt? */ 525 if ((irq & BPP_ALLIRQ) == 0) 526 return (0); 527 528 if ((sc->sc_flags & BPP_LOCKED) != 0) 529 wakeup(sc); 530 else if ((sc->sc_flags & BPP_WANT) != 0) { 531 sc->sc_flags &= ~BPP_WANT; 532 wakeup(sc->sc_buf); 533 } else { 534 selwakeup(&sc->sc_wsel); 535 if (sc->sc_asyncproc != NULL) 536 psignal(sc->sc_asyncproc, SIGIO); 537 } 538 return (1); 539 } 540
Indexes created Thu Oct 02 14:10:14 GMT 2025