bpp.c revision 1.8.6.2
1 /* $NetBSD: bpp.c,v 1.8.6.2 2001/10/10 11:57:00 fvdl Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <sys/param.h> 40 #include <sys/ioctl.h> 41 #include <sys/fcntl.h> 42 #include <sys/systm.h> 43 #include <sys/kernel.h> 44 #include <sys/vnode.h> 45 #include <sys/poll.h> 46 #include <sys/select.h> 47 #include <sys/malloc.h> 48 #include <sys/proc.h> 49 #include <sys/signalvar.h> 50 #include <sys/conf.h> 51 #include <sys/errno.h> 52 #include <sys/device.h> 53 #include <sys/vnode.h> 54 55 #include <machine/bus.h> 56 #include <machine/intr.h> 57 #include <machine/autoconf.h> 58 #include <machine/conf.h> 59 60 #include <dev/ic/lsi64854reg.h> 61 #include <dev/ic/lsi64854var.h> 62 63 #include <dev/sbus/sbusvar.h> 64 #include <dev/sbus/bppreg.h> 65 66 #define splbpp() spltty() /* XXX */ 67 68 #ifdef DEBUG 69 #define DPRINTF(x) do { if (bppdebug) printf x ; } while (0) 70 int bppdebug = 1; 71 #else 72 #define DPRINTF(x) 73 #endif 74 75 #if 0 76 struct bpp_param { 77 int bpp_dss; /* data setup to strobe */ 78 int bpp_dsw; /* data strobe width */ 79 int bpp_outputpins; /* Select/Autofeed/Init pins */ 80 int bpp_inputpins; /* Error/Select/Paperout pins */ 81 }; 82 #endif 83 84 struct hwstate { 85 u_int16_t hw_hcr; /* Hardware config register */ 86 u_int16_t hw_ocr; /* Operation config register */ 87 u_int8_t hw_tcr; /* Transfer Control register */ 88 u_int8_t hw_or; /* Output register */ 89 u_int16_t hw_irq; /* IRQ; polarity bits only */ 90 }; 91 92 struct bpp_softc { 93 struct lsi64854_softc sc_lsi64854; /* base device */ 94 struct sbusdev sc_sd; /* sbus device */ 95 96 size_t sc_bufsz; /* temp buffer */ 97 caddr_t sc_buf; 98 99 int sc_error; /* bottom-half error */ 100 int sc_flags; 101 #define BPP_OPEN 0x01 /* Device is open */ 102 #define BPP_XCLUDE 0x02 /* Exclusive-open mode */ 103 #define BPP_ASYNC 0x04 /* Asynchronous I/O mode */ 104 #define BPP_LOCKED 0x08 /* DMA in progress */ 105 #define BPP_WANT 0x10 /* Waiting for DMA */ 106 107 struct selinfo sc_rsel; 108 struct selinfo sc_wsel; 109 struct proc *sc_asyncproc; /* Process to notify if async */ 110 111 /* Hardware state */ 112 struct hwstate sc_hwdefault; 113 struct hwstate sc_hwcurrent; 114 }; 115 116 static int bppmatch __P((struct device *, struct cfdata *, void *)); 117 static void bppattach __P((struct device *, struct device *, void *)); 118 static int bppintr __P((void *)); 119 static void bpp_setparams __P((struct bpp_softc *, struct hwstate *)); 120 121 struct cfattach bpp_ca = { 122 sizeof(struct bpp_softc), bppmatch, bppattach 123 }; 124 125 extern struct cfdriver bpp_cd; 126 #define BPPUNIT(dev) (minor(dev)) 127 128 129 int 130 bppmatch(parent, cf, aux) 131 struct device *parent; 132 struct cfdata *cf; 133 void *aux; 134 { 135 struct sbus_attach_args *sa = aux; 136 137 return (strcmp("SUNW,bpp", sa->sa_name) == 0); 138 } 139 140 void 141 bppattach(parent, self, aux) 142 struct device *parent, *self; 143 void *aux; 144 { 145 struct sbus_attach_args *sa = aux; 146 struct bpp_softc *dsc = (void *)self; 147 struct lsi64854_softc *sc = &dsc->sc_lsi64854; 148 int burst, sbusburst; 149 int node; 150 151 sc->sc_bustag = sa->sa_bustag; 152 sc->sc_dmatag = sa->sa_dmatag; 153 node = sa->sa_node; 154 155 /* Map device registers */ 156 if (bus_space_map2(sa->sa_bustag, 157 sa->sa_slot, 158 sa->sa_offset, 159 sa->sa_size, 160 BUS_SPACE_MAP_LINEAR, 161 0, &sc->sc_regs) != 0) { 162 printf("%s: cannot map registers\n", self->dv_xname); 163 return; 164 } 165 166 /* 167 * Get transfer burst size from PROM and plug it into the 168 * controller registers. This is needed on the Sun4m; do 169 * others need it too? 170 */ 171 sbusburst = ((struct sbus_softc *)parent)->sc_burst; 172 if (sbusburst == 0) 173 sbusburst = SBUS_BURST_32 - 1; /* 1->16 */ 174 175 burst = PROM_getpropint(node, "burst-sizes", -1); 176 if (burst == -1) 177 /* take SBus burst sizes */ 178 burst = sbusburst; 179 180 /* Clamp at parent's burst sizes */ 181 burst &= sbusburst; 182 sc->sc_burst = (burst & SBUS_BURST_32) ? 32 : 183 (burst & SBUS_BURST_16) ? 16 : 0; 184 185 /* Join the Sbus device family */ 186 dsc->sc_sd.sd_reset = (void *)0; 187 sbus_establish(&dsc->sc_sd, self); 188 189 /* Initialize the DMA channel */ 190 sc->sc_channel = L64854_CHANNEL_PP; 191 lsi64854_attach(sc); 192 193 /* Establish interrupt handler */ 194 if (sa->sa_nintr) { 195 sc->sc_intrchain = bppintr; 196 sc->sc_intrchainarg = dsc; 197 (void)bus_intr_establish(sa->sa_bustag, sa->sa_pri, IPL_TTY, 0, 198 bppintr, sc); 199 } 200 201 /* Allocate buffer XXX - should actually use dmamap_uio() */ 202 dsc->sc_bufsz = 1024; 203 dsc->sc_buf = malloc(dsc->sc_bufsz, M_DEVBUF, M_NOWAIT); 204 205 /* XXX read default state */ 206 { 207 bus_space_handle_t h = sc->sc_regs; 208 struct hwstate *hw = &dsc->sc_hwdefault; 209 int ack_rate = sa->sa_frequency/1000000; 210 211 hw->hw_hcr = bus_space_read_2(sc->sc_bustag, h, L64854_REG_HCR); 212 hw->hw_ocr = bus_space_read_2(sc->sc_bustag, h, L64854_REG_OCR); 213 hw->hw_tcr = bus_space_read_1(sc->sc_bustag, h, L64854_REG_TCR); 214 hw->hw_or = bus_space_read_1(sc->sc_bustag, h, L64854_REG_OR); 215 216 DPRINTF(("bpp: hcr %x ocr %x tcr %x or %x\n", 217 hw->hw_hcr, hw->hw_ocr, hw->hw_tcr, hw->hw_or)); 218 /* Set these to sane values */ 219 hw->hw_hcr = ((ack_rate<<BPP_HCR_DSS_SHFT)&BPP_HCR_DSS_MASK) 220 | ((ack_rate<<BPP_HCR_DSW_SHFT)&BPP_HCR_DSW_MASK); 221 hw->hw_ocr |= BPP_OCR_ACK_OP; 222 } 223 } 224 225 void 226 bpp_setparams(sc, hw) 227 struct bpp_softc *sc; 228 struct hwstate *hw; 229 { 230 u_int16_t irq; 231 bus_space_tag_t t = sc->sc_lsi64854.sc_bustag; 232 bus_space_handle_t h = sc->sc_lsi64854.sc_regs; 233 234 bus_space_write_2(t, h, L64854_REG_HCR, hw->hw_hcr); 235 bus_space_write_2(t, h, L64854_REG_OCR, hw->hw_ocr); 236 bus_space_write_1(t, h, L64854_REG_TCR, hw->hw_tcr); 237 bus_space_write_1(t, h, L64854_REG_OR, hw->hw_or); 238 239 /* Only change IRP settings in interrupt status register */ 240 irq = bus_space_read_2(t, h, L64854_REG_ICR); 241 irq &= ~BPP_ALLIRP; 242 irq |= (hw->hw_irq & BPP_ALLIRP); 243 bus_space_write_2(t, h, L64854_REG_ICR, irq); 244 DPRINTF(("bpp_setparams: hcr %x ocr %x tcr %x or %x, irq %x\n", 245 hw->hw_hcr, hw->hw_ocr, hw->hw_tcr, hw->hw_or, irq)); 246 } 247 248 int 249 bppopen(devvp, flags, mode, p) 250 struct vnode *devvp; 251 int flags, mode; 252 struct proc *p; 253 { 254 dev_t dev = vdev_rdev(devvp); 255 int unit = BPPUNIT(dev); 256 struct bpp_softc *sc; 257 struct lsi64854_softc *lsi; 258 u_int16_t irq; 259 int s; 260 261 if (unit >= bpp_cd.cd_ndevs) 262 return (ENXIO); 263 sc = bpp_cd.cd_devs[unit]; 264 265 if ((sc->sc_flags & (BPP_OPEN|BPP_XCLUDE)) == (BPP_OPEN|BPP_XCLUDE)) 266 return (EBUSY); 267 268 lsi = &sc->sc_lsi64854; 269 270 /* Set default parameters */ 271 sc->sc_hwcurrent = sc->sc_hwdefault; 272 s = splbpp(); 273 bpp_setparams(sc, &sc->sc_hwdefault); 274 splx(s); 275 276 vdev_setprivdata(devvp, sc); 277 278 /* Enable interrupts */ 279 irq = BPP_ERR_IRQ_EN; 280 irq |= sc->sc_hwdefault.hw_irq; 281 bus_space_write_2(lsi->sc_bustag, lsi->sc_regs, L64854_REG_ICR, irq); 282 return (0); 283 } 284 285 int 286 bppclose(devvp, flags, mode, p) 287 struct vnode *devvp; 288 int flags, mode; 289 struct proc *p; 290 { 291 struct bpp_softc *sc = vdev_privdata(devvp); 292 struct lsi64854_softc *lsi = &sc->sc_lsi64854; 293 u_int16_t irq; 294 295 /* Turn off all interrupt enables */ 296 irq = sc->sc_hwdefault.hw_irq | BPP_ALLIRQ; 297 irq &= ~BPP_ALLEN; 298 bus_space_write_2(lsi->sc_bustag, lsi->sc_regs, L64854_REG_ICR, irq); 299 300 sc->sc_asyncproc = NULL; 301 sc->sc_flags = 0; 302 return (0); 303 } 304 305 int 306 bppread(devvp, uio, flags) 307 struct vnode *devvp; 308 struct uio *uio; 309 int flags; 310 { 311 312 return (ENXIO); 313 } 314 315 int 316 bppwrite(devvp, uio, flags) 317 struct vnode *devvp; 318 struct uio *uio; 319 int flags; 320 { 321 struct bpp_softc *sc = vdev_privdata(devvp); 322 struct lsi64854_softc *lsi = &sc->sc_lsi64854; 323 int error = 0; 324 int s; 325 326 /* 327 * Wait until the DMA engine is free. 328 */ 329 s = splbpp(); 330 while ((sc->sc_flags & BPP_LOCKED) != 0) { 331 if ((flags & IO_NDELAY) != 0) { 332 splx(s); 333 return (EWOULDBLOCK); 334 } 335 336 sc->sc_flags |= BPP_WANT; 337 error = tsleep(sc->sc_buf, PZERO|PCATCH, "bppwrite", 0); 338 if (error != 0) { 339 splx(s); 340 return (error); 341 } 342 } 343 sc->sc_flags |= BPP_LOCKED; 344 splx(s); 345 346 /* 347 * Move data from user space into our private buffer 348 * and start DMA. 349 */ 350 while (uio->uio_resid > 0) { 351 caddr_t bp = sc->sc_buf; 352 size_t len = min(sc->sc_bufsz, uio->uio_resid); 353 354 if ((error = uiomove(bp, len, uio)) != 0) 355 break; 356 357 while (len > 0) { 358 u_int8_t tcr; 359 size_t size = len; 360 DMA_SETUP(lsi, &bp, &len, 0, &size); 361 362 #ifdef DEBUG 363 if (bppdebug) { 364 int i; 365 printf("bpp: writing %ld : ", len); 366 for (i=0; i<len; i++) printf("%c(0x%x)", bp[i], bp[i]); 367 printf("\n"); 368 } 369 #endif 370 371 /* Clear direction control bit */ 372 tcr = bus_space_read_1(lsi->sc_bustag, lsi->sc_regs, 373 L64854_REG_TCR); 374 tcr &= ~BPP_TCR_DIR; 375 bus_space_write_1(lsi->sc_bustag, lsi->sc_regs, 376 L64854_REG_TCR, tcr); 377 378 /* Enable DMA */ 379 s = splbpp(); 380 DMA_GO(lsi); 381 error = tsleep(sc, PZERO|PCATCH, "bppdma", 0); 382 splx(s); 383 if (error != 0) 384 goto out; 385 386 /* Bail out if bottom half reported an error */ 387 if ((error = sc->sc_error) != 0) 388 goto out; 389 390 /* 391 * lsi64854_pp_intr() does this part. 392 * 393 * len -= size; 394 */ 395 } 396 } 397 398 out: 399 DPRINTF(("bpp done %x\n", error)); 400 s = splbpp(); 401 sc->sc_flags &= ~BPP_LOCKED; 402 if ((sc->sc_flags & BPP_WANT) != 0) { 403 sc->sc_flags &= ~BPP_WANT; 404 wakeup(sc->sc_buf); 405 } 406 splx(s); 407 return (error); 408 } 409 410 /* move to header: */ 411 #define BPPIOCSPARAM _IOW('P', 0x1, struct hwstate) 412 #define BPPIOCGPARAM _IOR('P', 0x2, struct hwstate) 413 414 int 415 bppioctl(devvp, cmd, data, flag, p) 416 struct vnode *devvp; 417 u_long cmd; 418 caddr_t data; 419 int flag; 420 struct proc *p; 421 { 422 struct bpp_softc *sc = vdev_privdata(devvp); 423 struct hwstate *hw, *chw; 424 int error = 0; 425 int s; 426 427 switch(cmd) { 428 case BPPIOCSPARAM: 429 chw = &sc->sc_hwcurrent; 430 hw = (struct hwstate *)data; 431 432 /* 433 * Extract and store user-settable bits. 434 */ 435 #define _bpp_set(reg,mask) do { \ 436 chw->reg &= ~(mask); \ 437 chw->reg |= (hw->reg & (mask)); \ 438 } while (0) 439 _bpp_set(hw_hcr, BPP_HCR_DSS_MASK|BPP_HCR_DSW_MASK); 440 _bpp_set(hw_ocr, BPP_OCR_USER); 441 _bpp_set(hw_tcr, BPP_TCR_USER); 442 _bpp_set(hw_or, BPP_OR_USER); 443 _bpp_set(hw_irq, BPP_IRQ_USER); 444 #undef _bpp_set 445 446 /* Apply settings */ 447 s = splbpp(); 448 bpp_setparams(sc, chw); 449 splx(s); 450 break; 451 case BPPIOCGPARAM: 452 *((struct hwstate *)data) = sc->sc_hwcurrent; 453 break; 454 case TIOCEXCL: 455 s = splbpp(); 456 sc->sc_flags |= BPP_XCLUDE; 457 splx(s); 458 break; 459 case TIOCNXCL: 460 s = splbpp(); 461 sc->sc_flags &= ~BPP_XCLUDE; 462 splx(s); 463 break; 464 case FIOASYNC: 465 s = splbpp(); 466 if (*(int *)data) { 467 if (sc->sc_asyncproc != NULL) 468 error = EBUSY; 469 else 470 sc->sc_asyncproc = p; 471 } else 472 sc->sc_asyncproc = NULL; 473 splx(s); 474 break; 475 default: 476 break; 477 } 478 479 return (error); 480 } 481 482 int 483 bpppoll(devvp, events, p) 484 struct vnode *devvp; 485 int events; 486 struct proc *p; 487 { 488 struct bpp_softc *sc = vdev_privdata(devvp); 489 int revents = 0; 490 491 if (events & (POLLIN | POLLRDNORM)) { 492 /* read is not yet implemented */ 493 } 494 495 if (events & (POLLOUT | POLLWRNORM)) { 496 if ((sc->sc_flags & BPP_LOCKED) == 0) 497 revents |= (POLLOUT | POLLWRNORM); 498 } 499 500 if (revents == 0) { 501 if (events & (POLLIN | POLLRDNORM)) 502 selrecord(p, &sc->sc_rsel); 503 if (events & (POLLOUT | POLLWRNORM)) 504 selrecord(p, &sc->sc_wsel); 505 } 506 507 return (revents); 508 } 509 510 int 511 bppintr(arg) 512 void *arg; 513 { 514 struct bpp_softc *sc = arg; 515 struct lsi64854_softc *lsi = &sc->sc_lsi64854; 516 u_int16_t irq; 517 518 /* First handle any possible DMA interrupts */ 519 if (lsi64854_pp_intr((void *)lsi) == -1) 520 sc->sc_error = 1; 521 522 irq = bus_space_read_2(lsi->sc_bustag, lsi->sc_regs, L64854_REG_ICR); 523 /* Ack all interrupts */ 524 bus_space_write_2(lsi->sc_bustag, lsi->sc_regs, L64854_REG_ICR, 525 irq | BPP_ALLIRQ); 526 527 DPRINTF(("bpp_intr: %x\n", irq)); 528 /* Did our device interrupt? */ 529 if ((irq & BPP_ALLIRQ) == 0) 530 return (0); 531 532 if ((sc->sc_flags & BPP_LOCKED) != 0) 533 wakeup(sc); 534 else if ((sc->sc_flags & BPP_WANT) != 0) { 535 sc->sc_flags &= ~BPP_WANT; 536 wakeup(sc->sc_buf); 537 } else { 538 selwakeup(&sc->sc_wsel); 539 if (sc->sc_asyncproc != NULL) 540 psignal(sc->sc_asyncproc, SIGIO); 541 } 542 return (1); 543 } 544
Indexes created Thu Oct 02 14:10:14 GMT 2025