cgtwelvereg.h revision 1.3
1 /* $NetBSD: cgtwelvereg.h,v 1.3 2016/04/21 18:24:02 macallan Exp $ */ 2 3 /*- 4 * Copyright (c) 2010 Michael Lorenz 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* 30 * some hardware constants for the CG12 / Matrox SG3 31 * mostly from SMI's cg12reg.h 32 */ 33 34 #ifndef CG12REG_H 35 #define CG12REG_H 36 37 /* SBus offsets known so far */ 38 #define CG12_FB_MONO 0x780000 39 40 #define CG12_OFF_PROM 0x000000 41 #define CG12_OFF_USSC 0x040000 42 #define CG12_OFF_REGISTERS 0x040000 43 #define CG12_OFF_DPU 0x040100 44 #define CG12_OFF_APU 0x040200 45 #define CG12_OFF_DAC 0x040300 46 #define CG12_OFF_DAC_ADDR0 0x040300 47 #define CG12_OFF_DAC_ADDR1 0x040400 48 #define CG12_OFF_DAC_CTRL 0x040500 49 #define CG12_OFF_DAC_PRIME 0x040600 50 #define CG12_OFF_EIC 0x040700 51 #define CG12_OFF_WSC 0x040800 52 #define CG12_OFF_WSC_DATA 0x040800 53 #define CG12_OFF_WSC_ADDR 0x040900 54 #define CG12_OFF_DRAM 0x400000 55 #define CG12_OFF_SHMEM CG12_OFF_DRAM + 0x0E0000 56 #define CG12_OFF_DISPLAY 0x600000 57 #define CG12_OFF_WID 0x600000 58 #define CG12_OFF_OVERLAY0 0x700000 59 #define CG12_OFF_OVERLAY1 0x780000 60 #define CG12_OFF_INTEN 0x800000 61 #define CG12_OFF_DEPTH 0xC00000 62 63 #define CG12_OFF_CTL CG12_OFF_USSC /* 0x040000 */ 64 65 #define CG12_PROM_SIZE 0x010000 66 #define CG12_USSC_SIZE 0x000060 /* ### check up */ 67 #define CG12_DPU_SIZE 0x000080 68 #define CG12_APU_SIZE 0x000100 69 #define CG12_DAC_SIZE 0x000400 70 #define CG12_EIC_SIZE 0x000040 71 #define CG12_WSC_SIZE 0x000200 72 #define CG12_WSC_ADDR_SIZE 0x000100 73 #define CG12_WSC_DATA_SIZE 0x000100 74 #define CG12_DRAM_SIZE 0x100000 75 #define CG12_COLOR24_SIZE 0x400000 76 #define CG12_COLOR8_SIZE 0x100000 77 #define CG12_ZBUF_SIZE 0x200000 78 #define CG12_WID_SIZE 0x100000 79 #define CG12_OVERLAY_SIZE 0x020000 80 #define CG12_ENABLE_SIZE 0x020000 81 82 #define CG12_SHMEM_SIZE 0x020000 83 #define CG12_FBCTL_SIZE 0x842000 84 #define CG12_PMCTL_SIZE 0x041000 85 86 /* DPU registers, all register offsets are relative to CG12_OFF_REGISTERS */ 87 #define CG12DPU_R0 0x0100 88 #define CG12DPU_R1 0x0104 89 #define CG12DPU_R2 0x0108 90 #define CG12DPU_R3 0x010c 91 #define CG12DPU_R4 0x0110 92 #define CG12DPU_R5 0x0114 93 #define CG12DPU_R6 0x0118 94 #define CG12DPU_R7 0x011c 95 #define CG12DPU_RELOAD_CTL 0x0120 96 #define CG12DPU_RELOAD_STB 0x0124 97 #define CG12DPU_ALU_CTL 0x0128 98 #define CG12DPU_BLU_CTL 0x012c 99 #define CG12DPU_CONTROL 0x0130 100 #define CG12DPU_XLEFT 0x0134 101 #define CG12DPU_SHIFT_0 0x0138 102 #define CG12DPU_SHIFT_1 0x013c 103 #define CG12DPU_ZOOM 0x0140 104 #define CG12DPU_BSR 0x0144 105 #define CG12DPU_COLOUR0 0x0148 106 #define CG12DPU_COLOUR1 0x014c 107 #define CG12DPU_COMP_OUT 0x0150 108 #define CG12DPU_PLN_RDMSK_HOST 0x0154 109 #define CG12DPU_PLN_WRMSK_HOST 0x0158 110 #define CG12DPU_PLN_RDMSK_LOC 0x015c 111 #define CG12DPU_PLN_WRMSK_LOC 0x0160 112 #define CG12DPU_SCIS_CTL 0x0164 113 #define CG12DPU_CSR 0x0168 114 #define CG12DPU_PLN_REG_SL 0x016c 115 #define CG12DPU_PLN_SL_HOST 0x0170 116 #define CG12DPU_PLN_SL_LOCAL0 0x0174 117 #define CG12DPU_PLN_SL_LOCAL1 0x0178 118 #define CG12DPU_BROADCAST 0x017c 119 120 /* APU registers */ 121 #define CG12APU_IMSG0 0x0200 122 #define CG12APU_MSG0 0x0204 123 #define CG12APU_IMSG1 0x0208 124 #define CG12APU_MSG1 0x020c 125 #define CG12APU_IEN0 0x0210 126 #define CG12APU_IEN1 0x0214 127 #define CG12APU_ICLEAR 0x0218 128 #define CG12APU_ISTATUS 0x021c 129 #define CG12APU_CFCNT 0x0220 130 #define CG12APU_CFWPTR 0x0224 131 #define CG12APU_CFRPTR 0x0228 132 #define CG12APU_CFILEV0 0x022c 133 #define CG12APU_CFILEV1 0x0230 134 #define CG12APU_RFCNT 0x0234 135 #define CG12APU_RFWPTR 0x0238 136 #define CG12APU_RFRPTR 0x023c 137 #define CG12APU_RFILEV0 0x0240 138 #define CG12APU_RFILEV1 0x0244 139 #define CG12APU_SIZE 0x0248 140 #define CG12APU_RES0 0x024c 141 #define CG12APU_RES1 0x0250 142 #define CG12APU_RES2 0x0254 143 #define CG12APU_HACCESS 0x0258 144 #define CG12APU_HPAGE 0x025c 145 #define CG12APU_LACCESS 0x0260 146 #define CG12APU_LPAGE 0x0264 147 #define CG12APU_MACCESS 0x0268 148 #define CG12APU_PPAGE 0x026c 149 #define CG12APU_DWG_CTL 0x0270 150 /* 151 * The following bits are from Matrox Athena docs, they're probably not all 152 * implemented or not in the same spot on the cg12. They're here strictly 153 * for testing. 154 */ 155 #define DWGCTL_LINE_OPEN 0x00000000 156 #define DWGCTL_AUTOLINE_OPEN 0x00000001 157 #define DWGCTL_LINE_CLOSED 0x00000002 158 #define DWGCTL_AUTOLINE_CLOSED 0x00000003 159 #define DWGCTL_TRAPEZOID 0x00000004 160 #define DWGCTL_BITBLT 0x00000008 161 #define DWGCTL_UPLOAD 0x00000009 162 #define DWGCTL_DOWNLOAD 0x0000000a 163 #define DWGCTL_WRITE 0x00000000 /* write only */ 164 #define DWGCTL_RASTER 0x00000010 /* read/write */ 165 #define DWGCTL_ANTIALIAS 0x00000020 166 #define DWGCTL_BLOCKMODE 0x00000040 167 #define DWGCTL_LINEAR 0x00000080 /* XY otherwise */ 168 #define DWGCTL_ROP_MASK 0x000f0000 169 #define DWGCTL_ROP_SHIFT 16 170 #define DWGCTL_TRANSLUCID_MASK 0x00f00000 171 #define DWGCTL_TRANSLUCID_SHIFT 20 /* selects pattern */ 172 #define DWGCTL_BLTMOD_MONO 0x00000000 173 #define DWGCTL_BLTMOD_PLANE 0x02000000 174 #define DWGCTL_BLTMOD_COLOR 0x04000000 /* clipping usable */ 175 #define DWGCTL_BLTMOD_UCOLOR 0x06000000 /* no clipping */ 176 #define DWGCTL_AFOR 0x08000000 /* set for antialias */ 177 #define DWGCTL_UPLOAD_RGB 0x08000000 /* BGR otherwise */ 178 #define DWGCTL_AA_BG 0x10000000 /* us BG color in AA */ 179 #define DWGCTL_UPLOAD_24BIT 0x10000000 /* 32bit otherwise */ 180 #define DWGCTL_EN_PATTERN 0x20000000 181 #define DWGCTL_BLT_TRANSPARENT 0x40000000 /* for color exp. */ 182 183 #define CG12APU_SAM 0x0274 184 #define CG12APU_SGN 0x0278 /* analog to Athena's SIGN register? */ 185 #define CG12APU_LENGTH 0x027c 186 #define CG12APU_DWG_R0 0x0280 187 #define CG12APU_DWG_R1 0x0284 188 #define CG12APU_DWG_R2 0x0288 189 #define CG12APU_DWG_R3 0x028c 190 #define CG12APU_DWG_R4 0x0290 191 #define CG12APU_DWG_R5 0x0294 192 #define CG12APU_DWG_R6 0x0298 193 #define CG12APU_DWG_R7 0x029c 194 #define CG12APU_RELOAD_CTL 0x02a0 195 #define CG12APU_RELOAD_STB 0x02a4 196 #define CG12APU_C_XLEFT 0x02a8 /* clipping? */ 197 #define CG12APU_C_YTOP 0x02ac 198 #define CG12APU_C_XRIGHT 0x02b0 199 #define CG12APU_C_YBOTTOM 0x02b4 200 #define CG12APU_F_XLEFT 0x02b8 201 #define CG12APU_F_XRIGHT 0x02bc 202 #define CG12APU_X_DST 0x02c0 203 #define CG12APU_Y_DST 0x02c4 204 #define CG12APU_DST_CTL 0x02c8 205 #define CG12APU_MORIGIN 0x02cc 206 #define CG12APU_VSG_CTL 0x02d0 207 #define CG12APU_H_SYNC 0x02d4 208 #define CG12APU_H_BLANK 0x02d8 209 #define CG12APU_V_SYNC 0x02dc 210 #define CG12APU_V_BLANK 0x02e0 211 #define CG12APU_VDPYINT 0x02e4 212 #define CG12APU_VSSYNCS 0x02e8 213 #define CG12APU_H_DELAYS 0x02ec 214 #define CG12APU_STDADDR 0x02f0 215 #define CG12APU_HPITCHES 0x02f4 216 #define CG12APU_ZOOM 0x02f8 217 #define CG12APU_TEST 0x02fc 218 219 /* 220 * The "direct port access" register constants. 221 * All HACCESSS values include noHSTXY, noHCLIP, and SWAP. 222 */ 223 224 #define CG12_HPAGE_OVERLAY 0x00000700 /* overlay page */ 225 #define CG12_HACCESS_OVERLAY 0x00000020 /* 1bit/pixel */ 226 #define CG12_PLN_SL_OVERLAY 0x00000017 /* plane 23 */ 227 #define CG12_PLN_WR_OVERLAY 0x00800000 /* write mask */ 228 #define CG12_PLN_RD_OVERLAY 0xffffffff /* read mask */ 229 230 #define CG12_HPAGE_ENABLE 0x00000700 /* overlay page */ 231 #define CG12_HACCESS_ENABLE 0x00000020 /* 1bit/pixel */ 232 #define CG12_PLN_SL_ENABLE 0x00000016 /* plane 22 */ 233 #define CG12_PLN_WR_ENABLE 0x00400000 234 #define CG12_PLN_RD_ENABLE 0xffffffff 235 236 #define CG12_HPAGE_24BIT 0x00000500 /* intensity page */ 237 #define CG12_HACCESS_24BIT 0x00000025 /* 32bits/pixel */ 238 #define CG12_PLN_SL_24BIT 0x00000000 /* all planes */ 239 #define CG12_PLN_WR_24BIT 0x00ffffff 240 #define CG12_PLN_RD_24BIT 0x00ffffff 241 242 #define CG12_HPAGE_8BIT 0x00000500 /* intensity page */ 243 #define CG12_HACCESS_8BIT 0x00000023 /* 8bits/pixel */ 244 #define CG12_PLN_SL_8BIT 0x00000000 245 #define CG12_PLN_WR_8BIT 0x00ffffff 246 #define CG12_PLN_RD_8BIT 0x000000ff 247 248 #define CG12_HPAGE_WID 0x00000700 /* overlay page */ 249 #define CG12_HACCESS_WID 0x00000023 /* 8bits/pixel */ 250 #define CG12_PLN_SL_WID 0x00000010 /* planes 16-23 */ 251 #define CG12_PLN_WR_WID 0x003f0000 252 #define CG12_PLN_RD_WID 0x003f0000 253 254 #define CG12_HPAGE_ZBUF 0x00000000 /* depth page */ 255 #define CG12_HACCESS_ZBUF 0x00000024 /* 16bits/pixel */ 256 #define CG12_PLN_SL_ZBUF 0x00000060 257 #define CG12_PLN_WR_ZBUF 0xffffffff 258 #define CG12_PLN_RD_ZBUF 0xffffffff 259 260 /* RAMDAC registers */ 261 #define CG12DAC_ADDR0 0x0300 262 #define CG12DAC_ADDR1 0x0400 263 #define CG12DAC_CTRL 0x0500 264 #define CG12DAC_DATA 0x0600 265 266 /* WIDs */ 267 #define CG12_WID_8_BIT 0 /* indexed color */ 268 #define CG12_WID_24_BIT 1 /* true color */ 269 #define CG12_WID_ENABLE_2 2 /* overlay/cursor enable has 2 colors */ 270 #define CG12_WID_ENABLE_3 3 /* overlay/cursor enable has 3 colors */ 271 #define CG12_WID_ALT_CMAP 4 /* use alternate colormap */ 272 #define CG12_WID_DBL_BUF_DISP_A 5 /* double buffering display A */ 273 #define CG12_WID_DBL_BUF_DISP_B 6 /* double buffering display B */ 274 #define CG12_WID_ATTRS 7 /* total no of attributes */ 275 276 /* WSC */ 277 #define CG12_WSC_DATA 0x0800 278 #define CG12_WSC_ADDR 0x0900 279 280 /* EIC registers */ 281 #define CG12_EIC_HOST_CONTROL 0x0700 282 #define CG12_EIC_CONTROL 0x0704 283 #define CG12_EIC_C30_CONTROL 0x0708 284 #define CG12_EIC_INTERRUPT 0x070c 285 #define CG12_EIC_DCADDRW 0x0710 286 #define CG12_EIC_DCBYTEW 0x0714 287 #define CG12_EIC_DCSHORTW 0x0718 288 #define CG12_EIC_DCLONGW 0x071c 289 #define CG12_EIC_DCFLOATW 0x0720 290 #define CG12_EIC_DCADDRR 0x0724 291 #define CG12_EIC_DCBYTER 0x0728 292 #define CG12_EIC_DCSHORTR 0x072c 293 #define CG12_EIC_DCLONGR 0x0730 294 #define CG12_EIC_DCFLOATR 0x0734 295 #define CG12_EIC_RESET 0x073c 296 #define CG12EIC_RESET_SYS 0x01000000 297 #define CG12EIC_RESET_DSP 0x02000000 298 299 #endif /* CG12REG_H */ 300
Indexes created Sun Sep 28 16:09:52 GMT 2025