cs4231_sbus.c revision 1.20 1 1.20 pk /* $NetBSD: cs4231_sbus.c,v 1.20 2002/03/27 16:03:52 pk Exp $ */
2 1.2 pk
3 1.2 pk /*-
4 1.18 uwe * Copyright (c) 1998, 1999, 2002 The NetBSD Foundation, Inc.
5 1.2 pk * All rights reserved.
6 1.2 pk *
7 1.2 pk * This code is derived from software contributed to The NetBSD Foundation
8 1.2 pk * by Paul Kranenburg.
9 1.2 pk *
10 1.2 pk * Redistribution and use in source and binary forms, with or without
11 1.2 pk * modification, are permitted provided that the following conditions
12 1.2 pk * are met:
13 1.2 pk * 1. Redistributions of source code must retain the above copyright
14 1.2 pk * notice, this list of conditions and the following disclaimer.
15 1.2 pk * 2. Redistributions in binary form must reproduce the above copyright
16 1.2 pk * notice, this list of conditions and the following disclaimer in the
17 1.2 pk * documentation and/or other materials provided with the distribution.
18 1.2 pk * 3. All advertising materials mentioning features or use of this software
19 1.2 pk * must display the following acknowledgement:
20 1.2 pk * This product includes software developed by the NetBSD
21 1.2 pk * Foundation, Inc. and its contributors.
22 1.2 pk * 4. Neither the name of The NetBSD Foundation nor the names of its
23 1.2 pk * contributors may be used to endorse or promote products derived
24 1.2 pk * from this software without specific prior written permission.
25 1.2 pk *
26 1.2 pk * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
27 1.2 pk * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
28 1.2 pk * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 1.2 pk * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
30 1.2 pk * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
31 1.2 pk * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
32 1.2 pk * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
33 1.2 pk * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
34 1.2 pk * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
35 1.2 pk * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
36 1.2 pk * POSSIBILITY OF SUCH DAMAGE.
37 1.2 pk */
38 1.16 lukem
39 1.16 lukem #include <sys/cdefs.h>
40 1.20 pk __KERNEL_RCSID(0, "$NetBSD: cs4231_sbus.c,v 1.20 2002/03/27 16:03:52 pk Exp $");
41 1.1 pk
42 1.1 pk #include "audio.h"
43 1.1 pk #if NAUDIO > 0
44 1.1 pk
45 1.1 pk #include <sys/param.h>
46 1.1 pk #include <sys/systm.h>
47 1.1 pk #include <sys/errno.h>
48 1.1 pk #include <sys/device.h>
49 1.1 pk #include <sys/malloc.h>
50 1.1 pk
51 1.15 pk #include <machine/bus.h>
52 1.15 pk #include <machine/intr.h>
53 1.15 pk
54 1.15 pk #include <dev/sbus/sbusvar.h>
55 1.1 pk
56 1.1 pk #include <sys/audioio.h>
57 1.1 pk #include <dev/audio_if.h>
58 1.1 pk
59 1.1 pk #include <dev/ic/ad1848reg.h>
60 1.1 pk #include <dev/ic/cs4231reg.h>
61 1.1 pk #include <dev/ic/ad1848var.h>
62 1.11 mrg #include <dev/ic/cs4231var.h>
63 1.1 pk
64 1.18 uwe #include <dev/ic/apcdmareg.h>
65 1.1 pk
66 1.18 uwe #ifdef AUDIO_DEBUG
67 1.18 uwe int cs4231_sbus_debug = 0;
68 1.18 uwe #define DPRINTF(x) if (cs4231_sbus_debug) printf x
69 1.18 uwe #else
70 1.18 uwe #define DPRINTF(x)
71 1.18 uwe #endif
72 1.18 uwe
73 1.18 uwe /* where APC DMA registers are located */
74 1.18 uwe #define CS4231_APCDMA_OFFSET 16
75 1.18 uwe
76 1.18 uwe /* interrupt enable bits except those specific for playback/capture */
77 1.18 uwe #define APC_ENABLE (APC_EI | APC_IE | APC_EIE)
78 1.18 uwe
79 1.18 uwe struct cs4231_sbus_softc {
80 1.18 uwe struct cs4231_softc sc_cs4231;
81 1.18 uwe
82 1.18 uwe struct sbusdev sc_sd; /* sbus device */
83 1.19 eeh bus_space_tag_t sc_bt; /* DMA controller tag */
84 1.19 eeh bus_space_handle_t sc_bh; /* DMA controller registers */
85 1.18 uwe };
86 1.18 uwe
87 1.18 uwe
88 1.18 uwe static int cs4231_sbus_match(struct device *, struct cfdata *, void *);
89 1.18 uwe static void cs4231_sbus_attach(struct device *, struct device *, void *);
90 1.1 pk
91 1.11 mrg struct cfattach audiocs_sbus_ca = {
92 1.18 uwe sizeof(struct cs4231_sbus_softc), cs4231_sbus_match, cs4231_sbus_attach
93 1.18 uwe };
94 1.18 uwe
95 1.18 uwe
96 1.18 uwe
97 1.18 uwe /* audio_hw_if methods specific to apc dma */
98 1.18 uwe static int cs4231_sbus_trigger_output(void *, void *, void *, int,
99 1.18 uwe void (*)(void *), void *,
100 1.18 uwe struct audio_params *);
101 1.18 uwe static int cs4231_sbus_trigger_input(void *, void *, void *, int,
102 1.18 uwe void (*)(void *), void *,
103 1.18 uwe struct audio_params *);
104 1.18 uwe static int cs4231_sbus_halt_output(void *);
105 1.18 uwe static int cs4231_sbus_halt_input(void *);
106 1.18 uwe
107 1.18 uwe struct audio_hw_if audiocs_sbus_hw_if = {
108 1.18 uwe cs4231_open,
109 1.18 uwe cs4231_close,
110 1.18 uwe NULL, /* drain */
111 1.18 uwe ad1848_query_encoding,
112 1.18 uwe ad1848_set_params,
113 1.18 uwe cs4231_round_blocksize,
114 1.18 uwe ad1848_commit_settings,
115 1.18 uwe NULL, /* init_output */
116 1.18 uwe NULL, /* init_input */
117 1.18 uwe NULL, /* start_output */
118 1.18 uwe NULL, /* start_input */
119 1.18 uwe cs4231_sbus_halt_output,
120 1.18 uwe cs4231_sbus_halt_input,
121 1.18 uwe NULL, /* speaker_ctl */
122 1.18 uwe cs4231_getdev,
123 1.18 uwe NULL, /* setfd */
124 1.18 uwe cs4231_set_port,
125 1.18 uwe cs4231_get_port,
126 1.18 uwe cs4231_query_devinfo,
127 1.18 uwe cs4231_malloc,
128 1.18 uwe cs4231_free,
129 1.18 uwe cs4231_round_buffersize,
130 1.18 uwe NULL, /* mappage */
131 1.18 uwe cs4231_get_props,
132 1.18 uwe cs4231_sbus_trigger_output,
133 1.18 uwe cs4231_sbus_trigger_input,
134 1.18 uwe NULL, /* dev_ioctl */
135 1.1 pk };
136 1.1 pk
137 1.1 pk
138 1.18 uwe #ifdef AUDIO_DEBUG
139 1.18 uwe static void cs4231_sbus_regdump(char *, struct cs4231_sbus_softc *);
140 1.18 uwe #endif
141 1.18 uwe
142 1.18 uwe static int cs4231_sbus_intr(void *);
143 1.18 uwe
144 1.18 uwe
145 1.18 uwe
146 1.18 uwe static int
147 1.18 uwe cs4231_sbus_match(parent, cf, aux)
148 1.1 pk struct device *parent;
149 1.1 pk struct cfdata *cf;
150 1.1 pk void *aux;
151 1.1 pk {
152 1.1 pk struct sbus_attach_args *sa = aux;
153 1.1 pk
154 1.18 uwe return (strcmp(sa->sa_name, AUDIOCS_PROM_NAME) == 0);
155 1.1 pk }
156 1.1 pk
157 1.18 uwe
158 1.18 uwe static void
159 1.18 uwe cs4231_sbus_attach(parent, self, aux)
160 1.1 pk struct device *parent, *self;
161 1.1 pk void *aux;
162 1.1 pk {
163 1.18 uwe struct cs4231_sbus_softc *sbsc = (struct cs4231_sbus_softc *)self;
164 1.18 uwe struct cs4231_softc *sc = &sbsc->sc_cs4231;
165 1.1 pk struct sbus_attach_args *sa = aux;
166 1.1 pk bus_space_handle_t bh;
167 1.1 pk
168 1.19 eeh sbsc->sc_bt = sc->sc_bustag = sa->sa_bustag;
169 1.1 pk sc->sc_dmatag = sa->sa_dmatag;
170 1.1 pk
171 1.1 pk /*
172 1.1 pk * Map my registers in, if they aren't already in virtual
173 1.1 pk * address space.
174 1.1 pk */
175 1.1 pk if (sa->sa_npromvaddrs) {
176 1.19 eeh sbus_promaddr_to_handle(sa->sa_bustag,
177 1.19 eeh sa->sa_promvaddrs[0], &bh);
178 1.1 pk } else {
179 1.19 eeh if (sbus_bus_map(sa->sa_bustag, sa->sa_slot,
180 1.19 eeh sa->sa_offset, sa->sa_size, 0, &bh) != 0) {
181 1.1 pk printf("%s @ sbus: cannot map registers\n",
182 1.1 pk self->dv_xname);
183 1.1 pk return;
184 1.1 pk }
185 1.1 pk }
186 1.1 pk
187 1.19 eeh bus_space_subregion(sa->sa_bustag, bh, CS4231_APCDMA_OFFSET,
188 1.19 eeh sizeof(struct apc_dma), &sbsc->sc_bh);
189 1.1 pk
190 1.18 uwe cs4231_common_attach(sc, bh);
191 1.1 pk printf("\n");
192 1.1 pk
193 1.18 uwe sbus_establish(&sbsc->sc_sd, &sc->sc_ad1848.sc_dev);
194 1.1 pk
195 1.1 pk /* Establish interrupt channel */
196 1.12 pk if (sa->sa_nintr)
197 1.12 pk bus_intr_establish(sa->sa_bustag,
198 1.15 pk sa->sa_pri, IPL_AUDIO, 0,
199 1.18 uwe cs4231_sbus_intr, sbsc);
200 1.18 uwe
201 1.18 uwe audio_attach_mi(&audiocs_sbus_hw_if, sbsc, &sc->sc_ad1848.sc_dev);
202 1.18 uwe }
203 1.18 uwe
204 1.18 uwe
205 1.18 uwe #ifdef AUDIO_DEBUG
206 1.18 uwe static void
207 1.18 uwe cs4231_sbus_regdump(label, sc)
208 1.18 uwe char *label;
209 1.18 uwe struct cs4231_sbus_softc *sc;
210 1.18 uwe {
211 1.18 uwe char bits[128];
212 1.19 eeh volatile struct apc_dma *dma = NULL;
213 1.18 uwe
214 1.18 uwe printf("cs4231regdump(%s): regs:", label);
215 1.19 eeh printf("dmapva: 0x%x; ",
216 1.19 eeh bus_space_read_4(sc->sc_bh, sc->sc_bh, &dma->dmapva));
217 1.19 eeh printf("dmapc: 0x%x; ",
218 1.19 eeh bus_space_read_4(sc->sc_bh, sc->sc_bh, &dma->dmapc));
219 1.19 eeh printf("dmapnva: 0x%x; ",
220 1.19 eeh bus_space_read_4(sc->sc_bh, sc->sc_bh, &dma->dmapnva));
221 1.19 eeh printf("dmapnc: 0x%x\n",
222 1.19 eeh bus_space_read_4(sc->sc_bh, sc->sc_bh, &dma->dmapnc));
223 1.19 eeh printf("dmacva: 0x%x; ",
224 1.19 eeh bus_space_read_4(sc->sc_bh, sc->sc_bh, &dma->dmacva));
225 1.19 eeh printf("dmacc: 0x%x; ",
226 1.19 eeh bus_space_read_4(sc->sc_bh, sc->sc_bh, &dma->dmacc));
227 1.19 eeh printf("dmacnva: 0x%x; ",
228 1.19 eeh bus_space_read_4(sc->sc_bh, sc->sc_bh, &dma->dmacnva));
229 1.19 eeh printf("dmacnc: 0x%x\n",
230 1.19 eeh bus_space_read_4(sc->sc_bh, sc->sc_bh, &dma->dmacnc));
231 1.18 uwe
232 1.18 uwe printf("apc_dmacsr=%s\n",
233 1.19 eeh bitmask_snprintf(
234 1.20 pk bus_space_read_4(sc->sc_bh, sc->sc_bh, &dma->dmacsr),
235 1.19 eeh APC_BITS, bits, sizeof(bits)));
236 1.18 uwe
237 1.18 uwe ad1848_dump_regs(&sc->sc_cs4231.sc_ad1848);
238 1.18 uwe }
239 1.18 uwe #endif /* AUDIO_DEBUG */
240 1.18 uwe
241 1.18 uwe
242 1.18 uwe static int
243 1.18 uwe cs4231_sbus_trigger_output(addr, start, end, blksize, intr, arg, param)
244 1.18 uwe void *addr;
245 1.18 uwe void *start, *end;
246 1.18 uwe int blksize;
247 1.18 uwe void (*intr)(void *);
248 1.18 uwe void *arg;
249 1.18 uwe struct audio_params *param;
250 1.18 uwe {
251 1.18 uwe struct cs4231_sbus_softc *sbsc = addr;
252 1.18 uwe struct cs4231_softc *sc = &sbsc->sc_cs4231;
253 1.18 uwe struct cs_transfer *t = &sc->sc_playback;
254 1.19 eeh volatile struct apc_dma *dma = NULL;
255 1.18 uwe u_int32_t csr;
256 1.18 uwe bus_addr_t dmaaddr;
257 1.18 uwe bus_size_t dmasize;
258 1.18 uwe int ret;
259 1.18 uwe #ifdef AUDIO_DEBUG
260 1.18 uwe char bits[128];
261 1.18 uwe #endif
262 1.18 uwe
263 1.18 uwe ret = cs4231_transfer_init(sc, t, &dmaaddr, &dmasize,
264 1.18 uwe start, end, blksize, intr, arg);
265 1.18 uwe if (ret != 0)
266 1.18 uwe return (ret);
267 1.18 uwe
268 1.18 uwe DPRINTF(("trigger_output: was: %x %d, %x %d\n",
269 1.19 eeh bus_space_read_4(sbsc->sc_bt, sbsc->sc_bh, (vaddr_t)&dma->dmapva),
270 1.19 eeh bus_space_read_4(sbsc->sc_bt, sbsc->sc_bh, (vaddr_t)&dma->dmapc),
271 1.19 eeh bus_space_read_4(sbsc->sc_bt, sbsc->sc_bh, (vaddr_t)&dma->dmapnva),
272 1.19 eeh bus_space_read_4(sbsc->sc_bt, sbsc->sc_bh, (vaddr_t)&dma->dmapnc)));
273 1.18 uwe
274 1.18 uwe /* load first block */
275 1.19 eeh bus_space_write_4(sbsc->sc_bt, sbsc->sc_bh, (vaddr_t)&dma->dmapnva, dmaaddr);
276 1.19 eeh bus_space_write_4(sbsc->sc_bt, sbsc->sc_bh, (vaddr_t)&dma->dmapnc, dmasize);
277 1.18 uwe
278 1.18 uwe DPRINTF(("trigger_output: 1st: %x %d, %x %d\n",
279 1.19 eeh bus_space_read_4(sbsc->sc_bt, sbsc->sc_bh, (vaddr_t)&dma->dmapva),
280 1.19 eeh bus_space_read_4(sbsc->sc_bt, sbsc->sc_bh, (vaddr_t)&dma->dmapc),
281 1.19 eeh bus_space_read_4(sbsc->sc_bt, sbsc->sc_bh, (vaddr_t)&dma->dmapnva),
282 1.19 eeh bus_space_read_4(sbsc->sc_bt, sbsc->sc_bh, (vaddr_t)&dma->dmapnc)));
283 1.18 uwe
284 1.19 eeh csr = bus_space_read_4(sbsc->sc_bt, sbsc->sc_bh, (vaddr_t)&dma->dmacsr);
285 1.19 eeh DPRINTF(("trigger_output: csr=%s\n",
286 1.19 eeh bitmask_snprintf(csr, APC_BITS, bits, sizeof(bits))));
287 1.18 uwe if ((csr & PDMA_GO) == 0 || (csr & APC_PPAUSE) != 0) {
288 1.18 uwe int cfg;
289 1.18 uwe
290 1.19 eeh csr &= ~(APC_PPAUSE | APC_PMIE | APC_INTR_MASK);
291 1.19 eeh bus_space_write_4(sbsc->sc_bt, sbsc->sc_bh, (vaddr_t)&dma->dmacsr, csr);
292 1.18 uwe
293 1.19 eeh csr = bus_space_read_4(sbsc->sc_bt, sbsc->sc_bh, (vaddr_t)&dma->dmacsr);
294 1.19 eeh csr &= ~APC_INTR_MASK;
295 1.18 uwe csr |= APC_ENABLE | APC_PIE | APC_PMIE | PDMA_GO;
296 1.19 eeh bus_space_write_4(sbsc->sc_bt, sbsc->sc_bh, (vaddr_t)&dma->dmacsr, csr);
297 1.18 uwe
298 1.18 uwe ad_write(&sc->sc_ad1848, SP_LOWER_BASE_COUNT, 0xff);
299 1.18 uwe ad_write(&sc->sc_ad1848, SP_UPPER_BASE_COUNT, 0xff);
300 1.18 uwe
301 1.18 uwe cfg = ad_read(&sc->sc_ad1848, SP_INTERFACE_CONFIG);
302 1.18 uwe ad_write(&sc->sc_ad1848, SP_INTERFACE_CONFIG,
303 1.18 uwe (cfg | PLAYBACK_ENABLE));
304 1.18 uwe } else {
305 1.18 uwe DPRINTF(("trigger_output: already: csr=%s\n",
306 1.18 uwe bitmask_snprintf(csr, APC_BITS, bits, sizeof(bits))));
307 1.18 uwe }
308 1.18 uwe
309 1.18 uwe /* load next block if we can */
310 1.19 eeh csr = bus_space_read_4(sbsc->sc_bt, sbsc->sc_bh, (vaddr_t)&dma->dmacsr);
311 1.19 eeh if (csr & APC_PD) {
312 1.18 uwe cs4231_transfer_advance(t, &dmaaddr, &dmasize);
313 1.19 eeh bus_space_write_4(sbsc->sc_bt, sbsc->sc_bh, (vaddr_t)&dma->dmapnva, dmaaddr);
314 1.19 eeh bus_space_write_4(sbsc->sc_bt, sbsc->sc_bh, (vaddr_t)&dma->dmapnc, dmasize);
315 1.19 eeh
316 1.18 uwe DPRINTF(("trigger_output: 2nd: %x %d, %x %d\n",
317 1.19 eeh bus_space_read_4(sbsc->sc_bt, sbsc->sc_bh, (vaddr_t)&dma->dmapva),
318 1.19 eeh bus_space_read_4(sbsc->sc_bt, sbsc->sc_bh, (vaddr_t)&dma->dmapc),
319 1.19 eeh bus_space_read_4(sbsc->sc_bt, sbsc->sc_bh, (vaddr_t)&dma->dmapnva),
320 1.19 eeh bus_space_read_4(sbsc->sc_bt, sbsc->sc_bh, (vaddr_t)&dma->dmapnc)));
321 1.18 uwe }
322 1.18 uwe
323 1.18 uwe return (0);
324 1.18 uwe }
325 1.18 uwe
326 1.18 uwe
327 1.18 uwe static int
328 1.18 uwe cs4231_sbus_halt_output(addr)
329 1.18 uwe void *addr;
330 1.18 uwe {
331 1.18 uwe struct cs4231_sbus_softc *sbsc = addr;
332 1.18 uwe struct cs4231_softc *sc = &sbsc->sc_cs4231;
333 1.19 eeh volatile struct apc_dma *dma = NULL;
334 1.18 uwe u_int32_t csr;
335 1.18 uwe int cfg;
336 1.18 uwe #ifdef AUDIO_DEBUG
337 1.18 uwe char bits[128];
338 1.18 uwe #endif
339 1.18 uwe
340 1.18 uwe sc->sc_playback.t_active = 0;
341 1.18 uwe
342 1.19 eeh csr = bus_space_read_4(sbsc->sc_bt, sbsc->sc_bh, (vaddr_t)&dma->dmacsr);
343 1.18 uwe DPRINTF(("halt_output: csr=%s\n",
344 1.19 eeh bitmask_snprintf(csr, APC_BITS, bits, sizeof(bits))));
345 1.18 uwe
346 1.18 uwe csr &= ~APC_INTR_MASK; /* do not clear interrupts accidentally */
347 1.18 uwe csr |= APC_PPAUSE; /* pause playback (let current complete) */
348 1.19 eeh bus_space_write_4(sbsc->sc_bt, sbsc->sc_bh, (vaddr_t)&dma->dmacsr, csr);
349 1.19 eeh
350 1.18 uwe /* let the curernt transfer complete */
351 1.18 uwe if (csr & PDMA_GO)
352 1.18 uwe do {
353 1.19 eeh csr = bus_space_read_4(sbsc->sc_bt, sbsc->sc_bh,
354 1.19 eeh (vaddr_t)&dma->dmacsr);
355 1.18 uwe DPRINTF(("halt_output: csr=%s\n",
356 1.19 eeh bitmask_snprintf(csr, APC_BITS,
357 1.18 uwe bits, sizeof(bits))));
358 1.18 uwe } while ((csr & APC_PM) == 0);
359 1.1 pk
360 1.18 uwe cfg = ad_read(&sc->sc_ad1848, SP_INTERFACE_CONFIG);
361 1.18 uwe ad_write(&sc->sc_ad1848, SP_INTERFACE_CONFIG,(cfg & ~PLAYBACK_ENABLE));
362 1.18 uwe
363 1.18 uwe return (0);
364 1.1 pk }
365 1.18 uwe
366 1.18 uwe
367 1.18 uwe /* NB: we don't enable APC_CMIE and won't use APC_CM */
368 1.18 uwe static int
369 1.18 uwe cs4231_sbus_trigger_input(addr, start, end, blksize, intr, arg, param)
370 1.18 uwe void *addr;
371 1.18 uwe void *start, *end;
372 1.18 uwe int blksize;
373 1.18 uwe void (*intr)(void *);
374 1.18 uwe void *arg;
375 1.18 uwe struct audio_params *param;
376 1.18 uwe {
377 1.18 uwe struct cs4231_sbus_softc *sbsc = addr;
378 1.18 uwe struct cs4231_softc *sc = &sbsc->sc_cs4231;
379 1.18 uwe struct cs_transfer *t = &sc->sc_capture;
380 1.19 eeh volatile struct apc_dma *dma = NULL;
381 1.18 uwe u_int32_t csr;
382 1.18 uwe bus_addr_t dmaaddr;
383 1.18 uwe bus_size_t dmasize;
384 1.18 uwe int ret;
385 1.18 uwe #ifdef AUDIO_DEBUG
386 1.18 uwe char bits[128];
387 1.1 pk #endif
388 1.18 uwe
389 1.18 uwe ret = cs4231_transfer_init(sc, t, &dmaaddr, &dmasize,
390 1.18 uwe start, end, blksize, intr, arg);
391 1.18 uwe if (ret != 0)
392 1.18 uwe return (ret);
393 1.18 uwe
394 1.19 eeh csr = bus_space_read_4(sbsc->sc_bt, sbsc->sc_bh, (vaddr_t)&dma->dmacsr);
395 1.18 uwe DPRINTF(("trigger_input: csr=%s\n",
396 1.18 uwe bitmask_snprintf(csr, APC_BITS, bits, sizeof(bits))));
397 1.18 uwe DPRINTF(("trigger_input: was: %x %d, %x %d\n",
398 1.19 eeh bus_space_read_4(sbsc->sc_bt, sbsc->sc_bh, (vaddr_t)&dma->dmacva),
399 1.19 eeh bus_space_read_4(sbsc->sc_bt, sbsc->sc_bh, (vaddr_t)&dma->dmacc),
400 1.19 eeh bus_space_read_4(sbsc->sc_bt, sbsc->sc_bh, (vaddr_t)&dma->dmacnva),
401 1.19 eeh bus_space_read_4(sbsc->sc_bt, sbsc->sc_bh, (vaddr_t)&dma->dmacnc)));
402 1.18 uwe
403 1.18 uwe /* supply first block */
404 1.19 eeh bus_space_write_4(sbsc->sc_bt, sbsc->sc_bh, (vaddr_t)&dma->dmacnva, dmaaddr);
405 1.19 eeh bus_space_write_4(sbsc->sc_bt, sbsc->sc_bh, (vaddr_t)&dma->dmacnc, dmasize);
406 1.18 uwe
407 1.18 uwe DPRINTF(("trigger_input: 1st: %x %d, %x %d\n",
408 1.19 eeh bus_space_read_4(sbsc->sc_bt, sbsc->sc_bh, (vaddr_t)&dma->dmacva),
409 1.19 eeh bus_space_read_4(sbsc->sc_bt, sbsc->sc_bh, (vaddr_t)&dma->dmacc),
410 1.19 eeh bus_space_read_4(sbsc->sc_bt, sbsc->sc_bh, (vaddr_t)&dma->dmacnva),
411 1.19 eeh bus_space_read_4(sbsc->sc_bt, sbsc->sc_bh, (vaddr_t)&dma->dmacnc)));
412 1.18 uwe
413 1.19 eeh csr = bus_space_read_4(sbsc->sc_bt, sbsc->sc_bh, (vaddr_t)&dma->dmacsr);
414 1.18 uwe if ((csr & CDMA_GO) == 0 || (csr & APC_CPAUSE) != 0) {
415 1.18 uwe int cfg;
416 1.18 uwe
417 1.19 eeh csr &= ~(APC_CPAUSE | APC_CMIE | APC_INTR_MASK);
418 1.19 eeh bus_space_write_4(sbsc->sc_bt, sbsc->sc_bh, (vaddr_t)&dma->dmacsr, csr);
419 1.18 uwe
420 1.19 eeh csr = bus_space_read_4(sbsc->sc_bt, sbsc->sc_bh, (vaddr_t)&dma->dmacsr);
421 1.19 eeh csr &= ~APC_INTR_MASK;
422 1.18 uwe csr |= APC_ENABLE | APC_CIE | CDMA_GO;
423 1.19 eeh bus_space_write_4(sbsc->sc_bt, sbsc->sc_bh, (vaddr_t)&dma->dmacsr, csr);
424 1.18 uwe
425 1.18 uwe ad_write(&sc->sc_ad1848, CS_LOWER_REC_CNT, 0xff);
426 1.18 uwe ad_write(&sc->sc_ad1848, CS_UPPER_REC_CNT, 0xff);
427 1.18 uwe
428 1.18 uwe cfg = ad_read(&sc->sc_ad1848, SP_INTERFACE_CONFIG);
429 1.18 uwe ad_write(&sc->sc_ad1848, SP_INTERFACE_CONFIG,
430 1.18 uwe (cfg | CAPTURE_ENABLE));
431 1.18 uwe } else {
432 1.18 uwe DPRINTF(("trigger_input: already: csr=%s\n",
433 1.18 uwe bitmask_snprintf(csr, APC_BITS, bits, sizeof(bits))));
434 1.18 uwe }
435 1.18 uwe
436 1.18 uwe /* supply next block if we can */
437 1.18 uwe if (dma->dmacsr & APC_CD) {
438 1.18 uwe cs4231_transfer_advance(t, &dmaaddr, &dmasize);
439 1.19 eeh bus_space_write_4(sbsc->sc_bt, sbsc->sc_bh, (vaddr_t)&dma->dmacnva, dmaaddr);
440 1.19 eeh bus_space_write_4(sbsc->sc_bt, sbsc->sc_bh, (vaddr_t)&dma->dmacnc, dmasize);
441 1.18 uwe DPRINTF(("trigger_input: 2nd: %x %d, %x %d\n",
442 1.19 eeh bus_space_read_4(sbsc->sc_bt, sbsc->sc_bh, (vaddr_t)&dma->dmacva),
443 1.19 eeh bus_space_read_4(sbsc->sc_bt, sbsc->sc_bh, (vaddr_t)&dma->dmacc),
444 1.19 eeh bus_space_read_4(sbsc->sc_bt, sbsc->sc_bh, (vaddr_t)&dma->dmacnva),
445 1.19 eeh bus_space_read_4(sbsc->sc_bt, sbsc->sc_bh, (vaddr_t)&dma->dmacnc)));
446 1.18 uwe }
447 1.18 uwe
448 1.18 uwe return (0);
449 1.18 uwe }
450 1.18 uwe
451 1.18 uwe
452 1.18 uwe static int
453 1.18 uwe cs4231_sbus_halt_input(addr)
454 1.18 uwe void *addr;
455 1.18 uwe {
456 1.18 uwe struct cs4231_sbus_softc *sbsc = addr;
457 1.18 uwe struct cs4231_softc *sc = &sbsc->sc_cs4231;
458 1.19 eeh volatile struct apc_dma *dma = NULL;
459 1.18 uwe u_int32_t csr;
460 1.18 uwe int cfg;
461 1.18 uwe #ifdef AUDIO_DEBUG
462 1.18 uwe char bits[128];
463 1.18 uwe #endif
464 1.18 uwe
465 1.18 uwe sc->sc_capture.t_active = 0;
466 1.18 uwe
467 1.19 eeh csr = bus_space_read_4(sbsc->sc_bt, sbsc->sc_bh, (vaddr_t)&dma->dmacsr);
468 1.18 uwe DPRINTF(("halt_input: csr=%s\n",
469 1.19 eeh bitmask_snprintf(csr, APC_BITS, bits, sizeof(bits))));
470 1.18 uwe
471 1.18 uwe csr &= ~APC_INTR_MASK; /* do not clear interrupts accidentally */
472 1.18 uwe csr |= APC_CPAUSE;
473 1.19 eeh bus_space_write_4(sbsc->sc_bt, sbsc->sc_bh, (vaddr_t)&dma->dmacsr, csr);
474 1.18 uwe
475 1.18 uwe /* let the curernt transfer complete */
476 1.18 uwe if (csr & CDMA_GO)
477 1.18 uwe do {
478 1.19 eeh csr = bus_space_read_4(sbsc->sc_bt, sbsc->sc_bh,
479 1.19 eeh (vaddr_t)&dma->dmacsr);
480 1.18 uwe DPRINTF(("halt_input: csr=%s\n",
481 1.19 eeh bitmask_snprintf(csr, APC_BITS,
482 1.18 uwe bits, sizeof(bits))));
483 1.18 uwe } while ((csr & APC_CM) == 0);
484 1.18 uwe
485 1.18 uwe cfg = ad_read(&sc->sc_ad1848, SP_INTERFACE_CONFIG);
486 1.18 uwe ad_write(&sc->sc_ad1848, SP_INTERFACE_CONFIG, (cfg & ~CAPTURE_ENABLE));
487 1.18 uwe
488 1.18 uwe return (0);
489 1.18 uwe }
490 1.18 uwe
491 1.18 uwe
492 1.18 uwe static int
493 1.18 uwe cs4231_sbus_intr(arg)
494 1.18 uwe void *arg;
495 1.18 uwe {
496 1.18 uwe struct cs4231_sbus_softc *sbsc = arg;
497 1.18 uwe struct cs4231_softc *sc = &sbsc->sc_cs4231;
498 1.19 eeh volatile struct apc_dma *dma = NULL;
499 1.18 uwe u_int32_t csr;
500 1.18 uwe int status;
501 1.18 uwe bus_addr_t dmaaddr;
502 1.18 uwe bus_size_t dmasize;
503 1.18 uwe int served;
504 1.18 uwe #if defined(AUDIO_DEBUG) || defined(DIAGNOSTIC)
505 1.18 uwe char bits[128];
506 1.18 uwe #endif
507 1.18 uwe
508 1.19 eeh csr = bus_space_read_4(sbsc->sc_bt, sbsc->sc_bh, (vaddr_t)&dma->dmacsr);
509 1.18 uwe if ((csr & APC_INTR_MASK) == 0) /* any interrupt pedning? */
510 1.18 uwe return (0);
511 1.18 uwe
512 1.19 eeh /* write back DMA status to clear interrupt */
513 1.19 eeh bus_space_write_4(sbsc->sc_bt, sbsc->sc_bh, (vaddr_t)&dma->dmacsr, csr);
514 1.18 uwe ++sc->sc_intrcnt.ev_count;
515 1.18 uwe served = 0;
516 1.18 uwe
517 1.18 uwe #ifdef AUDIO_DEBUG
518 1.18 uwe if (cs4231_sbus_debug > 1)
519 1.18 uwe cs4231_sbus_regdump("audiointr", sbsc);
520 1.18 uwe #endif
521 1.18 uwe
522 1.18 uwe status = ADREAD(&sc->sc_ad1848, AD1848_STATUS);
523 1.18 uwe DPRINTF(("%s: status: %s\n", sc->sc_ad1848.sc_dev.dv_xname,
524 1.18 uwe bitmask_snprintf(status, AD_R2_BITS, bits, sizeof(bits))));
525 1.18 uwe if (status & INTERRUPT_STATUS) {
526 1.18 uwe #ifdef AUDIO_DEBUG
527 1.18 uwe int reason;
528 1.18 uwe
529 1.18 uwe reason = ad_read(&sc->sc_ad1848, CS_IRQ_STATUS);
530 1.18 uwe DPRINTF(("%s: i24: %s\n", sc->sc_ad1848.sc_dev.dv_xname,
531 1.18 uwe bitmask_snprintf(reason, CS_I24_BITS, bits, sizeof(bits))));
532 1.18 uwe #endif
533 1.18 uwe /* clear ad1848 interrupt */
534 1.18 uwe ADWRITE(&sc->sc_ad1848, AD1848_STATUS, 0);
535 1.18 uwe }
536 1.18 uwe
537 1.18 uwe if (csr & APC_CI) {
538 1.18 uwe if (csr & APC_CD) { /* can supply new block */
539 1.18 uwe struct cs_transfer *t = &sc->sc_capture;
540 1.18 uwe
541 1.18 uwe cs4231_transfer_advance(t, &dmaaddr, &dmasize);
542 1.19 eeh bus_space_write_4(sbsc->sc_bt, sbsc->sc_bh,
543 1.19 eeh (vaddr_t)&dma->dmacnva, dmaaddr);
544 1.19 eeh bus_space_write_4(sbsc->sc_bt, sbsc->sc_bh,
545 1.19 eeh (vaddr_t)&dma->dmacnc, dmasize);
546 1.18 uwe
547 1.18 uwe if (t->t_intr != NULL)
548 1.18 uwe (*t->t_intr)(t->t_arg);
549 1.18 uwe ++t->t_intrcnt.ev_count;
550 1.18 uwe served = 1;
551 1.18 uwe }
552 1.18 uwe }
553 1.18 uwe
554 1.18 uwe if (csr & APC_PMI) {
555 1.18 uwe if (!sc->sc_playback.t_active)
556 1.18 uwe served = 1; /* draining in halt_output() */
557 1.18 uwe }
558 1.18 uwe
559 1.18 uwe if (csr & APC_PI) {
560 1.18 uwe if (csr & APC_PD) { /* can load new block */
561 1.18 uwe struct cs_transfer *t = &sc->sc_playback;
562 1.18 uwe
563 1.18 uwe if (t->t_active) {
564 1.18 uwe cs4231_transfer_advance(t, &dmaaddr, &dmasize);
565 1.19 eeh bus_space_write_4(sbsc->sc_bt, sbsc->sc_bh,
566 1.19 eeh (vaddr_t)&dma->dmapnva, dmaaddr);
567 1.19 eeh bus_space_write_4(sbsc->sc_bt, sbsc->sc_bh,
568 1.19 eeh (vaddr_t)&dma->dmapnc, dmasize);
569 1.18 uwe }
570 1.18 uwe
571 1.18 uwe if (t->t_intr != NULL)
572 1.18 uwe (*t->t_intr)(t->t_arg);
573 1.18 uwe ++t->t_intrcnt.ev_count;
574 1.18 uwe served = 1;
575 1.18 uwe }
576 1.18 uwe }
577 1.18 uwe
578 1.18 uwe /* got an interrupt we don't know how to handle */
579 1.18 uwe if (!served) {
580 1.18 uwe #ifdef DIAGNOSTIC
581 1.18 uwe printf("%s: unhandled csr=%s\n", sc->sc_ad1848.sc_dev.dv_xname,
582 1.18 uwe bitmask_snprintf(csr, APC_BITS, bits, sizeof(bits)));
583 1.18 uwe #endif
584 1.18 uwe /* evcnt? */
585 1.18 uwe }
586 1.18 uwe
587 1.18 uwe return (1);
588 1.18 uwe }
589 1.18 uwe
590 1.18 uwe #endif /* NAUDIO > 0 */
591