dbri.c revision 1.2.6.2 1 1.2.6.2 skrll /* $NetBSD: dbri.c,v 1.2.6.2 2005/11/10 14:07:47 skrll Exp $ */
2 1.2.6.2 skrll
3 1.2.6.2 skrll /*
4 1.2.6.2 skrll * Copyright (C) 1997 Rudolf Koenig (rfkoenig (at) immd4.informatik.uni-erlangen.de)
5 1.2.6.2 skrll * Copyright (c) 1998, 1999 Brent Baccala (baccala (at) freesoft.org)
6 1.2.6.2 skrll * Copyright (c) 2001, 2002 Jared D. McNeill <jmcneill (at) netbsd.org>
7 1.2.6.2 skrll * Copyright (c) 2005 Michael Lorenz <macallan (at) netbsd.org>
8 1.2.6.2 skrll * All rights reserved.
9 1.2.6.2 skrll *
10 1.2.6.2 skrll * This driver is losely based on a Linux driver written by Rudolf Koenig and
11 1.2.6.2 skrll * Brent Baccala who kindly gave their permission to use their code in a
12 1.2.6.2 skrll * BSD-licensed driver.
13 1.2.6.2 skrll *
14 1.2.6.2 skrll * Redistribution and use in source and binary forms, with or without
15 1.2.6.2 skrll * modification, are permitted provided that the following conditions
16 1.2.6.2 skrll * are met:
17 1.2.6.2 skrll * 1. Redistributions of source code must retain the above copyright
18 1.2.6.2 skrll * notice, this list of conditions and the following disclaimer.
19 1.2.6.2 skrll * 2. Redistributions in binary form must reproduce the above copyright
20 1.2.6.2 skrll * notice, this list of conditions and the following disclaimer in the
21 1.2.6.2 skrll * documentation and/or other materials provided with the distribution.
22 1.2.6.2 skrll * 3. All advertising materials mentioning features or use of this software
23 1.2.6.2 skrll * must display the following acknowledgement:
24 1.2.6.2 skrll * This product includes software developed by Rudolf Koenig, Brent
25 1.2.6.2 skrll * Baccala, Jared D. McNeill.
26 1.2.6.2 skrll * 4. Neither the name of the author nor the names of any contributors may
27 1.2.6.2 skrll * be used to endorse or promote products derived from this software
28 1.2.6.2 skrll * without specific prior written permission.
29 1.2.6.2 skrll *
30 1.2.6.2 skrll * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
31 1.2.6.2 skrll * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
32 1.2.6.2 skrll * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
33 1.2.6.2 skrll * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
34 1.2.6.2 skrll * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
35 1.2.6.2 skrll * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
36 1.2.6.2 skrll * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
37 1.2.6.2 skrll * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
38 1.2.6.2 skrll * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
39 1.2.6.2 skrll * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
40 1.2.6.2 skrll * SUCH DAMAGE.
41 1.2.6.2 skrll *
42 1.2.6.2 skrll */
43 1.2.6.2 skrll
44 1.2.6.2 skrll #include <sys/cdefs.h>
45 1.2.6.2 skrll __KERNEL_RCSID(0, "$NetBSD: dbri.c,v 1.2.6.2 2005/11/10 14:07:47 skrll Exp $");
46 1.2.6.2 skrll
47 1.2.6.2 skrll #include "audio.h"
48 1.2.6.2 skrll #if NAUDIO > 0
49 1.2.6.2 skrll
50 1.2.6.2 skrll #include <sys/param.h>
51 1.2.6.2 skrll #include <sys/systm.h>
52 1.2.6.2 skrll #include <sys/errno.h>
53 1.2.6.2 skrll #include <sys/device.h>
54 1.2.6.2 skrll #include <sys/malloc.h>
55 1.2.6.2 skrll #include <sys/proc.h>
56 1.2.6.2 skrll
57 1.2.6.2 skrll #include <machine/bus.h>
58 1.2.6.2 skrll #include <machine/intr.h>
59 1.2.6.2 skrll
60 1.2.6.2 skrll #include <dev/sbus/sbusvar.h>
61 1.2.6.2 skrll #include <sparc/sparc/auxreg.h>
62 1.2.6.2 skrll #include <machine/autoconf.h>
63 1.2.6.2 skrll
64 1.2.6.2 skrll #include <sys/audioio.h>
65 1.2.6.2 skrll #include <dev/audio_if.h>
66 1.2.6.2 skrll #include <dev/auconv.h>
67 1.2.6.2 skrll
68 1.2.6.2 skrll #include <dev/ic/cs4215reg.h>
69 1.2.6.2 skrll #include <dev/ic/cs4215var.h>
70 1.2.6.2 skrll #include <dev/sbus/dbrireg.h>
71 1.2.6.2 skrll #include <dev/sbus/dbrivar.h>
72 1.2.6.2 skrll
73 1.2.6.2 skrll #define DBRI_ROM_NAME_PREFIX "SUNW,DBRI"
74 1.2.6.2 skrll
75 1.2.6.2 skrll #define DBRI_BIG_BUFFER
76 1.2.6.2 skrll
77 1.2.6.2 skrll static const char *dbri_supported[] = {
78 1.2.6.2 skrll "e",
79 1.2.6.2 skrll "s3",
80 1.2.6.2 skrll ""
81 1.2.6.2 skrll };
82 1.2.6.2 skrll
83 1.2.6.2 skrll enum ms {
84 1.2.6.2 skrll CHImaster,
85 1.2.6.2 skrll CHIslave
86 1.2.6.2 skrll };
87 1.2.6.2 skrll
88 1.2.6.2 skrll enum io {
89 1.2.6.2 skrll PIPEinput,
90 1.2.6.2 skrll PIPEoutput
91 1.2.6.2 skrll };
92 1.2.6.2 skrll
93 1.2.6.2 skrll /*
94 1.2.6.2 skrll * Function prototypes
95 1.2.6.2 skrll */
96 1.2.6.2 skrll
97 1.2.6.2 skrll /* softc stuff */
98 1.2.6.2 skrll static void dbri_attach_sbus(struct device *, struct device *, void *);
99 1.2.6.2 skrll static int dbri_match_sbus(struct device *, struct cfdata *, void *);
100 1.2.6.2 skrll
101 1.2.6.2 skrll static void dbri_config_interrupts(struct device *);
102 1.2.6.2 skrll
103 1.2.6.2 skrll /* interrupt handler */
104 1.2.6.2 skrll static int dbri_intr(void *);
105 1.2.6.2 skrll
106 1.2.6.2 skrll /* supporting subroutines */
107 1.2.6.2 skrll static int dbri_init(struct dbri_softc *);
108 1.2.6.2 skrll static int dbri_reset(struct dbri_softc *);
109 1.2.6.2 skrll static volatile u_int32_t *dbri_command_lock(struct dbri_softc *);
110 1.2.6.2 skrll static void dbri_command_send(struct dbri_softc *, volatile u_int32_t *);
111 1.2.6.2 skrll static void dbri_process_interrupt_buffer(struct dbri_softc *);
112 1.2.6.2 skrll static void dbri_process_interrupt(struct dbri_softc *, int32_t);
113 1.2.6.2 skrll
114 1.2.6.2 skrll /* mmcodec subroutines */
115 1.2.6.2 skrll static int mmcodec_init(struct dbri_softc *);
116 1.2.6.2 skrll static void mmcodec_init_data(struct dbri_softc *);
117 1.2.6.2 skrll static void mmcodec_pipe_init(struct dbri_softc *);
118 1.2.6.2 skrll static void mmcodec_default(struct dbri_softc *);
119 1.2.6.2 skrll static void mmcodec_setgain(struct dbri_softc *, int);
120 1.2.6.2 skrll static int mmcodec_setcontrol(struct dbri_softc *);
121 1.2.6.2 skrll
122 1.2.6.2 skrll /* chi subroutines */
123 1.2.6.2 skrll static void chi_reset(struct dbri_softc *, enum ms, int);
124 1.2.6.2 skrll
125 1.2.6.2 skrll /* pipe subroutines */
126 1.2.6.2 skrll static void pipe_setup(struct dbri_softc *, int, int);
127 1.2.6.2 skrll static void pipe_reset(struct dbri_softc *, int);
128 1.2.6.2 skrll static void pipe_receive_fixed(struct dbri_softc *, int,
129 1.2.6.2 skrll volatile u_int32_t *);
130 1.2.6.2 skrll static void pipe_transmit_fixed(struct dbri_softc *, int, u_int32_t);
131 1.2.6.2 skrll
132 1.2.6.2 skrll static void pipe_ts_link(struct dbri_softc *, int, enum io, int, int, int);
133 1.2.6.2 skrll static int pipe_active(struct dbri_softc *, int);
134 1.2.6.2 skrll
135 1.2.6.2 skrll /* audio(9) stuff */
136 1.2.6.2 skrll static int dbri_query_encoding(void *, struct audio_encoding *);
137 1.2.6.2 skrll static int dbri_set_params(void *, int, int, struct audio_params *,
138 1.2.6.2 skrll struct audio_params *,stream_filter_list_t *, stream_filter_list_t *);
139 1.2.6.2 skrll static int dbri_round_blocksize(void *, int, int, const audio_params_t *);
140 1.2.6.2 skrll static int dbri_halt_output(void *);
141 1.2.6.2 skrll static int dbri_getdev(void *, struct audio_device *);
142 1.2.6.2 skrll static int dbri_set_port(void *, mixer_ctrl_t *);
143 1.2.6.2 skrll static int dbri_get_port(void *, mixer_ctrl_t *);
144 1.2.6.2 skrll static int dbri_query_devinfo(void *, mixer_devinfo_t *);
145 1.2.6.2 skrll static size_t dbri_round_buffersize(void *, int, size_t);
146 1.2.6.2 skrll static int dbri_get_props(void *);
147 1.2.6.2 skrll
148 1.2.6.2 skrll static void
149 1.2.6.2 skrll setup_ring(struct dbri_softc *, int, int, int, int, void (*)(void *), void *);
150 1.2.6.2 skrll
151 1.2.6.2 skrll static int dbri_trigger_output(void *, void *, void *, int,
152 1.2.6.2 skrll void (*)(void *), void *, const struct audio_params *);
153 1.2.6.2 skrll
154 1.2.6.2 skrll static void *dbri_malloc(void *, int, size_t, struct malloc_type *, int);
155 1.2.6.2 skrll static void dbri_free(void *, void *, struct malloc_type *);
156 1.2.6.2 skrll static paddr_t dbri_mappage(void *, void *, off_t, int);
157 1.2.6.2 skrll
158 1.2.6.2 skrll /* stupid support routines */
159 1.2.6.2 skrll static u_int32_t reverse_bytes(u_int32_t, int);
160 1.2.6.2 skrll
161 1.2.6.2 skrll struct audio_device dbri_device = {
162 1.2.6.2 skrll "CS4215",
163 1.2.6.2 skrll "",
164 1.2.6.2 skrll "dbri"
165 1.2.6.2 skrll };
166 1.2.6.2 skrll
167 1.2.6.2 skrll struct audio_hw_if dbri_hw_if = {
168 1.2.6.2 skrll NULL, /*dbri_open,*/
169 1.2.6.2 skrll NULL, /*dbri_close,*/
170 1.2.6.2 skrll NULL, /* drain */
171 1.2.6.2 skrll dbri_query_encoding,
172 1.2.6.2 skrll dbri_set_params,
173 1.2.6.2 skrll dbri_round_blocksize,
174 1.2.6.2 skrll NULL, /* commit_settings */
175 1.2.6.2 skrll NULL, /* init_output */
176 1.2.6.2 skrll NULL, /* init_input */
177 1.2.6.2 skrll NULL, /* start_output */
178 1.2.6.2 skrll NULL, /* start_input */
179 1.2.6.2 skrll dbri_halt_output,
180 1.2.6.2 skrll NULL, /* halt_input */
181 1.2.6.2 skrll NULL, /* speaker_ctl */
182 1.2.6.2 skrll dbri_getdev,
183 1.2.6.2 skrll NULL, /* setfd */
184 1.2.6.2 skrll dbri_set_port,
185 1.2.6.2 skrll dbri_get_port,
186 1.2.6.2 skrll dbri_query_devinfo,
187 1.2.6.2 skrll dbri_malloc,
188 1.2.6.2 skrll dbri_free,
189 1.2.6.2 skrll dbri_round_buffersize,
190 1.2.6.2 skrll dbri_mappage,
191 1.2.6.2 skrll dbri_get_props,
192 1.2.6.2 skrll dbri_trigger_output,
193 1.2.6.2 skrll NULL /* trigger_input */
194 1.2.6.2 skrll };
195 1.2.6.2 skrll
196 1.2.6.2 skrll CFATTACH_DECL(dbri, sizeof(struct dbri_softc),
197 1.2.6.2 skrll dbri_match_sbus, dbri_attach_sbus, NULL, NULL);
198 1.2.6.2 skrll
199 1.2.6.2 skrll enum {
200 1.2.6.2 skrll DBRI_MONITOR_CLASS,
201 1.2.6.2 skrll DBRI_VOL_OUTPUT,
202 1.2.6.2 skrll DBRI_ENABLE_MONO,
203 1.2.6.2 skrll DBRI_ENABLE_HEADPHONE,
204 1.2.6.2 skrll DBRI_ENABLE_LINE
205 1.2.6.2 skrll /*
206 1.2.6.2 skrll DBRI_INPUT_CLASS,
207 1.2.6.2 skrll DBRI_RECORD_CLASS,
208 1.2.6.2 skrll DBRI_INPUT_GAIN,
209 1.2.6.2 skrll DBRI_INPUT_SELECT,
210 1.2.6.2 skrll DBRI_ENUM_LAST
211 1.2.6.2 skrll */
212 1.2.6.2 skrll };
213 1.2.6.2 skrll
214 1.2.6.2 skrll /*
215 1.2.6.2 skrll * Autoconfig routines
216 1.2.6.2 skrll */
217 1.2.6.2 skrll int
218 1.2.6.2 skrll dbri_match_sbus(struct device *parent, struct cfdata *match, void *aux)
219 1.2.6.2 skrll {
220 1.2.6.2 skrll struct sbus_attach_args *sa = aux;
221 1.2.6.2 skrll char *ver;
222 1.2.6.2 skrll int i;
223 1.2.6.2 skrll
224 1.2.6.2 skrll if (strncmp(DBRI_ROM_NAME_PREFIX, sa->sa_name, 9))
225 1.2.6.2 skrll return (0);
226 1.2.6.2 skrll
227 1.2.6.2 skrll ver = &sa->sa_name[9];
228 1.2.6.2 skrll
229 1.2.6.2 skrll for (i = 0; dbri_supported[i][0] != '\0'; i++)
230 1.2.6.2 skrll if (strcmp(dbri_supported[i], ver) == 0)
231 1.2.6.2 skrll return (1);
232 1.2.6.2 skrll
233 1.2.6.2 skrll return (0);
234 1.2.6.2 skrll }
235 1.2.6.2 skrll
236 1.2.6.2 skrll void
237 1.2.6.2 skrll dbri_attach_sbus(struct device *parent, struct device *self, void *aux)
238 1.2.6.2 skrll {
239 1.2.6.2 skrll struct dbri_softc *sc = (struct dbri_softc *)self;
240 1.2.6.2 skrll struct sbus_attach_args *sa = aux;
241 1.2.6.2 skrll bus_space_handle_t ioh;
242 1.2.6.2 skrll bus_size_t size;
243 1.2.6.2 skrll int error, rseg, pwr;
244 1.2.6.2 skrll char *ver = &sa->sa_name[9];
245 1.2.6.2 skrll
246 1.2.6.2 skrll sc->sc_iot = sa->sa_bustag;
247 1.2.6.2 skrll sc->sc_dmat = sa->sa_dmatag;
248 1.2.6.2 skrll
249 1.2.6.2 skrll pwr=prom_getpropint(sa->sa_node,"pwr-on-auxio",0);
250 1.2.6.2 skrll if(pwr) {
251 1.2.6.2 skrll /* we need to power up the device first */
252 1.2.6.2 skrll uint8_t auxregval = 0;
253 1.2.6.2 skrll printf("\n%s: waiting to power up... ",self->dv_xname);
254 1.2.6.2 skrll auxregval = *AUXIO4M_REG;
255 1.2.6.2 skrll *AUXIO4M_REG = auxregval | (AUXIO4M_LED|4);
256 1.2.6.2 skrll DELAY(1000);
257 1.2.6.2 skrll printf("done\n"); /* more delay... */
258 1.2.6.2 skrll } else
259 1.2.6.2 skrll printf(": rev %s\n", ver);
260 1.2.6.2 skrll
261 1.2.6.2 skrll if (sa->sa_npromvaddrs)
262 1.2.6.2 skrll ioh = (bus_space_handle_t)sa->sa_promvaddrs[0];
263 1.2.6.2 skrll else {
264 1.2.6.2 skrll if (sbus_bus_map(sa->sa_bustag, sa->sa_slot,
265 1.2.6.2 skrll sa->sa_offset, sa->sa_size,
266 1.2.6.2 skrll BUS_SPACE_MAP_LINEAR, /*0,*/ &ioh) != 0) {
267 1.2.6.2 skrll printf("%s @ sbus: cannot map registers\n",
268 1.2.6.2 skrll self->dv_xname);
269 1.2.6.2 skrll return;
270 1.2.6.2 skrll }
271 1.2.6.2 skrll }
272 1.2.6.2 skrll
273 1.2.6.2 skrll sc->sc_ioh = ioh;
274 1.2.6.2 skrll
275 1.2.6.2 skrll size = sizeof(struct dbri_dma);
276 1.2.6.2 skrll
277 1.2.6.2 skrll /* get a DMA handle */
278 1.2.6.2 skrll if ((error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0,
279 1.2.6.2 skrll BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) {
280 1.2.6.2 skrll printf("%s: DMA map create error %d\n", self->dv_xname, error);
281 1.2.6.2 skrll return;
282 1.2.6.2 skrll }
283 1.2.6.2 skrll
284 1.2.6.2 skrll /* allocate DMA buffer */
285 1.2.6.2 skrll if ((error = bus_dmamem_alloc(sc->sc_dmat, size, 0, 0, &sc->sc_dmaseg,
286 1.2.6.2 skrll 1, &rseg, BUS_DMA_NOWAIT)) != 0) {
287 1.2.6.2 skrll printf("%s: DMA buffer alloc error %d\n",
288 1.2.6.2 skrll self->dv_xname, error);
289 1.2.6.2 skrll return;
290 1.2.6.2 skrll }
291 1.2.6.2 skrll
292 1.2.6.2 skrll /* map DMA buffer into CPU addressable space */
293 1.2.6.2 skrll if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_dmaseg, rseg, size,
294 1.2.6.2 skrll &sc->sc_membase,
295 1.2.6.2 skrll BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) {
296 1.2.6.2 skrll printf("%s: DMA buffer map error %d\n",
297 1.2.6.2 skrll self->dv_xname, error);
298 1.2.6.2 skrll return;
299 1.2.6.2 skrll }
300 1.2.6.2 skrll
301 1.2.6.2 skrll /* load the buffer */
302 1.2.6.2 skrll if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap,
303 1.2.6.2 skrll sc->sc_membase, size, NULL,
304 1.2.6.2 skrll BUS_DMA_NOWAIT)) != 0) {
305 1.2.6.2 skrll printf("%s: DMA buffer map load error %d\n",
306 1.2.6.2 skrll self->dv_xname, error);
307 1.2.6.2 skrll bus_dmamem_unmap(sc->sc_dmat, sc->sc_membase, size);
308 1.2.6.2 skrll bus_dmamem_free(sc->sc_dmat, &sc->sc_dmaseg, rseg);
309 1.2.6.2 skrll return;
310 1.2.6.2 skrll }
311 1.2.6.2 skrll
312 1.2.6.2 skrll /* map the registers into memory */
313 1.2.6.2 skrll
314 1.2.6.2 skrll sc->sc_dma = (struct dbri_dma *)sc->sc_membase; /* kernel virtual address of DMA buffer */
315 1.2.6.2 skrll sc->sc_dmabase = sc->sc_dmamap->dm_segs[0].ds_addr; /* physical address of DMA buffer */
316 1.2.6.2 skrll sc->sc_bufsiz = size;
317 1.2.6.2 skrll
318 1.2.6.2 skrll sbus_establish(&sc->sc_sd, &sc->sc_dev);
319 1.2.6.2 skrll
320 1.2.6.2 skrll bus_intr_establish(sa->sa_bustag, sa->sa_pri, IPL_AUDIO, /*0,*/
321 1.2.6.2 skrll dbri_intr, sc);
322 1.2.6.2 skrll
323 1.2.6.2 skrll sc->sc_locked = 0;
324 1.2.6.2 skrll sc->sc_desc_used = 0;
325 1.2.6.2 skrll
326 1.2.6.2 skrll config_interrupts(self, &dbri_config_interrupts);
327 1.2.6.2 skrll
328 1.2.6.2 skrll return;
329 1.2.6.2 skrll }
330 1.2.6.2 skrll
331 1.2.6.2 skrll void
332 1.2.6.2 skrll dbri_config_interrupts(struct device *dev)
333 1.2.6.2 skrll {
334 1.2.6.2 skrll struct dbri_softc *sc = (struct dbri_softc *)dev;
335 1.2.6.2 skrll dbri_init(sc);
336 1.2.6.2 skrll mmcodec_init(sc);
337 1.2.6.2 skrll /* Attach ourselves to the high level audio interface */
338 1.2.6.2 skrll audio_attach_mi(&dbri_hw_if, sc, &sc->sc_dev);
339 1.2.6.2 skrll
340 1.2.6.2 skrll return;
341 1.2.6.2 skrll }
342 1.2.6.2 skrll
343 1.2.6.2 skrll int
344 1.2.6.2 skrll dbri_intr(void *hdl)
345 1.2.6.2 skrll {
346 1.2.6.2 skrll struct dbri_softc *sc = hdl;
347 1.2.6.2 skrll bus_space_tag_t iot = sc->sc_iot;
348 1.2.6.2 skrll bus_space_handle_t ioh = sc->sc_ioh;
349 1.2.6.2 skrll int x;
350 1.2.6.2 skrll
351 1.2.6.2 skrll /* clear interrupt */
352 1.2.6.2 skrll x = bus_space_read_4(iot, ioh, DBRI_REG1);
353 1.2.6.2 skrll if (x & (DBRI_MRR | DBRI_MLE | DBRI_LBG | DBRI_MBE)) {
354 1.2.6.2 skrll u_int32_t tmp;
355 1.2.6.2 skrll
356 1.2.6.2 skrll if (x & DBRI_MRR)
357 1.2.6.2 skrll printf("%s: multiple ack error on sbus\n",
358 1.2.6.2 skrll sc->sc_dev.dv_xname);
359 1.2.6.2 skrll if (x & DBRI_MLE)
360 1.2.6.2 skrll printf("%s: multiple late error on sbus\n",
361 1.2.6.2 skrll sc->sc_dev.dv_xname);
362 1.2.6.2 skrll if (x & DBRI_LBG)
363 1.2.6.2 skrll printf("%s: lost bus grant on sbus\n",
364 1.2.6.2 skrll sc->sc_dev.dv_xname);
365 1.2.6.2 skrll if (x & DBRI_MBE)
366 1.2.6.2 skrll printf("%s: burst error on sbus\n",
367 1.2.6.2 skrll sc->sc_dev.dv_xname);
368 1.2.6.2 skrll
369 1.2.6.2 skrll /*
370 1.2.6.2 skrll * Some of these errors disable the chip's circuitry.
371 1.2.6.2 skrll * Re-enable the circuitry and keep on going.
372 1.2.6.2 skrll */
373 1.2.6.2 skrll
374 1.2.6.2 skrll tmp = bus_space_read_4(iot, ioh, DBRI_REG0);
375 1.2.6.2 skrll tmp &= ~(DBRI_DISABLE_MASTER);
376 1.2.6.2 skrll bus_space_write_4(iot, ioh, DBRI_REG0, tmp);
377 1.2.6.2 skrll }
378 1.2.6.2 skrll
379 1.2.6.2 skrll #if 0
380 1.2.6.2 skrll if (!x & 1) /* XXX: DBRI_INTR_REQ */
381 1.2.6.2 skrll return (1);
382 1.2.6.2 skrll #endif
383 1.2.6.2 skrll
384 1.2.6.2 skrll dbri_process_interrupt_buffer(sc);
385 1.2.6.2 skrll
386 1.2.6.2 skrll return (1);
387 1.2.6.2 skrll }
388 1.2.6.2 skrll
389 1.2.6.2 skrll int
390 1.2.6.2 skrll dbri_init(struct dbri_softc *sc)
391 1.2.6.2 skrll {
392 1.2.6.2 skrll bus_space_tag_t iot = sc->sc_iot;
393 1.2.6.2 skrll bus_space_handle_t ioh = sc->sc_ioh;
394 1.2.6.2 skrll u_int32_t reg;
395 1.2.6.2 skrll volatile u_int32_t *cmd;
396 1.2.6.2 skrll bus_addr_t dmaaddr;
397 1.2.6.2 skrll int n;
398 1.2.6.2 skrll
399 1.2.6.2 skrll dbri_reset(sc);
400 1.2.6.2 skrll
401 1.2.6.2 skrll cmd = dbri_command_lock(sc);
402 1.2.6.2 skrll
403 1.2.6.2 skrll /* XXX: Initialize interrupt ring buffer */
404 1.2.6.2 skrll sc->sc_dma->intr[0] = (u_int32_t)sc->sc_dmabase + dbri_dma_off(intr, 0);
405 1.2.6.2 skrll sc->sc_irqp = 1;
406 1.2.6.2 skrll
407 1.2.6.2 skrll /* Initialize pipes */
408 1.2.6.2 skrll for (n = 0; n < DBRI_PIPE_MAX; n++)
409 1.2.6.2 skrll sc->sc_pipe[n].desc = sc->sc_pipe[n].next = -1;
410 1.2.6.2 skrll
411 1.2.6.2 skrll for(n=1;n<DBRI_INT_BLOCKS;n++) {
412 1.2.6.2 skrll sc->sc_dma->intr[n]=0;
413 1.2.6.2 skrll }
414 1.2.6.2 skrll
415 1.2.6.2 skrll /* Disable all SBus bursts */
416 1.2.6.2 skrll /* XXX 16 byte bursts cause errors, the rest works */
417 1.2.6.2 skrll reg = bus_space_read_4(iot, ioh, DBRI_REG0);
418 1.2.6.2 skrll /*reg &= ~(DBRI_BURST_4 | DBRI_BURST_8 | DBRI_BURST_16);*/
419 1.2.6.2 skrll reg |= (DBRI_BURST_4 | DBRI_BURST_8);
420 1.2.6.2 skrll bus_space_write_4(iot, ioh, DBRI_REG0, reg);
421 1.2.6.2 skrll
422 1.2.6.2 skrll /* setup interrupt queue */
423 1.2.6.2 skrll dmaaddr = (u_int32_t)sc->sc_dmabase + dbri_dma_off(intr, 0);
424 1.2.6.2 skrll *(cmd++) = DBRI_CMD(DBRI_COMMAND_IIQ, 0, 0);
425 1.2.6.2 skrll *(cmd++) = dmaaddr;
426 1.2.6.2 skrll
427 1.2.6.2 skrll dbri_command_send(sc, cmd);
428 1.2.6.2 skrll return (0);
429 1.2.6.2 skrll }
430 1.2.6.2 skrll
431 1.2.6.2 skrll int
432 1.2.6.2 skrll dbri_reset(struct dbri_softc *sc)
433 1.2.6.2 skrll {
434 1.2.6.2 skrll int bail=0;
435 1.2.6.2 skrll bus_space_tag_t iot = sc->sc_iot;
436 1.2.6.2 skrll bus_space_handle_t ioh = sc->sc_ioh;
437 1.2.6.2 skrll
438 1.2.6.2 skrll bus_space_write_4(iot, ioh, DBRI_REG0, DBRI_SOFT_RESET);
439 1.2.6.2 skrll while ((bus_space_read_4(iot, ioh, DBRI_REG0) & DBRI_SOFT_RESET) &&
440 1.2.6.2 skrll (bail < 100000)) {
441 1.2.6.2 skrll bail++;
442 1.2.6.2 skrll delay(10);
443 1.2.6.2 skrll }
444 1.2.6.2 skrll if (bail == 100000) printf("%s: reset timed out\n",sc->sc_dev.dv_xname);
445 1.2.6.2 skrll return (0);
446 1.2.6.2 skrll }
447 1.2.6.2 skrll
448 1.2.6.2 skrll volatile u_int32_t *
449 1.2.6.2 skrll dbri_command_lock(struct dbri_softc *sc)
450 1.2.6.2 skrll {
451 1.2.6.2 skrll
452 1.2.6.2 skrll if (sc->sc_locked)
453 1.2.6.2 skrll printf("%s: command buffer locked\n", sc->sc_dev.dv_xname);
454 1.2.6.2 skrll
455 1.2.6.2 skrll sc->sc_locked++;
456 1.2.6.2 skrll
457 1.2.6.2 skrll return (&sc->sc_dma->command[0]);
458 1.2.6.2 skrll }
459 1.2.6.2 skrll
460 1.2.6.2 skrll void
461 1.2.6.2 skrll dbri_command_send(struct dbri_softc *sc, volatile u_int32_t *cmd)
462 1.2.6.2 skrll {
463 1.2.6.2 skrll bus_space_handle_t ioh = sc->sc_ioh;
464 1.2.6.2 skrll bus_space_tag_t iot = sc->sc_iot;
465 1.2.6.2 skrll int maxloops = 1000000;
466 1.2.6.2 skrll int x;
467 1.2.6.2 skrll
468 1.2.6.2 skrll x = splaudio();
469 1.2.6.2 skrll //x = splhigh();
470 1.2.6.2 skrll
471 1.2.6.2 skrll sc->sc_locked--;
472 1.2.6.2 skrll
473 1.2.6.2 skrll if (sc->sc_locked != 0) {
474 1.2.6.2 skrll printf("%s: command buffer improperly locked\n",
475 1.2.6.2 skrll sc->sc_dev.dv_xname);
476 1.2.6.2 skrll } else if ((cmd - &sc->sc_dma->command[0]) >= DBRI_NUM_COMMANDS - 1) {
477 1.2.6.2 skrll printf("%s: command buffer overflow\n", sc->sc_dev.dv_xname);
478 1.2.6.2 skrll } else {
479 1.2.6.2 skrll *(cmd++) = DBRI_CMD(DBRI_COMMAND_PAUSE, 0, 0);
480 1.2.6.2 skrll *(cmd++) = DBRI_CMD(DBRI_COMMAND_WAIT, 1, 0);
481 1.2.6.2 skrll sc->sc_waitseen = 0;
482 1.2.6.2 skrll bus_space_write_4(iot, ioh, DBRI_REG8, sc->sc_dmabase);
483 1.2.6.2 skrll while ((--maxloops) > 0 &&
484 1.2.6.2 skrll (bus_space_read_4(iot, ioh, DBRI_REG0)
485 1.2.6.2 skrll & DBRI_COMMAND_VALID)) {
486 1.2.6.2 skrll bus_space_barrier(iot, ioh, DBRI_REG0, 4,
487 1.2.6.2 skrll BUS_SPACE_BARRIER_READ);
488 1.2.6.2 skrll delay(1000);
489 1.2.6.2 skrll }
490 1.2.6.2 skrll
491 1.2.6.2 skrll if (maxloops == 0) {
492 1.2.6.2 skrll printf("%s: chip never completed command buffer\n",
493 1.2.6.2 skrll sc->sc_dev.dv_xname);
494 1.2.6.2 skrll } else {
495 1.2.6.2 skrll #ifdef DBRI_DEBUG
496 1.2.6.2 skrll printf("%s: command completed\n",sc->sc_dev.dv_xname);
497 1.2.6.2 skrll #endif
498 1.2.6.2 skrll while ((--maxloops) > 0 && (!sc->sc_waitseen))
499 1.2.6.2 skrll dbri_process_interrupt_buffer(sc);
500 1.2.6.2 skrll if (maxloops == 0) {
501 1.2.6.2 skrll printf("%s: chip never acked WAIT\n",
502 1.2.6.2 skrll sc->sc_dev.dv_xname);
503 1.2.6.2 skrll }
504 1.2.6.2 skrll }
505 1.2.6.2 skrll }
506 1.2.6.2 skrll
507 1.2.6.2 skrll splx(x);
508 1.2.6.2 skrll
509 1.2.6.2 skrll return;
510 1.2.6.2 skrll }
511 1.2.6.2 skrll
512 1.2.6.2 skrll void
513 1.2.6.2 skrll dbri_process_interrupt_buffer(struct dbri_softc *sc)
514 1.2.6.2 skrll {
515 1.2.6.2 skrll int32_t i;
516 1.2.6.2 skrll
517 1.2.6.2 skrll while ((i = sc->sc_dma->intr[sc->sc_irqp]) != 0) {
518 1.2.6.2 skrll sc->sc_dma->intr[sc->sc_irqp] = 0;
519 1.2.6.2 skrll sc->sc_irqp++;
520 1.2.6.2 skrll
521 1.2.6.2 skrll if (sc->sc_irqp == DBRI_INT_BLOCKS)
522 1.2.6.2 skrll sc->sc_irqp = 1;
523 1.2.6.2 skrll else if ((sc->sc_irqp & (DBRI_INT_BLOCKS - 1)) == 0)
524 1.2.6.2 skrll sc->sc_irqp++;
525 1.2.6.2 skrll
526 1.2.6.2 skrll dbri_process_interrupt(sc, i);
527 1.2.6.2 skrll }
528 1.2.6.2 skrll
529 1.2.6.2 skrll return;
530 1.2.6.2 skrll }
531 1.2.6.2 skrll
532 1.2.6.2 skrll void
533 1.2.6.2 skrll dbri_process_interrupt(struct dbri_softc *sc, int32_t i)
534 1.2.6.2 skrll {
535 1.2.6.2 skrll #if 0
536 1.2.6.2 skrll const int liu_states[] = { 1, 0, 8, 3, 4, 5, 6, 7 };
537 1.2.6.2 skrll #endif
538 1.2.6.2 skrll int val = DBRI_INTR_GETVAL(i);
539 1.2.6.2 skrll int channel = DBRI_INTR_GETCHAN(i);
540 1.2.6.2 skrll int command = DBRI_INTR_GETCMD(i);
541 1.2.6.2 skrll int code = DBRI_INTR_GETCODE(i);
542 1.2.6.2 skrll #if 0
543 1.2.6.2 skrll int rval = DBRI_INTR_GETRVAL(i);
544 1.2.6.2 skrll #endif
545 1.2.6.2 skrll if (channel == DBRI_INTR_CMD && command == DBRI_COMMAND_WAIT)
546 1.2.6.2 skrll sc->sc_waitseen++;
547 1.2.6.2 skrll
548 1.2.6.2 skrll switch (code) {
549 1.2.6.2 skrll case DBRI_INTR_XCMP: /* transmission complete */
550 1.2.6.2 skrll {
551 1.2.6.2 skrll int td;
552 1.2.6.2 skrll struct dbri_desc *dd;
553 1.2.6.2 skrll
554 1.2.6.2 skrll td = sc->sc_pipe[channel].desc;
555 1.2.6.2 skrll dd = &sc->sc_desc[td];
556 1.2.6.2 skrll
557 1.2.6.2 skrll if (dd->callback != NULL)
558 1.2.6.2 skrll dd->callback(dd->callback_args);
559 1.2.6.2 skrll break;
560 1.2.6.2 skrll }
561 1.2.6.2 skrll case DBRI_INTR_FXDT: /* fixed data change */
562 1.2.6.2 skrll #ifdef DBRI_DEBUG
563 1.2.6.2 skrll printf("dbri_intr: Fixed data change (%d: %x)\n",channel,val);
564 1.2.6.2 skrll #endif
565 1.2.6.2 skrll if (sc->sc_pipe[channel].sdp & DBRI_SDP_MSB)
566 1.2.6.2 skrll val = reverse_bytes(val, sc->sc_pipe[channel].length);
567 1.2.6.2 skrll if (sc->sc_pipe[channel].prec)
568 1.2.6.2 skrll *(sc->sc_pipe[channel].prec) = val;
569 1.2.6.2 skrll #ifdef DBRI_DEBUG
570 1.2.6.2 skrll printf("%s: wakeup %p\n", sc->sc_dev.dv_xname, sc);
571 1.2.6.2 skrll #endif
572 1.2.6.2 skrll #if 0
573 1.2.6.2 skrll wakeup(sc);
574 1.2.6.2 skrll #endif
575 1.2.6.2 skrll break;
576 1.2.6.2 skrll case DBRI_INTR_SBRI:
577 1.2.6.2 skrll #ifdef DBRI_DEBUG
578 1.2.6.2 skrll printf("dbri_intr: SBRI\n");
579 1.2.6.2 skrll #endif
580 1.2.6.2 skrll break;
581 1.2.6.2 skrll case DBRI_INTR_BRDY:
582 1.2.6.2 skrll {
583 1.2.6.2 skrll /* XXX no input (yet) */
584 1.2.6.2 skrll #if 0
585 1.2.6.2 skrll int rd = sc->sc_pipe[channel].desc;
586 1.2.6.2 skrll u_int32_t status;
587 1.2.6.2 skrll
588 1.2.6.2 skrll printf("dbri_intr: BRDY\n");
589 1.2.6.2 skrll if (rd < 0 || rd >= DBRI_NUM_DESCRIPTORS) {
590 1.2.6.2 skrll printf("%s: invalid rd on pipe\n", sc->sc_dev.dv_xname);
591 1.2.6.2 skrll break;
592 1.2.6.2 skrll }
593 1.2.6.2 skrll
594 1.2.6.2 skrll sc->sc_desc[rd].busy = 0;
595 1.2.6.2 skrll sc->sc_pipe[channel].desc = sc->sc_desc[rd].next;
596 1.2.6.2 skrll status = sc->sc_dma->desc[rd].word1;
597 1.2.6.2 skrll #endif
598 1.2.6.2 skrll /* XXX: callback ??? */
599 1.2.6.2 skrll
600 1.2.6.2 skrll break;
601 1.2.6.2 skrll }
602 1.2.6.2 skrll case DBRI_INTR_UNDR:
603 1.2.6.2 skrll {
604 1.2.6.2 skrll volatile u_int32_t *cmd;
605 1.2.6.2 skrll int td = sc->sc_pipe[channel].desc;
606 1.2.6.2 skrll
607 1.2.6.2 skrll printf("%s: DBRI_INTR_UNDR\n", sc->sc_dev.dv_xname);
608 1.2.6.2 skrll
609 1.2.6.2 skrll sc->sc_dma->desc[td].status = 0;
610 1.2.6.2 skrll
611 1.2.6.2 skrll cmd = dbri_command_lock(sc);
612 1.2.6.2 skrll *(cmd++) = DBRI_CMD(DBRI_COMMAND_SDP, 0,
613 1.2.6.2 skrll sc->sc_pipe[channel].sdp |
614 1.2.6.2 skrll DBRI_SDP_VALID_POINTER |
615 1.2.6.2 skrll DBRI_SDP_CLEAR |
616 1.2.6.2 skrll DBRI_SDP_2SAME);
617 1.2.6.2 skrll *(cmd++) = sc->sc_dmabase + dbri_dma_off(desc, td);
618 1.2.6.2 skrll dbri_command_send(sc, cmd);
619 1.2.6.2 skrll break;
620 1.2.6.2 skrll }
621 1.2.6.2 skrll default:
622 1.2.6.2 skrll #if 0
623 1.2.6.2 skrll printf("%s: unknown interrupt code %d\n",
624 1.2.6.2 skrll sc->sc_dev.dv_xname, code);
625 1.2.6.2 skrll #endif
626 1.2.6.2 skrll break;
627 1.2.6.2 skrll }
628 1.2.6.2 skrll
629 1.2.6.2 skrll return;
630 1.2.6.2 skrll }
631 1.2.6.2 skrll
632 1.2.6.2 skrll /*
633 1.2.6.2 skrll * mmcodec stuff
634 1.2.6.2 skrll */
635 1.2.6.2 skrll
636 1.2.6.2 skrll int
637 1.2.6.2 skrll mmcodec_init(struct dbri_softc *sc)
638 1.2.6.2 skrll {
639 1.2.6.2 skrll bus_space_handle_t ioh = sc->sc_ioh;
640 1.2.6.2 skrll bus_space_tag_t iot = sc->sc_iot;
641 1.2.6.2 skrll u_int32_t reg2;
642 1.2.6.2 skrll
643 1.2.6.2 skrll reg2 = bus_space_read_4(iot, ioh, DBRI_REG2);
644 1.2.6.2 skrll #ifdef DBRI_DEBUG
645 1.2.6.2 skrll printf("mmcodec_init: PIO reads %x\n",reg2);
646 1.2.6.2 skrll #endif
647 1.2.6.2 skrll if (reg2 & DBRI_PIO2) {
648 1.2.6.2 skrll printf("%s: onboard CS4215 detected\n",
649 1.2.6.2 skrll sc->sc_dev.dv_xname);
650 1.2.6.2 skrll sc->sc_mm.onboard = 1;
651 1.2.6.2 skrll }
652 1.2.6.2 skrll
653 1.2.6.2 skrll if (reg2 & DBRI_PIO0) {
654 1.2.6.2 skrll printf("%s: speakerbox detected\n",
655 1.2.6.2 skrll sc->sc_dev.dv_xname);
656 1.2.6.2 skrll sc->sc_mm.onboard = 0;
657 1.2.6.2 skrll }
658 1.2.6.2 skrll
659 1.2.6.2 skrll if ((reg2 & DBRI_PIO2) && (reg2 & DBRI_PIO0)) {
660 1.2.6.2 skrll printf("%s: using speakerbox\n",
661 1.2.6.2 skrll sc->sc_dev.dv_xname);
662 1.2.6.2 skrll bus_space_write_4(iot, ioh, DBRI_REG2, DBRI_PIO2_ENABLE);
663 1.2.6.2 skrll sc->sc_mm.onboard = 0;
664 1.2.6.2 skrll }
665 1.2.6.2 skrll
666 1.2.6.2 skrll if (!(reg2 & (DBRI_PIO0|DBRI_PIO2))) {
667 1.2.6.2 skrll printf("%s: no mmcodec found\n", sc->sc_dev.dv_xname);
668 1.2.6.2 skrll return -1;
669 1.2.6.2 skrll }
670 1.2.6.2 skrll
671 1.2.6.2 skrll sc->sc_version = 0xff;
672 1.2.6.2 skrll
673 1.2.6.2 skrll mmcodec_pipe_init(sc);
674 1.2.6.2 skrll mmcodec_default(sc);
675 1.2.6.2 skrll
676 1.2.6.2 skrll sc->sc_mm.offset = sc->sc_mm.onboard ? 0 : 8;
677 1.2.6.2 skrll
678 1.2.6.2 skrll if (mmcodec_setcontrol(sc) == -1 || sc->sc_version == 0xff) {
679 1.2.6.2 skrll printf("%s: cs4215 probe failed at offset %d\n",
680 1.2.6.2 skrll sc->sc_dev.dv_xname, sc->sc_mm.offset);
681 1.2.6.2 skrll return (-1);
682 1.2.6.2 skrll }
683 1.2.6.2 skrll
684 1.2.6.2 skrll printf("%s: cs4215 ver %d found at offset %d\n",
685 1.2.6.2 skrll sc->sc_dev.dv_xname, sc->sc_version & 0xf, sc->sc_mm.offset);
686 1.2.6.2 skrll
687 1.2.6.2 skrll /* set some sane defaults for mmcodec_init_data */
688 1.2.6.2 skrll sc->sc_params.channels = 2;
689 1.2.6.2 skrll sc->sc_params.precision = 16;
690 1.2.6.2 skrll
691 1.2.6.2 skrll mmcodec_init_data(sc);
692 1.2.6.2 skrll
693 1.2.6.2 skrll sc->sc_open = 0;
694 1.2.6.2 skrll
695 1.2.6.2 skrll return (0);
696 1.2.6.2 skrll }
697 1.2.6.2 skrll
698 1.2.6.2 skrll void
699 1.2.6.2 skrll mmcodec_init_data(struct dbri_softc *sc)
700 1.2.6.2 skrll {
701 1.2.6.2 skrll bus_space_tag_t iot = sc->sc_iot;
702 1.2.6.2 skrll bus_space_handle_t ioh = sc->sc_ioh;
703 1.2.6.2 skrll u_int32_t tmp;
704 1.2.6.2 skrll int data_width;
705 1.2.6.2 skrll
706 1.2.6.2 skrll tmp = bus_space_read_4(iot, ioh, DBRI_REG0);
707 1.2.6.2 skrll tmp &= ~(DBRI_CHI_ACTIVATE); /* disable CHI */
708 1.2.6.2 skrll bus_space_write_4(iot, ioh, DBRI_REG0, tmp);
709 1.2.6.2 skrll
710 1.2.6.2 skrll /* switch CS4215 to data mode - set PIO3 to 1 */
711 1.2.6.2 skrll tmp = DBRI_PIO_ENABLE_ALL | DBRI_PIO1 | DBRI_PIO3;
712 1.2.6.2 skrll /* XXX */
713 1.2.6.2 skrll tmp |= (sc->sc_mm.onboard ? DBRI_PIO0 : DBRI_PIO2);
714 1.2.6.2 skrll
715 1.2.6.2 skrll bus_space_write_4(iot, ioh, DBRI_REG2, tmp);
716 1.2.6.2 skrll chi_reset(sc, CHIslave, 128);
717 1.2.6.2 skrll
718 1.2.6.2 skrll data_width = sc->sc_params.channels
719 1.2.6.2 skrll * sc->sc_params.precision;
720 1.2.6.2 skrll pipe_ts_link(sc, 20, PIPEoutput, 16, 32, sc->sc_mm.offset + 32);
721 1.2.6.2 skrll pipe_ts_link(sc, 4, PIPEoutput, 16, data_width, sc->sc_mm.offset);
722 1.2.6.2 skrll pipe_ts_link(sc, 6, PIPEinput, 16, data_width, sc->sc_mm.offset);
723 1.2.6.2 skrll pipe_ts_link(sc, 21, PIPEinput, 16, 16, sc->sc_mm.offset + 40);
724 1.2.6.2 skrll
725 1.2.6.2 skrll mmcodec_setgain(sc, 0);
726 1.2.6.2 skrll
727 1.2.6.2 skrll tmp = bus_space_read_4(iot, ioh, DBRI_REG0);
728 1.2.6.2 skrll tmp |= DBRI_CHI_ACTIVATE;
729 1.2.6.2 skrll bus_space_write_4(iot, ioh, DBRI_REG0, tmp);
730 1.2.6.2 skrll
731 1.2.6.2 skrll return;
732 1.2.6.2 skrll }
733 1.2.6.2 skrll
734 1.2.6.2 skrll void
735 1.2.6.2 skrll mmcodec_pipe_init(struct dbri_softc *sc)
736 1.2.6.2 skrll {
737 1.2.6.2 skrll
738 1.2.6.2 skrll pipe_setup(sc, 4, DBRI_SDP_MEM | DBRI_SDP_TO_SER | DBRI_SDP_MSB);
739 1.2.6.2 skrll pipe_setup(sc, 20, DBRI_SDP_FIXED | DBRI_SDP_TO_SER | DBRI_SDP_MSB);
740 1.2.6.2 skrll pipe_setup(sc, 6, DBRI_SDP_MEM | DBRI_SDP_FROM_SER | DBRI_SDP_MSB);
741 1.2.6.2 skrll pipe_setup(sc, 21, DBRI_SDP_FIXED | DBRI_SDP_FROM_SER | DBRI_SDP_MSB);
742 1.2.6.2 skrll
743 1.2.6.2 skrll pipe_setup(sc, 17, DBRI_SDP_FIXED | DBRI_SDP_TO_SER | DBRI_SDP_MSB);
744 1.2.6.2 skrll pipe_setup(sc, 18, DBRI_SDP_FIXED | DBRI_SDP_FROM_SER | DBRI_SDP_MSB);
745 1.2.6.2 skrll pipe_setup(sc, 19, DBRI_SDP_FIXED | DBRI_SDP_FROM_SER | DBRI_SDP_MSB);
746 1.2.6.2 skrll
747 1.2.6.2 skrll sc->sc_mm.status = 0;
748 1.2.6.2 skrll
749 1.2.6.2 skrll pipe_receive_fixed(sc, 18, &sc->sc_mm.status);
750 1.2.6.2 skrll pipe_receive_fixed(sc, 19, &sc->sc_mm.version);
751 1.2.6.2 skrll
752 1.2.6.2 skrll return;
753 1.2.6.2 skrll }
754 1.2.6.2 skrll
755 1.2.6.2 skrll void
756 1.2.6.2 skrll mmcodec_default(struct dbri_softc *sc)
757 1.2.6.2 skrll {
758 1.2.6.2 skrll struct cs4215_state *mm = &sc->sc_mm;
759 1.2.6.2 skrll
760 1.2.6.2 skrll /*
761 1.2.6.2 skrll * no action, memory resetting only
762 1.2.6.2 skrll *
763 1.2.6.2 skrll * data time slots 5-8
764 1.2.6.2 skrll * speaker, line and headphone enable. set gain to half.
765 1.2.6.2 skrll * input is mic
766 1.2.6.2 skrll */
767 1.2.6.2 skrll mm->data[0] = sc->sc_latt = 0x20 | CS4215_HE | CS4215_LE;
768 1.2.6.2 skrll mm->data[1] = sc->sc_ratt = 0x20 | CS4215_SE;
769 1.2.6.2 skrll mm->data[2] = CS4215_LG(0x08) | CS4215_IS | CS4215_PIO0 | CS4215_PIO1;
770 1.2.6.2 skrll mm->data[3] = CS4215_RG(0x08) | CS4215_MA(0x0f);
771 1.2.6.2 skrll
772 1.2.6.2 skrll /*
773 1.2.6.2 skrll * control time slots 1-4
774 1.2.6.2 skrll *
775 1.2.6.2 skrll * 0: default I/O voltage scale
776 1.2.6.2 skrll * 1: 8 bit ulaw, 8kHz, mono, high pass filter disabled
777 1.2.6.2 skrll * 2: serial enable, CHI master, 128 bits per frame, clock 1
778 1.2.6.2 skrll * 3: tests disabled
779 1.2.6.2 skrll */
780 1.2.6.2 skrll mm->control[0] = CS4215_RSRVD_1 | CS4215_MLB;
781 1.2.6.2 skrll mm->control[1] = CS4215_DFR_ULAW | CS4215_FREQ[0].csval;
782 1.2.6.2 skrll mm->control[2] = CS4215_XCLK | CS4215_BSEL_128 | CS4215_FREQ[0].xtal;
783 1.2.6.2 skrll mm->control[3] = 0;
784 1.2.6.2 skrll
785 1.2.6.2 skrll return;
786 1.2.6.2 skrll }
787 1.2.6.2 skrll
788 1.2.6.2 skrll void
789 1.2.6.2 skrll mmcodec_setgain(struct dbri_softc *sc, int mute)
790 1.2.6.2 skrll {
791 1.2.6.2 skrll if (mute) {
792 1.2.6.2 skrll /* disable all outputs, max. attenuation */
793 1.2.6.2 skrll sc->sc_mm.data[0] = sc->sc_latt | 63;
794 1.2.6.2 skrll sc->sc_mm.data[1] = sc->sc_ratt | 63;
795 1.2.6.2 skrll } else {
796 1.2.6.2 skrll /*
797 1.2.6.2 skrll * We should be setting the proper output here.. for now,
798 1.2.6.2 skrll * use the speaker. Possible outputs:
799 1.2.6.2 skrll * Headphones:
800 1.2.6.2 skrll * data[0] |= CS4215_HE;
801 1.2.6.2 skrll * Line out:
802 1.2.6.2 skrll * data[0] |= CS4215_LE;
803 1.2.6.2 skrll * Speaker:
804 1.2.6.2 skrll * data[1] |= CS4215_SE;
805 1.2.6.2 skrll */
806 1.2.6.2 skrll sc->sc_mm.data[0] = sc->sc_latt;
807 1.2.6.2 skrll sc->sc_mm.data[1] = sc->sc_ratt;
808 1.2.6.2 skrll }
809 1.2.6.2 skrll
810 1.2.6.2 skrll pipe_transmit_fixed(sc, 20, *(u_int32_t *)__UNVOLATILE(sc->sc_mm.data));
811 1.2.6.2 skrll
812 1.2.6.2 skrll /* give the chip some time to execure the command */
813 1.2.6.2 skrll delay(250);
814 1.2.6.2 skrll
815 1.2.6.2 skrll return;
816 1.2.6.2 skrll }
817 1.2.6.2 skrll
818 1.2.6.2 skrll int
819 1.2.6.2 skrll mmcodec_setcontrol(struct dbri_softc *sc)
820 1.2.6.2 skrll {
821 1.2.6.2 skrll bus_space_tag_t iot = sc->sc_iot;
822 1.2.6.2 skrll bus_space_handle_t ioh = sc->sc_ioh;
823 1.2.6.2 skrll u_int32_t val;
824 1.2.6.2 skrll u_int32_t tmp;
825 1.2.6.2 skrll #if 1
826 1.2.6.2 skrll int i;
827 1.2.6.2 skrll #endif
828 1.2.6.2 skrll
829 1.2.6.2 skrll /*
830 1.2.6.2 skrll * Temporarily mute outputs and wait 125 us to make sure that it
831 1.2.6.2 skrll * happens. This avoids clicking noises.
832 1.2.6.2 skrll */
833 1.2.6.2 skrll mmcodec_setgain(sc, 1);
834 1.2.6.2 skrll //DELAY(125);
835 1.2.6.2 skrll
836 1.2.6.2 skrll /* enable control mode */
837 1.2.6.2 skrll val = DBRI_PIO_ENABLE_ALL | DBRI_PIO1; /* was PIO1 */
838 1.2.6.2 skrll
839 1.2.6.2 skrll /* XXX */
840 1.2.6.2 skrll val |= (sc->sc_mm.onboard ? DBRI_PIO0 : DBRI_PIO2);
841 1.2.6.2 skrll
842 1.2.6.2 skrll bus_space_write_4(iot, ioh, DBRI_REG2, val);
843 1.2.6.2 skrll
844 1.2.6.2 skrll DELAY(34);
845 1.2.6.2 skrll
846 1.2.6.2 skrll /*
847 1.2.6.2 skrll * in control mode, the cs4215 is the slave device, so the
848 1.2.6.2 skrll * DBRI must act as the CHI master.
849 1.2.6.2 skrll *
850 1.2.6.2 skrll * in data mode, the cs4215 must be the CHI master to insure
851 1.2.6.2 skrll * that the data stream is in sync with its codec
852 1.2.6.2 skrll */
853 1.2.6.2 skrll tmp = bus_space_read_4(iot, ioh, DBRI_REG0);
854 1.2.6.2 skrll tmp &= ~DBRI_COMMAND_CHI;
855 1.2.6.2 skrll bus_space_write_4(iot, ioh, DBRI_REG0, tmp);
856 1.2.6.2 skrll
857 1.2.6.2 skrll chi_reset(sc, CHImaster, 128);
858 1.2.6.2 skrll
859 1.2.6.2 skrll /* control mode */
860 1.2.6.2 skrll pipe_ts_link(sc, 17, PIPEoutput, 16, 32, sc->sc_mm.offset);
861 1.2.6.2 skrll pipe_ts_link(sc, 18, PIPEinput, 16, 8, sc->sc_mm.offset);
862 1.2.6.2 skrll pipe_ts_link(sc, 19, PIPEinput, 16, 8, sc->sc_mm.offset + 48);
863 1.2.6.2 skrll
864 1.2.6.2 skrll /* wait for the chip to echo back CLB as zero */
865 1.2.6.2 skrll sc->sc_mm.control[0] &= ~CS4215_CLB;
866 1.2.6.2 skrll pipe_transmit_fixed(sc, 17, *(int *)__UNVOLATILE(sc->sc_mm.control));
867 1.2.6.2 skrll
868 1.2.6.2 skrll tmp = bus_space_read_4(iot, ioh, DBRI_REG0);
869 1.2.6.2 skrll tmp |= DBRI_CHI_ACTIVATE;
870 1.2.6.2 skrll bus_space_write_4(iot, ioh, DBRI_REG0, tmp);
871 1.2.6.2 skrll
872 1.2.6.2 skrll #if 1
873 1.2.6.2 skrll i = 1024;
874 1.2.6.2 skrll while (((sc->sc_mm.status & 0xe4) != 0x20) && --i) {
875 1.2.6.2 skrll delay(125);
876 1.2.6.2 skrll }
877 1.2.6.2 skrll
878 1.2.6.2 skrll if (i == 0) {
879 1.2.6.2 skrll printf("%s: cs4215 didn't respond to CLB (0x%02x)\n",
880 1.2.6.2 skrll sc->sc_dev.dv_xname, sc->sc_mm.status);
881 1.2.6.2 skrll return (-1);
882 1.2.6.2 skrll }
883 1.2.6.2 skrll #else
884 1.2.6.2 skrll while ((sc->sc_mm.status & 0xe4) != 0x20) {
885 1.2.6.2 skrll printf("%s: tsleep %p\n", sc->sc_dev.dv_xname, sc);
886 1.2.6.2 skrll tsleep(sc, PCATCH | PZERO, "dbrifxdt", 0);
887 1.2.6.2 skrll }
888 1.2.6.2 skrll #endif
889 1.2.6.2 skrll
890 1.2.6.2 skrll /* copy the version information before it becomes unreadable again */
891 1.2.6.2 skrll sc->sc_version=sc->sc_mm.version;
892 1.2.6.2 skrll
893 1.2.6.2 skrll /* terminate cs4215 control mode */
894 1.2.6.2 skrll sc->sc_mm.control[0] |= CS4215_CLB;
895 1.2.6.2 skrll pipe_transmit_fixed(sc, 17, *(int *)__UNVOLATILE(sc->sc_mm.control));
896 1.2.6.2 skrll
897 1.2.6.2 skrll /* two frames of control info @ 8kHz frame rate = 250us delay */
898 1.2.6.2 skrll DELAY(250);
899 1.2.6.2 skrll
900 1.2.6.2 skrll mmcodec_setgain(sc, 0);
901 1.2.6.2 skrll
902 1.2.6.2 skrll return (0);
903 1.2.6.2 skrll
904 1.2.6.2 skrll }
905 1.2.6.2 skrll
906 1.2.6.2 skrll /*
907 1.2.6.2 skrll * CHI combo
908 1.2.6.2 skrll */
909 1.2.6.2 skrll void
910 1.2.6.2 skrll chi_reset(struct dbri_softc *sc, enum ms ms, int bpf)
911 1.2.6.2 skrll {
912 1.2.6.2 skrll volatile u_int32_t *cmd;
913 1.2.6.2 skrll int val;
914 1.2.6.2 skrll int clockrate, divisor;
915 1.2.6.2 skrll
916 1.2.6.2 skrll cmd = dbri_command_lock(sc);
917 1.2.6.2 skrll
918 1.2.6.2 skrll /* set CHI anchor: pipe 16 */
919 1.2.6.2 skrll val = DBRI_DTS_VI | DBRI_DTS_INS | DBRI_DTS_PRVIN(16) | DBRI_PIPE(16);
920 1.2.6.2 skrll *(cmd++) = DBRI_CMD(DBRI_COMMAND_DTS, 0, val);
921 1.2.6.2 skrll *(cmd++) = DBRI_TS_ANCHOR | DBRI_TS_NEXT(16);
922 1.2.6.2 skrll *(cmd++) = 0;
923 1.2.6.2 skrll
924 1.2.6.2 skrll val = DBRI_DTS_VO | DBRI_DTS_INS | DBRI_DTS_PRVOUT(16) | DBRI_PIPE(16);
925 1.2.6.2 skrll *(cmd++) = DBRI_CMD(DBRI_COMMAND_DTS, 0, val);
926 1.2.6.2 skrll *(cmd++) = 0;
927 1.2.6.2 skrll *(cmd++) = DBRI_TS_ANCHOR | DBRI_TS_NEXT(16);
928 1.2.6.2 skrll
929 1.2.6.2 skrll sc->sc_pipe[16].sdp = 1;
930 1.2.6.2 skrll sc->sc_pipe[16].next = 16;
931 1.2.6.2 skrll sc->sc_chi_pipe_in = 16;
932 1.2.6.2 skrll sc->sc_chi_pipe_out = 16;
933 1.2.6.2 skrll
934 1.2.6.2 skrll switch (ms) {
935 1.2.6.2 skrll case CHIslave:
936 1.2.6.2 skrll *(cmd++) = DBRI_CMD(DBRI_COMMAND_CHI, 0, DBRI_CHI_CHICM(0));
937 1.2.6.2 skrll break;
938 1.2.6.2 skrll case CHImaster:
939 1.2.6.2 skrll clockrate = bpf * 8;
940 1.2.6.2 skrll divisor = 12288 / clockrate;
941 1.2.6.2 skrll
942 1.2.6.2 skrll if (divisor > 255 || divisor * clockrate != 12288)
943 1.2.6.2 skrll printf("%s: illegal bits-per-frame %d\n",
944 1.2.6.2 skrll sc->sc_dev.dv_xname, bpf);
945 1.2.6.2 skrll
946 1.2.6.2 skrll *(cmd++) = DBRI_CMD(DBRI_COMMAND_CHI, 0,
947 1.2.6.2 skrll DBRI_CHI_CHICM(divisor) | DBRI_CHI_FD | DBRI_CHI_BPF(bpf));
948 1.2.6.2 skrll break;
949 1.2.6.2 skrll default:
950 1.2.6.2 skrll printf("%s: unknown value for ms!\n", sc->sc_dev.dv_xname);
951 1.2.6.2 skrll break;
952 1.2.6.2 skrll }
953 1.2.6.2 skrll
954 1.2.6.2 skrll sc->sc_chi_bpf = bpf;
955 1.2.6.2 skrll
956 1.2.6.2 skrll /* CHI data mode */
957 1.2.6.2 skrll *(cmd++) = DBRI_CMD(DBRI_COMMAND_PAUSE, 0, 0);
958 1.2.6.2 skrll *(cmd++) = DBRI_CMD(DBRI_COMMAND_CDM, 0,
959 1.2.6.2 skrll DBRI_CDM_XCE | DBRI_CDM_XEN | DBRI_CDM_REN);
960 1.2.6.2 skrll
961 1.2.6.2 skrll dbri_command_send(sc, cmd);
962 1.2.6.2 skrll
963 1.2.6.2 skrll return;
964 1.2.6.2 skrll }
965 1.2.6.2 skrll
966 1.2.6.2 skrll /*
967 1.2.6.2 skrll * pipe stuff
968 1.2.6.2 skrll */
969 1.2.6.2 skrll void
970 1.2.6.2 skrll pipe_setup(struct dbri_softc *sc, int pipe, int sdp)
971 1.2.6.2 skrll {
972 1.2.6.2 skrll #ifdef DBRI_DEBUG
973 1.2.6.2 skrll printf("pipe setup: %d\n",pipe);
974 1.2.6.2 skrll #endif
975 1.2.6.2 skrll if (pipe < 0 || pipe >= DBRI_PIPE_MAX) {
976 1.2.6.2 skrll printf("%s: illegal pipe number %d\n", sc->sc_dev.dv_xname,
977 1.2.6.2 skrll pipe);
978 1.2.6.2 skrll return;
979 1.2.6.2 skrll }
980 1.2.6.2 skrll
981 1.2.6.2 skrll if ((sdp & 0xf800) != sdp)
982 1.2.6.2 skrll printf("%s: strange SDP value %d\n", sc->sc_dev.dv_xname, sdp);
983 1.2.6.2 skrll
984 1.2.6.2 skrll if (DBRI_SDP_MODE(sdp) == DBRI_SDP_FIXED &&
985 1.2.6.2 skrll !(sdp & DBRI_SDP_TO_SER))
986 1.2.6.2 skrll sdp |= DBRI_SDP_CHANGE;
987 1.2.6.2 skrll
988 1.2.6.2 skrll sdp |= DBRI_PIPE(pipe);
989 1.2.6.2 skrll
990 1.2.6.2 skrll sc->sc_pipe[pipe].sdp = sdp;
991 1.2.6.2 skrll sc->sc_pipe[pipe].desc = -1;
992 1.2.6.2 skrll
993 1.2.6.2 skrll pipe_reset(sc, pipe);
994 1.2.6.2 skrll
995 1.2.6.2 skrll return;
996 1.2.6.2 skrll }
997 1.2.6.2 skrll
998 1.2.6.2 skrll void
999 1.2.6.2 skrll pipe_reset(struct dbri_softc *sc, int pipe)
1000 1.2.6.2 skrll {
1001 1.2.6.2 skrll struct dbri_desc *dd;
1002 1.2.6.2 skrll int sdp;
1003 1.2.6.2 skrll int desc;
1004 1.2.6.2 skrll volatile u_int32_t *cmd;
1005 1.2.6.2 skrll
1006 1.2.6.2 skrll if (pipe < 0 || pipe >= DBRI_PIPE_MAX) {
1007 1.2.6.2 skrll printf("%s: illegal pipe number %d\n", sc->sc_dev.dv_xname,
1008 1.2.6.2 skrll pipe);
1009 1.2.6.2 skrll return;
1010 1.2.6.2 skrll }
1011 1.2.6.2 skrll
1012 1.2.6.2 skrll sdp = sc->sc_pipe[pipe].sdp;
1013 1.2.6.2 skrll if (sdp == 0) {
1014 1.2.6.2 skrll printf("%s: can not reset uninitialized pipe %d\n",
1015 1.2.6.2 skrll sc->sc_dev.dv_xname, pipe);
1016 1.2.6.2 skrll return;
1017 1.2.6.2 skrll }
1018 1.2.6.2 skrll
1019 1.2.6.2 skrll cmd = dbri_command_lock(sc);
1020 1.2.6.2 skrll *(cmd++) = DBRI_CMD(DBRI_COMMAND_SDP, 0,
1021 1.2.6.2 skrll sdp | DBRI_SDP_CLEAR | DBRI_SDP_VALID_POINTER);
1022 1.2.6.2 skrll *(cmd++) = 0;
1023 1.2.6.2 skrll dbri_command_send(sc, cmd);
1024 1.2.6.2 skrll
1025 1.2.6.2 skrll desc = sc->sc_pipe[pipe].desc;
1026 1.2.6.2 skrll
1027 1.2.6.2 skrll dd = &sc->sc_desc[desc];
1028 1.2.6.2 skrll
1029 1.2.6.2 skrll dd->busy = 0;
1030 1.2.6.2 skrll
1031 1.2.6.2 skrll #if 0
1032 1.2.6.2 skrll if (dd->callback)
1033 1.2.6.2 skrll (*dd->callback)(dd->callback_args);
1034 1.2.6.2 skrll #endif
1035 1.2.6.2 skrll
1036 1.2.6.2 skrll sc->sc_pipe[pipe].desc = -1;
1037 1.2.6.2 skrll
1038 1.2.6.2 skrll return;
1039 1.2.6.2 skrll }
1040 1.2.6.2 skrll
1041 1.2.6.2 skrll void
1042 1.2.6.2 skrll pipe_receive_fixed(struct dbri_softc *sc, int pipe, volatile u_int32_t *prec)
1043 1.2.6.2 skrll {
1044 1.2.6.2 skrll
1045 1.2.6.2 skrll if (pipe < DBRI_PIPE_MAX / 2 || pipe >= DBRI_PIPE_MAX) {
1046 1.2.6.2 skrll printf("%s: illegal pipe number %d\n", sc->sc_dev.dv_xname,
1047 1.2.6.2 skrll pipe);
1048 1.2.6.2 skrll return;
1049 1.2.6.2 skrll }
1050 1.2.6.2 skrll
1051 1.2.6.2 skrll if (DBRI_SDP_MODE(sc->sc_pipe[pipe].sdp) != DBRI_SDP_FIXED) {
1052 1.2.6.2 skrll printf("%s: non-fixed pipe %d\n", sc->sc_dev.dv_xname,
1053 1.2.6.2 skrll pipe);
1054 1.2.6.2 skrll return;
1055 1.2.6.2 skrll }
1056 1.2.6.2 skrll
1057 1.2.6.2 skrll if (sc->sc_pipe[pipe].sdp & DBRI_SDP_TO_SER) {
1058 1.2.6.2 skrll printf("%s: can not receive on transmit pipe %d\b",
1059 1.2.6.2 skrll sc->sc_dev.dv_xname, pipe);
1060 1.2.6.2 skrll return;
1061 1.2.6.2 skrll }
1062 1.2.6.2 skrll
1063 1.2.6.2 skrll sc->sc_pipe[pipe].prec = prec;
1064 1.2.6.2 skrll
1065 1.2.6.2 skrll return;
1066 1.2.6.2 skrll }
1067 1.2.6.2 skrll
1068 1.2.6.2 skrll void
1069 1.2.6.2 skrll pipe_transmit_fixed(struct dbri_softc *sc, int pipe, u_int32_t data)
1070 1.2.6.2 skrll {
1071 1.2.6.2 skrll volatile u_int32_t *cmd;
1072 1.2.6.2 skrll
1073 1.2.6.2 skrll if (pipe < DBRI_PIPE_MAX / 2 || pipe >= DBRI_PIPE_MAX) {
1074 1.2.6.2 skrll printf("%s: illegal pipe number %d\n", sc->sc_dev.dv_xname,
1075 1.2.6.2 skrll pipe);
1076 1.2.6.2 skrll return;
1077 1.2.6.2 skrll }
1078 1.2.6.2 skrll
1079 1.2.6.2 skrll if (DBRI_SDP_MODE(sc->sc_pipe[pipe].sdp) == 0) {
1080 1.2.6.2 skrll printf("%s: uninitialized pipe %d\n", sc->sc_dev.dv_xname,
1081 1.2.6.2 skrll pipe);
1082 1.2.6.2 skrll return;
1083 1.2.6.2 skrll }
1084 1.2.6.2 skrll
1085 1.2.6.2 skrll if (DBRI_SDP_MODE(sc->sc_pipe[pipe].sdp) != DBRI_SDP_FIXED) {
1086 1.2.6.2 skrll printf("%s: non-fixed pipe %d\n", sc->sc_dev.dv_xname, pipe);
1087 1.2.6.2 skrll return;
1088 1.2.6.2 skrll }
1089 1.2.6.2 skrll
1090 1.2.6.2 skrll if (!(sc->sc_pipe[pipe].sdp & DBRI_SDP_TO_SER)) {
1091 1.2.6.2 skrll printf("%s: called on receive pipe %d\n", sc->sc_dev.dv_xname,
1092 1.2.6.2 skrll pipe);
1093 1.2.6.2 skrll return;
1094 1.2.6.2 skrll }
1095 1.2.6.2 skrll
1096 1.2.6.2 skrll if (sc->sc_pipe[pipe].sdp & DBRI_SDP_MSB)
1097 1.2.6.2 skrll data = reverse_bytes(data, sc->sc_pipe[pipe].length);
1098 1.2.6.2 skrll
1099 1.2.6.2 skrll cmd = dbri_command_lock(sc);
1100 1.2.6.2 skrll *(cmd++) = DBRI_CMD(DBRI_COMMAND_SSP, 0, pipe);
1101 1.2.6.2 skrll *(cmd++) = data;
1102 1.2.6.2 skrll
1103 1.2.6.2 skrll dbri_command_send(sc, cmd);
1104 1.2.6.2 skrll
1105 1.2.6.2 skrll return;
1106 1.2.6.2 skrll }
1107 1.2.6.2 skrll
1108 1.2.6.2 skrll void
1109 1.2.6.2 skrll setup_ring(struct dbri_softc *sc, int pipe, int which, int num, int blksz,
1110 1.2.6.2 skrll void (*callback)(void *), void *callback_args)
1111 1.2.6.2 skrll {
1112 1.2.6.2 skrll volatile u_int32_t *cmd;
1113 1.2.6.2 skrll int x, i;
1114 1.2.6.2 skrll int td;
1115 1.2.6.2 skrll int td_first, td_last;
1116 1.2.6.2 skrll bus_addr_t dmabuf, dmabase;
1117 1.2.6.2 skrll struct dbri_desc *dd = &sc->sc_desc[which];
1118 1.2.6.2 skrll
1119 1.2.6.2 skrll td = 0;
1120 1.2.6.2 skrll td_first = td_last = -1;
1121 1.2.6.2 skrll
1122 1.2.6.2 skrll if (pipe < 0 || pipe >= DBRI_PIPE_MAX / 2) {
1123 1.2.6.2 skrll printf("%s: illegal pipe number %d\n", sc->sc_dev.dv_xname,
1124 1.2.6.2 skrll pipe);
1125 1.2.6.2 skrll return;
1126 1.2.6.2 skrll }
1127 1.2.6.2 skrll
1128 1.2.6.2 skrll if (sc->sc_pipe[pipe].sdp == 0) {
1129 1.2.6.2 skrll printf("%s: uninitialized pipe %d\n", sc->sc_dev.dv_xname,
1130 1.2.6.2 skrll pipe);
1131 1.2.6.2 skrll return;
1132 1.2.6.2 skrll }
1133 1.2.6.2 skrll
1134 1.2.6.2 skrll if (!(sc->sc_pipe[pipe].sdp & DBRI_SDP_TO_SER)) {
1135 1.2.6.2 skrll printf("%s: called on receive pipe %d\n",
1136 1.2.6.2 skrll sc->sc_dev.dv_xname, pipe);
1137 1.2.6.2 skrll return;
1138 1.2.6.2 skrll }
1139 1.2.6.2 skrll
1140 1.2.6.2 skrll
1141 1.2.6.2 skrll dmabuf = dd->dmabase;
1142 1.2.6.2 skrll dmabase = sc->sc_dmabase;
1143 1.2.6.2 skrll td = 0;
1144 1.2.6.2 skrll
1145 1.2.6.2 skrll for (i = 0; i < (num-1); i++) {
1146 1.2.6.2 skrll
1147 1.2.6.2 skrll sc->sc_dma->desc[i].flags = TX_BCNT(blksz)
1148 1.2.6.2 skrll | TX_EOF | TX_BINT;
1149 1.2.6.2 skrll sc->sc_dma->desc[i].ba = dmabuf;
1150 1.2.6.2 skrll sc->sc_dma->desc[i].nda = dmabase + dbri_dma_off(desc, i + 1);
1151 1.2.6.2 skrll sc->sc_dma->desc[i].status = 0;
1152 1.2.6.2 skrll
1153 1.2.6.2 skrll td_last = td;
1154 1.2.6.2 skrll dmabuf += blksz;
1155 1.2.6.2 skrll }
1156 1.2.6.2 skrll
1157 1.2.6.2 skrll sc->sc_dma->desc[i].flags = TX_BCNT(blksz) | TX_EOF | TX_BINT;
1158 1.2.6.2 skrll sc->sc_dma->desc[i].ba = dmabuf;
1159 1.2.6.2 skrll sc->sc_dma->desc[i].nda = dmabase + dbri_dma_off(desc, 0);
1160 1.2.6.2 skrll sc->sc_dma->desc[i].status = 0;
1161 1.2.6.2 skrll
1162 1.2.6.2 skrll dd->callback = callback; //sc->intr;
1163 1.2.6.2 skrll dd->callback_args = callback_args; //sc->intrarg;
1164 1.2.6.2 skrll
1165 1.2.6.2 skrll x = splaudio();
1166 1.2.6.2 skrll
1167 1.2.6.2 skrll /* the pipe shouldn't be active */
1168 1.2.6.2 skrll if (pipe_active(sc, pipe)) {
1169 1.2.6.2 skrll printf("pipe active (CDP)\n");
1170 1.2.6.2 skrll /* pipe is already active */
1171 1.2.6.2 skrll #if 0
1172 1.2.6.2 skrll td_last = sc->sc_pipe[pipe].desc;
1173 1.2.6.2 skrll while (sc->sc_desc[td_last].next != -1)
1174 1.2.6.2 skrll td_last = sc->sc_desc[td_last].next;
1175 1.2.6.2 skrll
1176 1.2.6.2 skrll sc->sc_desc[td_last].next = td_first;
1177 1.2.6.2 skrll sc->sc_dma->desc[td_last].nda =
1178 1.2.6.2 skrll sc->sc_dmabase + dbri_dma_off(desc, td_first);
1179 1.2.6.2 skrll
1180 1.2.6.2 skrll cmd = dbri_command_lock(sc);
1181 1.2.6.2 skrll *(cmd++) = DBRI_CMD(DBRI_COMMAND_CDP, 0, pipe);
1182 1.2.6.2 skrll dbri_command_send(sc, cmd);
1183 1.2.6.2 skrll #endif
1184 1.2.6.2 skrll } else {
1185 1.2.6.2 skrll /*
1186 1.2.6.2 skrll * pipe isn't active - issue an SDP command to start our
1187 1.2.6.2 skrll * chain of TDs running
1188 1.2.6.2 skrll */
1189 1.2.6.2 skrll sc->sc_pipe[pipe].desc = which;
1190 1.2.6.2 skrll cmd = dbri_command_lock(sc);
1191 1.2.6.2 skrll *(cmd++) = DBRI_CMD(DBRI_COMMAND_SDP, 0,
1192 1.2.6.2 skrll sc->sc_pipe[pipe].sdp |
1193 1.2.6.2 skrll DBRI_SDP_VALID_POINTER |
1194 1.2.6.2 skrll DBRI_SDP_EVERY |
1195 1.2.6.2 skrll DBRI_SDP_CLEAR);
1196 1.2.6.2 skrll *(cmd++) = sc->sc_dmabase + dbri_dma_off(desc, 0);
1197 1.2.6.2 skrll dbri_command_send(sc, cmd);
1198 1.2.6.2 skrll }
1199 1.2.6.2 skrll
1200 1.2.6.2 skrll splx(x);
1201 1.2.6.2 skrll
1202 1.2.6.2 skrll return;
1203 1.2.6.2 skrll }
1204 1.2.6.2 skrll
1205 1.2.6.2 skrll void
1206 1.2.6.2 skrll pipe_ts_link(struct dbri_softc *sc, int pipe, enum io dir, int basepipe,
1207 1.2.6.2 skrll int len, int cycle)
1208 1.2.6.2 skrll {
1209 1.2.6.2 skrll volatile u_int32_t *cmd;
1210 1.2.6.2 skrll int prevpipe, nextpipe;
1211 1.2.6.2 skrll int val;
1212 1.2.6.2 skrll
1213 1.2.6.2 skrll if (pipe < 0 || pipe >= DBRI_PIPE_MAX ||
1214 1.2.6.2 skrll basepipe < 0 || basepipe >= DBRI_PIPE_MAX) {
1215 1.2.6.2 skrll printf("%s: illegal pipe numbers (%d, %d)\n",
1216 1.2.6.2 skrll sc->sc_dev.dv_xname, pipe, basepipe);
1217 1.2.6.2 skrll return;
1218 1.2.6.2 skrll }
1219 1.2.6.2 skrll
1220 1.2.6.2 skrll if (sc->sc_pipe[pipe].sdp == 0 || sc->sc_pipe[basepipe].sdp == 0) {
1221 1.2.6.2 skrll printf("%s: uninitialized pipe (%d, %d)\n",
1222 1.2.6.2 skrll sc->sc_dev.dv_xname, pipe, basepipe);
1223 1.2.6.2 skrll return;
1224 1.2.6.2 skrll }
1225 1.2.6.2 skrll
1226 1.2.6.2 skrll if (basepipe == 16 && dir == PIPEoutput && cycle == 0)
1227 1.2.6.2 skrll cycle = sc->sc_chi_bpf;
1228 1.2.6.2 skrll
1229 1.2.6.2 skrll if (basepipe == pipe)
1230 1.2.6.2 skrll prevpipe = nextpipe = pipe;
1231 1.2.6.2 skrll else {
1232 1.2.6.2 skrll if (basepipe == 16) {
1233 1.2.6.2 skrll if (dir == PIPEinput) {
1234 1.2.6.2 skrll prevpipe = sc->sc_chi_pipe_in;
1235 1.2.6.2 skrll } else {
1236 1.2.6.2 skrll prevpipe = sc->sc_chi_pipe_out;
1237 1.2.6.2 skrll }
1238 1.2.6.2 skrll } else
1239 1.2.6.2 skrll prevpipe = basepipe;
1240 1.2.6.2 skrll
1241 1.2.6.2 skrll nextpipe = sc->sc_pipe[prevpipe].next;
1242 1.2.6.2 skrll
1243 1.2.6.2 skrll while (sc->sc_pipe[nextpipe].cycle < cycle &&
1244 1.2.6.2 skrll sc->sc_pipe[nextpipe].next != basepipe) {
1245 1.2.6.2 skrll prevpipe = nextpipe;
1246 1.2.6.2 skrll nextpipe = sc->sc_pipe[nextpipe].next;
1247 1.2.6.2 skrll }
1248 1.2.6.2 skrll }
1249 1.2.6.2 skrll
1250 1.2.6.2 skrll if (prevpipe == 16) {
1251 1.2.6.2 skrll if (dir == PIPEinput) {
1252 1.2.6.2 skrll sc->sc_chi_pipe_in = pipe;
1253 1.2.6.2 skrll } else {
1254 1.2.6.2 skrll sc->sc_chi_pipe_out = pipe;
1255 1.2.6.2 skrll }
1256 1.2.6.2 skrll } else
1257 1.2.6.2 skrll sc->sc_pipe[prevpipe].next = pipe;
1258 1.2.6.2 skrll
1259 1.2.6.2 skrll sc->sc_pipe[pipe].next = nextpipe;
1260 1.2.6.2 skrll sc->sc_pipe[pipe].cycle = cycle;
1261 1.2.6.2 skrll sc->sc_pipe[pipe].length = len;
1262 1.2.6.2 skrll
1263 1.2.6.2 skrll cmd = dbri_command_lock(sc);
1264 1.2.6.2 skrll
1265 1.2.6.2 skrll switch (dir) {
1266 1.2.6.2 skrll case PIPEinput:
1267 1.2.6.2 skrll val = DBRI_DTS_VI | DBRI_DTS_INS | DBRI_DTS_PRVIN(prevpipe);
1268 1.2.6.2 skrll val |= pipe;
1269 1.2.6.2 skrll *(cmd++) = DBRI_CMD(DBRI_COMMAND_DTS, 0, val);
1270 1.2.6.2 skrll *(cmd++) = DBRI_TS_LEN(len) | DBRI_TS_CYCLE(cycle) |
1271 1.2.6.2 skrll DBRI_TS_NEXT(nextpipe);
1272 1.2.6.2 skrll *(cmd++) = 0;
1273 1.2.6.2 skrll break;
1274 1.2.6.2 skrll case PIPEoutput:
1275 1.2.6.2 skrll val = DBRI_DTS_VO | DBRI_DTS_INS | DBRI_DTS_PRVOUT(prevpipe);
1276 1.2.6.2 skrll val |= pipe;
1277 1.2.6.2 skrll *(cmd++) = DBRI_CMD(DBRI_COMMAND_DTS, 0, val);
1278 1.2.6.2 skrll *(cmd++) = 0;
1279 1.2.6.2 skrll *(cmd++) = DBRI_TS_LEN(len) | DBRI_TS_CYCLE(cycle) |
1280 1.2.6.2 skrll DBRI_TS_NEXT(nextpipe);
1281 1.2.6.2 skrll break;
1282 1.2.6.2 skrll default:
1283 1.2.6.2 skrll printf("%s: should not have happened!\n",
1284 1.2.6.2 skrll sc->sc_dev.dv_xname);
1285 1.2.6.2 skrll break;
1286 1.2.6.2 skrll }
1287 1.2.6.2 skrll
1288 1.2.6.2 skrll dbri_command_send(sc, cmd);
1289 1.2.6.2 skrll
1290 1.2.6.2 skrll return;
1291 1.2.6.2 skrll }
1292 1.2.6.2 skrll
1293 1.2.6.2 skrll int
1294 1.2.6.2 skrll pipe_active(struct dbri_softc *sc, int pipe)
1295 1.2.6.2 skrll {
1296 1.2.6.2 skrll
1297 1.2.6.2 skrll return (sc->sc_pipe[pipe].desc != -1);
1298 1.2.6.2 skrll }
1299 1.2.6.2 skrll
1300 1.2.6.2 skrll /*
1301 1.2.6.2 skrll * subroutines required to interface with audio(9)
1302 1.2.6.2 skrll */
1303 1.2.6.2 skrll
1304 1.2.6.2 skrll int
1305 1.2.6.2 skrll dbri_query_encoding(void *hdl, struct audio_encoding *ae)
1306 1.2.6.2 skrll {
1307 1.2.6.2 skrll
1308 1.2.6.2 skrll /* XXX we shouldn't claim we support LE samples */
1309 1.2.6.2 skrll switch (ae->index) {
1310 1.2.6.2 skrll case 0:
1311 1.2.6.2 skrll strcpy(ae->name, AudioEulinear);
1312 1.2.6.2 skrll ae->encoding = AUDIO_ENCODING_ULINEAR;
1313 1.2.6.2 skrll ae->precision = 8;
1314 1.2.6.2 skrll ae->flags = AUDIO_ENCODINGFLAG_EMULATED;
1315 1.2.6.2 skrll break;
1316 1.2.6.2 skrll case 1:
1317 1.2.6.2 skrll strcpy(ae->name, AudioEmulaw);
1318 1.2.6.2 skrll ae->encoding = AUDIO_ENCODING_ULAW;
1319 1.2.6.2 skrll ae->precision = 8;
1320 1.2.6.2 skrll ae->flags = 0;
1321 1.2.6.2 skrll break;
1322 1.2.6.2 skrll case 2:
1323 1.2.6.2 skrll strcpy(ae->name, AudioEalaw);
1324 1.2.6.2 skrll ae->encoding = AUDIO_ENCODING_ALAW;
1325 1.2.6.2 skrll ae->precision = 8;
1326 1.2.6.2 skrll ae->flags = 0;
1327 1.2.6.2 skrll break;
1328 1.2.6.2 skrll case 3:
1329 1.2.6.2 skrll strcpy(ae->name, AudioEslinear);
1330 1.2.6.2 skrll ae->encoding = AUDIO_ENCODING_SLINEAR;
1331 1.2.6.2 skrll ae->precision = 8;
1332 1.2.6.2 skrll ae->flags = AUDIO_ENCODINGFLAG_EMULATED;
1333 1.2.6.2 skrll break;
1334 1.2.6.2 skrll case 4:
1335 1.2.6.2 skrll strcpy(ae->name, AudioEslinear_le);
1336 1.2.6.2 skrll ae->encoding = AUDIO_ENCODING_SLINEAR_LE;
1337 1.2.6.2 skrll ae->precision = 16;
1338 1.2.6.2 skrll ae->flags = AUDIO_ENCODINGFLAG_EMULATED;
1339 1.2.6.2 skrll break;
1340 1.2.6.2 skrll case 5:
1341 1.2.6.2 skrll strcpy(ae->name, AudioEulinear_le);
1342 1.2.6.2 skrll ae->encoding = AUDIO_ENCODING_ULINEAR_LE;
1343 1.2.6.2 skrll ae->precision = 16;
1344 1.2.6.2 skrll ae->flags = AUDIO_ENCODINGFLAG_EMULATED;
1345 1.2.6.2 skrll break;
1346 1.2.6.2 skrll case 6:
1347 1.2.6.2 skrll strcpy(ae->name, AudioEslinear_be);
1348 1.2.6.2 skrll ae->encoding = AUDIO_ENCODING_SLINEAR_BE;
1349 1.2.6.2 skrll ae->precision = 16;
1350 1.2.6.2 skrll ae->flags = 0;
1351 1.2.6.2 skrll break;
1352 1.2.6.2 skrll case 7:
1353 1.2.6.2 skrll strcpy(ae->name, AudioEulinear_be);
1354 1.2.6.2 skrll ae->encoding = AUDIO_ENCODING_ULINEAR_BE;
1355 1.2.6.2 skrll ae->precision = 16;
1356 1.2.6.2 skrll ae->flags = 0;
1357 1.2.6.2 skrll break;
1358 1.2.6.2 skrll default:
1359 1.2.6.2 skrll return (EINVAL);
1360 1.2.6.2 skrll }
1361 1.2.6.2 skrll
1362 1.2.6.2 skrll return (0);
1363 1.2.6.2 skrll }
1364 1.2.6.2 skrll
1365 1.2.6.2 skrll /*
1366 1.2.6.2 skrll * XXX: recording isn't supported - jmcneill
1367 1.2.6.2 skrll */
1368 1.2.6.2 skrll int
1369 1.2.6.2 skrll dbri_set_params(void *hdl, int setmode, int usemode,
1370 1.2.6.2 skrll struct audio_params *play, struct audio_params *rec,
1371 1.2.6.2 skrll stream_filter_list_t *pfil, stream_filter_list_t *rfil)
1372 1.2.6.2 skrll {
1373 1.2.6.2 skrll struct dbri_softc *sc = hdl;
1374 1.2.6.2 skrll int i;
1375 1.2.6.2 skrll
1376 1.2.6.2 skrll if ((play->precision != 8 && play->precision != 16) ||
1377 1.2.6.2 skrll (play->channels != 1 && play->channels != 2))
1378 1.2.6.2 skrll return (EINVAL);
1379 1.2.6.2 skrll
1380 1.2.6.2 skrll for (i = 0; CS4215_FREQ[i].freq; i++)
1381 1.2.6.2 skrll if (CS4215_FREQ[i].freq == play->sample_rate)
1382 1.2.6.2 skrll break;
1383 1.2.6.2 skrll
1384 1.2.6.2 skrll if (CS4215_FREQ[i].freq == 0)
1385 1.2.6.2 skrll return (EINVAL);
1386 1.2.6.2 skrll
1387 1.2.6.2 skrll /* set frequency */
1388 1.2.6.2 skrll sc->sc_mm.control[1] &= ~0x38;
1389 1.2.6.2 skrll sc->sc_mm.control[1] |= CS4215_FREQ[i].csval;
1390 1.2.6.2 skrll sc->sc_mm.control[2] &= ~0x70;
1391 1.2.6.2 skrll sc->sc_mm.control[2] |= CS4215_FREQ[i].xtal;
1392 1.2.6.2 skrll
1393 1.2.6.2 skrll /*play->factor = 1;
1394 1.2.6.2 skrll play->sw_code = NULL;*/
1395 1.2.6.2 skrll
1396 1.2.6.2 skrll switch (play->encoding) {
1397 1.2.6.2 skrll case AUDIO_ENCODING_ULAW:
1398 1.2.6.2 skrll sc->sc_mm.control[1] &= ~3;
1399 1.2.6.2 skrll sc->sc_mm.control[1] |= CS4215_DFR_ULAW;
1400 1.2.6.2 skrll break;
1401 1.2.6.2 skrll case AUDIO_ENCODING_ALAW:
1402 1.2.6.2 skrll sc->sc_mm.control[1] &= ~3;
1403 1.2.6.2 skrll sc->sc_mm.control[1] |= CS4215_DFR_ALAW;
1404 1.2.6.2 skrll break;
1405 1.2.6.2 skrll case AUDIO_ENCODING_SLINEAR_LE:
1406 1.2.6.2 skrll case AUDIO_ENCODING_ULINEAR_LE:
1407 1.2.6.2 skrll if (play->precision == 16) {
1408 1.2.6.2 skrll /* XXX this surely needs some changes elsewhere */
1409 1.2.6.2 skrll /*play->sw_code = swap_bytes;*/
1410 1.2.6.2 skrll sc->sc_mm.control[1] &= ~3;
1411 1.2.6.2 skrll sc->sc_mm.control[1] |= CS4215_DFR_LINEAR16;
1412 1.2.6.2 skrll }
1413 1.2.6.2 skrll break;
1414 1.2.6.2 skrll case AUDIO_ENCODING_ULINEAR:
1415 1.2.6.2 skrll case AUDIO_ENCODING_SLINEAR:
1416 1.2.6.2 skrll sc->sc_mm.control[1] &= ~3;
1417 1.2.6.2 skrll if (play->precision == 8) {
1418 1.2.6.2 skrll sc->sc_mm.control[1] |= CS4215_DFR_LINEAR8;
1419 1.2.6.2 skrll } else {
1420 1.2.6.2 skrll sc->sc_mm.control[1] |= CS4215_DFR_LINEAR16;
1421 1.2.6.2 skrll }
1422 1.2.6.2 skrll break;
1423 1.2.6.2 skrll case AUDIO_ENCODING_ULINEAR_BE:
1424 1.2.6.2 skrll case AUDIO_ENCODING_SLINEAR_BE:
1425 1.2.6.2 skrll sc->sc_mm.control[1] &= ~3;
1426 1.2.6.2 skrll sc->sc_mm.control[1] |= CS4215_DFR_LINEAR16;
1427 1.2.6.2 skrll break;
1428 1.2.6.2 skrll }
1429 1.2.6.2 skrll
1430 1.2.6.2 skrll switch (play->channels) {
1431 1.2.6.2 skrll case 1:
1432 1.2.6.2 skrll sc->sc_mm.control[1] &= ~CS4215_DFR_STEREO;
1433 1.2.6.2 skrll break;
1434 1.2.6.2 skrll case 2:
1435 1.2.6.2 skrll sc->sc_mm.control[1] |= CS4215_DFR_STEREO;
1436 1.2.6.2 skrll break;
1437 1.2.6.2 skrll }
1438 1.2.6.2 skrll
1439 1.2.6.2 skrll return (0);
1440 1.2.6.2 skrll }
1441 1.2.6.2 skrll
1442 1.2.6.2 skrll int
1443 1.2.6.2 skrll dbri_round_blocksize(void *hdl, int bs, int mode,
1444 1.2.6.2 skrll const audio_params_t *param)
1445 1.2.6.2 skrll {
1446 1.2.6.2 skrll
1447 1.2.6.2 skrll /* DBRI DMA segment size, rounded town to 32bit alignment */
1448 1.2.6.2 skrll return 0x1ffc;
1449 1.2.6.2 skrll }
1450 1.2.6.2 skrll
1451 1.2.6.2 skrll int
1452 1.2.6.2 skrll dbri_halt_output(void *hdl)
1453 1.2.6.2 skrll {
1454 1.2.6.2 skrll struct dbri_softc *sc = hdl;
1455 1.2.6.2 skrll
1456 1.2.6.2 skrll pipe_reset(sc, 4);
1457 1.2.6.2 skrll
1458 1.2.6.2 skrll return (0);
1459 1.2.6.2 skrll }
1460 1.2.6.2 skrll
1461 1.2.6.2 skrll int
1462 1.2.6.2 skrll dbri_getdev(void *hdl, struct audio_device *ret)
1463 1.2.6.2 skrll {
1464 1.2.6.2 skrll
1465 1.2.6.2 skrll *ret = dbri_device;
1466 1.2.6.2 skrll return (0);
1467 1.2.6.2 skrll }
1468 1.2.6.2 skrll
1469 1.2.6.2 skrll int
1470 1.2.6.2 skrll dbri_set_port(void *hdl, mixer_ctrl_t *mc)
1471 1.2.6.2 skrll {
1472 1.2.6.2 skrll struct dbri_softc *sc = hdl;
1473 1.2.6.2 skrll int latt = sc->sc_latt, ratt = sc->sc_ratt;
1474 1.2.6.2 skrll
1475 1.2.6.2 skrll switch (mc->dev) {
1476 1.2.6.2 skrll case DBRI_VOL_OUTPUT: /* master volume */
1477 1.2.6.2 skrll latt = (latt & 0xc0) | (63 -
1478 1.2.6.2 skrll min(mc->un.value.level[AUDIO_MIXER_LEVEL_LEFT] >> 2, 63));
1479 1.2.6.2 skrll ratt = (ratt & 0xc0) | (63 -
1480 1.2.6.2 skrll min(mc->un.value.level[AUDIO_MIXER_LEVEL_RIGHT] >> 2, 63));
1481 1.2.6.2 skrll break;
1482 1.2.6.2 skrll case DBRI_ENABLE_MONO: /* built-in speaker */
1483 1.2.6.2 skrll if (mc->un.ord == 1) {
1484 1.2.6.2 skrll ratt |= CS4215_SE;
1485 1.2.6.2 skrll } else
1486 1.2.6.2 skrll ratt &= ~CS4215_SE;
1487 1.2.6.2 skrll break;
1488 1.2.6.2 skrll case DBRI_ENABLE_HEADPHONE: /* headphones output */
1489 1.2.6.2 skrll if (mc->un.ord == 1) {
1490 1.2.6.2 skrll latt |= CS4215_HE;
1491 1.2.6.2 skrll } else
1492 1.2.6.2 skrll latt &= ~CS4215_HE;
1493 1.2.6.2 skrll break;
1494 1.2.6.2 skrll case DBRI_ENABLE_LINE: /* line out */
1495 1.2.6.2 skrll if (mc->un.ord == 1) {
1496 1.2.6.2 skrll latt |= CS4215_LE;
1497 1.2.6.2 skrll } else
1498 1.2.6.2 skrll latt &= ~CS4215_LE;
1499 1.2.6.2 skrll break;
1500 1.2.6.2 skrll }
1501 1.2.6.2 skrll
1502 1.2.6.2 skrll sc->sc_latt = latt;
1503 1.2.6.2 skrll sc->sc_ratt = ratt;
1504 1.2.6.2 skrll
1505 1.2.6.2 skrll /* no need to do that here - mmcodec_setgain does it anyway */
1506 1.2.6.2 skrll /*pipe_transmit_fixed(sc, 20, *(int *)__UNVOLATILE(sc->sc_mm.data));*/
1507 1.2.6.2 skrll
1508 1.2.6.2 skrll mmcodec_setgain(sc, 0);
1509 1.2.6.2 skrll
1510 1.2.6.2 skrll return (0);
1511 1.2.6.2 skrll }
1512 1.2.6.2 skrll
1513 1.2.6.2 skrll int
1514 1.2.6.2 skrll dbri_get_port(void *hdl, mixer_ctrl_t *mc)
1515 1.2.6.2 skrll {
1516 1.2.6.2 skrll struct dbri_softc *sc = hdl;
1517 1.2.6.2 skrll
1518 1.2.6.2 skrll switch (mc->dev) {
1519 1.2.6.2 skrll case DBRI_VOL_OUTPUT: /* master volume */
1520 1.2.6.2 skrll mc->un.value.level[AUDIO_MIXER_LEVEL_LEFT] =
1521 1.2.6.2 skrll (63 - (sc->sc_latt & 0x3f)) << 2;
1522 1.2.6.2 skrll mc->un.value.level[AUDIO_MIXER_LEVEL_RIGHT] =
1523 1.2.6.2 skrll (63 - (sc->sc_ratt & 0x3f)) << 2;
1524 1.2.6.2 skrll return (0);
1525 1.2.6.2 skrll case DBRI_ENABLE_MONO: /* built-in speaker */
1526 1.2.6.2 skrll mc->un.ord = (sc->sc_ratt & CS4215_SE) ? 1 : 0;
1527 1.2.6.2 skrll return 0;
1528 1.2.6.2 skrll case DBRI_ENABLE_HEADPHONE: /* headphones output */
1529 1.2.6.2 skrll mc->un.ord = (sc->sc_latt & CS4215_HE) ? 1 : 0;
1530 1.2.6.2 skrll return 0;
1531 1.2.6.2 skrll case DBRI_ENABLE_LINE: /* line out */
1532 1.2.6.2 skrll mc->un.ord = (sc->sc_latt & CS4215_LE) ? 1 : 0;
1533 1.2.6.2 skrll return 0;
1534 1.2.6.2 skrll }
1535 1.2.6.2 skrll return (EINVAL);
1536 1.2.6.2 skrll }
1537 1.2.6.2 skrll
1538 1.2.6.2 skrll int
1539 1.2.6.2 skrll dbri_query_devinfo(void *hdl, mixer_devinfo_t *di)
1540 1.2.6.2 skrll {
1541 1.2.6.2 skrll
1542 1.2.6.2 skrll switch (di->index) {
1543 1.2.6.2 skrll case DBRI_MONITOR_CLASS:
1544 1.2.6.2 skrll di->mixer_class = DBRI_MONITOR_CLASS;
1545 1.2.6.2 skrll strcpy(di->label.name, AudioCmonitor);
1546 1.2.6.2 skrll di->type = AUDIO_MIXER_CLASS;
1547 1.2.6.2 skrll di->next = di->prev = AUDIO_MIXER_LAST;
1548 1.2.6.2 skrll return 0;
1549 1.2.6.2 skrll case DBRI_VOL_OUTPUT: /* master volume */
1550 1.2.6.2 skrll di->mixer_class = DBRI_MONITOR_CLASS;
1551 1.2.6.2 skrll di->next = di->prev = AUDIO_MIXER_LAST;
1552 1.2.6.2 skrll strcpy(di->label.name, AudioNmaster);
1553 1.2.6.2 skrll di->type = AUDIO_MIXER_VALUE;
1554 1.2.6.2 skrll di->un.v.num_channels = 2;
1555 1.2.6.2 skrll strcpy(di->un.v.units.name, AudioNvolume);
1556 1.2.6.2 skrll return (0);
1557 1.2.6.2 skrll case DBRI_ENABLE_MONO: /* built-in speaker */
1558 1.2.6.2 skrll di->mixer_class = DBRI_MONITOR_CLASS;
1559 1.2.6.2 skrll di->next = di->prev = AUDIO_MIXER_LAST;
1560 1.2.6.2 skrll strcpy(di->label.name, AudioNmono);
1561 1.2.6.2 skrll di->type = AUDIO_MIXER_ENUM;
1562 1.2.6.2 skrll di->un.e.num_mem = 2;
1563 1.2.6.2 skrll strcpy(di->un.e.member[0].label.name, AudioNoff);
1564 1.2.6.2 skrll di->un.e.member[0].ord = 0;
1565 1.2.6.2 skrll strcpy(di->un.e.member[1].label.name, AudioNon);
1566 1.2.6.2 skrll di->un.e.member[1].ord = 1;
1567 1.2.6.2 skrll return (0);
1568 1.2.6.2 skrll case DBRI_ENABLE_HEADPHONE: /* headphones output */
1569 1.2.6.2 skrll di->mixer_class = DBRI_MONITOR_CLASS;
1570 1.2.6.2 skrll di->next = di->prev = AUDIO_MIXER_LAST;
1571 1.2.6.2 skrll strcpy(di->label.name, AudioNheadphone);
1572 1.2.6.2 skrll di->type = AUDIO_MIXER_ENUM;
1573 1.2.6.2 skrll di->un.e.num_mem = 2;
1574 1.2.6.2 skrll strcpy(di->un.e.member[0].label.name, AudioNoff);
1575 1.2.6.2 skrll di->un.e.member[0].ord = 0;
1576 1.2.6.2 skrll strcpy(di->un.e.member[1].label.name, AudioNon);
1577 1.2.6.2 skrll di->un.e.member[1].ord = 1;
1578 1.2.6.2 skrll return (0);
1579 1.2.6.2 skrll case DBRI_ENABLE_LINE: /* line out */
1580 1.2.6.2 skrll di->mixer_class = DBRI_MONITOR_CLASS;
1581 1.2.6.2 skrll di->next = di->prev = AUDIO_MIXER_LAST;
1582 1.2.6.2 skrll strcpy(di->label.name, AudioNline);
1583 1.2.6.2 skrll di->type = AUDIO_MIXER_ENUM;
1584 1.2.6.2 skrll di->un.e.num_mem = 2;
1585 1.2.6.2 skrll strcpy(di->un.e.member[0].label.name, AudioNoff);
1586 1.2.6.2 skrll di->un.e.member[0].ord = 0;
1587 1.2.6.2 skrll strcpy(di->un.e.member[1].label.name, AudioNon);
1588 1.2.6.2 skrll di->un.e.member[1].ord = 1;
1589 1.2.6.2 skrll return (0);
1590 1.2.6.2 skrll }
1591 1.2.6.2 skrll
1592 1.2.6.2 skrll return (ENXIO);
1593 1.2.6.2 skrll }
1594 1.2.6.2 skrll
1595 1.2.6.2 skrll size_t
1596 1.2.6.2 skrll dbri_round_buffersize(void *hdl, int dir, size_t bufsize)
1597 1.2.6.2 skrll {
1598 1.2.6.2 skrll #ifdef DBRI_BIG_BUFFER
1599 1.2.6.2 skrll return 16*0x1ffc; /* use ~128KB buffer */
1600 1.2.6.2 skrll #else
1601 1.2.6.2 skrll return bufsize;
1602 1.2.6.2 skrll #endif
1603 1.2.6.2 skrll }
1604 1.2.6.2 skrll
1605 1.2.6.2 skrll int
1606 1.2.6.2 skrll dbri_get_props(void *hdl)
1607 1.2.6.2 skrll {
1608 1.2.6.2 skrll
1609 1.2.6.2 skrll return (AUDIO_PROP_MMAP/* | AUDIO_PROP_INDEPENDENT*/);
1610 1.2.6.2 skrll //return (0);
1611 1.2.6.2 skrll }
1612 1.2.6.2 skrll
1613 1.2.6.2 skrll int
1614 1.2.6.2 skrll dbri_trigger_output(void *hdl, void *start, void *end, int blksize,
1615 1.2.6.2 skrll void (*intr)(void *), void *intrarg,
1616 1.2.6.2 skrll const struct audio_params *param)
1617 1.2.6.2 skrll {
1618 1.2.6.2 skrll struct dbri_softc *sc = hdl;
1619 1.2.6.2 skrll unsigned long count, current, num;
1620 1.2.6.2 skrll
1621 1.2.6.2 skrll count = (unsigned long)(((caddr_t)end - (caddr_t)start));
1622 1.2.6.2 skrll num = count / blksize;
1623 1.2.6.2 skrll #ifdef DBRI_DEBUG
1624 1.2.6.2 skrll printf("trigger_output(%lx %lx) : %d %ld %ld\n",
1625 1.2.6.2 skrll (unsigned long)intr,
1626 1.2.6.2 skrll (unsigned long)intrarg, blksize, count, num);
1627 1.2.6.2 skrll #endif
1628 1.2.6.2 skrll sc->sc_params = *param;
1629 1.2.6.2 skrll
1630 1.2.6.2 skrll mmcodec_setcontrol(sc);
1631 1.2.6.2 skrll mmcodec_init_data(sc);
1632 1.2.6.2 skrll current = 0;
1633 1.2.6.2 skrll while ((current < sc->sc_desc_used) &&
1634 1.2.6.2 skrll (sc->sc_desc[current].buf != start))
1635 1.2.6.2 skrll current++;
1636 1.2.6.2 skrll
1637 1.2.6.2 skrll if (current < sc->sc_desc_used) {
1638 1.2.6.2 skrll setup_ring(sc, 4, current, num, blksize, intr, intrarg);
1639 1.2.6.2 skrll return 0;
1640 1.2.6.2 skrll }
1641 1.2.6.2 skrll return EINVAL;
1642 1.2.6.2 skrll }
1643 1.2.6.2 skrll
1644 1.2.6.2 skrll u_int32_t
1645 1.2.6.2 skrll reverse_bytes(u_int32_t b, int len)
1646 1.2.6.2 skrll {
1647 1.2.6.2 skrll switch (len) {
1648 1.2.6.2 skrll case 32:
1649 1.2.6.2 skrll b = ((b & 0xffff0000) >> 16) | ((b & 0x0000ffff) << 16);
1650 1.2.6.2 skrll case 16:
1651 1.2.6.2 skrll b = ((b & 0xff00ff00) >> 8) | ((b & 0x00ff00ff) << 8);
1652 1.2.6.2 skrll case 8:
1653 1.2.6.2 skrll b = ((b & 0xf0f0f0f0) >> 4) | ((b & 0x0f0f0f0f) << 4);
1654 1.2.6.2 skrll case 4:
1655 1.2.6.2 skrll b = ((b & 0xcccccccc) >> 2) | ((b & 0x33333333) << 2);
1656 1.2.6.2 skrll case 2:
1657 1.2.6.2 skrll b = ((b & 0xaaaaaaaa) >> 1) | ((b & 0x55555555) << 1);
1658 1.2.6.2 skrll case 1:
1659 1.2.6.2 skrll case 0:
1660 1.2.6.2 skrll break;
1661 1.2.6.2 skrll default:
1662 1.2.6.2 skrll printf("reverse_bytes: unsupported length\n");
1663 1.2.6.2 skrll };
1664 1.2.6.2 skrll
1665 1.2.6.2 skrll return (b);
1666 1.2.6.2 skrll }
1667 1.2.6.2 skrll
1668 1.2.6.2 skrll static void
1669 1.2.6.2 skrll *dbri_malloc(void *v, int dir, size_t s, struct malloc_type *mt, int flags)
1670 1.2.6.2 skrll {
1671 1.2.6.2 skrll struct dbri_softc *sc = v;
1672 1.2.6.2 skrll struct dbri_desc *dd = &sc->sc_desc[sc->sc_desc_used];
1673 1.2.6.2 skrll int rseg;
1674 1.2.6.2 skrll
1675 1.2.6.2 skrll if (bus_dmamap_create(sc->sc_dmat, s, 1, s, 0, BUS_DMA_NOWAIT,
1676 1.2.6.2 skrll &dd->dmamap) == 0) {
1677 1.2.6.2 skrll if (bus_dmamem_alloc(sc->sc_dmat, s, 0, 0, &dd->dmaseg,
1678 1.2.6.2 skrll 1, &rseg, BUS_DMA_NOWAIT) == 0) {
1679 1.2.6.2 skrll if (bus_dmamem_map(sc->sc_dmat, &dd->dmaseg, rseg, s,
1680 1.2.6.2 skrll &dd->buf, BUS_DMA_NOWAIT|BUS_DMA_COHERENT) == 0) {
1681 1.2.6.2 skrll if (dd->buf!=NULL) {
1682 1.2.6.2 skrll if (bus_dmamap_load(sc->sc_dmat,
1683 1.2.6.2 skrll dd->dmamap, dd->buf, s, NULL,
1684 1.2.6.2 skrll BUS_DMA_NOWAIT) == 0) {
1685 1.2.6.2 skrll dd->len = s;
1686 1.2.6.2 skrll dd->busy = 0;
1687 1.2.6.2 skrll dd->callback = NULL;
1688 1.2.6.2 skrll dd->dmabase =
1689 1.2.6.2 skrll dd->dmamap->dm_segs[0].ds_addr;
1690 1.2.6.2 skrll #ifdef DBRI_DEBUG
1691 1.2.6.2 skrll printf("dbri_malloc: using buffer %d\n",
1692 1.2.6.2 skrll sc->sc_desc_used);
1693 1.2.6.2 skrll #endif
1694 1.2.6.2 skrll sc->sc_desc_used++;
1695 1.2.6.2 skrll return dd->buf;
1696 1.2.6.2 skrll } else
1697 1.2.6.2 skrll printf("dbri_malloc: load failed\n");
1698 1.2.6.2 skrll } else
1699 1.2.6.2 skrll printf("dbri_malloc: map returned NULL\n");
1700 1.2.6.2 skrll } else
1701 1.2.6.2 skrll printf("dbri_malloc: map failed\n");
1702 1.2.6.2 skrll bus_dmamem_free(sc->sc_dmat, &dd->dmaseg, rseg);
1703 1.2.6.2 skrll } else
1704 1.2.6.2 skrll printf("dbri_malloc: malloc() failed\n");
1705 1.2.6.2 skrll bus_dmamap_destroy(sc->sc_dmat, dd->dmamap);
1706 1.2.6.2 skrll } else
1707 1.2.6.2 skrll printf("dbri_malloc: bus_dmamap_create() failed\n");
1708 1.2.6.2 skrll return NULL;
1709 1.2.6.2 skrll }
1710 1.2.6.2 skrll
1711 1.2.6.2 skrll static void
1712 1.2.6.2 skrll dbri_free(void *v, void *p, struct malloc_type *mt)
1713 1.2.6.2 skrll {
1714 1.2.6.2 skrll free(p, mt);
1715 1.2.6.2 skrll }
1716 1.2.6.2 skrll
1717 1.2.6.2 skrll static paddr_t
1718 1.2.6.2 skrll dbri_mappage(void *v, void *mem, off_t off, int prot)
1719 1.2.6.2 skrll {
1720 1.2.6.2 skrll struct dbri_softc *sc = v;;
1721 1.2.6.2 skrll int current;
1722 1.2.6.2 skrll
1723 1.2.6.2 skrll if (off < 0)
1724 1.2.6.2 skrll return -1;
1725 1.2.6.2 skrll
1726 1.2.6.2 skrll current = 0;
1727 1.2.6.2 skrll while ((current < sc->sc_desc_used) &&
1728 1.2.6.2 skrll (sc->sc_desc[current].buf != mem))
1729 1.2.6.2 skrll current++;
1730 1.2.6.2 skrll
1731 1.2.6.2 skrll if (current < sc->sc_desc_used) {
1732 1.2.6.2 skrll return bus_dmamem_mmap(sc->sc_dmat,
1733 1.2.6.2 skrll &sc->sc_desc[current].dmaseg, 1, off, prot, BUS_DMA_WAITOK);
1734 1.2.6.2 skrll }
1735 1.2.6.2 skrll
1736 1.2.6.2 skrll return -1;
1737 1.2.6.2 skrll }
1738 1.2.6.2 skrll
1739 1.2.6.2 skrll #endif
1740