dbri.c revision 1.4 1 1.4 macallan /* $NetBSD: dbri.c,v 1.4 2006/03/09 20:44:18 macallan Exp $ */
2 1.1 macallan
3 1.1 macallan /*
4 1.2 macallan * Copyright (C) 1997 Rudolf Koenig (rfkoenig (at) immd4.informatik.uni-erlangen.de)
5 1.2 macallan * Copyright (c) 1998, 1999 Brent Baccala (baccala (at) freesoft.org)
6 1.2 macallan * Copyright (c) 2001, 2002 Jared D. McNeill <jmcneill (at) netbsd.org>
7 1.1 macallan * Copyright (c) 2005 Michael Lorenz <macallan (at) netbsd.org>
8 1.1 macallan * All rights reserved.
9 1.1 macallan *
10 1.2 macallan * This driver is losely based on a Linux driver written by Rudolf Koenig and
11 1.2 macallan * Brent Baccala who kindly gave their permission to use their code in a
12 1.2 macallan * BSD-licensed driver.
13 1.2 macallan *
14 1.1 macallan * Redistribution and use in source and binary forms, with or without
15 1.1 macallan * modification, are permitted provided that the following conditions
16 1.1 macallan * are met:
17 1.1 macallan * 1. Redistributions of source code must retain the above copyright
18 1.1 macallan * notice, this list of conditions and the following disclaimer.
19 1.1 macallan * 2. Redistributions in binary form must reproduce the above copyright
20 1.1 macallan * notice, this list of conditions and the following disclaimer in the
21 1.1 macallan * documentation and/or other materials provided with the distribution.
22 1.1 macallan * 3. All advertising materials mentioning features or use of this software
23 1.1 macallan * must display the following acknowledgement:
24 1.2 macallan * This product includes software developed by Rudolf Koenig, Brent
25 1.2 macallan * Baccala, Jared D. McNeill.
26 1.1 macallan * 4. Neither the name of the author nor the names of any contributors may
27 1.1 macallan * be used to endorse or promote products derived from this software
28 1.1 macallan * without specific prior written permission.
29 1.1 macallan *
30 1.1 macallan * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
31 1.1 macallan * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
32 1.1 macallan * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
33 1.1 macallan * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
34 1.1 macallan * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
35 1.1 macallan * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
36 1.1 macallan * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
37 1.1 macallan * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
38 1.1 macallan * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
39 1.1 macallan * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
40 1.1 macallan * SUCH DAMAGE.
41 1.1 macallan *
42 1.1 macallan */
43 1.1 macallan
44 1.1 macallan #include <sys/cdefs.h>
45 1.4 macallan __KERNEL_RCSID(0, "$NetBSD: dbri.c,v 1.4 2006/03/09 20:44:18 macallan Exp $");
46 1.1 macallan
47 1.1 macallan #include "audio.h"
48 1.1 macallan #if NAUDIO > 0
49 1.1 macallan
50 1.1 macallan #include <sys/param.h>
51 1.1 macallan #include <sys/systm.h>
52 1.1 macallan #include <sys/errno.h>
53 1.1 macallan #include <sys/device.h>
54 1.1 macallan #include <sys/malloc.h>
55 1.1 macallan #include <sys/proc.h>
56 1.1 macallan
57 1.1 macallan #include <machine/bus.h>
58 1.1 macallan #include <machine/intr.h>
59 1.1 macallan
60 1.1 macallan #include <dev/sbus/sbusvar.h>
61 1.1 macallan #include <sparc/sparc/auxreg.h>
62 1.1 macallan #include <machine/autoconf.h>
63 1.1 macallan
64 1.1 macallan #include <sys/audioio.h>
65 1.1 macallan #include <dev/audio_if.h>
66 1.1 macallan #include <dev/auconv.h>
67 1.1 macallan
68 1.1 macallan #include <dev/ic/cs4215reg.h>
69 1.1 macallan #include <dev/ic/cs4215var.h>
70 1.1 macallan #include <dev/sbus/dbrireg.h>
71 1.1 macallan #include <dev/sbus/dbrivar.h>
72 1.1 macallan
73 1.4 macallan #include "opt_sbus_dbri.h"
74 1.4 macallan
75 1.1 macallan #define DBRI_ROM_NAME_PREFIX "SUNW,DBRI"
76 1.1 macallan
77 1.4 macallan #ifdef DBRI_DEBUG
78 1.4 macallan #define DPRINTF(x) printf x
79 1.4 macallan #else
80 1.4 macallan #define DPRINTF(x)
81 1.4 macallan #endif
82 1.1 macallan
83 1.1 macallan static const char *dbri_supported[] = {
84 1.1 macallan "e",
85 1.1 macallan "s3",
86 1.1 macallan ""
87 1.1 macallan };
88 1.1 macallan
89 1.1 macallan enum ms {
90 1.1 macallan CHImaster,
91 1.1 macallan CHIslave
92 1.1 macallan };
93 1.1 macallan
94 1.1 macallan enum io {
95 1.1 macallan PIPEinput,
96 1.1 macallan PIPEoutput
97 1.1 macallan };
98 1.1 macallan
99 1.1 macallan /*
100 1.1 macallan * Function prototypes
101 1.1 macallan */
102 1.1 macallan
103 1.1 macallan /* softc stuff */
104 1.1 macallan static void dbri_attach_sbus(struct device *, struct device *, void *);
105 1.1 macallan static int dbri_match_sbus(struct device *, struct cfdata *, void *);
106 1.1 macallan
107 1.1 macallan static void dbri_config_interrupts(struct device *);
108 1.1 macallan
109 1.1 macallan /* interrupt handler */
110 1.1 macallan static int dbri_intr(void *);
111 1.1 macallan
112 1.1 macallan /* supporting subroutines */
113 1.1 macallan static int dbri_init(struct dbri_softc *);
114 1.1 macallan static int dbri_reset(struct dbri_softc *);
115 1.1 macallan static volatile u_int32_t *dbri_command_lock(struct dbri_softc *);
116 1.1 macallan static void dbri_command_send(struct dbri_softc *, volatile u_int32_t *);
117 1.1 macallan static void dbri_process_interrupt_buffer(struct dbri_softc *);
118 1.1 macallan static void dbri_process_interrupt(struct dbri_softc *, int32_t);
119 1.1 macallan
120 1.1 macallan /* mmcodec subroutines */
121 1.1 macallan static int mmcodec_init(struct dbri_softc *);
122 1.1 macallan static void mmcodec_init_data(struct dbri_softc *);
123 1.1 macallan static void mmcodec_pipe_init(struct dbri_softc *);
124 1.1 macallan static void mmcodec_default(struct dbri_softc *);
125 1.1 macallan static void mmcodec_setgain(struct dbri_softc *, int);
126 1.1 macallan static int mmcodec_setcontrol(struct dbri_softc *);
127 1.1 macallan
128 1.1 macallan /* chi subroutines */
129 1.1 macallan static void chi_reset(struct dbri_softc *, enum ms, int);
130 1.1 macallan
131 1.1 macallan /* pipe subroutines */
132 1.1 macallan static void pipe_setup(struct dbri_softc *, int, int);
133 1.1 macallan static void pipe_reset(struct dbri_softc *, int);
134 1.1 macallan static void pipe_receive_fixed(struct dbri_softc *, int,
135 1.1 macallan volatile u_int32_t *);
136 1.1 macallan static void pipe_transmit_fixed(struct dbri_softc *, int, u_int32_t);
137 1.1 macallan
138 1.1 macallan static void pipe_ts_link(struct dbri_softc *, int, enum io, int, int, int);
139 1.1 macallan static int pipe_active(struct dbri_softc *, int);
140 1.1 macallan
141 1.1 macallan /* audio(9) stuff */
142 1.1 macallan static int dbri_query_encoding(void *, struct audio_encoding *);
143 1.1 macallan static int dbri_set_params(void *, int, int, struct audio_params *,
144 1.1 macallan struct audio_params *,stream_filter_list_t *, stream_filter_list_t *);
145 1.1 macallan static int dbri_round_blocksize(void *, int, int, const audio_params_t *);
146 1.1 macallan static int dbri_halt_output(void *);
147 1.1 macallan static int dbri_getdev(void *, struct audio_device *);
148 1.1 macallan static int dbri_set_port(void *, mixer_ctrl_t *);
149 1.1 macallan static int dbri_get_port(void *, mixer_ctrl_t *);
150 1.1 macallan static int dbri_query_devinfo(void *, mixer_devinfo_t *);
151 1.1 macallan static size_t dbri_round_buffersize(void *, int, size_t);
152 1.1 macallan static int dbri_get_props(void *);
153 1.4 macallan static int dbri_open(void *, int);
154 1.4 macallan static void dbri_close(void *);
155 1.1 macallan
156 1.1 macallan static void
157 1.1 macallan setup_ring(struct dbri_softc *, int, int, int, int, void (*)(void *), void *);
158 1.1 macallan
159 1.1 macallan static int dbri_trigger_output(void *, void *, void *, int,
160 1.1 macallan void (*)(void *), void *, const struct audio_params *);
161 1.1 macallan
162 1.1 macallan static void *dbri_malloc(void *, int, size_t, struct malloc_type *, int);
163 1.1 macallan static void dbri_free(void *, void *, struct malloc_type *);
164 1.1 macallan static paddr_t dbri_mappage(void *, void *, off_t, int);
165 1.4 macallan static void dbri_set_power(struct dbri_softc *, int);
166 1.4 macallan static void dbri_bring_up(struct dbri_softc *);
167 1.4 macallan static void dbri_powerhook(int, void *);
168 1.1 macallan
169 1.1 macallan /* stupid support routines */
170 1.1 macallan static u_int32_t reverse_bytes(u_int32_t, int);
171 1.1 macallan
172 1.1 macallan struct audio_device dbri_device = {
173 1.1 macallan "CS4215",
174 1.1 macallan "",
175 1.1 macallan "dbri"
176 1.1 macallan };
177 1.1 macallan
178 1.1 macallan struct audio_hw_if dbri_hw_if = {
179 1.4 macallan dbri_open,
180 1.4 macallan dbri_close,
181 1.1 macallan NULL, /* drain */
182 1.1 macallan dbri_query_encoding,
183 1.1 macallan dbri_set_params,
184 1.1 macallan dbri_round_blocksize,
185 1.1 macallan NULL, /* commit_settings */
186 1.1 macallan NULL, /* init_output */
187 1.1 macallan NULL, /* init_input */
188 1.1 macallan NULL, /* start_output */
189 1.1 macallan NULL, /* start_input */
190 1.1 macallan dbri_halt_output,
191 1.1 macallan NULL, /* halt_input */
192 1.1 macallan NULL, /* speaker_ctl */
193 1.1 macallan dbri_getdev,
194 1.1 macallan NULL, /* setfd */
195 1.1 macallan dbri_set_port,
196 1.1 macallan dbri_get_port,
197 1.1 macallan dbri_query_devinfo,
198 1.1 macallan dbri_malloc,
199 1.1 macallan dbri_free,
200 1.1 macallan dbri_round_buffersize,
201 1.1 macallan dbri_mappage,
202 1.1 macallan dbri_get_props,
203 1.1 macallan dbri_trigger_output,
204 1.1 macallan NULL /* trigger_input */
205 1.1 macallan };
206 1.1 macallan
207 1.1 macallan CFATTACH_DECL(dbri, sizeof(struct dbri_softc),
208 1.1 macallan dbri_match_sbus, dbri_attach_sbus, NULL, NULL);
209 1.1 macallan
210 1.1 macallan enum {
211 1.1 macallan DBRI_MONITOR_CLASS,
212 1.1 macallan DBRI_VOL_OUTPUT,
213 1.1 macallan DBRI_ENABLE_MONO,
214 1.1 macallan DBRI_ENABLE_HEADPHONE,
215 1.1 macallan DBRI_ENABLE_LINE
216 1.1 macallan /*
217 1.1 macallan DBRI_INPUT_CLASS,
218 1.1 macallan DBRI_RECORD_CLASS,
219 1.1 macallan DBRI_INPUT_GAIN,
220 1.1 macallan DBRI_INPUT_SELECT,
221 1.1 macallan DBRI_ENUM_LAST
222 1.1 macallan */
223 1.1 macallan };
224 1.1 macallan
225 1.1 macallan /*
226 1.1 macallan * Autoconfig routines
227 1.1 macallan */
228 1.1 macallan int
229 1.1 macallan dbri_match_sbus(struct device *parent, struct cfdata *match, void *aux)
230 1.1 macallan {
231 1.1 macallan struct sbus_attach_args *sa = aux;
232 1.1 macallan char *ver;
233 1.1 macallan int i;
234 1.1 macallan
235 1.1 macallan if (strncmp(DBRI_ROM_NAME_PREFIX, sa->sa_name, 9))
236 1.1 macallan return (0);
237 1.1 macallan
238 1.1 macallan ver = &sa->sa_name[9];
239 1.1 macallan
240 1.1 macallan for (i = 0; dbri_supported[i][0] != '\0'; i++)
241 1.1 macallan if (strcmp(dbri_supported[i], ver) == 0)
242 1.1 macallan return (1);
243 1.1 macallan
244 1.1 macallan return (0);
245 1.1 macallan }
246 1.1 macallan
247 1.1 macallan void
248 1.1 macallan dbri_attach_sbus(struct device *parent, struct device *self, void *aux)
249 1.1 macallan {
250 1.1 macallan struct dbri_softc *sc = (struct dbri_softc *)self;
251 1.1 macallan struct sbus_attach_args *sa = aux;
252 1.1 macallan bus_space_handle_t ioh;
253 1.1 macallan bus_size_t size;
254 1.1 macallan int error, rseg, pwr;
255 1.1 macallan char *ver = &sa->sa_name[9];
256 1.1 macallan
257 1.1 macallan sc->sc_iot = sa->sa_bustag;
258 1.1 macallan sc->sc_dmat = sa->sa_dmatag;
259 1.4 macallan sc->sc_powerstate = PWR_RESUME;
260 1.1 macallan
261 1.4 macallan pwr = prom_getpropint(sa->sa_node,"pwr-on-auxio",0);
262 1.1 macallan if(pwr) {
263 1.4 macallan /*
264 1.4 macallan * we can control DBRI power via auxio and we're initially
265 1.4 macallan * powered down
266 1.4 macallan */
267 1.4 macallan
268 1.4 macallan sc->sc_have_powerctl = 1;
269 1.4 macallan sc->sc_powerstate = 0;
270 1.4 macallan printf("\n");
271 1.4 macallan dbri_set_power(sc, 1);
272 1.4 macallan powerhook_establish(dbri_powerhook, sc);
273 1.4 macallan } else {
274 1.4 macallan /* we can't control power so we're always up */
275 1.4 macallan sc->sc_have_powerctl = 0;
276 1.4 macallan sc->sc_powerstate = 1;
277 1.1 macallan printf(": rev %s\n", ver);
278 1.4 macallan }
279 1.4 macallan
280 1.1 macallan if (sa->sa_npromvaddrs)
281 1.1 macallan ioh = (bus_space_handle_t)sa->sa_promvaddrs[0];
282 1.1 macallan else {
283 1.1 macallan if (sbus_bus_map(sa->sa_bustag, sa->sa_slot,
284 1.1 macallan sa->sa_offset, sa->sa_size,
285 1.1 macallan BUS_SPACE_MAP_LINEAR, /*0,*/ &ioh) != 0) {
286 1.1 macallan printf("%s @ sbus: cannot map registers\n",
287 1.1 macallan self->dv_xname);
288 1.1 macallan return;
289 1.1 macallan }
290 1.1 macallan }
291 1.1 macallan
292 1.1 macallan sc->sc_ioh = ioh;
293 1.1 macallan
294 1.1 macallan size = sizeof(struct dbri_dma);
295 1.1 macallan
296 1.1 macallan /* get a DMA handle */
297 1.1 macallan if ((error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0,
298 1.1 macallan BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) {
299 1.1 macallan printf("%s: DMA map create error %d\n", self->dv_xname, error);
300 1.1 macallan return;
301 1.1 macallan }
302 1.1 macallan
303 1.1 macallan /* allocate DMA buffer */
304 1.1 macallan if ((error = bus_dmamem_alloc(sc->sc_dmat, size, 0, 0, &sc->sc_dmaseg,
305 1.1 macallan 1, &rseg, BUS_DMA_NOWAIT)) != 0) {
306 1.1 macallan printf("%s: DMA buffer alloc error %d\n",
307 1.1 macallan self->dv_xname, error);
308 1.1 macallan return;
309 1.1 macallan }
310 1.1 macallan
311 1.1 macallan /* map DMA buffer into CPU addressable space */
312 1.1 macallan if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_dmaseg, rseg, size,
313 1.1 macallan &sc->sc_membase,
314 1.1 macallan BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) {
315 1.1 macallan printf("%s: DMA buffer map error %d\n",
316 1.1 macallan self->dv_xname, error);
317 1.1 macallan return;
318 1.1 macallan }
319 1.1 macallan
320 1.1 macallan /* load the buffer */
321 1.1 macallan if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap,
322 1.1 macallan sc->sc_membase, size, NULL,
323 1.1 macallan BUS_DMA_NOWAIT)) != 0) {
324 1.1 macallan printf("%s: DMA buffer map load error %d\n",
325 1.1 macallan self->dv_xname, error);
326 1.1 macallan bus_dmamem_unmap(sc->sc_dmat, sc->sc_membase, size);
327 1.1 macallan bus_dmamem_free(sc->sc_dmat, &sc->sc_dmaseg, rseg);
328 1.1 macallan return;
329 1.1 macallan }
330 1.1 macallan
331 1.1 macallan /* map the registers into memory */
332 1.1 macallan
333 1.1 macallan sc->sc_dma = (struct dbri_dma *)sc->sc_membase; /* kernel virtual address of DMA buffer */
334 1.1 macallan sc->sc_dmabase = sc->sc_dmamap->dm_segs[0].ds_addr; /* physical address of DMA buffer */
335 1.1 macallan sc->sc_bufsiz = size;
336 1.1 macallan
337 1.1 macallan sbus_establish(&sc->sc_sd, &sc->sc_dev);
338 1.1 macallan
339 1.1 macallan bus_intr_establish(sa->sa_bustag, sa->sa_pri, IPL_AUDIO, /*0,*/
340 1.1 macallan dbri_intr, sc);
341 1.1 macallan
342 1.1 macallan sc->sc_locked = 0;
343 1.1 macallan sc->sc_desc_used = 0;
344 1.1 macallan
345 1.1 macallan config_interrupts(self, &dbri_config_interrupts);
346 1.1 macallan
347 1.1 macallan return;
348 1.1 macallan }
349 1.1 macallan
350 1.4 macallan /*
351 1.4 macallan * lowlevel routine to switch power for the DBRI chip
352 1.4 macallan */
353 1.4 macallan static void
354 1.4 macallan dbri_set_power(struct dbri_softc *sc, int state)
355 1.4 macallan {
356 1.4 macallan int s;
357 1.4 macallan
358 1.4 macallan if (sc->sc_have_powerctl == 0)
359 1.4 macallan return;
360 1.4 macallan if (sc->sc_powerstate == state)
361 1.4 macallan return;
362 1.4 macallan
363 1.4 macallan if (state) {
364 1.4 macallan DPRINTF(("%s: waiting to power up... ", sc->sc_dev.dv_xname));
365 1.4 macallan s = splhigh();
366 1.4 macallan *AUXIO4M_REG |= (AUXIO4M_MMX);
367 1.4 macallan splx(s);
368 1.4 macallan DELAY(1000);
369 1.4 macallan DPRINTF(("done\n")); /* more delay... */
370 1.4 macallan } else {
371 1.4 macallan DPRINTF(("%s: powering down\n", sc->sc_dev.dv_xname));
372 1.4 macallan s = splhigh();
373 1.4 macallan *AUXIO4M_REG &= ~AUXIO4M_MMX;
374 1.4 macallan splx(s);
375 1.4 macallan }
376 1.4 macallan sc->sc_powerstate = state;
377 1.4 macallan }
378 1.4 macallan
379 1.4 macallan /*
380 1.4 macallan * power up and re-initialize the chip
381 1.4 macallan */
382 1.4 macallan static void
383 1.4 macallan dbri_bring_up(struct dbri_softc *sc)
384 1.4 macallan {
385 1.4 macallan
386 1.4 macallan if (sc->sc_have_powerctl == 0)
387 1.4 macallan return;
388 1.4 macallan if (sc->sc_powerstate == 1)
389 1.4 macallan return;
390 1.4 macallan
391 1.4 macallan /* ok, we really need to do something */
392 1.4 macallan dbri_set_power(sc, 1);
393 1.4 macallan
394 1.4 macallan /*
395 1.4 macallan * re-initialize the chip but skip all the probing, don't overwrite
396 1.4 macallan * any other settings either
397 1.4 macallan */
398 1.4 macallan dbri_init(sc);
399 1.4 macallan mmcodec_setgain(sc, 1);
400 1.4 macallan mmcodec_pipe_init(sc);
401 1.4 macallan mmcodec_init_data(sc);
402 1.4 macallan mmcodec_setgain(sc, 0);
403 1.4 macallan }
404 1.4 macallan
405 1.1 macallan void
406 1.1 macallan dbri_config_interrupts(struct device *dev)
407 1.1 macallan {
408 1.1 macallan struct dbri_softc *sc = (struct dbri_softc *)dev;
409 1.1 macallan dbri_init(sc);
410 1.1 macallan mmcodec_init(sc);
411 1.1 macallan /* Attach ourselves to the high level audio interface */
412 1.1 macallan audio_attach_mi(&dbri_hw_if, sc, &sc->sc_dev);
413 1.4 macallan
414 1.4 macallan /* power down until open() */
415 1.4 macallan dbri_set_power(sc, 0);
416 1.1 macallan return;
417 1.1 macallan }
418 1.1 macallan
419 1.1 macallan int
420 1.1 macallan dbri_intr(void *hdl)
421 1.1 macallan {
422 1.1 macallan struct dbri_softc *sc = hdl;
423 1.1 macallan bus_space_tag_t iot = sc->sc_iot;
424 1.1 macallan bus_space_handle_t ioh = sc->sc_ioh;
425 1.1 macallan int x;
426 1.1 macallan
427 1.1 macallan /* clear interrupt */
428 1.1 macallan x = bus_space_read_4(iot, ioh, DBRI_REG1);
429 1.1 macallan if (x & (DBRI_MRR | DBRI_MLE | DBRI_LBG | DBRI_MBE)) {
430 1.1 macallan u_int32_t tmp;
431 1.1 macallan
432 1.1 macallan if (x & DBRI_MRR)
433 1.1 macallan printf("%s: multiple ack error on sbus\n",
434 1.1 macallan sc->sc_dev.dv_xname);
435 1.1 macallan if (x & DBRI_MLE)
436 1.1 macallan printf("%s: multiple late error on sbus\n",
437 1.1 macallan sc->sc_dev.dv_xname);
438 1.1 macallan if (x & DBRI_LBG)
439 1.1 macallan printf("%s: lost bus grant on sbus\n",
440 1.1 macallan sc->sc_dev.dv_xname);
441 1.1 macallan if (x & DBRI_MBE)
442 1.1 macallan printf("%s: burst error on sbus\n",
443 1.1 macallan sc->sc_dev.dv_xname);
444 1.1 macallan
445 1.1 macallan /*
446 1.1 macallan * Some of these errors disable the chip's circuitry.
447 1.1 macallan * Re-enable the circuitry and keep on going.
448 1.1 macallan */
449 1.1 macallan
450 1.1 macallan tmp = bus_space_read_4(iot, ioh, DBRI_REG0);
451 1.1 macallan tmp &= ~(DBRI_DISABLE_MASTER);
452 1.1 macallan bus_space_write_4(iot, ioh, DBRI_REG0, tmp);
453 1.1 macallan }
454 1.1 macallan
455 1.1 macallan #if 0
456 1.1 macallan if (!x & 1) /* XXX: DBRI_INTR_REQ */
457 1.1 macallan return (1);
458 1.1 macallan #endif
459 1.1 macallan
460 1.1 macallan dbri_process_interrupt_buffer(sc);
461 1.1 macallan
462 1.1 macallan return (1);
463 1.1 macallan }
464 1.1 macallan
465 1.1 macallan int
466 1.1 macallan dbri_init(struct dbri_softc *sc)
467 1.1 macallan {
468 1.1 macallan bus_space_tag_t iot = sc->sc_iot;
469 1.1 macallan bus_space_handle_t ioh = sc->sc_ioh;
470 1.1 macallan u_int32_t reg;
471 1.1 macallan volatile u_int32_t *cmd;
472 1.1 macallan bus_addr_t dmaaddr;
473 1.1 macallan int n;
474 1.1 macallan
475 1.1 macallan dbri_reset(sc);
476 1.1 macallan
477 1.1 macallan cmd = dbri_command_lock(sc);
478 1.1 macallan
479 1.1 macallan /* XXX: Initialize interrupt ring buffer */
480 1.1 macallan sc->sc_dma->intr[0] = (u_int32_t)sc->sc_dmabase + dbri_dma_off(intr, 0);
481 1.1 macallan sc->sc_irqp = 1;
482 1.1 macallan
483 1.1 macallan /* Initialize pipes */
484 1.1 macallan for (n = 0; n < DBRI_PIPE_MAX; n++)
485 1.1 macallan sc->sc_pipe[n].desc = sc->sc_pipe[n].next = -1;
486 1.1 macallan
487 1.1 macallan for(n=1;n<DBRI_INT_BLOCKS;n++) {
488 1.1 macallan sc->sc_dma->intr[n]=0;
489 1.1 macallan }
490 1.1 macallan
491 1.1 macallan /* Disable all SBus bursts */
492 1.1 macallan /* XXX 16 byte bursts cause errors, the rest works */
493 1.1 macallan reg = bus_space_read_4(iot, ioh, DBRI_REG0);
494 1.1 macallan /*reg &= ~(DBRI_BURST_4 | DBRI_BURST_8 | DBRI_BURST_16);*/
495 1.1 macallan reg |= (DBRI_BURST_4 | DBRI_BURST_8);
496 1.1 macallan bus_space_write_4(iot, ioh, DBRI_REG0, reg);
497 1.1 macallan
498 1.1 macallan /* setup interrupt queue */
499 1.1 macallan dmaaddr = (u_int32_t)sc->sc_dmabase + dbri_dma_off(intr, 0);
500 1.1 macallan *(cmd++) = DBRI_CMD(DBRI_COMMAND_IIQ, 0, 0);
501 1.1 macallan *(cmd++) = dmaaddr;
502 1.1 macallan
503 1.1 macallan dbri_command_send(sc, cmd);
504 1.1 macallan return (0);
505 1.1 macallan }
506 1.1 macallan
507 1.1 macallan int
508 1.1 macallan dbri_reset(struct dbri_softc *sc)
509 1.1 macallan {
510 1.1 macallan int bail=0;
511 1.1 macallan bus_space_tag_t iot = sc->sc_iot;
512 1.1 macallan bus_space_handle_t ioh = sc->sc_ioh;
513 1.1 macallan
514 1.1 macallan bus_space_write_4(iot, ioh, DBRI_REG0, DBRI_SOFT_RESET);
515 1.1 macallan while ((bus_space_read_4(iot, ioh, DBRI_REG0) & DBRI_SOFT_RESET) &&
516 1.1 macallan (bail < 100000)) {
517 1.1 macallan bail++;
518 1.1 macallan delay(10);
519 1.1 macallan }
520 1.1 macallan if (bail == 100000) printf("%s: reset timed out\n",sc->sc_dev.dv_xname);
521 1.1 macallan return (0);
522 1.1 macallan }
523 1.1 macallan
524 1.1 macallan volatile u_int32_t *
525 1.1 macallan dbri_command_lock(struct dbri_softc *sc)
526 1.1 macallan {
527 1.1 macallan
528 1.1 macallan if (sc->sc_locked)
529 1.1 macallan printf("%s: command buffer locked\n", sc->sc_dev.dv_xname);
530 1.1 macallan
531 1.1 macallan sc->sc_locked++;
532 1.1 macallan
533 1.1 macallan return (&sc->sc_dma->command[0]);
534 1.1 macallan }
535 1.1 macallan
536 1.1 macallan void
537 1.1 macallan dbri_command_send(struct dbri_softc *sc, volatile u_int32_t *cmd)
538 1.1 macallan {
539 1.1 macallan bus_space_handle_t ioh = sc->sc_ioh;
540 1.1 macallan bus_space_tag_t iot = sc->sc_iot;
541 1.1 macallan int maxloops = 1000000;
542 1.1 macallan int x;
543 1.1 macallan
544 1.1 macallan x = splaudio();
545 1.1 macallan //x = splhigh();
546 1.1 macallan
547 1.1 macallan sc->sc_locked--;
548 1.1 macallan
549 1.1 macallan if (sc->sc_locked != 0) {
550 1.1 macallan printf("%s: command buffer improperly locked\n",
551 1.1 macallan sc->sc_dev.dv_xname);
552 1.1 macallan } else if ((cmd - &sc->sc_dma->command[0]) >= DBRI_NUM_COMMANDS - 1) {
553 1.1 macallan printf("%s: command buffer overflow\n", sc->sc_dev.dv_xname);
554 1.1 macallan } else {
555 1.1 macallan *(cmd++) = DBRI_CMD(DBRI_COMMAND_PAUSE, 0, 0);
556 1.1 macallan *(cmd++) = DBRI_CMD(DBRI_COMMAND_WAIT, 1, 0);
557 1.1 macallan sc->sc_waitseen = 0;
558 1.1 macallan bus_space_write_4(iot, ioh, DBRI_REG8, sc->sc_dmabase);
559 1.1 macallan while ((--maxloops) > 0 &&
560 1.1 macallan (bus_space_read_4(iot, ioh, DBRI_REG0)
561 1.1 macallan & DBRI_COMMAND_VALID)) {
562 1.1 macallan bus_space_barrier(iot, ioh, DBRI_REG0, 4,
563 1.1 macallan BUS_SPACE_BARRIER_READ);
564 1.1 macallan delay(1000);
565 1.1 macallan }
566 1.1 macallan
567 1.1 macallan if (maxloops == 0) {
568 1.1 macallan printf("%s: chip never completed command buffer\n",
569 1.1 macallan sc->sc_dev.dv_xname);
570 1.1 macallan } else {
571 1.1 macallan #ifdef DBRI_DEBUG
572 1.1 macallan printf("%s: command completed\n",sc->sc_dev.dv_xname);
573 1.1 macallan #endif
574 1.1 macallan while ((--maxloops) > 0 && (!sc->sc_waitseen))
575 1.1 macallan dbri_process_interrupt_buffer(sc);
576 1.1 macallan if (maxloops == 0) {
577 1.1 macallan printf("%s: chip never acked WAIT\n",
578 1.1 macallan sc->sc_dev.dv_xname);
579 1.1 macallan }
580 1.1 macallan }
581 1.1 macallan }
582 1.1 macallan
583 1.1 macallan splx(x);
584 1.1 macallan
585 1.1 macallan return;
586 1.1 macallan }
587 1.1 macallan
588 1.1 macallan void
589 1.1 macallan dbri_process_interrupt_buffer(struct dbri_softc *sc)
590 1.1 macallan {
591 1.1 macallan int32_t i;
592 1.1 macallan
593 1.1 macallan while ((i = sc->sc_dma->intr[sc->sc_irqp]) != 0) {
594 1.1 macallan sc->sc_dma->intr[sc->sc_irqp] = 0;
595 1.1 macallan sc->sc_irqp++;
596 1.1 macallan
597 1.1 macallan if (sc->sc_irqp == DBRI_INT_BLOCKS)
598 1.1 macallan sc->sc_irqp = 1;
599 1.1 macallan else if ((sc->sc_irqp & (DBRI_INT_BLOCKS - 1)) == 0)
600 1.1 macallan sc->sc_irqp++;
601 1.1 macallan
602 1.1 macallan dbri_process_interrupt(sc, i);
603 1.1 macallan }
604 1.1 macallan
605 1.1 macallan return;
606 1.1 macallan }
607 1.1 macallan
608 1.1 macallan void
609 1.1 macallan dbri_process_interrupt(struct dbri_softc *sc, int32_t i)
610 1.1 macallan {
611 1.1 macallan #if 0
612 1.1 macallan const int liu_states[] = { 1, 0, 8, 3, 4, 5, 6, 7 };
613 1.1 macallan #endif
614 1.1 macallan int val = DBRI_INTR_GETVAL(i);
615 1.1 macallan int channel = DBRI_INTR_GETCHAN(i);
616 1.1 macallan int command = DBRI_INTR_GETCMD(i);
617 1.1 macallan int code = DBRI_INTR_GETCODE(i);
618 1.1 macallan #if 0
619 1.1 macallan int rval = DBRI_INTR_GETRVAL(i);
620 1.1 macallan #endif
621 1.1 macallan if (channel == DBRI_INTR_CMD && command == DBRI_COMMAND_WAIT)
622 1.1 macallan sc->sc_waitseen++;
623 1.1 macallan
624 1.1 macallan switch (code) {
625 1.1 macallan case DBRI_INTR_XCMP: /* transmission complete */
626 1.1 macallan {
627 1.1 macallan int td;
628 1.1 macallan struct dbri_desc *dd;
629 1.1 macallan
630 1.1 macallan td = sc->sc_pipe[channel].desc;
631 1.1 macallan dd = &sc->sc_desc[td];
632 1.1 macallan
633 1.1 macallan if (dd->callback != NULL)
634 1.1 macallan dd->callback(dd->callback_args);
635 1.1 macallan break;
636 1.1 macallan }
637 1.1 macallan case DBRI_INTR_FXDT: /* fixed data change */
638 1.4 macallan DPRINTF(("dbri_intr: Fixed data change (%d: %x)\n", channel,
639 1.4 macallan val));
640 1.4 macallan
641 1.1 macallan if (sc->sc_pipe[channel].sdp & DBRI_SDP_MSB)
642 1.1 macallan val = reverse_bytes(val, sc->sc_pipe[channel].length);
643 1.1 macallan if (sc->sc_pipe[channel].prec)
644 1.1 macallan *(sc->sc_pipe[channel].prec) = val;
645 1.4 macallan DPRINTF(("%s: wakeup %p\n", sc->sc_dev.dv_xname, sc));
646 1.1 macallan #if 0
647 1.1 macallan wakeup(sc);
648 1.1 macallan #endif
649 1.1 macallan break;
650 1.1 macallan case DBRI_INTR_SBRI:
651 1.4 macallan DPRINTF(("dbri_intr: SBRI\n"));
652 1.1 macallan break;
653 1.1 macallan case DBRI_INTR_BRDY:
654 1.1 macallan {
655 1.1 macallan /* XXX no input (yet) */
656 1.1 macallan #if 0
657 1.1 macallan int rd = sc->sc_pipe[channel].desc;
658 1.1 macallan u_int32_t status;
659 1.1 macallan
660 1.1 macallan printf("dbri_intr: BRDY\n");
661 1.1 macallan if (rd < 0 || rd >= DBRI_NUM_DESCRIPTORS) {
662 1.1 macallan printf("%s: invalid rd on pipe\n", sc->sc_dev.dv_xname);
663 1.1 macallan break;
664 1.1 macallan }
665 1.1 macallan
666 1.1 macallan sc->sc_desc[rd].busy = 0;
667 1.1 macallan sc->sc_pipe[channel].desc = sc->sc_desc[rd].next;
668 1.1 macallan status = sc->sc_dma->desc[rd].word1;
669 1.1 macallan #endif
670 1.1 macallan /* XXX: callback ??? */
671 1.1 macallan
672 1.1 macallan break;
673 1.1 macallan }
674 1.1 macallan case DBRI_INTR_UNDR:
675 1.1 macallan {
676 1.1 macallan volatile u_int32_t *cmd;
677 1.1 macallan int td = sc->sc_pipe[channel].desc;
678 1.1 macallan
679 1.1 macallan printf("%s: DBRI_INTR_UNDR\n", sc->sc_dev.dv_xname);
680 1.1 macallan
681 1.1 macallan sc->sc_dma->desc[td].status = 0;
682 1.1 macallan
683 1.1 macallan cmd = dbri_command_lock(sc);
684 1.1 macallan *(cmd++) = DBRI_CMD(DBRI_COMMAND_SDP, 0,
685 1.1 macallan sc->sc_pipe[channel].sdp |
686 1.1 macallan DBRI_SDP_VALID_POINTER |
687 1.1 macallan DBRI_SDP_CLEAR |
688 1.1 macallan DBRI_SDP_2SAME);
689 1.1 macallan *(cmd++) = sc->sc_dmabase + dbri_dma_off(desc, td);
690 1.1 macallan dbri_command_send(sc, cmd);
691 1.1 macallan break;
692 1.1 macallan }
693 1.1 macallan default:
694 1.1 macallan #if 0
695 1.1 macallan printf("%s: unknown interrupt code %d\n",
696 1.1 macallan sc->sc_dev.dv_xname, code);
697 1.1 macallan #endif
698 1.1 macallan break;
699 1.1 macallan }
700 1.1 macallan
701 1.1 macallan return;
702 1.1 macallan }
703 1.1 macallan
704 1.1 macallan /*
705 1.1 macallan * mmcodec stuff
706 1.1 macallan */
707 1.1 macallan
708 1.1 macallan int
709 1.1 macallan mmcodec_init(struct dbri_softc *sc)
710 1.1 macallan {
711 1.1 macallan bus_space_handle_t ioh = sc->sc_ioh;
712 1.1 macallan bus_space_tag_t iot = sc->sc_iot;
713 1.1 macallan u_int32_t reg2;
714 1.1 macallan
715 1.1 macallan reg2 = bus_space_read_4(iot, ioh, DBRI_REG2);
716 1.4 macallan DPRINTF(("mmcodec_init: PIO reads %x\n", reg2));
717 1.4 macallan
718 1.1 macallan if (reg2 & DBRI_PIO2) {
719 1.1 macallan printf("%s: onboard CS4215 detected\n",
720 1.1 macallan sc->sc_dev.dv_xname);
721 1.1 macallan sc->sc_mm.onboard = 1;
722 1.1 macallan }
723 1.1 macallan
724 1.1 macallan if (reg2 & DBRI_PIO0) {
725 1.1 macallan printf("%s: speakerbox detected\n",
726 1.1 macallan sc->sc_dev.dv_xname);
727 1.1 macallan sc->sc_mm.onboard = 0;
728 1.1 macallan }
729 1.1 macallan
730 1.1 macallan if ((reg2 & DBRI_PIO2) && (reg2 & DBRI_PIO0)) {
731 1.1 macallan printf("%s: using speakerbox\n",
732 1.1 macallan sc->sc_dev.dv_xname);
733 1.1 macallan bus_space_write_4(iot, ioh, DBRI_REG2, DBRI_PIO2_ENABLE);
734 1.1 macallan sc->sc_mm.onboard = 0;
735 1.1 macallan }
736 1.1 macallan
737 1.1 macallan if (!(reg2 & (DBRI_PIO0|DBRI_PIO2))) {
738 1.1 macallan printf("%s: no mmcodec found\n", sc->sc_dev.dv_xname);
739 1.1 macallan return -1;
740 1.1 macallan }
741 1.1 macallan
742 1.1 macallan sc->sc_version = 0xff;
743 1.1 macallan
744 1.1 macallan mmcodec_pipe_init(sc);
745 1.1 macallan mmcodec_default(sc);
746 1.1 macallan
747 1.1 macallan sc->sc_mm.offset = sc->sc_mm.onboard ? 0 : 8;
748 1.1 macallan
749 1.1 macallan if (mmcodec_setcontrol(sc) == -1 || sc->sc_version == 0xff) {
750 1.1 macallan printf("%s: cs4215 probe failed at offset %d\n",
751 1.1 macallan sc->sc_dev.dv_xname, sc->sc_mm.offset);
752 1.1 macallan return (-1);
753 1.1 macallan }
754 1.1 macallan
755 1.1 macallan printf("%s: cs4215 ver %d found at offset %d\n",
756 1.1 macallan sc->sc_dev.dv_xname, sc->sc_version & 0xf, sc->sc_mm.offset);
757 1.1 macallan
758 1.1 macallan /* set some sane defaults for mmcodec_init_data */
759 1.1 macallan sc->sc_params.channels = 2;
760 1.1 macallan sc->sc_params.precision = 16;
761 1.1 macallan
762 1.1 macallan mmcodec_init_data(sc);
763 1.1 macallan
764 1.1 macallan sc->sc_open = 0;
765 1.1 macallan
766 1.1 macallan return (0);
767 1.1 macallan }
768 1.1 macallan
769 1.1 macallan void
770 1.1 macallan mmcodec_init_data(struct dbri_softc *sc)
771 1.1 macallan {
772 1.1 macallan bus_space_tag_t iot = sc->sc_iot;
773 1.1 macallan bus_space_handle_t ioh = sc->sc_ioh;
774 1.1 macallan u_int32_t tmp;
775 1.1 macallan int data_width;
776 1.1 macallan
777 1.1 macallan tmp = bus_space_read_4(iot, ioh, DBRI_REG0);
778 1.1 macallan tmp &= ~(DBRI_CHI_ACTIVATE); /* disable CHI */
779 1.1 macallan bus_space_write_4(iot, ioh, DBRI_REG0, tmp);
780 1.1 macallan
781 1.1 macallan /* switch CS4215 to data mode - set PIO3 to 1 */
782 1.1 macallan tmp = DBRI_PIO_ENABLE_ALL | DBRI_PIO1 | DBRI_PIO3;
783 1.1 macallan /* XXX */
784 1.1 macallan tmp |= (sc->sc_mm.onboard ? DBRI_PIO0 : DBRI_PIO2);
785 1.1 macallan
786 1.1 macallan bus_space_write_4(iot, ioh, DBRI_REG2, tmp);
787 1.1 macallan chi_reset(sc, CHIslave, 128);
788 1.1 macallan
789 1.1 macallan data_width = sc->sc_params.channels
790 1.1 macallan * sc->sc_params.precision;
791 1.1 macallan pipe_ts_link(sc, 20, PIPEoutput, 16, 32, sc->sc_mm.offset + 32);
792 1.1 macallan pipe_ts_link(sc, 4, PIPEoutput, 16, data_width, sc->sc_mm.offset);
793 1.1 macallan pipe_ts_link(sc, 6, PIPEinput, 16, data_width, sc->sc_mm.offset);
794 1.1 macallan pipe_ts_link(sc, 21, PIPEinput, 16, 16, sc->sc_mm.offset + 40);
795 1.1 macallan
796 1.1 macallan mmcodec_setgain(sc, 0);
797 1.1 macallan
798 1.1 macallan tmp = bus_space_read_4(iot, ioh, DBRI_REG0);
799 1.1 macallan tmp |= DBRI_CHI_ACTIVATE;
800 1.1 macallan bus_space_write_4(iot, ioh, DBRI_REG0, tmp);
801 1.1 macallan
802 1.1 macallan return;
803 1.1 macallan }
804 1.1 macallan
805 1.1 macallan void
806 1.1 macallan mmcodec_pipe_init(struct dbri_softc *sc)
807 1.1 macallan {
808 1.1 macallan
809 1.1 macallan pipe_setup(sc, 4, DBRI_SDP_MEM | DBRI_SDP_TO_SER | DBRI_SDP_MSB);
810 1.1 macallan pipe_setup(sc, 20, DBRI_SDP_FIXED | DBRI_SDP_TO_SER | DBRI_SDP_MSB);
811 1.1 macallan pipe_setup(sc, 6, DBRI_SDP_MEM | DBRI_SDP_FROM_SER | DBRI_SDP_MSB);
812 1.1 macallan pipe_setup(sc, 21, DBRI_SDP_FIXED | DBRI_SDP_FROM_SER | DBRI_SDP_MSB);
813 1.1 macallan
814 1.1 macallan pipe_setup(sc, 17, DBRI_SDP_FIXED | DBRI_SDP_TO_SER | DBRI_SDP_MSB);
815 1.1 macallan pipe_setup(sc, 18, DBRI_SDP_FIXED | DBRI_SDP_FROM_SER | DBRI_SDP_MSB);
816 1.1 macallan pipe_setup(sc, 19, DBRI_SDP_FIXED | DBRI_SDP_FROM_SER | DBRI_SDP_MSB);
817 1.1 macallan
818 1.1 macallan sc->sc_mm.status = 0;
819 1.1 macallan
820 1.1 macallan pipe_receive_fixed(sc, 18, &sc->sc_mm.status);
821 1.1 macallan pipe_receive_fixed(sc, 19, &sc->sc_mm.version);
822 1.1 macallan
823 1.1 macallan return;
824 1.1 macallan }
825 1.1 macallan
826 1.1 macallan void
827 1.1 macallan mmcodec_default(struct dbri_softc *sc)
828 1.1 macallan {
829 1.1 macallan struct cs4215_state *mm = &sc->sc_mm;
830 1.1 macallan
831 1.1 macallan /*
832 1.1 macallan * no action, memory resetting only
833 1.1 macallan *
834 1.1 macallan * data time slots 5-8
835 1.1 macallan * speaker, line and headphone enable. set gain to half.
836 1.1 macallan * input is mic
837 1.1 macallan */
838 1.1 macallan mm->data[0] = sc->sc_latt = 0x20 | CS4215_HE | CS4215_LE;
839 1.1 macallan mm->data[1] = sc->sc_ratt = 0x20 | CS4215_SE;
840 1.1 macallan mm->data[2] = CS4215_LG(0x08) | CS4215_IS | CS4215_PIO0 | CS4215_PIO1;
841 1.1 macallan mm->data[3] = CS4215_RG(0x08) | CS4215_MA(0x0f);
842 1.1 macallan
843 1.1 macallan /*
844 1.1 macallan * control time slots 1-4
845 1.1 macallan *
846 1.1 macallan * 0: default I/O voltage scale
847 1.1 macallan * 1: 8 bit ulaw, 8kHz, mono, high pass filter disabled
848 1.1 macallan * 2: serial enable, CHI master, 128 bits per frame, clock 1
849 1.1 macallan * 3: tests disabled
850 1.1 macallan */
851 1.1 macallan mm->control[0] = CS4215_RSRVD_1 | CS4215_MLB;
852 1.1 macallan mm->control[1] = CS4215_DFR_ULAW | CS4215_FREQ[0].csval;
853 1.1 macallan mm->control[2] = CS4215_XCLK | CS4215_BSEL_128 | CS4215_FREQ[0].xtal;
854 1.1 macallan mm->control[3] = 0;
855 1.1 macallan
856 1.1 macallan return;
857 1.1 macallan }
858 1.1 macallan
859 1.1 macallan void
860 1.1 macallan mmcodec_setgain(struct dbri_softc *sc, int mute)
861 1.1 macallan {
862 1.1 macallan if (mute) {
863 1.1 macallan /* disable all outputs, max. attenuation */
864 1.2 macallan sc->sc_mm.data[0] = sc->sc_latt | 63;
865 1.2 macallan sc->sc_mm.data[1] = sc->sc_ratt | 63;
866 1.1 macallan } else {
867 1.1 macallan /*
868 1.1 macallan * We should be setting the proper output here.. for now,
869 1.1 macallan * use the speaker. Possible outputs:
870 1.1 macallan * Headphones:
871 1.1 macallan * data[0] |= CS4215_HE;
872 1.1 macallan * Line out:
873 1.1 macallan * data[0] |= CS4215_LE;
874 1.1 macallan * Speaker:
875 1.1 macallan * data[1] |= CS4215_SE;
876 1.1 macallan */
877 1.1 macallan sc->sc_mm.data[0] = sc->sc_latt;
878 1.1 macallan sc->sc_mm.data[1] = sc->sc_ratt;
879 1.1 macallan }
880 1.1 macallan
881 1.4 macallan if (sc->sc_powerstate == 0)
882 1.4 macallan return;
883 1.1 macallan pipe_transmit_fixed(sc, 20, *(u_int32_t *)__UNVOLATILE(sc->sc_mm.data));
884 1.1 macallan
885 1.1 macallan /* give the chip some time to execure the command */
886 1.1 macallan delay(250);
887 1.1 macallan
888 1.1 macallan return;
889 1.1 macallan }
890 1.1 macallan
891 1.1 macallan int
892 1.1 macallan mmcodec_setcontrol(struct dbri_softc *sc)
893 1.1 macallan {
894 1.1 macallan bus_space_tag_t iot = sc->sc_iot;
895 1.1 macallan bus_space_handle_t ioh = sc->sc_ioh;
896 1.1 macallan u_int32_t val;
897 1.1 macallan u_int32_t tmp;
898 1.1 macallan #if 1
899 1.1 macallan int i;
900 1.1 macallan #endif
901 1.1 macallan
902 1.1 macallan /*
903 1.1 macallan * Temporarily mute outputs and wait 125 us to make sure that it
904 1.1 macallan * happens. This avoids clicking noises.
905 1.1 macallan */
906 1.1 macallan mmcodec_setgain(sc, 1);
907 1.1 macallan //DELAY(125);
908 1.1 macallan
909 1.1 macallan /* enable control mode */
910 1.1 macallan val = DBRI_PIO_ENABLE_ALL | DBRI_PIO1; /* was PIO1 */
911 1.1 macallan
912 1.1 macallan /* XXX */
913 1.1 macallan val |= (sc->sc_mm.onboard ? DBRI_PIO0 : DBRI_PIO2);
914 1.1 macallan
915 1.1 macallan bus_space_write_4(iot, ioh, DBRI_REG2, val);
916 1.1 macallan
917 1.1 macallan DELAY(34);
918 1.1 macallan
919 1.1 macallan /*
920 1.1 macallan * in control mode, the cs4215 is the slave device, so the
921 1.1 macallan * DBRI must act as the CHI master.
922 1.1 macallan *
923 1.1 macallan * in data mode, the cs4215 must be the CHI master to insure
924 1.1 macallan * that the data stream is in sync with its codec
925 1.1 macallan */
926 1.1 macallan tmp = bus_space_read_4(iot, ioh, DBRI_REG0);
927 1.1 macallan tmp &= ~DBRI_COMMAND_CHI;
928 1.1 macallan bus_space_write_4(iot, ioh, DBRI_REG0, tmp);
929 1.1 macallan
930 1.1 macallan chi_reset(sc, CHImaster, 128);
931 1.1 macallan
932 1.1 macallan /* control mode */
933 1.1 macallan pipe_ts_link(sc, 17, PIPEoutput, 16, 32, sc->sc_mm.offset);
934 1.1 macallan pipe_ts_link(sc, 18, PIPEinput, 16, 8, sc->sc_mm.offset);
935 1.1 macallan pipe_ts_link(sc, 19, PIPEinput, 16, 8, sc->sc_mm.offset + 48);
936 1.1 macallan
937 1.1 macallan /* wait for the chip to echo back CLB as zero */
938 1.1 macallan sc->sc_mm.control[0] &= ~CS4215_CLB;
939 1.1 macallan pipe_transmit_fixed(sc, 17, *(int *)__UNVOLATILE(sc->sc_mm.control));
940 1.1 macallan
941 1.1 macallan tmp = bus_space_read_4(iot, ioh, DBRI_REG0);
942 1.1 macallan tmp |= DBRI_CHI_ACTIVATE;
943 1.1 macallan bus_space_write_4(iot, ioh, DBRI_REG0, tmp);
944 1.1 macallan
945 1.1 macallan #if 1
946 1.1 macallan i = 1024;
947 1.1 macallan while (((sc->sc_mm.status & 0xe4) != 0x20) && --i) {
948 1.1 macallan delay(125);
949 1.1 macallan }
950 1.1 macallan
951 1.1 macallan if (i == 0) {
952 1.1 macallan printf("%s: cs4215 didn't respond to CLB (0x%02x)\n",
953 1.1 macallan sc->sc_dev.dv_xname, sc->sc_mm.status);
954 1.1 macallan return (-1);
955 1.1 macallan }
956 1.1 macallan #else
957 1.1 macallan while ((sc->sc_mm.status & 0xe4) != 0x20) {
958 1.1 macallan printf("%s: tsleep %p\n", sc->sc_dev.dv_xname, sc);
959 1.1 macallan tsleep(sc, PCATCH | PZERO, "dbrifxdt", 0);
960 1.1 macallan }
961 1.1 macallan #endif
962 1.1 macallan
963 1.1 macallan /* copy the version information before it becomes unreadable again */
964 1.1 macallan sc->sc_version=sc->sc_mm.version;
965 1.1 macallan
966 1.1 macallan /* terminate cs4215 control mode */
967 1.1 macallan sc->sc_mm.control[0] |= CS4215_CLB;
968 1.1 macallan pipe_transmit_fixed(sc, 17, *(int *)__UNVOLATILE(sc->sc_mm.control));
969 1.1 macallan
970 1.1 macallan /* two frames of control info @ 8kHz frame rate = 250us delay */
971 1.1 macallan DELAY(250);
972 1.1 macallan
973 1.1 macallan mmcodec_setgain(sc, 0);
974 1.1 macallan
975 1.1 macallan return (0);
976 1.1 macallan
977 1.1 macallan }
978 1.1 macallan
979 1.1 macallan /*
980 1.1 macallan * CHI combo
981 1.1 macallan */
982 1.1 macallan void
983 1.1 macallan chi_reset(struct dbri_softc *sc, enum ms ms, int bpf)
984 1.1 macallan {
985 1.1 macallan volatile u_int32_t *cmd;
986 1.1 macallan int val;
987 1.1 macallan int clockrate, divisor;
988 1.1 macallan
989 1.1 macallan cmd = dbri_command_lock(sc);
990 1.1 macallan
991 1.1 macallan /* set CHI anchor: pipe 16 */
992 1.1 macallan val = DBRI_DTS_VI | DBRI_DTS_INS | DBRI_DTS_PRVIN(16) | DBRI_PIPE(16);
993 1.1 macallan *(cmd++) = DBRI_CMD(DBRI_COMMAND_DTS, 0, val);
994 1.1 macallan *(cmd++) = DBRI_TS_ANCHOR | DBRI_TS_NEXT(16);
995 1.1 macallan *(cmd++) = 0;
996 1.1 macallan
997 1.1 macallan val = DBRI_DTS_VO | DBRI_DTS_INS | DBRI_DTS_PRVOUT(16) | DBRI_PIPE(16);
998 1.1 macallan *(cmd++) = DBRI_CMD(DBRI_COMMAND_DTS, 0, val);
999 1.1 macallan *(cmd++) = 0;
1000 1.1 macallan *(cmd++) = DBRI_TS_ANCHOR | DBRI_TS_NEXT(16);
1001 1.1 macallan
1002 1.1 macallan sc->sc_pipe[16].sdp = 1;
1003 1.1 macallan sc->sc_pipe[16].next = 16;
1004 1.1 macallan sc->sc_chi_pipe_in = 16;
1005 1.1 macallan sc->sc_chi_pipe_out = 16;
1006 1.1 macallan
1007 1.1 macallan switch (ms) {
1008 1.1 macallan case CHIslave:
1009 1.1 macallan *(cmd++) = DBRI_CMD(DBRI_COMMAND_CHI, 0, DBRI_CHI_CHICM(0));
1010 1.1 macallan break;
1011 1.1 macallan case CHImaster:
1012 1.1 macallan clockrate = bpf * 8;
1013 1.1 macallan divisor = 12288 / clockrate;
1014 1.1 macallan
1015 1.1 macallan if (divisor > 255 || divisor * clockrate != 12288)
1016 1.1 macallan printf("%s: illegal bits-per-frame %d\n",
1017 1.1 macallan sc->sc_dev.dv_xname, bpf);
1018 1.1 macallan
1019 1.1 macallan *(cmd++) = DBRI_CMD(DBRI_COMMAND_CHI, 0,
1020 1.1 macallan DBRI_CHI_CHICM(divisor) | DBRI_CHI_FD | DBRI_CHI_BPF(bpf));
1021 1.1 macallan break;
1022 1.1 macallan default:
1023 1.1 macallan printf("%s: unknown value for ms!\n", sc->sc_dev.dv_xname);
1024 1.1 macallan break;
1025 1.1 macallan }
1026 1.1 macallan
1027 1.1 macallan sc->sc_chi_bpf = bpf;
1028 1.1 macallan
1029 1.1 macallan /* CHI data mode */
1030 1.1 macallan *(cmd++) = DBRI_CMD(DBRI_COMMAND_PAUSE, 0, 0);
1031 1.1 macallan *(cmd++) = DBRI_CMD(DBRI_COMMAND_CDM, 0,
1032 1.1 macallan DBRI_CDM_XCE | DBRI_CDM_XEN | DBRI_CDM_REN);
1033 1.1 macallan
1034 1.1 macallan dbri_command_send(sc, cmd);
1035 1.1 macallan
1036 1.1 macallan return;
1037 1.1 macallan }
1038 1.1 macallan
1039 1.1 macallan /*
1040 1.1 macallan * pipe stuff
1041 1.1 macallan */
1042 1.1 macallan void
1043 1.1 macallan pipe_setup(struct dbri_softc *sc, int pipe, int sdp)
1044 1.1 macallan {
1045 1.4 macallan DPRINTF(("pipe setup: %d\n", pipe));
1046 1.1 macallan if (pipe < 0 || pipe >= DBRI_PIPE_MAX) {
1047 1.1 macallan printf("%s: illegal pipe number %d\n", sc->sc_dev.dv_xname,
1048 1.1 macallan pipe);
1049 1.1 macallan return;
1050 1.1 macallan }
1051 1.1 macallan
1052 1.1 macallan if ((sdp & 0xf800) != sdp)
1053 1.1 macallan printf("%s: strange SDP value %d\n", sc->sc_dev.dv_xname, sdp);
1054 1.1 macallan
1055 1.1 macallan if (DBRI_SDP_MODE(sdp) == DBRI_SDP_FIXED &&
1056 1.1 macallan !(sdp & DBRI_SDP_TO_SER))
1057 1.1 macallan sdp |= DBRI_SDP_CHANGE;
1058 1.1 macallan
1059 1.1 macallan sdp |= DBRI_PIPE(pipe);
1060 1.1 macallan
1061 1.1 macallan sc->sc_pipe[pipe].sdp = sdp;
1062 1.1 macallan sc->sc_pipe[pipe].desc = -1;
1063 1.1 macallan
1064 1.1 macallan pipe_reset(sc, pipe);
1065 1.1 macallan
1066 1.1 macallan return;
1067 1.1 macallan }
1068 1.1 macallan
1069 1.1 macallan void
1070 1.1 macallan pipe_reset(struct dbri_softc *sc, int pipe)
1071 1.1 macallan {
1072 1.1 macallan struct dbri_desc *dd;
1073 1.1 macallan int sdp;
1074 1.1 macallan int desc;
1075 1.1 macallan volatile u_int32_t *cmd;
1076 1.1 macallan
1077 1.1 macallan if (pipe < 0 || pipe >= DBRI_PIPE_MAX) {
1078 1.1 macallan printf("%s: illegal pipe number %d\n", sc->sc_dev.dv_xname,
1079 1.1 macallan pipe);
1080 1.1 macallan return;
1081 1.1 macallan }
1082 1.1 macallan
1083 1.1 macallan sdp = sc->sc_pipe[pipe].sdp;
1084 1.1 macallan if (sdp == 0) {
1085 1.1 macallan printf("%s: can not reset uninitialized pipe %d\n",
1086 1.1 macallan sc->sc_dev.dv_xname, pipe);
1087 1.1 macallan return;
1088 1.1 macallan }
1089 1.1 macallan
1090 1.1 macallan cmd = dbri_command_lock(sc);
1091 1.1 macallan *(cmd++) = DBRI_CMD(DBRI_COMMAND_SDP, 0,
1092 1.1 macallan sdp | DBRI_SDP_CLEAR | DBRI_SDP_VALID_POINTER);
1093 1.1 macallan *(cmd++) = 0;
1094 1.1 macallan dbri_command_send(sc, cmd);
1095 1.1 macallan
1096 1.1 macallan desc = sc->sc_pipe[pipe].desc;
1097 1.1 macallan
1098 1.1 macallan dd = &sc->sc_desc[desc];
1099 1.1 macallan
1100 1.1 macallan dd->busy = 0;
1101 1.1 macallan
1102 1.1 macallan #if 0
1103 1.1 macallan if (dd->callback)
1104 1.1 macallan (*dd->callback)(dd->callback_args);
1105 1.1 macallan #endif
1106 1.1 macallan
1107 1.1 macallan sc->sc_pipe[pipe].desc = -1;
1108 1.1 macallan
1109 1.1 macallan return;
1110 1.1 macallan }
1111 1.1 macallan
1112 1.1 macallan void
1113 1.1 macallan pipe_receive_fixed(struct dbri_softc *sc, int pipe, volatile u_int32_t *prec)
1114 1.1 macallan {
1115 1.1 macallan
1116 1.1 macallan if (pipe < DBRI_PIPE_MAX / 2 || pipe >= DBRI_PIPE_MAX) {
1117 1.1 macallan printf("%s: illegal pipe number %d\n", sc->sc_dev.dv_xname,
1118 1.1 macallan pipe);
1119 1.1 macallan return;
1120 1.1 macallan }
1121 1.1 macallan
1122 1.1 macallan if (DBRI_SDP_MODE(sc->sc_pipe[pipe].sdp) != DBRI_SDP_FIXED) {
1123 1.1 macallan printf("%s: non-fixed pipe %d\n", sc->sc_dev.dv_xname,
1124 1.1 macallan pipe);
1125 1.1 macallan return;
1126 1.1 macallan }
1127 1.1 macallan
1128 1.1 macallan if (sc->sc_pipe[pipe].sdp & DBRI_SDP_TO_SER) {
1129 1.1 macallan printf("%s: can not receive on transmit pipe %d\b",
1130 1.1 macallan sc->sc_dev.dv_xname, pipe);
1131 1.1 macallan return;
1132 1.1 macallan }
1133 1.1 macallan
1134 1.1 macallan sc->sc_pipe[pipe].prec = prec;
1135 1.1 macallan
1136 1.1 macallan return;
1137 1.1 macallan }
1138 1.1 macallan
1139 1.1 macallan void
1140 1.1 macallan pipe_transmit_fixed(struct dbri_softc *sc, int pipe, u_int32_t data)
1141 1.1 macallan {
1142 1.1 macallan volatile u_int32_t *cmd;
1143 1.1 macallan
1144 1.1 macallan if (pipe < DBRI_PIPE_MAX / 2 || pipe >= DBRI_PIPE_MAX) {
1145 1.1 macallan printf("%s: illegal pipe number %d\n", sc->sc_dev.dv_xname,
1146 1.1 macallan pipe);
1147 1.1 macallan return;
1148 1.1 macallan }
1149 1.1 macallan
1150 1.1 macallan if (DBRI_SDP_MODE(sc->sc_pipe[pipe].sdp) == 0) {
1151 1.1 macallan printf("%s: uninitialized pipe %d\n", sc->sc_dev.dv_xname,
1152 1.1 macallan pipe);
1153 1.1 macallan return;
1154 1.1 macallan }
1155 1.1 macallan
1156 1.1 macallan if (DBRI_SDP_MODE(sc->sc_pipe[pipe].sdp) != DBRI_SDP_FIXED) {
1157 1.1 macallan printf("%s: non-fixed pipe %d\n", sc->sc_dev.dv_xname, pipe);
1158 1.1 macallan return;
1159 1.1 macallan }
1160 1.1 macallan
1161 1.1 macallan if (!(sc->sc_pipe[pipe].sdp & DBRI_SDP_TO_SER)) {
1162 1.1 macallan printf("%s: called on receive pipe %d\n", sc->sc_dev.dv_xname,
1163 1.1 macallan pipe);
1164 1.1 macallan return;
1165 1.1 macallan }
1166 1.1 macallan
1167 1.1 macallan if (sc->sc_pipe[pipe].sdp & DBRI_SDP_MSB)
1168 1.1 macallan data = reverse_bytes(data, sc->sc_pipe[pipe].length);
1169 1.1 macallan
1170 1.1 macallan cmd = dbri_command_lock(sc);
1171 1.1 macallan *(cmd++) = DBRI_CMD(DBRI_COMMAND_SSP, 0, pipe);
1172 1.1 macallan *(cmd++) = data;
1173 1.1 macallan
1174 1.1 macallan dbri_command_send(sc, cmd);
1175 1.1 macallan
1176 1.1 macallan return;
1177 1.1 macallan }
1178 1.1 macallan
1179 1.1 macallan void
1180 1.1 macallan setup_ring(struct dbri_softc *sc, int pipe, int which, int num, int blksz,
1181 1.1 macallan void (*callback)(void *), void *callback_args)
1182 1.1 macallan {
1183 1.1 macallan volatile u_int32_t *cmd;
1184 1.1 macallan int x, i;
1185 1.1 macallan int td;
1186 1.1 macallan int td_first, td_last;
1187 1.1 macallan bus_addr_t dmabuf, dmabase;
1188 1.1 macallan struct dbri_desc *dd = &sc->sc_desc[which];
1189 1.1 macallan
1190 1.1 macallan td = 0;
1191 1.1 macallan td_first = td_last = -1;
1192 1.1 macallan
1193 1.1 macallan if (pipe < 0 || pipe >= DBRI_PIPE_MAX / 2) {
1194 1.1 macallan printf("%s: illegal pipe number %d\n", sc->sc_dev.dv_xname,
1195 1.1 macallan pipe);
1196 1.1 macallan return;
1197 1.1 macallan }
1198 1.1 macallan
1199 1.1 macallan if (sc->sc_pipe[pipe].sdp == 0) {
1200 1.1 macallan printf("%s: uninitialized pipe %d\n", sc->sc_dev.dv_xname,
1201 1.1 macallan pipe);
1202 1.1 macallan return;
1203 1.1 macallan }
1204 1.1 macallan
1205 1.1 macallan if (!(sc->sc_pipe[pipe].sdp & DBRI_SDP_TO_SER)) {
1206 1.1 macallan printf("%s: called on receive pipe %d\n",
1207 1.1 macallan sc->sc_dev.dv_xname, pipe);
1208 1.1 macallan return;
1209 1.1 macallan }
1210 1.1 macallan
1211 1.1 macallan
1212 1.1 macallan dmabuf = dd->dmabase;
1213 1.1 macallan dmabase = sc->sc_dmabase;
1214 1.1 macallan td = 0;
1215 1.1 macallan
1216 1.1 macallan for (i = 0; i < (num-1); i++) {
1217 1.1 macallan
1218 1.1 macallan sc->sc_dma->desc[i].flags = TX_BCNT(blksz)
1219 1.1 macallan | TX_EOF | TX_BINT;
1220 1.1 macallan sc->sc_dma->desc[i].ba = dmabuf;
1221 1.1 macallan sc->sc_dma->desc[i].nda = dmabase + dbri_dma_off(desc, i + 1);
1222 1.1 macallan sc->sc_dma->desc[i].status = 0;
1223 1.1 macallan
1224 1.1 macallan td_last = td;
1225 1.1 macallan dmabuf += blksz;
1226 1.1 macallan }
1227 1.1 macallan
1228 1.1 macallan sc->sc_dma->desc[i].flags = TX_BCNT(blksz) | TX_EOF | TX_BINT;
1229 1.1 macallan sc->sc_dma->desc[i].ba = dmabuf;
1230 1.1 macallan sc->sc_dma->desc[i].nda = dmabase + dbri_dma_off(desc, 0);
1231 1.1 macallan sc->sc_dma->desc[i].status = 0;
1232 1.1 macallan
1233 1.1 macallan dd->callback = callback; //sc->intr;
1234 1.1 macallan dd->callback_args = callback_args; //sc->intrarg;
1235 1.1 macallan
1236 1.1 macallan x = splaudio();
1237 1.1 macallan
1238 1.1 macallan /* the pipe shouldn't be active */
1239 1.1 macallan if (pipe_active(sc, pipe)) {
1240 1.1 macallan printf("pipe active (CDP)\n");
1241 1.1 macallan /* pipe is already active */
1242 1.1 macallan #if 0
1243 1.1 macallan td_last = sc->sc_pipe[pipe].desc;
1244 1.1 macallan while (sc->sc_desc[td_last].next != -1)
1245 1.1 macallan td_last = sc->sc_desc[td_last].next;
1246 1.1 macallan
1247 1.1 macallan sc->sc_desc[td_last].next = td_first;
1248 1.1 macallan sc->sc_dma->desc[td_last].nda =
1249 1.1 macallan sc->sc_dmabase + dbri_dma_off(desc, td_first);
1250 1.1 macallan
1251 1.1 macallan cmd = dbri_command_lock(sc);
1252 1.1 macallan *(cmd++) = DBRI_CMD(DBRI_COMMAND_CDP, 0, pipe);
1253 1.1 macallan dbri_command_send(sc, cmd);
1254 1.1 macallan #endif
1255 1.1 macallan } else {
1256 1.1 macallan /*
1257 1.1 macallan * pipe isn't active - issue an SDP command to start our
1258 1.1 macallan * chain of TDs running
1259 1.1 macallan */
1260 1.1 macallan sc->sc_pipe[pipe].desc = which;
1261 1.1 macallan cmd = dbri_command_lock(sc);
1262 1.1 macallan *(cmd++) = DBRI_CMD(DBRI_COMMAND_SDP, 0,
1263 1.1 macallan sc->sc_pipe[pipe].sdp |
1264 1.1 macallan DBRI_SDP_VALID_POINTER |
1265 1.1 macallan DBRI_SDP_EVERY |
1266 1.1 macallan DBRI_SDP_CLEAR);
1267 1.1 macallan *(cmd++) = sc->sc_dmabase + dbri_dma_off(desc, 0);
1268 1.1 macallan dbri_command_send(sc, cmd);
1269 1.1 macallan }
1270 1.1 macallan
1271 1.1 macallan splx(x);
1272 1.1 macallan
1273 1.1 macallan return;
1274 1.1 macallan }
1275 1.1 macallan
1276 1.1 macallan void
1277 1.1 macallan pipe_ts_link(struct dbri_softc *sc, int pipe, enum io dir, int basepipe,
1278 1.1 macallan int len, int cycle)
1279 1.1 macallan {
1280 1.1 macallan volatile u_int32_t *cmd;
1281 1.1 macallan int prevpipe, nextpipe;
1282 1.1 macallan int val;
1283 1.1 macallan
1284 1.1 macallan if (pipe < 0 || pipe >= DBRI_PIPE_MAX ||
1285 1.1 macallan basepipe < 0 || basepipe >= DBRI_PIPE_MAX) {
1286 1.1 macallan printf("%s: illegal pipe numbers (%d, %d)\n",
1287 1.1 macallan sc->sc_dev.dv_xname, pipe, basepipe);
1288 1.1 macallan return;
1289 1.1 macallan }
1290 1.1 macallan
1291 1.1 macallan if (sc->sc_pipe[pipe].sdp == 0 || sc->sc_pipe[basepipe].sdp == 0) {
1292 1.1 macallan printf("%s: uninitialized pipe (%d, %d)\n",
1293 1.1 macallan sc->sc_dev.dv_xname, pipe, basepipe);
1294 1.1 macallan return;
1295 1.1 macallan }
1296 1.1 macallan
1297 1.1 macallan if (basepipe == 16 && dir == PIPEoutput && cycle == 0)
1298 1.1 macallan cycle = sc->sc_chi_bpf;
1299 1.1 macallan
1300 1.1 macallan if (basepipe == pipe)
1301 1.1 macallan prevpipe = nextpipe = pipe;
1302 1.1 macallan else {
1303 1.1 macallan if (basepipe == 16) {
1304 1.1 macallan if (dir == PIPEinput) {
1305 1.1 macallan prevpipe = sc->sc_chi_pipe_in;
1306 1.1 macallan } else {
1307 1.1 macallan prevpipe = sc->sc_chi_pipe_out;
1308 1.1 macallan }
1309 1.1 macallan } else
1310 1.1 macallan prevpipe = basepipe;
1311 1.1 macallan
1312 1.1 macallan nextpipe = sc->sc_pipe[prevpipe].next;
1313 1.1 macallan
1314 1.1 macallan while (sc->sc_pipe[nextpipe].cycle < cycle &&
1315 1.1 macallan sc->sc_pipe[nextpipe].next != basepipe) {
1316 1.1 macallan prevpipe = nextpipe;
1317 1.1 macallan nextpipe = sc->sc_pipe[nextpipe].next;
1318 1.1 macallan }
1319 1.1 macallan }
1320 1.1 macallan
1321 1.1 macallan if (prevpipe == 16) {
1322 1.1 macallan if (dir == PIPEinput) {
1323 1.1 macallan sc->sc_chi_pipe_in = pipe;
1324 1.1 macallan } else {
1325 1.1 macallan sc->sc_chi_pipe_out = pipe;
1326 1.1 macallan }
1327 1.1 macallan } else
1328 1.1 macallan sc->sc_pipe[prevpipe].next = pipe;
1329 1.1 macallan
1330 1.1 macallan sc->sc_pipe[pipe].next = nextpipe;
1331 1.1 macallan sc->sc_pipe[pipe].cycle = cycle;
1332 1.1 macallan sc->sc_pipe[pipe].length = len;
1333 1.1 macallan
1334 1.1 macallan cmd = dbri_command_lock(sc);
1335 1.1 macallan
1336 1.1 macallan switch (dir) {
1337 1.1 macallan case PIPEinput:
1338 1.1 macallan val = DBRI_DTS_VI | DBRI_DTS_INS | DBRI_DTS_PRVIN(prevpipe);
1339 1.1 macallan val |= pipe;
1340 1.1 macallan *(cmd++) = DBRI_CMD(DBRI_COMMAND_DTS, 0, val);
1341 1.1 macallan *(cmd++) = DBRI_TS_LEN(len) | DBRI_TS_CYCLE(cycle) |
1342 1.1 macallan DBRI_TS_NEXT(nextpipe);
1343 1.1 macallan *(cmd++) = 0;
1344 1.1 macallan break;
1345 1.1 macallan case PIPEoutput:
1346 1.1 macallan val = DBRI_DTS_VO | DBRI_DTS_INS | DBRI_DTS_PRVOUT(prevpipe);
1347 1.1 macallan val |= pipe;
1348 1.1 macallan *(cmd++) = DBRI_CMD(DBRI_COMMAND_DTS, 0, val);
1349 1.1 macallan *(cmd++) = 0;
1350 1.1 macallan *(cmd++) = DBRI_TS_LEN(len) | DBRI_TS_CYCLE(cycle) |
1351 1.1 macallan DBRI_TS_NEXT(nextpipe);
1352 1.1 macallan break;
1353 1.1 macallan default:
1354 1.1 macallan printf("%s: should not have happened!\n",
1355 1.1 macallan sc->sc_dev.dv_xname);
1356 1.1 macallan break;
1357 1.1 macallan }
1358 1.1 macallan
1359 1.1 macallan dbri_command_send(sc, cmd);
1360 1.1 macallan
1361 1.1 macallan return;
1362 1.1 macallan }
1363 1.1 macallan
1364 1.1 macallan int
1365 1.1 macallan pipe_active(struct dbri_softc *sc, int pipe)
1366 1.1 macallan {
1367 1.1 macallan
1368 1.1 macallan return (sc->sc_pipe[pipe].desc != -1);
1369 1.1 macallan }
1370 1.1 macallan
1371 1.1 macallan /*
1372 1.1 macallan * subroutines required to interface with audio(9)
1373 1.1 macallan */
1374 1.1 macallan
1375 1.1 macallan int
1376 1.1 macallan dbri_query_encoding(void *hdl, struct audio_encoding *ae)
1377 1.1 macallan {
1378 1.1 macallan
1379 1.1 macallan /* XXX we shouldn't claim we support LE samples */
1380 1.1 macallan switch (ae->index) {
1381 1.1 macallan case 0:
1382 1.1 macallan strcpy(ae->name, AudioEulinear);
1383 1.1 macallan ae->encoding = AUDIO_ENCODING_ULINEAR;
1384 1.1 macallan ae->precision = 8;
1385 1.1 macallan ae->flags = AUDIO_ENCODINGFLAG_EMULATED;
1386 1.1 macallan break;
1387 1.1 macallan case 1:
1388 1.1 macallan strcpy(ae->name, AudioEmulaw);
1389 1.1 macallan ae->encoding = AUDIO_ENCODING_ULAW;
1390 1.1 macallan ae->precision = 8;
1391 1.1 macallan ae->flags = 0;
1392 1.1 macallan break;
1393 1.1 macallan case 2:
1394 1.1 macallan strcpy(ae->name, AudioEalaw);
1395 1.1 macallan ae->encoding = AUDIO_ENCODING_ALAW;
1396 1.1 macallan ae->precision = 8;
1397 1.1 macallan ae->flags = 0;
1398 1.1 macallan break;
1399 1.1 macallan case 3:
1400 1.1 macallan strcpy(ae->name, AudioEslinear);
1401 1.1 macallan ae->encoding = AUDIO_ENCODING_SLINEAR;
1402 1.1 macallan ae->precision = 8;
1403 1.1 macallan ae->flags = AUDIO_ENCODINGFLAG_EMULATED;
1404 1.1 macallan break;
1405 1.1 macallan case 4:
1406 1.1 macallan strcpy(ae->name, AudioEslinear_le);
1407 1.1 macallan ae->encoding = AUDIO_ENCODING_SLINEAR_LE;
1408 1.1 macallan ae->precision = 16;
1409 1.1 macallan ae->flags = AUDIO_ENCODINGFLAG_EMULATED;
1410 1.1 macallan break;
1411 1.1 macallan case 5:
1412 1.1 macallan strcpy(ae->name, AudioEulinear_le);
1413 1.1 macallan ae->encoding = AUDIO_ENCODING_ULINEAR_LE;
1414 1.1 macallan ae->precision = 16;
1415 1.1 macallan ae->flags = AUDIO_ENCODINGFLAG_EMULATED;
1416 1.1 macallan break;
1417 1.1 macallan case 6:
1418 1.1 macallan strcpy(ae->name, AudioEslinear_be);
1419 1.1 macallan ae->encoding = AUDIO_ENCODING_SLINEAR_BE;
1420 1.1 macallan ae->precision = 16;
1421 1.1 macallan ae->flags = 0;
1422 1.1 macallan break;
1423 1.1 macallan case 7:
1424 1.1 macallan strcpy(ae->name, AudioEulinear_be);
1425 1.1 macallan ae->encoding = AUDIO_ENCODING_ULINEAR_BE;
1426 1.1 macallan ae->precision = 16;
1427 1.1 macallan ae->flags = 0;
1428 1.1 macallan break;
1429 1.1 macallan default:
1430 1.1 macallan return (EINVAL);
1431 1.1 macallan }
1432 1.1 macallan
1433 1.1 macallan return (0);
1434 1.1 macallan }
1435 1.1 macallan
1436 1.1 macallan /*
1437 1.1 macallan * XXX: recording isn't supported - jmcneill
1438 1.1 macallan */
1439 1.1 macallan int
1440 1.1 macallan dbri_set_params(void *hdl, int setmode, int usemode,
1441 1.1 macallan struct audio_params *play, struct audio_params *rec,
1442 1.1 macallan stream_filter_list_t *pfil, stream_filter_list_t *rfil)
1443 1.1 macallan {
1444 1.1 macallan struct dbri_softc *sc = hdl;
1445 1.1 macallan int i;
1446 1.1 macallan
1447 1.1 macallan if ((play->precision != 8 && play->precision != 16) ||
1448 1.1 macallan (play->channels != 1 && play->channels != 2))
1449 1.1 macallan return (EINVAL);
1450 1.1 macallan
1451 1.1 macallan for (i = 0; CS4215_FREQ[i].freq; i++)
1452 1.1 macallan if (CS4215_FREQ[i].freq == play->sample_rate)
1453 1.1 macallan break;
1454 1.1 macallan
1455 1.1 macallan if (CS4215_FREQ[i].freq == 0)
1456 1.1 macallan return (EINVAL);
1457 1.1 macallan
1458 1.1 macallan /* set frequency */
1459 1.1 macallan sc->sc_mm.control[1] &= ~0x38;
1460 1.1 macallan sc->sc_mm.control[1] |= CS4215_FREQ[i].csval;
1461 1.1 macallan sc->sc_mm.control[2] &= ~0x70;
1462 1.1 macallan sc->sc_mm.control[2] |= CS4215_FREQ[i].xtal;
1463 1.1 macallan
1464 1.1 macallan /*play->factor = 1;
1465 1.1 macallan play->sw_code = NULL;*/
1466 1.1 macallan
1467 1.1 macallan switch (play->encoding) {
1468 1.1 macallan case AUDIO_ENCODING_ULAW:
1469 1.1 macallan sc->sc_mm.control[1] &= ~3;
1470 1.1 macallan sc->sc_mm.control[1] |= CS4215_DFR_ULAW;
1471 1.1 macallan break;
1472 1.1 macallan case AUDIO_ENCODING_ALAW:
1473 1.1 macallan sc->sc_mm.control[1] &= ~3;
1474 1.1 macallan sc->sc_mm.control[1] |= CS4215_DFR_ALAW;
1475 1.1 macallan break;
1476 1.1 macallan case AUDIO_ENCODING_SLINEAR_LE:
1477 1.1 macallan case AUDIO_ENCODING_ULINEAR_LE:
1478 1.1 macallan if (play->precision == 16) {
1479 1.1 macallan /* XXX this surely needs some changes elsewhere */
1480 1.1 macallan /*play->sw_code = swap_bytes;*/
1481 1.1 macallan sc->sc_mm.control[1] &= ~3;
1482 1.1 macallan sc->sc_mm.control[1] |= CS4215_DFR_LINEAR16;
1483 1.1 macallan }
1484 1.1 macallan break;
1485 1.1 macallan case AUDIO_ENCODING_ULINEAR:
1486 1.1 macallan case AUDIO_ENCODING_SLINEAR:
1487 1.1 macallan sc->sc_mm.control[1] &= ~3;
1488 1.1 macallan if (play->precision == 8) {
1489 1.1 macallan sc->sc_mm.control[1] |= CS4215_DFR_LINEAR8;
1490 1.1 macallan } else {
1491 1.1 macallan sc->sc_mm.control[1] |= CS4215_DFR_LINEAR16;
1492 1.1 macallan }
1493 1.1 macallan break;
1494 1.1 macallan case AUDIO_ENCODING_ULINEAR_BE:
1495 1.1 macallan case AUDIO_ENCODING_SLINEAR_BE:
1496 1.1 macallan sc->sc_mm.control[1] &= ~3;
1497 1.1 macallan sc->sc_mm.control[1] |= CS4215_DFR_LINEAR16;
1498 1.1 macallan break;
1499 1.1 macallan }
1500 1.1 macallan
1501 1.1 macallan switch (play->channels) {
1502 1.1 macallan case 1:
1503 1.1 macallan sc->sc_mm.control[1] &= ~CS4215_DFR_STEREO;
1504 1.1 macallan break;
1505 1.1 macallan case 2:
1506 1.1 macallan sc->sc_mm.control[1] |= CS4215_DFR_STEREO;
1507 1.1 macallan break;
1508 1.1 macallan }
1509 1.1 macallan
1510 1.1 macallan return (0);
1511 1.1 macallan }
1512 1.1 macallan
1513 1.1 macallan int
1514 1.1 macallan dbri_round_blocksize(void *hdl, int bs, int mode,
1515 1.1 macallan const audio_params_t *param)
1516 1.1 macallan {
1517 1.1 macallan
1518 1.1 macallan /* DBRI DMA segment size, rounded town to 32bit alignment */
1519 1.1 macallan return 0x1ffc;
1520 1.1 macallan }
1521 1.1 macallan
1522 1.1 macallan int
1523 1.1 macallan dbri_halt_output(void *hdl)
1524 1.1 macallan {
1525 1.1 macallan struct dbri_softc *sc = hdl;
1526 1.1 macallan
1527 1.1 macallan pipe_reset(sc, 4);
1528 1.1 macallan
1529 1.1 macallan return (0);
1530 1.1 macallan }
1531 1.1 macallan
1532 1.1 macallan int
1533 1.1 macallan dbri_getdev(void *hdl, struct audio_device *ret)
1534 1.1 macallan {
1535 1.1 macallan
1536 1.1 macallan *ret = dbri_device;
1537 1.1 macallan return (0);
1538 1.1 macallan }
1539 1.1 macallan
1540 1.1 macallan int
1541 1.1 macallan dbri_set_port(void *hdl, mixer_ctrl_t *mc)
1542 1.1 macallan {
1543 1.1 macallan struct dbri_softc *sc = hdl;
1544 1.1 macallan int latt = sc->sc_latt, ratt = sc->sc_ratt;
1545 1.1 macallan
1546 1.1 macallan switch (mc->dev) {
1547 1.1 macallan case DBRI_VOL_OUTPUT: /* master volume */
1548 1.1 macallan latt = (latt & 0xc0) | (63 -
1549 1.1 macallan min(mc->un.value.level[AUDIO_MIXER_LEVEL_LEFT] >> 2, 63));
1550 1.1 macallan ratt = (ratt & 0xc0) | (63 -
1551 1.1 macallan min(mc->un.value.level[AUDIO_MIXER_LEVEL_RIGHT] >> 2, 63));
1552 1.1 macallan break;
1553 1.1 macallan case DBRI_ENABLE_MONO: /* built-in speaker */
1554 1.1 macallan if (mc->un.ord == 1) {
1555 1.1 macallan ratt |= CS4215_SE;
1556 1.1 macallan } else
1557 1.1 macallan ratt &= ~CS4215_SE;
1558 1.1 macallan break;
1559 1.1 macallan case DBRI_ENABLE_HEADPHONE: /* headphones output */
1560 1.1 macallan if (mc->un.ord == 1) {
1561 1.1 macallan latt |= CS4215_HE;
1562 1.1 macallan } else
1563 1.1 macallan latt &= ~CS4215_HE;
1564 1.1 macallan break;
1565 1.1 macallan case DBRI_ENABLE_LINE: /* line out */
1566 1.1 macallan if (mc->un.ord == 1) {
1567 1.1 macallan latt |= CS4215_LE;
1568 1.1 macallan } else
1569 1.1 macallan latt &= ~CS4215_LE;
1570 1.1 macallan break;
1571 1.1 macallan }
1572 1.1 macallan
1573 1.1 macallan sc->sc_latt = latt;
1574 1.1 macallan sc->sc_ratt = ratt;
1575 1.1 macallan
1576 1.1 macallan /* no need to do that here - mmcodec_setgain does it anyway */
1577 1.1 macallan /*pipe_transmit_fixed(sc, 20, *(int *)__UNVOLATILE(sc->sc_mm.data));*/
1578 1.1 macallan
1579 1.1 macallan mmcodec_setgain(sc, 0);
1580 1.1 macallan
1581 1.1 macallan return (0);
1582 1.1 macallan }
1583 1.1 macallan
1584 1.1 macallan int
1585 1.1 macallan dbri_get_port(void *hdl, mixer_ctrl_t *mc)
1586 1.1 macallan {
1587 1.1 macallan struct dbri_softc *sc = hdl;
1588 1.1 macallan
1589 1.1 macallan switch (mc->dev) {
1590 1.1 macallan case DBRI_VOL_OUTPUT: /* master volume */
1591 1.1 macallan mc->un.value.level[AUDIO_MIXER_LEVEL_LEFT] =
1592 1.1 macallan (63 - (sc->sc_latt & 0x3f)) << 2;
1593 1.1 macallan mc->un.value.level[AUDIO_MIXER_LEVEL_RIGHT] =
1594 1.1 macallan (63 - (sc->sc_ratt & 0x3f)) << 2;
1595 1.1 macallan return (0);
1596 1.1 macallan case DBRI_ENABLE_MONO: /* built-in speaker */
1597 1.1 macallan mc->un.ord = (sc->sc_ratt & CS4215_SE) ? 1 : 0;
1598 1.1 macallan return 0;
1599 1.1 macallan case DBRI_ENABLE_HEADPHONE: /* headphones output */
1600 1.1 macallan mc->un.ord = (sc->sc_latt & CS4215_HE) ? 1 : 0;
1601 1.1 macallan return 0;
1602 1.1 macallan case DBRI_ENABLE_LINE: /* line out */
1603 1.1 macallan mc->un.ord = (sc->sc_latt & CS4215_LE) ? 1 : 0;
1604 1.1 macallan return 0;
1605 1.1 macallan }
1606 1.1 macallan return (EINVAL);
1607 1.1 macallan }
1608 1.1 macallan
1609 1.1 macallan int
1610 1.1 macallan dbri_query_devinfo(void *hdl, mixer_devinfo_t *di)
1611 1.1 macallan {
1612 1.1 macallan
1613 1.1 macallan switch (di->index) {
1614 1.1 macallan case DBRI_MONITOR_CLASS:
1615 1.1 macallan di->mixer_class = DBRI_MONITOR_CLASS;
1616 1.1 macallan strcpy(di->label.name, AudioCmonitor);
1617 1.1 macallan di->type = AUDIO_MIXER_CLASS;
1618 1.1 macallan di->next = di->prev = AUDIO_MIXER_LAST;
1619 1.1 macallan return 0;
1620 1.1 macallan case DBRI_VOL_OUTPUT: /* master volume */
1621 1.1 macallan di->mixer_class = DBRI_MONITOR_CLASS;
1622 1.1 macallan di->next = di->prev = AUDIO_MIXER_LAST;
1623 1.1 macallan strcpy(di->label.name, AudioNmaster);
1624 1.1 macallan di->type = AUDIO_MIXER_VALUE;
1625 1.1 macallan di->un.v.num_channels = 2;
1626 1.1 macallan strcpy(di->un.v.units.name, AudioNvolume);
1627 1.1 macallan return (0);
1628 1.1 macallan case DBRI_ENABLE_MONO: /* built-in speaker */
1629 1.1 macallan di->mixer_class = DBRI_MONITOR_CLASS;
1630 1.1 macallan di->next = di->prev = AUDIO_MIXER_LAST;
1631 1.1 macallan strcpy(di->label.name, AudioNmono);
1632 1.1 macallan di->type = AUDIO_MIXER_ENUM;
1633 1.1 macallan di->un.e.num_mem = 2;
1634 1.1 macallan strcpy(di->un.e.member[0].label.name, AudioNoff);
1635 1.1 macallan di->un.e.member[0].ord = 0;
1636 1.1 macallan strcpy(di->un.e.member[1].label.name, AudioNon);
1637 1.1 macallan di->un.e.member[1].ord = 1;
1638 1.1 macallan return (0);
1639 1.1 macallan case DBRI_ENABLE_HEADPHONE: /* headphones output */
1640 1.1 macallan di->mixer_class = DBRI_MONITOR_CLASS;
1641 1.1 macallan di->next = di->prev = AUDIO_MIXER_LAST;
1642 1.1 macallan strcpy(di->label.name, AudioNheadphone);
1643 1.1 macallan di->type = AUDIO_MIXER_ENUM;
1644 1.1 macallan di->un.e.num_mem = 2;
1645 1.1 macallan strcpy(di->un.e.member[0].label.name, AudioNoff);
1646 1.1 macallan di->un.e.member[0].ord = 0;
1647 1.1 macallan strcpy(di->un.e.member[1].label.name, AudioNon);
1648 1.1 macallan di->un.e.member[1].ord = 1;
1649 1.1 macallan return (0);
1650 1.1 macallan case DBRI_ENABLE_LINE: /* line out */
1651 1.1 macallan di->mixer_class = DBRI_MONITOR_CLASS;
1652 1.1 macallan di->next = di->prev = AUDIO_MIXER_LAST;
1653 1.1 macallan strcpy(di->label.name, AudioNline);
1654 1.1 macallan di->type = AUDIO_MIXER_ENUM;
1655 1.1 macallan di->un.e.num_mem = 2;
1656 1.1 macallan strcpy(di->un.e.member[0].label.name, AudioNoff);
1657 1.1 macallan di->un.e.member[0].ord = 0;
1658 1.1 macallan strcpy(di->un.e.member[1].label.name, AudioNon);
1659 1.1 macallan di->un.e.member[1].ord = 1;
1660 1.1 macallan return (0);
1661 1.1 macallan }
1662 1.1 macallan
1663 1.1 macallan return (ENXIO);
1664 1.1 macallan }
1665 1.1 macallan
1666 1.1 macallan size_t
1667 1.1 macallan dbri_round_buffersize(void *hdl, int dir, size_t bufsize)
1668 1.1 macallan {
1669 1.1 macallan #ifdef DBRI_BIG_BUFFER
1670 1.1 macallan return 16*0x1ffc; /* use ~128KB buffer */
1671 1.1 macallan #else
1672 1.1 macallan return bufsize;
1673 1.1 macallan #endif
1674 1.1 macallan }
1675 1.1 macallan
1676 1.1 macallan int
1677 1.1 macallan dbri_get_props(void *hdl)
1678 1.1 macallan {
1679 1.1 macallan
1680 1.1 macallan return (AUDIO_PROP_MMAP/* | AUDIO_PROP_INDEPENDENT*/);
1681 1.1 macallan //return (0);
1682 1.1 macallan }
1683 1.1 macallan
1684 1.1 macallan int
1685 1.1 macallan dbri_trigger_output(void *hdl, void *start, void *end, int blksize,
1686 1.1 macallan void (*intr)(void *), void *intrarg,
1687 1.1 macallan const struct audio_params *param)
1688 1.1 macallan {
1689 1.1 macallan struct dbri_softc *sc = hdl;
1690 1.1 macallan unsigned long count, current, num;
1691 1.1 macallan
1692 1.1 macallan count = (unsigned long)(((caddr_t)end - (caddr_t)start));
1693 1.1 macallan num = count / blksize;
1694 1.4 macallan
1695 1.4 macallan DPRINTF(("trigger_output(%lx %lx) : %d %ld %ld\n",
1696 1.1 macallan (unsigned long)intr,
1697 1.4 macallan (unsigned long)intrarg, blksize, count, num));
1698 1.4 macallan
1699 1.1 macallan sc->sc_params = *param;
1700 1.1 macallan
1701 1.1 macallan mmcodec_setcontrol(sc);
1702 1.1 macallan mmcodec_init_data(sc);
1703 1.1 macallan current = 0;
1704 1.1 macallan while ((current < sc->sc_desc_used) &&
1705 1.1 macallan (sc->sc_desc[current].buf != start))
1706 1.1 macallan current++;
1707 1.1 macallan
1708 1.1 macallan if (current < sc->sc_desc_used) {
1709 1.1 macallan setup_ring(sc, 4, current, num, blksize, intr, intrarg);
1710 1.1 macallan return 0;
1711 1.1 macallan }
1712 1.1 macallan return EINVAL;
1713 1.1 macallan }
1714 1.1 macallan
1715 1.1 macallan u_int32_t
1716 1.1 macallan reverse_bytes(u_int32_t b, int len)
1717 1.1 macallan {
1718 1.1 macallan switch (len) {
1719 1.1 macallan case 32:
1720 1.1 macallan b = ((b & 0xffff0000) >> 16) | ((b & 0x0000ffff) << 16);
1721 1.1 macallan case 16:
1722 1.1 macallan b = ((b & 0xff00ff00) >> 8) | ((b & 0x00ff00ff) << 8);
1723 1.1 macallan case 8:
1724 1.1 macallan b = ((b & 0xf0f0f0f0) >> 4) | ((b & 0x0f0f0f0f) << 4);
1725 1.1 macallan case 4:
1726 1.1 macallan b = ((b & 0xcccccccc) >> 2) | ((b & 0x33333333) << 2);
1727 1.1 macallan case 2:
1728 1.1 macallan b = ((b & 0xaaaaaaaa) >> 1) | ((b & 0x55555555) << 1);
1729 1.1 macallan case 1:
1730 1.1 macallan case 0:
1731 1.1 macallan break;
1732 1.1 macallan default:
1733 1.1 macallan printf("reverse_bytes: unsupported length\n");
1734 1.1 macallan };
1735 1.1 macallan
1736 1.1 macallan return (b);
1737 1.1 macallan }
1738 1.1 macallan
1739 1.1 macallan static void
1740 1.1 macallan *dbri_malloc(void *v, int dir, size_t s, struct malloc_type *mt, int flags)
1741 1.1 macallan {
1742 1.1 macallan struct dbri_softc *sc = v;
1743 1.1 macallan struct dbri_desc *dd = &sc->sc_desc[sc->sc_desc_used];
1744 1.1 macallan int rseg;
1745 1.1 macallan
1746 1.1 macallan if (bus_dmamap_create(sc->sc_dmat, s, 1, s, 0, BUS_DMA_NOWAIT,
1747 1.1 macallan &dd->dmamap) == 0) {
1748 1.1 macallan if (bus_dmamem_alloc(sc->sc_dmat, s, 0, 0, &dd->dmaseg,
1749 1.1 macallan 1, &rseg, BUS_DMA_NOWAIT) == 0) {
1750 1.1 macallan if (bus_dmamem_map(sc->sc_dmat, &dd->dmaseg, rseg, s,
1751 1.1 macallan &dd->buf, BUS_DMA_NOWAIT|BUS_DMA_COHERENT) == 0) {
1752 1.1 macallan if (dd->buf!=NULL) {
1753 1.1 macallan if (bus_dmamap_load(sc->sc_dmat,
1754 1.1 macallan dd->dmamap, dd->buf, s, NULL,
1755 1.1 macallan BUS_DMA_NOWAIT) == 0) {
1756 1.1 macallan dd->len = s;
1757 1.1 macallan dd->busy = 0;
1758 1.1 macallan dd->callback = NULL;
1759 1.1 macallan dd->dmabase =
1760 1.1 macallan dd->dmamap->dm_segs[0].ds_addr;
1761 1.4 macallan DPRINTF(("dbri_malloc: using buffer %d\n",
1762 1.4 macallan sc->sc_desc_used));
1763 1.1 macallan sc->sc_desc_used++;
1764 1.1 macallan return dd->buf;
1765 1.1 macallan } else
1766 1.1 macallan printf("dbri_malloc: load failed\n");
1767 1.1 macallan } else
1768 1.1 macallan printf("dbri_malloc: map returned NULL\n");
1769 1.1 macallan } else
1770 1.1 macallan printf("dbri_malloc: map failed\n");
1771 1.1 macallan bus_dmamem_free(sc->sc_dmat, &dd->dmaseg, rseg);
1772 1.1 macallan } else
1773 1.1 macallan printf("dbri_malloc: malloc() failed\n");
1774 1.1 macallan bus_dmamap_destroy(sc->sc_dmat, dd->dmamap);
1775 1.1 macallan } else
1776 1.1 macallan printf("dbri_malloc: bus_dmamap_create() failed\n");
1777 1.1 macallan return NULL;
1778 1.1 macallan }
1779 1.1 macallan
1780 1.1 macallan static void
1781 1.1 macallan dbri_free(void *v, void *p, struct malloc_type *mt)
1782 1.1 macallan {
1783 1.1 macallan free(p, mt);
1784 1.1 macallan }
1785 1.1 macallan
1786 1.1 macallan static paddr_t
1787 1.1 macallan dbri_mappage(void *v, void *mem, off_t off, int prot)
1788 1.1 macallan {
1789 1.1 macallan struct dbri_softc *sc = v;;
1790 1.1 macallan int current;
1791 1.1 macallan
1792 1.1 macallan if (off < 0)
1793 1.1 macallan return -1;
1794 1.1 macallan
1795 1.1 macallan current = 0;
1796 1.1 macallan while ((current < sc->sc_desc_used) &&
1797 1.1 macallan (sc->sc_desc[current].buf != mem))
1798 1.1 macallan current++;
1799 1.1 macallan
1800 1.1 macallan if (current < sc->sc_desc_used) {
1801 1.1 macallan return bus_dmamem_mmap(sc->sc_dmat,
1802 1.1 macallan &sc->sc_desc[current].dmaseg, 1, off, prot, BUS_DMA_WAITOK);
1803 1.1 macallan }
1804 1.1 macallan
1805 1.1 macallan return -1;
1806 1.1 macallan }
1807 1.1 macallan
1808 1.4 macallan static int
1809 1.4 macallan dbri_open(void *cookie, int flags)
1810 1.4 macallan {
1811 1.4 macallan struct dbri_softc *sc = cookie;
1812 1.4 macallan
1813 1.4 macallan dbri_bring_up(sc);
1814 1.4 macallan return 0;
1815 1.4 macallan }
1816 1.4 macallan
1817 1.4 macallan static void
1818 1.4 macallan dbri_close(void *cookie)
1819 1.4 macallan {
1820 1.4 macallan struct dbri_softc *sc = cookie;
1821 1.4 macallan
1822 1.4 macallan dbri_set_power(sc, 0);
1823 1.4 macallan }
1824 1.4 macallan
1825 1.4 macallan static void
1826 1.4 macallan dbri_powerhook(int why, void *cookie)
1827 1.4 macallan {
1828 1.4 macallan struct dbri_softc *sc = cookie;
1829 1.4 macallan
1830 1.4 macallan switch(why)
1831 1.4 macallan {
1832 1.4 macallan case PWR_SUSPEND:
1833 1.4 macallan case PWR_STANDBY:
1834 1.4 macallan dbri_set_power(sc, 0);
1835 1.4 macallan break;
1836 1.4 macallan case PWR_RESUME:
1837 1.4 macallan dbri_bring_up(sc);
1838 1.4 macallan break;
1839 1.4 macallan }
1840 1.4 macallan }
1841 1.4 macallan
1842 1.4 macallan #endif /* NAUDIO > 0 */
1843 1.4 macallan
1844