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dbri.c revision 1.9.2.2
      1  1.9.2.2        ad /*	$NetBSD: dbri.c,v 1.9.2.2 2007/04/10 13:24:33 ad Exp $	*/
      2      1.1  macallan 
      3      1.1  macallan /*
      4      1.2  macallan  * Copyright (C) 1997 Rudolf Koenig (rfkoenig (at) immd4.informatik.uni-erlangen.de)
      5      1.2  macallan  * Copyright (c) 1998, 1999 Brent Baccala (baccala (at) freesoft.org)
      6      1.2  macallan  * Copyright (c) 2001, 2002 Jared D. McNeill <jmcneill (at) netbsd.org>
      7      1.1  macallan  * Copyright (c) 2005 Michael Lorenz <macallan (at) netbsd.org>
      8      1.1  macallan  * All rights reserved.
      9      1.1  macallan  *
     10      1.5     blymn  * This driver is losely based on a Linux driver written by Rudolf Koenig and
     11      1.5     blymn  * Brent Baccala who kindly gave their permission to use their code in a
     12      1.2  macallan  * BSD-licensed driver.
     13      1.2  macallan  *
     14      1.1  macallan  * Redistribution and use in source and binary forms, with or without
     15      1.1  macallan  * modification, are permitted provided that the following conditions
     16      1.1  macallan  * are met:
     17      1.1  macallan  * 1. Redistributions of source code must retain the above copyright
     18      1.1  macallan  *    notice, this list of conditions and the following disclaimer.
     19      1.1  macallan  * 2. Redistributions in binary form must reproduce the above copyright
     20      1.1  macallan  *    notice, this list of conditions and the following disclaimer in the
     21      1.1  macallan  *    documentation and/or other materials provided with the distribution.
     22      1.1  macallan  * 3. All advertising materials mentioning features or use of this software
     23      1.1  macallan  *    must display the following acknowledgement:
     24      1.5     blymn  *	This product includes software developed by Rudolf Koenig, Brent
     25      1.2  macallan  *      Baccala, Jared D. McNeill.
     26      1.1  macallan  * 4. Neither the name of the author nor the names of any contributors may
     27      1.1  macallan  *    be used to endorse or promote products derived from this software
     28      1.1  macallan  *    without specific prior written permission.
     29      1.1  macallan  *
     30      1.1  macallan  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
     31      1.1  macallan  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
     32      1.1  macallan  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
     33      1.1  macallan  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
     34      1.1  macallan  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
     35      1.1  macallan  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
     36      1.1  macallan  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     37      1.1  macallan  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     38      1.1  macallan  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     39      1.1  macallan  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     40      1.1  macallan  * SUCH DAMAGE.
     41      1.1  macallan  *
     42      1.1  macallan  */
     43      1.1  macallan 
     44      1.1  macallan #include <sys/cdefs.h>
     45  1.9.2.2        ad __KERNEL_RCSID(0, "$NetBSD: dbri.c,v 1.9.2.2 2007/04/10 13:24:33 ad Exp $");
     46      1.1  macallan 
     47      1.1  macallan #include "audio.h"
     48      1.1  macallan #if NAUDIO > 0
     49      1.1  macallan 
     50      1.1  macallan #include <sys/param.h>
     51      1.1  macallan #include <sys/systm.h>
     52      1.1  macallan #include <sys/errno.h>
     53      1.1  macallan #include <sys/device.h>
     54      1.1  macallan #include <sys/malloc.h>
     55      1.1  macallan #include <sys/proc.h>
     56      1.1  macallan 
     57      1.1  macallan #include <machine/bus.h>
     58      1.1  macallan #include <machine/intr.h>
     59      1.1  macallan 
     60      1.1  macallan #include <dev/sbus/sbusvar.h>
     61      1.1  macallan #include <sparc/sparc/auxreg.h>
     62      1.1  macallan #include <machine/autoconf.h>
     63      1.1  macallan 
     64      1.1  macallan #include <sys/audioio.h>
     65      1.1  macallan #include <dev/audio_if.h>
     66      1.1  macallan #include <dev/auconv.h>
     67      1.1  macallan 
     68      1.1  macallan #include <dev/ic/cs4215reg.h>
     69      1.1  macallan #include <dev/ic/cs4215var.h>
     70      1.1  macallan #include <dev/sbus/dbrireg.h>
     71      1.1  macallan #include <dev/sbus/dbrivar.h>
     72      1.1  macallan 
     73      1.4  macallan #include "opt_sbus_dbri.h"
     74      1.4  macallan 
     75      1.1  macallan #define DBRI_ROM_NAME_PREFIX		"SUNW,DBRI"
     76      1.1  macallan 
     77      1.4  macallan #ifdef DBRI_DEBUG
     78  1.9.2.1        ad # define DPRINTF aprint_normal
     79      1.4  macallan #else
     80  1.9.2.1        ad # define DPRINTF while (0) printf
     81      1.4  macallan #endif
     82      1.1  macallan 
     83      1.1  macallan static const char *dbri_supported[] = {
     84      1.1  macallan 	"e",
     85      1.1  macallan 	"s3",
     86      1.1  macallan 	""
     87      1.1  macallan };
     88      1.1  macallan 
     89      1.1  macallan enum ms {
     90      1.1  macallan 	CHImaster,
     91      1.1  macallan 	CHIslave
     92      1.1  macallan };
     93      1.1  macallan 
     94      1.1  macallan enum io {
     95      1.1  macallan 	PIPEinput,
     96      1.1  macallan 	PIPEoutput
     97      1.1  macallan };
     98      1.1  macallan 
     99      1.1  macallan /*
    100      1.1  macallan  * Function prototypes
    101      1.1  macallan  */
    102      1.1  macallan 
    103      1.1  macallan /* softc stuff */
    104      1.1  macallan static void	dbri_attach_sbus(struct device *, struct device *, void *);
    105      1.1  macallan static int	dbri_match_sbus(struct device *, struct cfdata *, void *);
    106      1.1  macallan 
    107      1.1  macallan static void	dbri_config_interrupts(struct device *);
    108      1.1  macallan 
    109      1.1  macallan /* interrupt handler */
    110      1.1  macallan static int	dbri_intr(void *);
    111      1.1  macallan 
    112      1.1  macallan /* supporting subroutines */
    113      1.1  macallan static int	dbri_init(struct dbri_softc *);
    114      1.1  macallan static int	dbri_reset(struct dbri_softc *);
    115      1.1  macallan static volatile u_int32_t *dbri_command_lock(struct dbri_softc *);
    116      1.1  macallan static void	dbri_command_send(struct dbri_softc *, volatile u_int32_t *);
    117      1.1  macallan static void	dbri_process_interrupt_buffer(struct dbri_softc *);
    118      1.1  macallan static void	dbri_process_interrupt(struct dbri_softc *, int32_t);
    119      1.1  macallan 
    120      1.1  macallan /* mmcodec subroutines */
    121      1.1  macallan static int	mmcodec_init(struct dbri_softc *);
    122      1.1  macallan static void	mmcodec_init_data(struct dbri_softc *);
    123      1.1  macallan static void	mmcodec_pipe_init(struct dbri_softc *);
    124      1.1  macallan static void	mmcodec_default(struct dbri_softc *);
    125      1.1  macallan static void	mmcodec_setgain(struct dbri_softc *, int);
    126      1.1  macallan static int	mmcodec_setcontrol(struct dbri_softc *);
    127      1.1  macallan 
    128      1.1  macallan /* chi subroutines */
    129      1.1  macallan static void	chi_reset(struct dbri_softc *, enum ms, int);
    130      1.1  macallan 
    131      1.1  macallan /* pipe subroutines */
    132      1.1  macallan static void	pipe_setup(struct dbri_softc *, int, int);
    133      1.1  macallan static void	pipe_reset(struct dbri_softc *, int);
    134      1.5     blymn static void	pipe_receive_fixed(struct dbri_softc *, int,
    135      1.1  macallan     volatile u_int32_t *);
    136      1.1  macallan static void	pipe_transmit_fixed(struct dbri_softc *, int, u_int32_t);
    137      1.1  macallan 
    138      1.1  macallan static void	pipe_ts_link(struct dbri_softc *, int, enum io, int, int, int);
    139      1.1  macallan static int	pipe_active(struct dbri_softc *, int);
    140      1.1  macallan 
    141      1.1  macallan /* audio(9) stuff */
    142      1.1  macallan static int	dbri_query_encoding(void *, struct audio_encoding *);
    143      1.1  macallan static int	dbri_set_params(void *, int, int, struct audio_params *,
    144      1.1  macallan     struct audio_params *,stream_filter_list_t *, stream_filter_list_t *);
    145      1.1  macallan static int	dbri_round_blocksize(void *, int, int, const audio_params_t *);
    146      1.1  macallan static int	dbri_halt_output(void *);
    147  1.9.2.2        ad static int	dbri_halt_input(void *);
    148      1.1  macallan static int	dbri_getdev(void *, struct audio_device *);
    149      1.1  macallan static int	dbri_set_port(void *, mixer_ctrl_t *);
    150      1.1  macallan static int	dbri_get_port(void *, mixer_ctrl_t *);
    151      1.1  macallan static int	dbri_query_devinfo(void *, mixer_devinfo_t *);
    152      1.1  macallan static size_t	dbri_round_buffersize(void *, int, size_t);
    153      1.1  macallan static int	dbri_get_props(void *);
    154      1.4  macallan static int	dbri_open(void *, int);
    155      1.4  macallan static void	dbri_close(void *);
    156      1.1  macallan 
    157  1.9.2.1        ad static void	setup_ring(struct dbri_softc *, int, int, int, int,
    158  1.9.2.1        ad     void (*)(void *), void *);
    159      1.1  macallan 
    160      1.5     blymn static int	dbri_trigger_output(void *, void *, void *, int,
    161      1.1  macallan     void (*)(void *), void *, const struct audio_params *);
    162  1.9.2.2        ad static int	dbri_trigger_input(void *, void *, void *, int,
    163  1.9.2.2        ad     void (*)(void *), void *, const struct audio_params *);
    164      1.1  macallan 
    165      1.1  macallan static void	*dbri_malloc(void *, int, size_t, struct malloc_type *, int);
    166      1.1  macallan static void	dbri_free(void *, void *, struct malloc_type *);
    167      1.1  macallan static paddr_t	dbri_mappage(void *, void *, off_t, int);
    168      1.4  macallan static void	dbri_set_power(struct dbri_softc *, int);
    169      1.4  macallan static void	dbri_bring_up(struct dbri_softc *);
    170      1.4  macallan static void	dbri_powerhook(int, void *);
    171      1.1  macallan 
    172      1.1  macallan /* stupid support routines */
    173      1.1  macallan static u_int32_t	reverse_bytes(u_int32_t, int);
    174      1.1  macallan 
    175      1.1  macallan struct audio_device dbri_device = {
    176      1.1  macallan 	"CS4215",
    177      1.1  macallan 	"",
    178      1.1  macallan 	"dbri"
    179      1.1  macallan };
    180      1.1  macallan 
    181      1.1  macallan struct audio_hw_if dbri_hw_if = {
    182      1.4  macallan 	dbri_open,
    183      1.4  macallan 	dbri_close,
    184      1.1  macallan 	NULL,	/* drain */
    185      1.1  macallan 	dbri_query_encoding,
    186      1.1  macallan 	dbri_set_params,
    187      1.1  macallan 	dbri_round_blocksize,
    188      1.1  macallan 	NULL,	/* commit_settings */
    189      1.1  macallan 	NULL,	/* init_output */
    190      1.1  macallan 	NULL,	/* init_input */
    191      1.1  macallan 	NULL,	/* start_output */
    192      1.1  macallan 	NULL,	/* start_input */
    193      1.1  macallan 	dbri_halt_output,
    194  1.9.2.2        ad 	dbri_halt_input,
    195      1.1  macallan 	NULL,	/* speaker_ctl */
    196      1.1  macallan 	dbri_getdev,
    197      1.1  macallan 	NULL,	/* setfd */
    198      1.1  macallan 	dbri_set_port,
    199      1.1  macallan 	dbri_get_port,
    200      1.1  macallan 	dbri_query_devinfo,
    201      1.1  macallan 	dbri_malloc,
    202      1.1  macallan 	dbri_free,
    203      1.1  macallan 	dbri_round_buffersize,
    204      1.1  macallan 	dbri_mappage,
    205      1.1  macallan 	dbri_get_props,
    206      1.1  macallan 	dbri_trigger_output,
    207  1.9.2.2        ad 	dbri_trigger_input
    208      1.1  macallan };
    209      1.1  macallan 
    210      1.1  macallan CFATTACH_DECL(dbri, sizeof(struct dbri_softc),
    211      1.1  macallan     dbri_match_sbus, dbri_attach_sbus, NULL, NULL);
    212      1.1  macallan 
    213  1.9.2.1        ad #define DBRI_NFORMATS		7
    214  1.9.2.1        ad static const struct audio_format dbri_formats[DBRI_NFORMATS] = {
    215  1.9.2.1        ad 	{NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_SLINEAR_BE, 16, 16,
    216  1.9.2.1        ad 	 2, AUFMT_STEREO, 8, {8000, 9600, 11025, 16000, 22050, 32000, 44100, 48000}},
    217  1.9.2.1        ad 	{NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_ULAW, 8, 8,
    218  1.9.2.1        ad 	 2, AUFMT_STEREO, 8, {8000, 9600, 11025, 16000, 22050, 32000, 44100, 48000}},
    219  1.9.2.1        ad 	{NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_ALAW, 8, 8,
    220  1.9.2.1        ad 	 2, AUFMT_STEREO, 8, {8000, 9600, 11025, 16000, 22050, 32000, 44100, 48000}},
    221  1.9.2.1        ad 	{NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_ULINEAR, 8, 8,
    222  1.9.2.1        ad 	 2, AUFMT_STEREO, 8, {8000, 9600, 11025, 16000, 22050, 32000, 44100, 48000}},
    223  1.9.2.1        ad 	{NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_ULAW, 8, 8,
    224  1.9.2.1        ad 	 1, AUFMT_STEREO, 8, {8000, 9600, 11025, 16000, 22050, 32000, 44100, 48000}},
    225  1.9.2.1        ad 	{NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_ALAW, 8, 8,
    226  1.9.2.1        ad 	 1, AUFMT_STEREO, 8, {8000, 9600, 11025, 16000, 22050, 32000, 44100, 48000}},
    227  1.9.2.1        ad 	{NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_ULINEAR, 8, 8,
    228  1.9.2.1        ad 	 1, AUFMT_STEREO, 8, {8000, 9600, 11025, 16000, 22050, 32000, 44100, 48000}},
    229  1.9.2.1        ad };
    230  1.9.2.1        ad 
    231      1.1  macallan enum {
    232  1.9.2.2        ad 	DBRI_OUTPUT_CLASS,
    233      1.1  macallan 	DBRI_VOL_OUTPUT,
    234      1.1  macallan 	DBRI_ENABLE_MONO,
    235      1.1  macallan 	DBRI_ENABLE_HEADPHONE,
    236  1.9.2.2        ad 	DBRI_ENABLE_LINE,
    237  1.9.2.2        ad 	DBRI_MONITOR_CLASS,
    238  1.9.2.2        ad 	DBRI_VOL_MONITOR,
    239      1.1  macallan 	DBRI_INPUT_CLASS,
    240      1.1  macallan 	DBRI_INPUT_GAIN,
    241      1.1  macallan 	DBRI_INPUT_SELECT,
    242  1.9.2.2        ad 	DBRI_RECORD_CLASS,
    243      1.1  macallan 	DBRI_ENUM_LAST
    244      1.1  macallan };
    245      1.1  macallan 
    246      1.1  macallan /*
    247      1.1  macallan  * Autoconfig routines
    248      1.1  macallan  */
    249  1.9.2.1        ad static int
    250      1.1  macallan dbri_match_sbus(struct device *parent, struct cfdata *match, void *aux)
    251      1.1  macallan {
    252      1.1  macallan 	struct sbus_attach_args *sa = aux;
    253      1.1  macallan 	char *ver;
    254      1.1  macallan 	int i;
    255      1.1  macallan 
    256      1.1  macallan 	if (strncmp(DBRI_ROM_NAME_PREFIX, sa->sa_name, 9))
    257      1.1  macallan 		return (0);
    258      1.1  macallan 
    259      1.1  macallan 	ver = &sa->sa_name[9];
    260      1.1  macallan 
    261      1.1  macallan 	for (i = 0; dbri_supported[i][0] != '\0'; i++)
    262      1.1  macallan 		if (strcmp(dbri_supported[i], ver) == 0)
    263      1.1  macallan 			return (1);
    264      1.1  macallan 
    265      1.1  macallan 	return (0);
    266      1.1  macallan }
    267      1.1  macallan 
    268  1.9.2.1        ad static void
    269      1.1  macallan dbri_attach_sbus(struct device *parent, struct device *self, void *aux)
    270      1.1  macallan {
    271      1.1  macallan 	struct dbri_softc *sc = (struct dbri_softc *)self;
    272      1.1  macallan 	struct sbus_attach_args *sa = aux;
    273      1.1  macallan 	bus_space_handle_t ioh;
    274      1.1  macallan 	bus_size_t size;
    275      1.1  macallan 	int error, rseg, pwr;
    276      1.1  macallan 	char *ver = &sa->sa_name[9];
    277      1.1  macallan 
    278      1.1  macallan 	sc->sc_iot = sa->sa_bustag;
    279      1.1  macallan 	sc->sc_dmat = sa->sa_dmatag;
    280      1.4  macallan 	sc->sc_powerstate = PWR_RESUME;
    281      1.5     blymn 
    282      1.4  macallan 	pwr = prom_getpropint(sa->sa_node,"pwr-on-auxio",0);
    283  1.9.2.2        ad 	aprint_normal(": rev %s\n", ver);
    284  1.9.2.1        ad 
    285  1.9.2.1        ad 	if (pwr) {
    286      1.5     blymn 		/*
    287      1.4  macallan 		 * we can control DBRI power via auxio and we're initially
    288      1.4  macallan 		 * powered down
    289      1.4  macallan 		 */
    290      1.5     blymn 
    291      1.4  macallan 		sc->sc_have_powerctl = 1;
    292      1.4  macallan 		sc->sc_powerstate = 0;
    293      1.4  macallan 		dbri_set_power(sc, 1);
    294      1.6  jmcneill 		powerhook_establish(self->dv_xname, dbri_powerhook, sc);
    295      1.4  macallan 	} else {
    296      1.4  macallan 		/* we can't control power so we're always up */
    297      1.4  macallan 		sc->sc_have_powerctl = 0;
    298      1.4  macallan 		sc->sc_powerstate = 1;
    299      1.4  macallan 	}
    300      1.5     blymn 
    301      1.1  macallan 	if (sa->sa_npromvaddrs)
    302      1.1  macallan 		ioh = (bus_space_handle_t)sa->sa_promvaddrs[0];
    303      1.1  macallan 	else {
    304      1.1  macallan 		if (sbus_bus_map(sa->sa_bustag, sa->sa_slot,
    305      1.1  macallan 				 sa->sa_offset, sa->sa_size,
    306      1.1  macallan 				 BUS_SPACE_MAP_LINEAR, /*0,*/ &ioh) != 0) {
    307  1.9.2.1        ad 			aprint_error("%s @ sbus: cannot map registers\n",
    308      1.1  macallan 				self->dv_xname);
    309      1.1  macallan 			return;
    310      1.1  macallan 		}
    311      1.1  macallan 	}
    312      1.1  macallan 
    313      1.1  macallan 	sc->sc_ioh = ioh;
    314      1.1  macallan 
    315      1.1  macallan 	size = sizeof(struct dbri_dma);
    316      1.1  macallan 
    317      1.1  macallan 	/* get a DMA handle */
    318      1.1  macallan 	if ((error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0,
    319      1.1  macallan 				       BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) {
    320  1.9.2.1        ad 		aprint_error("%s: DMA map create error %d\n", self->dv_xname, error);
    321      1.1  macallan 		return;
    322      1.1  macallan 	}
    323      1.1  macallan 
    324      1.1  macallan 	/* allocate DMA buffer */
    325      1.1  macallan 	if ((error = bus_dmamem_alloc(sc->sc_dmat, size, 0, 0, &sc->sc_dmaseg,
    326      1.1  macallan 				      1, &rseg, BUS_DMA_NOWAIT)) != 0) {
    327  1.9.2.1        ad 		aprint_error("%s: DMA buffer alloc error %d\n",
    328      1.1  macallan 		    self->dv_xname, error);
    329      1.1  macallan 		return;
    330      1.1  macallan 	}
    331      1.1  macallan 
    332      1.1  macallan 	/* map DMA buffer into CPU addressable space */
    333      1.1  macallan 	if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_dmaseg, rseg, size,
    334      1.1  macallan 				    &sc->sc_membase,
    335      1.1  macallan 				    BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) {
    336  1.9.2.1        ad 		aprint_error("%s: DMA buffer map error %d\n",
    337      1.1  macallan 		    self->dv_xname, error);
    338      1.1  macallan 		return;
    339      1.1  macallan 	}
    340      1.1  macallan 
    341      1.1  macallan 	/* load the buffer */
    342      1.1  macallan 	if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap,
    343      1.1  macallan 				     sc->sc_membase, size, NULL,
    344      1.1  macallan 				     BUS_DMA_NOWAIT)) != 0) {
    345  1.9.2.1        ad 		aprint_error("%s: DMA buffer map load error %d\n",
    346      1.1  macallan 		    self->dv_xname, error);
    347      1.1  macallan 		bus_dmamem_unmap(sc->sc_dmat, sc->sc_membase, size);
    348      1.1  macallan 		bus_dmamem_free(sc->sc_dmat, &sc->sc_dmaseg, rseg);
    349      1.1  macallan 		return;
    350      1.1  macallan 	}
    351      1.1  macallan 
    352      1.1  macallan 	/* map the registers into memory */
    353      1.1  macallan 
    354      1.9  macallan 	/* kernel virtual address of DMA buffer */
    355      1.9  macallan 	sc->sc_dma = (struct dbri_dma *)sc->sc_membase;
    356      1.9  macallan 	/* physical address of DMA buffer */
    357      1.9  macallan 	sc->sc_dmabase = sc->sc_dmamap->dm_segs[0].ds_addr;
    358      1.1  macallan 	sc->sc_bufsiz = size;
    359      1.1  macallan 
    360      1.1  macallan 	sbus_establish(&sc->sc_sd, &sc->sc_dev);
    361      1.1  macallan 
    362  1.9.2.1        ad 	bus_intr_establish(sa->sa_bustag, sa->sa_pri, IPL_AUDIO, dbri_intr,
    363  1.9.2.1        ad 	    sc);
    364      1.1  macallan 
    365      1.1  macallan 	sc->sc_locked = 0;
    366      1.1  macallan 	sc->sc_desc_used = 0;
    367  1.9.2.2        ad 	sc->sc_open = 0;
    368  1.9.2.2        ad 	sc->sc_playing = 0;
    369  1.9.2.2        ad 	sc->sc_pmgrstate = PWR_RESUME;
    370      1.1  macallan 	config_interrupts(self, &dbri_config_interrupts);
    371      1.1  macallan 
    372      1.1  macallan 	return;
    373      1.1  macallan }
    374      1.1  macallan 
    375      1.4  macallan /*
    376      1.4  macallan  * lowlevel routine to switch power for the DBRI chip
    377      1.4  macallan  */
    378      1.4  macallan static void
    379      1.4  macallan dbri_set_power(struct dbri_softc *sc, int state)
    380      1.4  macallan {
    381      1.4  macallan 	int s;
    382      1.5     blymn 
    383      1.4  macallan 	if (sc->sc_have_powerctl == 0)
    384      1.4  macallan 		return;
    385      1.4  macallan 	if (sc->sc_powerstate == state)
    386      1.4  macallan 		return;
    387      1.5     blymn 
    388      1.4  macallan 	if (state) {
    389  1.9.2.1        ad 		DPRINTF("%s: waiting to power up... ", sc->sc_dev.dv_xname);
    390      1.4  macallan 		s = splhigh();
    391      1.4  macallan 		*AUXIO4M_REG |= (AUXIO4M_MMX);
    392      1.4  macallan 		splx(s);
    393      1.9  macallan 		delay(10000);
    394  1.9.2.2        ad 		DPRINTF("done (%02x)\n", *AUXIO4M_REG);
    395      1.4  macallan 	} else {
    396  1.9.2.1        ad 		DPRINTF("%s: powering down\n", sc->sc_dev.dv_xname);
    397      1.4  macallan 		s = splhigh();
    398      1.4  macallan 		*AUXIO4M_REG &= ~AUXIO4M_MMX;
    399      1.4  macallan 		splx(s);
    400  1.9.2.1        ad 		DPRINTF("done (%02x})\n", *AUXIO4M_REG);
    401      1.4  macallan 	}
    402      1.4  macallan 	sc->sc_powerstate = state;
    403      1.4  macallan }
    404      1.4  macallan 
    405      1.4  macallan /*
    406      1.4  macallan  * power up and re-initialize the chip
    407      1.4  macallan  */
    408      1.4  macallan static void
    409      1.4  macallan dbri_bring_up(struct dbri_softc *sc)
    410      1.4  macallan {
    411      1.4  macallan 
    412      1.4  macallan 	if (sc->sc_have_powerctl == 0)
    413      1.4  macallan 		return;
    414      1.4  macallan 	if (sc->sc_powerstate == 1)
    415      1.4  macallan 		return;
    416      1.5     blymn 
    417      1.4  macallan 	/* ok, we really need to do something */
    418      1.4  macallan 	dbri_set_power(sc, 1);
    419      1.4  macallan 
    420      1.4  macallan 	/*
    421      1.4  macallan 	 * re-initialize the chip but skip all the probing, don't overwrite
    422      1.4  macallan 	 * any other settings either
    423      1.4  macallan 	 */
    424      1.4  macallan 	dbri_init(sc);
    425      1.4  macallan 	mmcodec_setgain(sc, 1);
    426      1.4  macallan 	mmcodec_pipe_init(sc);
    427      1.4  macallan 	mmcodec_init_data(sc);
    428      1.4  macallan 	mmcodec_setgain(sc, 0);
    429      1.4  macallan }
    430      1.4  macallan 
    431  1.9.2.1        ad static void
    432      1.1  macallan dbri_config_interrupts(struct device *dev)
    433      1.1  macallan {
    434      1.1  macallan 	struct dbri_softc *sc = (struct dbri_softc *)dev;
    435      1.9  macallan 
    436      1.1  macallan 	dbri_init(sc);
    437      1.1  macallan 	mmcodec_init(sc);
    438      1.9  macallan 
    439      1.1  macallan 	/* Attach ourselves to the high level audio interface */
    440      1.1  macallan 	audio_attach_mi(&dbri_hw_if, sc, &sc->sc_dev);
    441      1.5     blymn 
    442      1.4  macallan 	/* power down until open() */
    443      1.4  macallan 	dbri_set_power(sc, 0);
    444      1.1  macallan 	return;
    445      1.1  macallan }
    446      1.1  macallan 
    447  1.9.2.1        ad static int
    448      1.1  macallan dbri_intr(void *hdl)
    449      1.1  macallan {
    450      1.1  macallan 	struct dbri_softc *sc = hdl;
    451      1.1  macallan 	bus_space_tag_t iot = sc->sc_iot;
    452      1.1  macallan 	bus_space_handle_t ioh = sc->sc_ioh;
    453      1.1  macallan 	int x;
    454      1.1  macallan 
    455      1.1  macallan 	/* clear interrupt */
    456      1.1  macallan 	x = bus_space_read_4(iot, ioh, DBRI_REG1);
    457      1.1  macallan 	if (x & (DBRI_MRR | DBRI_MLE | DBRI_LBG | DBRI_MBE)) {
    458      1.1  macallan 		u_int32_t tmp;
    459      1.1  macallan 
    460      1.1  macallan 		if (x & DBRI_MRR)
    461  1.9.2.1        ad 			aprint_debug("%s: multiple ack error on sbus\n",
    462      1.1  macallan 			    sc->sc_dev.dv_xname);
    463      1.1  macallan 		if (x & DBRI_MLE)
    464  1.9.2.1        ad 			aprint_debug("%s: multiple late error on sbus\n",
    465      1.1  macallan 			    sc->sc_dev.dv_xname);
    466      1.1  macallan 		if (x & DBRI_LBG)
    467  1.9.2.1        ad 			aprint_debug("%s: lost bus grant on sbus\n",
    468      1.1  macallan 			    sc->sc_dev.dv_xname);
    469      1.1  macallan 		if (x & DBRI_MBE)
    470  1.9.2.1        ad 			aprint_debug("%s: burst error on sbus\n",
    471      1.1  macallan 			    sc->sc_dev.dv_xname);
    472      1.1  macallan 
    473      1.1  macallan 		/*
    474      1.1  macallan 		 * Some of these errors disable the chip's circuitry.
    475      1.1  macallan 		 * Re-enable the circuitry and keep on going.
    476      1.1  macallan 		 */
    477      1.1  macallan 
    478      1.1  macallan 		tmp = bus_space_read_4(iot, ioh, DBRI_REG0);
    479      1.1  macallan 		tmp &= ~(DBRI_DISABLE_MASTER);
    480      1.1  macallan 		bus_space_write_4(iot, ioh, DBRI_REG0, tmp);
    481      1.1  macallan 	}
    482      1.1  macallan 
    483      1.1  macallan #if 0
    484      1.1  macallan 	if (!x & 1)	/* XXX: DBRI_INTR_REQ */
    485      1.1  macallan 		return (1);
    486      1.1  macallan #endif
    487      1.1  macallan 
    488      1.1  macallan 	dbri_process_interrupt_buffer(sc);
    489      1.1  macallan 
    490      1.1  macallan 	return (1);
    491      1.1  macallan }
    492      1.1  macallan 
    493  1.9.2.1        ad static int
    494      1.1  macallan dbri_init(struct dbri_softc *sc)
    495      1.1  macallan {
    496      1.1  macallan 	bus_space_tag_t iot = sc->sc_iot;
    497      1.1  macallan 	bus_space_handle_t ioh = sc->sc_ioh;
    498      1.1  macallan 	u_int32_t reg;
    499      1.1  macallan 	volatile u_int32_t *cmd;
    500      1.1  macallan 	bus_addr_t dmaaddr;
    501      1.1  macallan 	int n;
    502      1.1  macallan 
    503      1.1  macallan 	dbri_reset(sc);
    504      1.1  macallan 
    505      1.1  macallan 	cmd = dbri_command_lock(sc);
    506      1.1  macallan 
    507      1.1  macallan 	/* XXX: Initialize interrupt ring buffer */
    508      1.1  macallan 	sc->sc_dma->intr[0] = (u_int32_t)sc->sc_dmabase + dbri_dma_off(intr, 0);
    509      1.1  macallan 	sc->sc_irqp = 1;
    510      1.5     blymn 
    511      1.1  macallan 	/* Initialize pipes */
    512      1.1  macallan 	for (n = 0; n < DBRI_PIPE_MAX; n++)
    513      1.1  macallan 		sc->sc_pipe[n].desc = sc->sc_pipe[n].next = -1;
    514      1.5     blymn 
    515  1.9.2.1        ad 	for (n = 1; n < DBRI_INT_BLOCKS; n++) {
    516  1.9.2.1        ad 		sc->sc_dma->intr[n] = 0;
    517      1.1  macallan 	}
    518      1.5     blymn 
    519      1.1  macallan 	/* Disable all SBus bursts */
    520      1.1  macallan 	/* XXX 16 byte bursts cause errors, the rest works */
    521      1.1  macallan 	reg = bus_space_read_4(iot, ioh, DBRI_REG0);
    522      1.9  macallan 
    523      1.1  macallan 	/*reg &= ~(DBRI_BURST_4 | DBRI_BURST_8 | DBRI_BURST_16);*/
    524      1.1  macallan 	reg |= (DBRI_BURST_4 | DBRI_BURST_8);
    525      1.1  macallan 	bus_space_write_4(iot, ioh, DBRI_REG0, reg);
    526      1.5     blymn 
    527      1.1  macallan 	/* setup interrupt queue */
    528      1.1  macallan 	dmaaddr = (u_int32_t)sc->sc_dmabase + dbri_dma_off(intr, 0);
    529      1.1  macallan 	*(cmd++) = DBRI_CMD(DBRI_COMMAND_IIQ, 0, 0);
    530      1.1  macallan 	*(cmd++) = dmaaddr;
    531      1.5     blymn 
    532      1.1  macallan 	dbri_command_send(sc, cmd);
    533      1.1  macallan 	return (0);
    534      1.1  macallan }
    535      1.1  macallan 
    536  1.9.2.1        ad static int
    537      1.1  macallan dbri_reset(struct dbri_softc *sc)
    538      1.1  macallan {
    539  1.9.2.1        ad 	int bail = 0;
    540  1.9.2.1        ad 
    541      1.1  macallan 	bus_space_tag_t iot = sc->sc_iot;
    542      1.1  macallan 	bus_space_handle_t ioh = sc->sc_ioh;
    543      1.1  macallan 
    544      1.1  macallan 	bus_space_write_4(iot, ioh, DBRI_REG0, DBRI_SOFT_RESET);
    545      1.5     blymn 	while ((bus_space_read_4(iot, ioh, DBRI_REG0) & DBRI_SOFT_RESET) &&
    546      1.5     blymn 	    (bail < 100000)) {
    547      1.1  macallan 		bail++;
    548      1.1  macallan 		delay(10);
    549      1.1  macallan 	}
    550  1.9.2.1        ad 	if (bail == 100000) aprint_error("%s: reset timed out\n",
    551  1.9.2.1        ad 	    sc->sc_dev.dv_xname);
    552      1.1  macallan 	return (0);
    553      1.1  macallan }
    554      1.1  macallan 
    555  1.9.2.1        ad static volatile u_int32_t *
    556      1.1  macallan dbri_command_lock(struct dbri_softc *sc)
    557      1.1  macallan {
    558      1.1  macallan 
    559      1.1  macallan 	if (sc->sc_locked)
    560  1.9.2.1        ad 		aprint_debug("%s: command buffer locked\n", sc->sc_dev.dv_xname);
    561      1.1  macallan 
    562      1.1  macallan 	sc->sc_locked++;
    563      1.1  macallan 
    564      1.1  macallan 	return (&sc->sc_dma->command[0]);
    565      1.1  macallan }
    566      1.1  macallan 
    567  1.9.2.1        ad static void
    568      1.1  macallan dbri_command_send(struct dbri_softc *sc, volatile u_int32_t *cmd)
    569      1.1  macallan {
    570      1.1  macallan 	bus_space_handle_t ioh = sc->sc_ioh;
    571      1.1  macallan 	bus_space_tag_t iot = sc->sc_iot;
    572      1.1  macallan 	int maxloops = 1000000;
    573      1.1  macallan 	int x;
    574      1.1  macallan 
    575      1.1  macallan 	x = splaudio();
    576      1.1  macallan 
    577      1.1  macallan 	sc->sc_locked--;
    578      1.1  macallan 
    579      1.1  macallan 	if (sc->sc_locked != 0) {
    580  1.9.2.1        ad 		aprint_error("%s: command buffer improperly locked\n",
    581      1.1  macallan 		    sc->sc_dev.dv_xname);
    582      1.1  macallan 	} else if ((cmd - &sc->sc_dma->command[0]) >= DBRI_NUM_COMMANDS - 1) {
    583  1.9.2.1        ad 		aprint_error("%s: command buffer overflow\n", sc->sc_dev.dv_xname);
    584      1.1  macallan 	} else {
    585      1.1  macallan 		*(cmd++) = DBRI_CMD(DBRI_COMMAND_PAUSE, 0, 0);
    586      1.1  macallan 		*(cmd++) = DBRI_CMD(DBRI_COMMAND_WAIT, 1, 0);
    587      1.1  macallan 		sc->sc_waitseen = 0;
    588      1.1  macallan 		bus_space_write_4(iot, ioh, DBRI_REG8, sc->sc_dmabase);
    589      1.1  macallan 		while ((--maxloops) > 0 &&
    590      1.1  macallan 		    (bus_space_read_4(iot, ioh, DBRI_REG0)
    591      1.1  macallan 		     & DBRI_COMMAND_VALID)) {
    592      1.1  macallan 			bus_space_barrier(iot, ioh, DBRI_REG0, 4,
    593      1.1  macallan 					  BUS_SPACE_BARRIER_READ);
    594      1.1  macallan 			delay(1000);
    595      1.1  macallan 		}
    596      1.1  macallan 
    597      1.1  macallan 		if (maxloops == 0) {
    598  1.9.2.1        ad 			aprint_error("%s: chip never completed command buffer\n",
    599      1.1  macallan 			    sc->sc_dev.dv_xname);
    600      1.1  macallan 		} else {
    601      1.9  macallan 
    602  1.9.2.1        ad 			DPRINTF("%s: command completed\n",
    603  1.9.2.1        ad 			    sc->sc_dev.dv_xname);
    604      1.9  macallan 
    605      1.1  macallan 			while ((--maxloops) > 0 && (!sc->sc_waitseen))
    606      1.1  macallan 				dbri_process_interrupt_buffer(sc);
    607      1.1  macallan 			if (maxloops == 0) {
    608  1.9.2.1        ad 				aprint_error("%s: chip never acked WAIT\n",
    609      1.1  macallan 				    sc->sc_dev.dv_xname);
    610      1.1  macallan 			}
    611      1.1  macallan 		}
    612      1.1  macallan 	}
    613      1.1  macallan 
    614      1.1  macallan 	splx(x);
    615      1.1  macallan 
    616      1.1  macallan 	return;
    617      1.1  macallan }
    618      1.1  macallan 
    619  1.9.2.1        ad static void
    620      1.1  macallan dbri_process_interrupt_buffer(struct dbri_softc *sc)
    621      1.1  macallan {
    622      1.1  macallan 	int32_t i;
    623      1.1  macallan 
    624      1.1  macallan 	while ((i = sc->sc_dma->intr[sc->sc_irqp]) != 0) {
    625      1.1  macallan 		sc->sc_dma->intr[sc->sc_irqp] = 0;
    626      1.1  macallan 		sc->sc_irqp++;
    627      1.1  macallan 
    628      1.1  macallan 		if (sc->sc_irqp == DBRI_INT_BLOCKS)
    629      1.1  macallan 			sc->sc_irqp = 1;
    630      1.1  macallan 		else if ((sc->sc_irqp & (DBRI_INT_BLOCKS - 1)) == 0)
    631      1.1  macallan 			sc->sc_irqp++;
    632      1.1  macallan 
    633      1.1  macallan 		dbri_process_interrupt(sc, i);
    634      1.1  macallan 	}
    635      1.1  macallan 
    636      1.1  macallan 	return;
    637      1.1  macallan }
    638      1.1  macallan 
    639  1.9.2.1        ad static void
    640      1.1  macallan dbri_process_interrupt(struct dbri_softc *sc, int32_t i)
    641      1.1  macallan {
    642      1.1  macallan #if 0
    643      1.1  macallan 	const int liu_states[] = { 1, 0, 8, 3, 4, 5, 6, 7 };
    644      1.1  macallan #endif
    645      1.1  macallan 	int val = DBRI_INTR_GETVAL(i);
    646      1.1  macallan 	int channel = DBRI_INTR_GETCHAN(i);
    647      1.1  macallan 	int command = DBRI_INTR_GETCMD(i);
    648      1.1  macallan 	int code = DBRI_INTR_GETCODE(i);
    649      1.1  macallan #if 0
    650      1.1  macallan 	int rval = DBRI_INTR_GETRVAL(i);
    651      1.1  macallan #endif
    652      1.1  macallan 	if (channel == DBRI_INTR_CMD && command == DBRI_COMMAND_WAIT)
    653      1.1  macallan 		sc->sc_waitseen++;
    654      1.1  macallan 
    655      1.1  macallan 	switch (code) {
    656      1.1  macallan 	case DBRI_INTR_XCMP:	/* transmission complete */
    657      1.1  macallan 	{
    658      1.1  macallan 		int td;
    659      1.1  macallan 		struct dbri_desc *dd;
    660      1.1  macallan 
    661      1.1  macallan 		td = sc->sc_pipe[channel].desc;
    662      1.1  macallan 		dd = &sc->sc_desc[td];
    663      1.5     blymn 
    664      1.1  macallan 		if (dd->callback != NULL)
    665      1.1  macallan 			dd->callback(dd->callback_args);
    666      1.1  macallan 		break;
    667      1.1  macallan 	}
    668      1.1  macallan 	case DBRI_INTR_FXDT:		/* fixed data change */
    669  1.9.2.1        ad 		DPRINTF("dbri_intr: Fixed data change (%d: %x)\n", channel,
    670  1.9.2.1        ad 		    val);
    671      1.4  macallan 
    672      1.1  macallan 		if (sc->sc_pipe[channel].sdp & DBRI_SDP_MSB)
    673      1.1  macallan 			val = reverse_bytes(val, sc->sc_pipe[channel].length);
    674      1.1  macallan 		if (sc->sc_pipe[channel].prec)
    675      1.1  macallan 			*(sc->sc_pipe[channel].prec) = val;
    676  1.9.2.2        ad #ifndef DBRI_SPIN
    677  1.9.2.1        ad 		DPRINTF("%s: wakeup %p\n", sc->sc_dev.dv_xname, sc);
    678      1.1  macallan 		wakeup(sc);
    679      1.1  macallan #endif
    680      1.1  macallan 		break;
    681      1.1  macallan 	case DBRI_INTR_SBRI:
    682  1.9.2.1        ad 		DPRINTF("dbri_intr: SBRI\n");
    683      1.1  macallan 		break;
    684      1.1  macallan 	case DBRI_INTR_BRDY:
    685      1.1  macallan 	{
    686      1.1  macallan 		/* XXX no input (yet) */
    687      1.1  macallan #if 0
    688      1.1  macallan 		int rd = sc->sc_pipe[channel].desc;
    689      1.1  macallan 		u_int32_t status;
    690      1.1  macallan 
    691  1.9.2.1        ad 		DPRINTF("dbri_intr: BRDY\n");
    692      1.1  macallan 		if (rd < 0 || rd >= DBRI_NUM_DESCRIPTORS) {
    693  1.9.2.2        ad 			aprint_error("%s: invalid rd on pipe\n",
    694  1.9.2.2        ad 			    sc->sc_dev.dv_xname);
    695      1.1  macallan 			break;
    696      1.1  macallan 		}
    697      1.1  macallan 
    698      1.1  macallan 		sc->sc_desc[rd].busy = 0;
    699      1.1  macallan 		sc->sc_pipe[channel].desc = sc->sc_desc[rd].next;
    700      1.1  macallan 		status = sc->sc_dma->desc[rd].word1;
    701      1.1  macallan #endif
    702      1.1  macallan 		/* XXX: callback ??? */
    703      1.1  macallan 
    704      1.1  macallan 		break;
    705      1.1  macallan 	}
    706      1.1  macallan 	case DBRI_INTR_UNDR:
    707      1.1  macallan 	{
    708      1.1  macallan 		volatile u_int32_t *cmd;
    709      1.1  macallan 		int td = sc->sc_pipe[channel].desc;
    710      1.1  macallan 
    711  1.9.2.1        ad 		DPRINTF("%s: DBRI_INTR_UNDR\n", sc->sc_dev.dv_xname);
    712      1.1  macallan 
    713      1.1  macallan 		sc->sc_dma->desc[td].status = 0;
    714      1.1  macallan 
    715      1.1  macallan 		cmd = dbri_command_lock(sc);
    716      1.1  macallan 		*(cmd++) = DBRI_CMD(DBRI_COMMAND_SDP, 0,
    717      1.1  macallan 				    sc->sc_pipe[channel].sdp |
    718      1.1  macallan 				    DBRI_SDP_VALID_POINTER |
    719      1.1  macallan 				    DBRI_SDP_CLEAR |
    720      1.1  macallan 				    DBRI_SDP_2SAME);
    721      1.1  macallan 		*(cmd++) = sc->sc_dmabase + dbri_dma_off(desc, td);
    722      1.1  macallan 		dbri_command_send(sc, cmd);
    723      1.1  macallan 		break;
    724      1.1  macallan 	}
    725      1.9  macallan 	case DBRI_INTR_CMDI:
    726      1.9  macallan 		break;
    727      1.1  macallan 	default:
    728      1.9  macallan 
    729  1.9.2.1        ad 		DPRINTF("%s: unknown interrupt code %d\n",
    730  1.9.2.1        ad 		    sc->sc_dev.dv_xname, code);
    731      1.1  macallan 		break;
    732      1.1  macallan 	}
    733      1.1  macallan 
    734      1.1  macallan 	return;
    735      1.1  macallan }
    736      1.1  macallan 
    737      1.1  macallan /*
    738      1.1  macallan  * mmcodec stuff
    739      1.1  macallan  */
    740      1.1  macallan 
    741  1.9.2.1        ad static int
    742      1.1  macallan mmcodec_init(struct dbri_softc *sc)
    743      1.1  macallan {
    744      1.1  macallan 	bus_space_handle_t ioh = sc->sc_ioh;
    745      1.1  macallan 	bus_space_tag_t iot = sc->sc_iot;
    746      1.1  macallan 	u_int32_t reg2;
    747      1.9  macallan 	int bail;
    748      1.1  macallan 
    749      1.1  macallan 	reg2 = bus_space_read_4(iot, ioh, DBRI_REG2);
    750  1.9.2.1        ad 	DPRINTF("mmcodec_init: PIO reads %x\n", reg2);
    751      1.5     blymn 
    752      1.1  macallan 	if (reg2 & DBRI_PIO2) {
    753  1.9.2.1        ad 		aprint_normal("%s: onboard CS4215 detected\n",
    754      1.1  macallan 		    sc->sc_dev.dv_xname);
    755      1.1  macallan 		sc->sc_mm.onboard = 1;
    756      1.1  macallan 	}
    757      1.1  macallan 
    758      1.1  macallan 	if (reg2 & DBRI_PIO0) {
    759  1.9.2.1        ad 		aprint_normal("%s: speakerbox detected\n",
    760      1.1  macallan 		    sc->sc_dev.dv_xname);
    761      1.1  macallan 		sc->sc_mm.onboard = 0;
    762      1.1  macallan 	}
    763      1.1  macallan 
    764      1.1  macallan 	if ((reg2 & DBRI_PIO2) && (reg2 & DBRI_PIO0)) {
    765  1.9.2.1        ad 		aprint_normal("%s: using speakerbox\n",
    766      1.1  macallan 		    sc->sc_dev.dv_xname);
    767      1.1  macallan 		bus_space_write_4(iot, ioh, DBRI_REG2, DBRI_PIO2_ENABLE);
    768      1.1  macallan 		sc->sc_mm.onboard = 0;
    769      1.1  macallan 	}
    770      1.1  macallan 
    771      1.1  macallan 	if (!(reg2 & (DBRI_PIO0|DBRI_PIO2))) {
    772  1.9.2.1        ad 		aprint_normal("%s: no mmcodec found\n", sc->sc_dev.dv_xname);
    773      1.1  macallan 		return -1;
    774      1.1  macallan 	}
    775      1.1  macallan 
    776      1.1  macallan 	sc->sc_version = 0xff;
    777      1.1  macallan 
    778      1.1  macallan 	mmcodec_pipe_init(sc);
    779      1.1  macallan 	mmcodec_default(sc);
    780      1.1  macallan 
    781      1.1  macallan 	sc->sc_mm.offset = sc->sc_mm.onboard ? 0 : 8;
    782      1.1  macallan 
    783      1.9  macallan 	/*
    784      1.9  macallan 	 * mmcodec_setcontrol() sometimes fails right after powerup
    785      1.9  macallan 	 * so we just try again until we either get a useful response or run
    786      1.9  macallan 	 * out of time
    787      1.9  macallan 	 */
    788      1.9  macallan 	bail = 0;
    789      1.9  macallan 	while (mmcodec_setcontrol(sc) == -1 || sc->sc_version == 0xff) {
    790      1.9  macallan 
    791      1.9  macallan 		bail++;
    792      1.9  macallan 		if (bail > 100) {
    793  1.9.2.1        ad 			DPRINTF("%s: cs4215 probe failed at offset %d\n",
    794      1.9  macallan 		    	    sc->sc_dev.dv_xname, sc->sc_mm.offset);
    795      1.9  macallan 			return (-1);
    796      1.9  macallan 		}
    797      1.9  macallan 		delay(10000);
    798      1.1  macallan 	}
    799      1.1  macallan 
    800  1.9.2.1        ad 	aprint_normal("%s: cs4215 ver %d found at offset %d\n",
    801      1.1  macallan 	    sc->sc_dev.dv_xname, sc->sc_version & 0xf, sc->sc_mm.offset);
    802      1.1  macallan 
    803      1.1  macallan 	/* set some sane defaults for mmcodec_init_data */
    804      1.1  macallan 	sc->sc_params.channels = 2;
    805      1.1  macallan 	sc->sc_params.precision = 16;
    806      1.1  macallan 
    807      1.1  macallan 	mmcodec_init_data(sc);
    808      1.1  macallan 
    809      1.1  macallan 	return (0);
    810      1.1  macallan }
    811      1.1  macallan 
    812  1.9.2.1        ad static void
    813      1.1  macallan mmcodec_init_data(struct dbri_softc *sc)
    814      1.1  macallan {
    815      1.1  macallan 	bus_space_tag_t iot = sc->sc_iot;
    816      1.1  macallan 	bus_space_handle_t ioh = sc->sc_ioh;
    817      1.1  macallan 	u_int32_t tmp;
    818      1.1  macallan 	int data_width;
    819      1.1  macallan 
    820      1.1  macallan 	tmp = bus_space_read_4(iot, ioh, DBRI_REG0);
    821      1.1  macallan 	tmp &= ~(DBRI_CHI_ACTIVATE);	/* disable CHI */
    822      1.1  macallan 	bus_space_write_4(iot, ioh, DBRI_REG0, tmp);
    823      1.1  macallan 
    824      1.1  macallan 	/* switch CS4215 to data mode - set PIO3 to 1 */
    825      1.1  macallan 	tmp = DBRI_PIO_ENABLE_ALL | DBRI_PIO1 | DBRI_PIO3;
    826  1.9.2.1        ad 
    827  1.9.2.1        ad 	/* XXX */
    828      1.1  macallan 	tmp |= (sc->sc_mm.onboard ? DBRI_PIO0 : DBRI_PIO2);
    829      1.5     blymn 
    830      1.1  macallan 	bus_space_write_4(iot, ioh, DBRI_REG2, tmp);
    831      1.1  macallan 	chi_reset(sc, CHIslave, 128);
    832      1.1  macallan 
    833  1.9.2.1        ad 	data_width = sc->sc_params.channels * sc->sc_params.precision;
    834      1.1  macallan 	pipe_ts_link(sc, 20, PIPEoutput, 16, 32, sc->sc_mm.offset + 32);
    835      1.1  macallan 	pipe_ts_link(sc, 4, PIPEoutput, 16, data_width, sc->sc_mm.offset);
    836      1.1  macallan 	pipe_ts_link(sc, 6, PIPEinput, 16, data_width, sc->sc_mm.offset);
    837      1.1  macallan 	pipe_ts_link(sc, 21, PIPEinput, 16, 16, sc->sc_mm.offset + 40);
    838      1.1  macallan 
    839      1.1  macallan 	mmcodec_setgain(sc, 0);
    840      1.1  macallan 
    841      1.1  macallan 	tmp = bus_space_read_4(iot, ioh, DBRI_REG0);
    842      1.1  macallan 	tmp |= DBRI_CHI_ACTIVATE;
    843      1.1  macallan 	bus_space_write_4(iot, ioh, DBRI_REG0, tmp);
    844      1.1  macallan 
    845      1.1  macallan 	return;
    846      1.1  macallan }
    847      1.1  macallan 
    848  1.9.2.1        ad static void
    849      1.1  macallan mmcodec_pipe_init(struct dbri_softc *sc)
    850      1.1  macallan {
    851      1.1  macallan 
    852      1.1  macallan 	pipe_setup(sc, 4, DBRI_SDP_MEM | DBRI_SDP_TO_SER | DBRI_SDP_MSB);
    853      1.1  macallan 	pipe_setup(sc, 20, DBRI_SDP_FIXED | DBRI_SDP_TO_SER | DBRI_SDP_MSB);
    854      1.1  macallan 	pipe_setup(sc, 6, DBRI_SDP_MEM | DBRI_SDP_FROM_SER | DBRI_SDP_MSB);
    855      1.1  macallan 	pipe_setup(sc, 21, DBRI_SDP_FIXED | DBRI_SDP_FROM_SER | DBRI_SDP_MSB);
    856      1.1  macallan 
    857      1.1  macallan 	pipe_setup(sc, 17, DBRI_SDP_FIXED | DBRI_SDP_TO_SER | DBRI_SDP_MSB);
    858      1.1  macallan 	pipe_setup(sc, 18, DBRI_SDP_FIXED | DBRI_SDP_FROM_SER | DBRI_SDP_MSB);
    859      1.1  macallan 	pipe_setup(sc, 19, DBRI_SDP_FIXED | DBRI_SDP_FROM_SER | DBRI_SDP_MSB);
    860      1.1  macallan 
    861      1.1  macallan 	sc->sc_mm.status = 0;
    862      1.1  macallan 
    863      1.1  macallan 	pipe_receive_fixed(sc, 18, &sc->sc_mm.status);
    864      1.1  macallan 	pipe_receive_fixed(sc, 19, &sc->sc_mm.version);
    865      1.1  macallan 
    866      1.1  macallan 	return;
    867      1.1  macallan }
    868      1.1  macallan 
    869  1.9.2.1        ad static void
    870      1.1  macallan mmcodec_default(struct dbri_softc *sc)
    871      1.1  macallan {
    872      1.1  macallan 	struct cs4215_state *mm = &sc->sc_mm;
    873      1.1  macallan 
    874      1.1  macallan 	/*
    875      1.1  macallan 	 * no action, memory resetting only
    876      1.1  macallan 	 *
    877      1.1  macallan 	 * data time slots 5-8
    878      1.1  macallan 	 * speaker, line and headphone enable. set gain to half.
    879      1.1  macallan 	 * input is mic
    880      1.1  macallan 	 */
    881      1.9  macallan 	mm->d.bdata[0] = sc->sc_latt = 0x20 | CS4215_HE | CS4215_LE;
    882      1.9  macallan 	mm->d.bdata[1] = sc->sc_ratt = 0x20 | CS4215_SE;
    883  1.9.2.2        ad 	sc->sc_linp = 128;
    884  1.9.2.2        ad 	sc->sc_rinp = 128;
    885  1.9.2.2        ad 	sc->sc_monitor = 0;
    886  1.9.2.2        ad 	sc->sc_input = 1;	/* line */
    887  1.9.2.2        ad 	mm->d.bdata[2] = (CS4215_LG((sc->sc_linp >> 4)) & 0x0f) |
    888  1.9.2.2        ad 	    ((sc->sc_input == 2) ? CS4215_IS : 0) | CS4215_PIO0 | CS4215_PIO1;
    889  1.9.2.2        ad 	mm->d.bdata[3] = (CS4215_RG((sc->sc_rinp >> 4) & 0x0f)) |
    890  1.9.2.2        ad 	    CS4215_MA(15 - ((sc->sc_monitor >> 4) & 0x0f));
    891  1.9.2.2        ad 
    892      1.1  macallan 
    893      1.1  macallan 	/*
    894      1.1  macallan 	 * control time slots 1-4
    895      1.1  macallan 	 *
    896      1.1  macallan 	 * 0: default I/O voltage scale
    897      1.1  macallan 	 * 1: 8 bit ulaw, 8kHz, mono, high pass filter disabled
    898      1.1  macallan 	 * 2: serial enable, CHI master, 128 bits per frame, clock 1
    899      1.1  macallan 	 * 3: tests disabled
    900      1.1  macallan 	 */
    901      1.9  macallan 	mm->c.bcontrol[0] = CS4215_RSRVD_1 | CS4215_MLB;
    902      1.9  macallan 	mm->c.bcontrol[1] = CS4215_DFR_ULAW | CS4215_FREQ[0].csval;
    903      1.9  macallan 	mm->c.bcontrol[2] = CS4215_XCLK | CS4215_BSEL_128 | CS4215_FREQ[0].xtal;
    904      1.9  macallan 	mm->c.bcontrol[3] = 0;
    905      1.1  macallan 
    906      1.1  macallan 	return;
    907      1.1  macallan }
    908      1.1  macallan 
    909  1.9.2.1        ad static void
    910      1.1  macallan mmcodec_setgain(struct dbri_softc *sc, int mute)
    911      1.1  macallan {
    912      1.1  macallan 	if (mute) {
    913      1.1  macallan 		/* disable all outputs, max. attenuation */
    914      1.9  macallan 		sc->sc_mm.d.bdata[0] = sc->sc_latt | 63;
    915      1.9  macallan 		sc->sc_mm.d.bdata[1] = sc->sc_ratt | 63;
    916      1.1  macallan 	} else {
    917  1.9.2.2        ad 
    918      1.9  macallan 		sc->sc_mm.d.bdata[0] = sc->sc_latt;
    919      1.9  macallan 		sc->sc_mm.d.bdata[1] = sc->sc_ratt;
    920      1.1  macallan 	}
    921      1.1  macallan 
    922  1.9.2.2        ad 	/* input stuff */
    923  1.9.2.2        ad 	sc->sc_mm.d.bdata[2] = CS4215_LG((sc->sc_linp >> 4) & 0x0f) |
    924  1.9.2.2        ad 	    ((sc->sc_input == 2) ? CS4215_IS : 0) | CS4215_PIO0 | CS4215_PIO1;
    925  1.9.2.2        ad 	sc->sc_mm.d.bdata[3] = (CS4215_RG((sc->sc_rinp >> 4)) & 0x0f) |
    926  1.9.2.2        ad 	    (CS4215_MA(15 - ((sc->sc_monitor >> 4) & 0x0f)));
    927  1.9.2.2        ad 
    928      1.4  macallan 	if (sc->sc_powerstate == 0)
    929      1.4  macallan 		return;
    930      1.9  macallan 	pipe_transmit_fixed(sc, 20, sc->sc_mm.d.ldata);
    931      1.5     blymn 
    932  1.9.2.2        ad 	DPRINTF("mmcodec_setgain: %08x\n", sc->sc_mm.d.ldata);
    933  1.9.2.2        ad 	/* give the chip some time to execute the command */
    934      1.1  macallan 	delay(250);
    935      1.5     blymn 
    936      1.1  macallan 	return;
    937      1.1  macallan }
    938      1.1  macallan 
    939  1.9.2.1        ad static int
    940      1.1  macallan mmcodec_setcontrol(struct dbri_softc *sc)
    941      1.1  macallan {
    942      1.1  macallan 	bus_space_tag_t iot = sc->sc_iot;
    943      1.1  macallan 	bus_space_handle_t ioh = sc->sc_ioh;
    944      1.1  macallan 	u_int32_t val;
    945      1.1  macallan 	u_int32_t tmp;
    946  1.9.2.2        ad #if DBRI_SPIN
    947      1.1  macallan 	int i;
    948      1.1  macallan #endif
    949      1.1  macallan 
    950      1.1  macallan 	/*
    951      1.1  macallan 	 * Temporarily mute outputs and wait 125 us to make sure that it
    952      1.1  macallan 	 * happens. This avoids clicking noises.
    953      1.1  macallan 	 */
    954      1.1  macallan 	mmcodec_setgain(sc, 1);
    955      1.9  macallan 	delay(125);
    956      1.1  macallan 
    957      1.1  macallan 	/* enable control mode */
    958      1.1  macallan 	val = DBRI_PIO_ENABLE_ALL | DBRI_PIO1;	/* was PIO1 */
    959      1.1  macallan 
    960  1.9.2.1        ad 	/* XXX */
    961      1.1  macallan 	val |= (sc->sc_mm.onboard ? DBRI_PIO0 : DBRI_PIO2);
    962      1.1  macallan 
    963      1.1  macallan 	bus_space_write_4(iot, ioh, DBRI_REG2, val);
    964      1.1  macallan 
    965      1.9  macallan 	delay(34);
    966      1.1  macallan 
    967      1.1  macallan 	/*
    968      1.1  macallan 	 * in control mode, the cs4215 is the slave device, so the
    969      1.1  macallan 	 * DBRI must act as the CHI master.
    970      1.1  macallan 	 *
    971      1.1  macallan 	 * in data mode, the cs4215 must be the CHI master to insure
    972      1.1  macallan 	 * that the data stream is in sync with its codec
    973      1.1  macallan 	 */
    974      1.1  macallan 	tmp = bus_space_read_4(iot, ioh, DBRI_REG0);
    975      1.1  macallan 	tmp &= ~DBRI_COMMAND_CHI;
    976      1.1  macallan 	bus_space_write_4(iot, ioh, DBRI_REG0, tmp);
    977      1.1  macallan 
    978      1.1  macallan 	chi_reset(sc, CHImaster, 128);
    979      1.1  macallan 
    980      1.1  macallan 	/* control mode */
    981      1.1  macallan 	pipe_ts_link(sc, 17, PIPEoutput, 16, 32, sc->sc_mm.offset);
    982      1.1  macallan 	pipe_ts_link(sc, 18, PIPEinput, 16, 8, sc->sc_mm.offset);
    983      1.1  macallan 	pipe_ts_link(sc, 19, PIPEinput, 16, 8, sc->sc_mm.offset + 48);
    984      1.1  macallan 
    985      1.1  macallan 	/* wait for the chip to echo back CLB as zero */
    986      1.9  macallan 	sc->sc_mm.c.bcontrol[0] &= ~CS4215_CLB;
    987      1.9  macallan 	pipe_transmit_fixed(sc, 17, sc->sc_mm.c.lcontrol);
    988      1.1  macallan 
    989      1.1  macallan 	tmp = bus_space_read_4(iot, ioh, DBRI_REG0);
    990      1.1  macallan 	tmp |= DBRI_CHI_ACTIVATE;
    991      1.1  macallan 	bus_space_write_4(iot, ioh, DBRI_REG0, tmp);
    992      1.5     blymn 
    993  1.9.2.2        ad #if DBRI_SPIN
    994      1.1  macallan 	i = 1024;
    995      1.1  macallan 	while (((sc->sc_mm.status & 0xe4) != 0x20) && --i) {
    996      1.1  macallan 		delay(125);
    997      1.1  macallan 	}
    998      1.1  macallan 
    999      1.1  macallan 	if (i == 0) {
   1000  1.9.2.1        ad 		DPRINTF("%s: cs4215 didn't respond to CLB (0x%02x)\n",
   1001      1.1  macallan 		    sc->sc_dev.dv_xname, sc->sc_mm.status);
   1002      1.1  macallan 		return (-1);
   1003      1.1  macallan 	}
   1004      1.1  macallan #else
   1005      1.1  macallan 	while ((sc->sc_mm.status & 0xe4) != 0x20) {
   1006  1.9.2.1        ad 		DPRINTF("%s: tsleep %p\n", sc->sc_dev.dv_xname, sc);
   1007      1.1  macallan 		tsleep(sc, PCATCH | PZERO, "dbrifxdt", 0);
   1008      1.1  macallan 	}
   1009      1.1  macallan #endif
   1010      1.5     blymn 
   1011      1.1  macallan 	/* copy the version information before it becomes unreadable again */
   1012      1.9  macallan 	sc->sc_version = sc->sc_mm.version;
   1013      1.1  macallan 
   1014      1.1  macallan 	/* terminate cs4215 control mode */
   1015      1.9  macallan 	sc->sc_mm.c.bcontrol[0] |= CS4215_CLB;
   1016      1.9  macallan 	pipe_transmit_fixed(sc, 17, sc->sc_mm.c.lcontrol);
   1017      1.1  macallan 
   1018      1.1  macallan 	/* two frames of control info @ 8kHz frame rate = 250us delay */
   1019      1.9  macallan 	delay(250);
   1020      1.1  macallan 
   1021      1.1  macallan 	mmcodec_setgain(sc, 0);
   1022      1.1  macallan 
   1023      1.1  macallan 	return (0);
   1024      1.5     blymn 
   1025      1.1  macallan }
   1026      1.1  macallan 
   1027      1.1  macallan /*
   1028      1.1  macallan  * CHI combo
   1029      1.1  macallan  */
   1030  1.9.2.1        ad static void
   1031      1.1  macallan chi_reset(struct dbri_softc *sc, enum ms ms, int bpf)
   1032      1.1  macallan {
   1033      1.1  macallan 	volatile u_int32_t *cmd;
   1034      1.1  macallan 	int val;
   1035      1.1  macallan 	int clockrate, divisor;
   1036      1.1  macallan 
   1037      1.1  macallan 	cmd = dbri_command_lock(sc);
   1038      1.1  macallan 
   1039      1.1  macallan 	/* set CHI anchor: pipe 16 */
   1040      1.1  macallan 	val = DBRI_DTS_VI | DBRI_DTS_INS | DBRI_DTS_PRVIN(16) | DBRI_PIPE(16);
   1041      1.1  macallan 	*(cmd++) = DBRI_CMD(DBRI_COMMAND_DTS, 0, val);
   1042      1.1  macallan 	*(cmd++) = DBRI_TS_ANCHOR | DBRI_TS_NEXT(16);
   1043      1.1  macallan 	*(cmd++) = 0;
   1044      1.1  macallan 
   1045      1.1  macallan 	val = DBRI_DTS_VO | DBRI_DTS_INS | DBRI_DTS_PRVOUT(16) | DBRI_PIPE(16);
   1046      1.1  macallan 	*(cmd++) = DBRI_CMD(DBRI_COMMAND_DTS, 0, val);
   1047      1.1  macallan 	*(cmd++) = 0;
   1048      1.1  macallan 	*(cmd++) = DBRI_TS_ANCHOR | DBRI_TS_NEXT(16);
   1049      1.1  macallan 
   1050      1.1  macallan 	sc->sc_pipe[16].sdp = 1;
   1051      1.1  macallan 	sc->sc_pipe[16].next = 16;
   1052      1.1  macallan 	sc->sc_chi_pipe_in = 16;
   1053      1.1  macallan 	sc->sc_chi_pipe_out = 16;
   1054      1.1  macallan 
   1055      1.1  macallan 	switch (ms) {
   1056      1.1  macallan 	case CHIslave:
   1057      1.1  macallan 		*(cmd++) = DBRI_CMD(DBRI_COMMAND_CHI, 0, DBRI_CHI_CHICM(0));
   1058      1.1  macallan 		break;
   1059      1.1  macallan 	case CHImaster:
   1060      1.1  macallan 		clockrate = bpf * 8;
   1061      1.1  macallan 		divisor = 12288 / clockrate;
   1062      1.1  macallan 
   1063      1.1  macallan 		if (divisor > 255 || divisor * clockrate != 12288)
   1064  1.9.2.1        ad 			aprint_error("%s: illegal bits-per-frame %d\n",
   1065      1.1  macallan 			    sc->sc_dev.dv_xname, bpf);
   1066      1.1  macallan 
   1067      1.1  macallan 		*(cmd++) = DBRI_CMD(DBRI_COMMAND_CHI, 0,
   1068      1.1  macallan 		    DBRI_CHI_CHICM(divisor) | DBRI_CHI_FD | DBRI_CHI_BPF(bpf));
   1069      1.1  macallan 		break;
   1070      1.1  macallan 	default:
   1071  1.9.2.1        ad 		aprint_error("%s: unknown value for ms!\n", sc->sc_dev.dv_xname);
   1072      1.1  macallan 		break;
   1073      1.1  macallan 	}
   1074      1.1  macallan 
   1075      1.1  macallan 	sc->sc_chi_bpf = bpf;
   1076      1.1  macallan 
   1077      1.1  macallan 	/* CHI data mode */
   1078      1.1  macallan 	*(cmd++) = DBRI_CMD(DBRI_COMMAND_PAUSE, 0, 0);
   1079      1.1  macallan 	*(cmd++) = DBRI_CMD(DBRI_COMMAND_CDM, 0,
   1080      1.1  macallan 	    DBRI_CDM_XCE | DBRI_CDM_XEN | DBRI_CDM_REN);
   1081      1.1  macallan 
   1082      1.1  macallan 	dbri_command_send(sc, cmd);
   1083      1.1  macallan 
   1084      1.1  macallan 	return;
   1085      1.1  macallan }
   1086      1.1  macallan 
   1087      1.1  macallan /*
   1088      1.1  macallan  * pipe stuff
   1089      1.1  macallan  */
   1090  1.9.2.1        ad static void
   1091      1.1  macallan pipe_setup(struct dbri_softc *sc, int pipe, int sdp)
   1092      1.1  macallan {
   1093  1.9.2.1        ad 	DPRINTF("pipe setup: %d\n", pipe);
   1094      1.1  macallan 	if (pipe < 0 || pipe >= DBRI_PIPE_MAX) {
   1095  1.9.2.1        ad 		aprint_error("%s: illegal pipe number %d\n", sc->sc_dev.dv_xname,
   1096      1.1  macallan 		    pipe);
   1097      1.1  macallan 		return;
   1098      1.1  macallan 	}
   1099      1.1  macallan 
   1100      1.1  macallan 	if ((sdp & 0xf800) != sdp)
   1101  1.9.2.1        ad 		aprint_error("%s: strange SDP value %d\n", sc->sc_dev.dv_xname, sdp);
   1102      1.1  macallan 
   1103      1.1  macallan 	if (DBRI_SDP_MODE(sdp) == DBRI_SDP_FIXED &&
   1104      1.1  macallan 	    !(sdp & DBRI_SDP_TO_SER))
   1105      1.1  macallan 		sdp |= DBRI_SDP_CHANGE;
   1106      1.1  macallan 
   1107      1.1  macallan 	sdp |= DBRI_PIPE(pipe);
   1108      1.1  macallan 
   1109      1.1  macallan 	sc->sc_pipe[pipe].sdp = sdp;
   1110      1.1  macallan 	sc->sc_pipe[pipe].desc = -1;
   1111      1.1  macallan 
   1112      1.1  macallan 	pipe_reset(sc, pipe);
   1113      1.1  macallan 
   1114      1.1  macallan 	return;
   1115      1.1  macallan }
   1116      1.1  macallan 
   1117  1.9.2.1        ad static void
   1118      1.1  macallan pipe_reset(struct dbri_softc *sc, int pipe)
   1119      1.1  macallan {
   1120      1.1  macallan 	struct dbri_desc *dd;
   1121      1.1  macallan 	int sdp;
   1122      1.1  macallan 	int desc;
   1123      1.1  macallan 	volatile u_int32_t *cmd;
   1124      1.1  macallan 
   1125      1.1  macallan 	if (pipe < 0 || pipe >= DBRI_PIPE_MAX) {
   1126  1.9.2.1        ad 		aprint_error("%s: illegal pipe number %d\n", sc->sc_dev.dv_xname,
   1127      1.1  macallan 		    pipe);
   1128      1.1  macallan 		return;
   1129      1.1  macallan 	}
   1130      1.1  macallan 
   1131      1.1  macallan 	sdp = sc->sc_pipe[pipe].sdp;
   1132      1.1  macallan 	if (sdp == 0) {
   1133  1.9.2.1        ad 		aprint_error("%s: can not reset uninitialized pipe %d\n",
   1134      1.1  macallan 		    sc->sc_dev.dv_xname, pipe);
   1135      1.1  macallan 		return;
   1136      1.1  macallan 	}
   1137      1.1  macallan 
   1138      1.1  macallan 	cmd = dbri_command_lock(sc);
   1139      1.1  macallan 	*(cmd++) = DBRI_CMD(DBRI_COMMAND_SDP, 0,
   1140      1.1  macallan 	    sdp | DBRI_SDP_CLEAR | DBRI_SDP_VALID_POINTER);
   1141      1.1  macallan 	*(cmd++) = 0;
   1142      1.1  macallan 	dbri_command_send(sc, cmd);
   1143      1.1  macallan 
   1144      1.1  macallan 	desc = sc->sc_pipe[pipe].desc;
   1145      1.1  macallan 
   1146      1.1  macallan 	dd = &sc->sc_desc[desc];
   1147      1.5     blymn 
   1148      1.1  macallan 	dd->busy = 0;
   1149      1.1  macallan 
   1150  1.9.2.1        ad #if 0
   1151      1.1  macallan 	if (dd->callback)
   1152      1.1  macallan 		(*dd->callback)(dd->callback_args);
   1153  1.9.2.1        ad #endif
   1154      1.1  macallan 
   1155      1.1  macallan 	sc->sc_pipe[pipe].desc = -1;
   1156      1.1  macallan 
   1157      1.1  macallan 	return;
   1158      1.1  macallan }
   1159      1.1  macallan 
   1160  1.9.2.1        ad static void
   1161      1.1  macallan pipe_receive_fixed(struct dbri_softc *sc, int pipe, volatile u_int32_t *prec)
   1162      1.1  macallan {
   1163      1.1  macallan 
   1164      1.1  macallan 	if (pipe < DBRI_PIPE_MAX / 2 || pipe >= DBRI_PIPE_MAX) {
   1165  1.9.2.1        ad 		aprint_error("%s: illegal pipe number %d\n",
   1166  1.9.2.1        ad 		    sc->sc_dev.dv_xname, pipe);
   1167      1.1  macallan 		return;
   1168      1.1  macallan 	}
   1169      1.1  macallan 
   1170      1.1  macallan 	if (DBRI_SDP_MODE(sc->sc_pipe[pipe].sdp) != DBRI_SDP_FIXED) {
   1171  1.9.2.1        ad 		aprint_error("%s: non-fixed pipe %d\n", sc->sc_dev.dv_xname,
   1172      1.1  macallan 		    pipe);
   1173      1.1  macallan 		return;
   1174      1.1  macallan 	}
   1175      1.1  macallan 
   1176      1.1  macallan 	if (sc->sc_pipe[pipe].sdp & DBRI_SDP_TO_SER) {
   1177  1.9.2.1        ad 		aprint_error("%s: can not receive on transmit pipe %d\b",
   1178      1.1  macallan 		    sc->sc_dev.dv_xname, pipe);
   1179      1.1  macallan 		return;
   1180      1.1  macallan 	}
   1181      1.1  macallan 
   1182      1.1  macallan 	sc->sc_pipe[pipe].prec = prec;
   1183      1.1  macallan 
   1184      1.1  macallan 	return;
   1185      1.1  macallan }
   1186      1.1  macallan 
   1187  1.9.2.1        ad static void
   1188      1.1  macallan pipe_transmit_fixed(struct dbri_softc *sc, int pipe, u_int32_t data)
   1189      1.1  macallan {
   1190      1.1  macallan 	volatile u_int32_t *cmd;
   1191      1.1  macallan 
   1192      1.1  macallan 	if (pipe < DBRI_PIPE_MAX / 2 || pipe >= DBRI_PIPE_MAX) {
   1193  1.9.2.1        ad 		aprint_error("%s: illegal pipe number %d\n",
   1194  1.9.2.1        ad 		    sc->sc_dev.dv_xname, pipe);
   1195      1.1  macallan 		return;
   1196      1.1  macallan 	}
   1197      1.1  macallan 
   1198      1.1  macallan 	if (DBRI_SDP_MODE(sc->sc_pipe[pipe].sdp) == 0) {
   1199  1.9.2.1        ad 		aprint_error("%s: uninitialized pipe %d\n",
   1200  1.9.2.1        ad 		    sc->sc_dev.dv_xname, pipe);
   1201      1.1  macallan 		return;
   1202      1.1  macallan 	}
   1203      1.1  macallan 
   1204      1.1  macallan 	if (DBRI_SDP_MODE(sc->sc_pipe[pipe].sdp) != DBRI_SDP_FIXED) {
   1205  1.9.2.1        ad 		aprint_error("%s: non-fixed pipe %d\n", sc->sc_dev.dv_xname,
   1206  1.9.2.1        ad 		    pipe);
   1207      1.1  macallan 		return;
   1208      1.1  macallan 	}
   1209      1.1  macallan 
   1210      1.1  macallan 	if (!(sc->sc_pipe[pipe].sdp & DBRI_SDP_TO_SER)) {
   1211  1.9.2.1        ad 		aprint_error("%s: called on receive pipe %d\n",
   1212  1.9.2.1        ad 		    sc->sc_dev.dv_xname, pipe);
   1213      1.1  macallan 		return;
   1214      1.1  macallan 	}
   1215      1.1  macallan 
   1216      1.1  macallan 	if (sc->sc_pipe[pipe].sdp & DBRI_SDP_MSB)
   1217      1.1  macallan 		data = reverse_bytes(data, sc->sc_pipe[pipe].length);
   1218      1.1  macallan 
   1219      1.1  macallan 	cmd = dbri_command_lock(sc);
   1220      1.1  macallan 	*(cmd++) = DBRI_CMD(DBRI_COMMAND_SSP, 0, pipe);
   1221      1.1  macallan 	*(cmd++) = data;
   1222      1.1  macallan 
   1223      1.1  macallan 	dbri_command_send(sc, cmd);
   1224      1.1  macallan 
   1225      1.1  macallan 	return;
   1226      1.1  macallan }
   1227      1.1  macallan 
   1228  1.9.2.1        ad static void
   1229      1.1  macallan setup_ring(struct dbri_softc *sc, int pipe, int which, int num, int blksz,
   1230      1.1  macallan 		void (*callback)(void *), void *callback_args)
   1231      1.1  macallan {
   1232      1.1  macallan 	volatile u_int32_t *cmd;
   1233      1.1  macallan 	int x, i;
   1234      1.1  macallan 	int td;
   1235      1.1  macallan 	int td_first, td_last;
   1236      1.1  macallan 	bus_addr_t dmabuf, dmabase;
   1237      1.1  macallan 	struct dbri_desc *dd = &sc->sc_desc[which];
   1238      1.1  macallan 
   1239      1.1  macallan 	td = 0;
   1240      1.1  macallan 	td_first = td_last = -1;
   1241      1.1  macallan 
   1242      1.1  macallan 	if (pipe < 0 || pipe >= DBRI_PIPE_MAX / 2) {
   1243  1.9.2.1        ad 		aprint_error("%s: illegal pipe number %d\n",
   1244  1.9.2.1        ad 		    sc->sc_dev.dv_xname, pipe);
   1245      1.1  macallan 		return;
   1246      1.1  macallan 	}
   1247      1.1  macallan 
   1248      1.1  macallan 	if (sc->sc_pipe[pipe].sdp == 0) {
   1249  1.9.2.1        ad 		aprint_error("%s: uninitialized pipe %d\n",
   1250  1.9.2.1        ad 		    sc->sc_dev.dv_xname, pipe);
   1251      1.1  macallan 		return;
   1252      1.1  macallan 	}
   1253      1.1  macallan 
   1254      1.1  macallan 	if (!(sc->sc_pipe[pipe].sdp & DBRI_SDP_TO_SER)) {
   1255  1.9.2.1        ad 		aprint_error("%s: called on receive pipe %d\n",
   1256      1.1  macallan 		    sc->sc_dev.dv_xname, pipe);
   1257      1.1  macallan 		return;
   1258      1.1  macallan 	}
   1259      1.1  macallan 
   1260      1.1  macallan 
   1261      1.1  macallan 	dmabuf = dd->dmabase;
   1262      1.1  macallan 	dmabase = sc->sc_dmabase;
   1263      1.1  macallan 	td = 0;
   1264      1.1  macallan 
   1265      1.1  macallan 	for (i = 0; i < (num-1); i++) {
   1266      1.1  macallan 
   1267      1.5     blymn 		sc->sc_dma->desc[i].flags = TX_BCNT(blksz)
   1268      1.1  macallan 		    | TX_EOF | TX_BINT;
   1269      1.1  macallan 		sc->sc_dma->desc[i].ba = dmabuf;
   1270      1.1  macallan 		sc->sc_dma->desc[i].nda = dmabase + dbri_dma_off(desc, i + 1);
   1271      1.1  macallan 		sc->sc_dma->desc[i].status = 0;
   1272      1.1  macallan 
   1273      1.1  macallan 		td_last = td;
   1274      1.1  macallan 		dmabuf += blksz;
   1275      1.1  macallan 	}
   1276      1.5     blymn 
   1277      1.1  macallan 	sc->sc_dma->desc[i].flags = TX_BCNT(blksz) | TX_EOF | TX_BINT;
   1278      1.1  macallan 	sc->sc_dma->desc[i].ba = dmabuf;
   1279      1.1  macallan 	sc->sc_dma->desc[i].nda = dmabase + dbri_dma_off(desc, 0);
   1280      1.1  macallan 	sc->sc_dma->desc[i].status = 0;
   1281      1.5     blymn 
   1282  1.9.2.1        ad 	dd->callback = callback;
   1283  1.9.2.1        ad 	dd->callback_args = callback_args;
   1284      1.1  macallan 
   1285      1.1  macallan 	x = splaudio();
   1286      1.1  macallan 
   1287      1.1  macallan 	/* the pipe shouldn't be active */
   1288      1.1  macallan 	if (pipe_active(sc, pipe)) {
   1289  1.9.2.1        ad 		aprint_error("pipe active (CDP)\n");
   1290      1.1  macallan 		/* pipe is already active */
   1291  1.9.2.1        ad #if 0
   1292      1.1  macallan 		td_last = sc->sc_pipe[pipe].desc;
   1293      1.1  macallan 		while (sc->sc_desc[td_last].next != -1)
   1294      1.1  macallan 			td_last = sc->sc_desc[td_last].next;
   1295      1.1  macallan 
   1296      1.1  macallan 		sc->sc_desc[td_last].next = td_first;
   1297      1.1  macallan 		sc->sc_dma->desc[td_last].nda =
   1298      1.1  macallan 		    sc->sc_dmabase + dbri_dma_off(desc, td_first);
   1299      1.1  macallan 
   1300      1.1  macallan 		cmd = dbri_command_lock(sc);
   1301      1.1  macallan 		*(cmd++) = DBRI_CMD(DBRI_COMMAND_CDP, 0, pipe);
   1302      1.1  macallan 		dbri_command_send(sc, cmd);
   1303  1.9.2.1        ad #endif
   1304      1.1  macallan 	} else {
   1305      1.1  macallan 		/*
   1306      1.1  macallan 		 * pipe isn't active - issue an SDP command to start our
   1307      1.1  macallan 		 * chain of TDs running
   1308      1.1  macallan 		 */
   1309      1.1  macallan 		sc->sc_pipe[pipe].desc = which;
   1310      1.1  macallan 		cmd = dbri_command_lock(sc);
   1311      1.1  macallan 		*(cmd++) = DBRI_CMD(DBRI_COMMAND_SDP, 0,
   1312      1.1  macallan 					sc->sc_pipe[pipe].sdp |
   1313      1.1  macallan 					DBRI_SDP_VALID_POINTER |
   1314      1.1  macallan 					DBRI_SDP_EVERY |
   1315      1.1  macallan 					DBRI_SDP_CLEAR);
   1316      1.1  macallan 		*(cmd++) = sc->sc_dmabase + dbri_dma_off(desc, 0);
   1317      1.1  macallan 		dbri_command_send(sc, cmd);
   1318      1.1  macallan 	}
   1319      1.1  macallan 
   1320      1.1  macallan 	splx(x);
   1321      1.1  macallan 
   1322      1.1  macallan 	return;
   1323      1.1  macallan }
   1324      1.1  macallan 
   1325  1.9.2.1        ad static void
   1326      1.1  macallan pipe_ts_link(struct dbri_softc *sc, int pipe, enum io dir, int basepipe,
   1327      1.1  macallan 		int len, int cycle)
   1328      1.1  macallan {
   1329      1.1  macallan 	volatile u_int32_t *cmd;
   1330      1.1  macallan 	int prevpipe, nextpipe;
   1331      1.1  macallan 	int val;
   1332      1.1  macallan 
   1333      1.1  macallan 	if (pipe < 0 || pipe >= DBRI_PIPE_MAX ||
   1334      1.1  macallan 	    basepipe < 0 || basepipe >= DBRI_PIPE_MAX) {
   1335  1.9.2.1        ad 		aprint_error("%s: illegal pipe numbers (%d, %d)\n",
   1336      1.1  macallan 		    sc->sc_dev.dv_xname, pipe, basepipe);
   1337      1.1  macallan 		return;
   1338      1.1  macallan 	}
   1339      1.1  macallan 
   1340      1.1  macallan 	if (sc->sc_pipe[pipe].sdp == 0 || sc->sc_pipe[basepipe].sdp == 0) {
   1341  1.9.2.1        ad 		aprint_error("%s: uninitialized pipe (%d, %d)\n",
   1342      1.1  macallan 		    sc->sc_dev.dv_xname, pipe, basepipe);
   1343      1.1  macallan 		return;
   1344      1.1  macallan 	}
   1345      1.1  macallan 
   1346      1.1  macallan 	if (basepipe == 16 && dir == PIPEoutput && cycle == 0)
   1347      1.1  macallan 		cycle = sc->sc_chi_bpf;
   1348      1.1  macallan 
   1349      1.1  macallan 	if (basepipe == pipe)
   1350      1.1  macallan 		prevpipe = nextpipe = pipe;
   1351      1.1  macallan 	else {
   1352      1.1  macallan 		if (basepipe == 16) {
   1353      1.1  macallan 			if (dir == PIPEinput) {
   1354      1.1  macallan 				prevpipe = sc->sc_chi_pipe_in;
   1355      1.1  macallan 			} else {
   1356      1.1  macallan 				prevpipe = sc->sc_chi_pipe_out;
   1357      1.1  macallan 			}
   1358      1.1  macallan 		} else
   1359      1.1  macallan 			prevpipe = basepipe;
   1360      1.1  macallan 
   1361      1.1  macallan 		nextpipe = sc->sc_pipe[prevpipe].next;
   1362      1.1  macallan 
   1363      1.1  macallan 		while (sc->sc_pipe[nextpipe].cycle < cycle &&
   1364      1.1  macallan 		    sc->sc_pipe[nextpipe].next != basepipe) {
   1365      1.1  macallan 			prevpipe = nextpipe;
   1366      1.1  macallan 			nextpipe = sc->sc_pipe[nextpipe].next;
   1367      1.1  macallan 		}
   1368      1.1  macallan 	}
   1369      1.1  macallan 
   1370      1.1  macallan 	if (prevpipe == 16) {
   1371      1.1  macallan 		if (dir == PIPEinput) {
   1372      1.1  macallan 			sc->sc_chi_pipe_in = pipe;
   1373      1.1  macallan 		} else {
   1374      1.1  macallan 			sc->sc_chi_pipe_out = pipe;
   1375      1.1  macallan 		}
   1376      1.1  macallan 	} else
   1377      1.1  macallan 		sc->sc_pipe[prevpipe].next = pipe;
   1378      1.1  macallan 
   1379      1.1  macallan 	sc->sc_pipe[pipe].next = nextpipe;
   1380      1.1  macallan 	sc->sc_pipe[pipe].cycle = cycle;
   1381      1.1  macallan 	sc->sc_pipe[pipe].length = len;
   1382      1.1  macallan 
   1383      1.1  macallan 	cmd = dbri_command_lock(sc);
   1384      1.1  macallan 
   1385      1.1  macallan 	switch (dir) {
   1386      1.1  macallan 	case PIPEinput:
   1387      1.1  macallan 		val = DBRI_DTS_VI | DBRI_DTS_INS | DBRI_DTS_PRVIN(prevpipe);
   1388      1.1  macallan 		val |= pipe;
   1389      1.1  macallan 		*(cmd++) = DBRI_CMD(DBRI_COMMAND_DTS, 0, val);
   1390      1.1  macallan 		*(cmd++) = DBRI_TS_LEN(len) | DBRI_TS_CYCLE(cycle) |
   1391      1.1  macallan 		    DBRI_TS_NEXT(nextpipe);
   1392      1.1  macallan 		*(cmd++) = 0;
   1393      1.1  macallan 		break;
   1394      1.1  macallan 	case PIPEoutput:
   1395      1.1  macallan 		val = DBRI_DTS_VO | DBRI_DTS_INS | DBRI_DTS_PRVOUT(prevpipe);
   1396      1.1  macallan 		val |= pipe;
   1397      1.1  macallan 		*(cmd++) = DBRI_CMD(DBRI_COMMAND_DTS, 0, val);
   1398      1.1  macallan 		*(cmd++) = 0;
   1399      1.1  macallan 		*(cmd++) = DBRI_TS_LEN(len) | DBRI_TS_CYCLE(cycle) |
   1400      1.1  macallan 		    DBRI_TS_NEXT(nextpipe);
   1401      1.1  macallan 		break;
   1402      1.1  macallan 	default:
   1403  1.9.2.1        ad 		DPRINTF("%s: should not have happened!\n",
   1404      1.1  macallan 		    sc->sc_dev.dv_xname);
   1405      1.1  macallan 		break;
   1406      1.1  macallan 	}
   1407      1.1  macallan 
   1408      1.1  macallan 	dbri_command_send(sc, cmd);
   1409      1.1  macallan 
   1410      1.1  macallan 	return;
   1411      1.1  macallan }
   1412      1.1  macallan 
   1413  1.9.2.1        ad static int
   1414      1.1  macallan pipe_active(struct dbri_softc *sc, int pipe)
   1415      1.1  macallan {
   1416      1.1  macallan 
   1417      1.1  macallan 	return (sc->sc_pipe[pipe].desc != -1);
   1418      1.1  macallan }
   1419      1.1  macallan 
   1420      1.1  macallan /*
   1421      1.1  macallan  * subroutines required to interface with audio(9)
   1422      1.1  macallan  */
   1423      1.1  macallan 
   1424  1.9.2.1        ad static int
   1425      1.1  macallan dbri_query_encoding(void *hdl, struct audio_encoding *ae)
   1426      1.1  macallan {
   1427      1.1  macallan 
   1428      1.1  macallan 	switch (ae->index) {
   1429      1.1  macallan 	case 0:
   1430      1.1  macallan 		strcpy(ae->name, AudioEulinear);
   1431      1.1  macallan 		ae->encoding = AUDIO_ENCODING_ULINEAR;
   1432      1.1  macallan 		ae->precision = 8;
   1433  1.9.2.1        ad 		ae->flags = 0;
   1434      1.1  macallan 		break;
   1435      1.1  macallan 	case 1:
   1436      1.1  macallan 		strcpy(ae->name, AudioEmulaw);
   1437      1.1  macallan 		ae->encoding = AUDIO_ENCODING_ULAW;
   1438      1.1  macallan 		ae->precision = 8;
   1439      1.1  macallan 		ae->flags = 0;
   1440      1.1  macallan 		break;
   1441      1.1  macallan 	case 2:
   1442      1.1  macallan 		strcpy(ae->name, AudioEalaw);
   1443      1.1  macallan 		ae->encoding = AUDIO_ENCODING_ALAW;
   1444      1.1  macallan 		ae->precision = 8;
   1445      1.1  macallan 		ae->flags = 0;
   1446      1.1  macallan 		break;
   1447      1.1  macallan 	case 3:
   1448      1.1  macallan 		strcpy(ae->name, AudioEslinear);
   1449      1.1  macallan 		ae->encoding = AUDIO_ENCODING_SLINEAR;
   1450      1.1  macallan 		ae->precision = 8;
   1451      1.1  macallan 		ae->flags = AUDIO_ENCODINGFLAG_EMULATED;
   1452      1.1  macallan 		break;
   1453      1.1  macallan 	case 4:
   1454      1.1  macallan 		strcpy(ae->name, AudioEslinear_le);
   1455      1.1  macallan 		ae->encoding = AUDIO_ENCODING_SLINEAR_LE;
   1456      1.1  macallan 		ae->precision = 16;
   1457      1.1  macallan 		ae->flags = AUDIO_ENCODINGFLAG_EMULATED;
   1458      1.1  macallan 		break;
   1459      1.1  macallan 	case 5:
   1460      1.1  macallan 		strcpy(ae->name, AudioEulinear_le);
   1461      1.1  macallan 		ae->encoding = AUDIO_ENCODING_ULINEAR_LE;
   1462      1.1  macallan 		ae->precision = 16;
   1463      1.1  macallan 		ae->flags = AUDIO_ENCODINGFLAG_EMULATED;
   1464      1.1  macallan 		break;
   1465      1.1  macallan 	case 6:
   1466      1.1  macallan 		strcpy(ae->name, AudioEslinear_be);
   1467      1.1  macallan 		ae->encoding = AUDIO_ENCODING_SLINEAR_BE;
   1468      1.1  macallan 		ae->precision = 16;
   1469      1.1  macallan 		ae->flags = 0;
   1470      1.1  macallan 		break;
   1471      1.1  macallan 	case 7:
   1472      1.1  macallan 		strcpy(ae->name, AudioEulinear_be);
   1473      1.1  macallan 		ae->encoding = AUDIO_ENCODING_ULINEAR_BE;
   1474      1.1  macallan 		ae->precision = 16;
   1475  1.9.2.1        ad 		ae->flags = AUDIO_ENCODINGFLAG_EMULATED;
   1476  1.9.2.1        ad 		break;
   1477  1.9.2.1        ad 	case 8:
   1478  1.9.2.1        ad 		strcpy(ae->name, AudioEslinear);
   1479  1.9.2.1        ad 		ae->encoding = AUDIO_ENCODING_SLINEAR;
   1480  1.9.2.1        ad 		ae->precision = 16;
   1481      1.1  macallan 		ae->flags = 0;
   1482      1.1  macallan 		break;
   1483      1.1  macallan 	default:
   1484      1.1  macallan 		return (EINVAL);
   1485      1.1  macallan 	}
   1486      1.1  macallan 
   1487      1.1  macallan 	return (0);
   1488      1.1  macallan }
   1489      1.1  macallan 
   1490      1.1  macallan /*
   1491      1.1  macallan  * XXX: recording isn't supported - jmcneill
   1492      1.1  macallan  */
   1493  1.9.2.1        ad static int
   1494      1.1  macallan dbri_set_params(void *hdl, int setmode, int usemode,
   1495      1.1  macallan 		struct audio_params *play, struct audio_params *rec,
   1496      1.1  macallan 		stream_filter_list_t *pfil, stream_filter_list_t *rfil)
   1497      1.1  macallan {
   1498      1.1  macallan 	struct dbri_softc *sc = hdl;
   1499  1.9.2.1        ad 	int rate;
   1500  1.9.2.1        ad 	audio_params_t *p = NULL;
   1501  1.9.2.1        ad 	stream_filter_list_t *fil;
   1502  1.9.2.1        ad 	int mode;
   1503      1.1  macallan 
   1504  1.9.2.1        ad 	/*
   1505  1.9.2.1        ad 	 * This device only has one clock, so make the sample rates match.
   1506  1.9.2.1        ad 	 */
   1507  1.9.2.1        ad 	if (play->sample_rate != rec->sample_rate &&
   1508  1.9.2.1        ad 	    usemode == (AUMODE_PLAY | AUMODE_RECORD)) {
   1509  1.9.2.1        ad 		if (setmode == AUMODE_PLAY) {
   1510  1.9.2.1        ad 			rec->sample_rate = play->sample_rate;
   1511  1.9.2.1        ad 			setmode |= AUMODE_RECORD;
   1512  1.9.2.1        ad 		} else if (setmode == AUMODE_RECORD) {
   1513  1.9.2.1        ad 			play->sample_rate = rec->sample_rate;
   1514  1.9.2.1        ad 			setmode |= AUMODE_PLAY;
   1515  1.9.2.1        ad 		} else
   1516  1.9.2.1        ad 			return EINVAL;
   1517  1.9.2.1        ad 	}
   1518      1.1  macallan 
   1519  1.9.2.1        ad 	for (mode = AUMODE_RECORD; mode != -1;
   1520  1.9.2.1        ad 	     mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) {
   1521  1.9.2.1        ad 		if ((setmode & mode) == 0)
   1522  1.9.2.1        ad 			continue;
   1523  1.9.2.1        ad 
   1524  1.9.2.1        ad 		p = mode == AUMODE_PLAY ? play : rec;
   1525  1.9.2.1        ad 		if (p->sample_rate < 4000 || p->sample_rate > 50000) {
   1526  1.9.2.1        ad 			DPRINTF("dbri_set_params: invalid rate %d\n",
   1527  1.9.2.1        ad 			    p->sample_rate);
   1528  1.9.2.1        ad 			return EINVAL;
   1529  1.9.2.1        ad 		}
   1530  1.9.2.1        ad 
   1531  1.9.2.1        ad 		fil = mode == AUMODE_PLAY ? pfil : rfil;
   1532  1.9.2.1        ad 	DPRINTF("enc: %d rate: %d prec: %d chan: %d\n", p->encoding,
   1533  1.9.2.1        ad 	    p->sample_rate, p->precision, p->channels);
   1534  1.9.2.1        ad 		if (auconv_set_converter(dbri_formats, DBRI_NFORMATS,
   1535  1.9.2.1        ad 					 mode, p, true, fil) < 0) {
   1536  1.9.2.1        ad 			DPRINTF("dbri_set_params: auconv_set_converter failed\n");
   1537  1.9.2.1        ad 			return EINVAL;
   1538  1.9.2.1        ad 		}
   1539  1.9.2.1        ad 		if (fil->req_size > 0)
   1540  1.9.2.1        ad 			p = &fil->filters[0].param;
   1541  1.9.2.1        ad 	}
   1542  1.9.2.1        ad 
   1543  1.9.2.1        ad 	if (p == NULL) {
   1544  1.9.2.1        ad 		DPRINTF("dbri_set_params: no parameters to set\n");
   1545  1.9.2.1        ad 		return 0;
   1546  1.9.2.1        ad 	}
   1547  1.9.2.1        ad 
   1548  1.9.2.1        ad 	DPRINTF("enc: %d rate: %d prec: %d chan: %d\n", p->encoding,
   1549  1.9.2.1        ad 	    p->sample_rate, p->precision, p->channels);
   1550  1.9.2.1        ad 
   1551  1.9.2.1        ad 	for (rate = 0; CS4215_FREQ[rate].freq; rate++)
   1552  1.9.2.1        ad 		if (CS4215_FREQ[rate].freq == p->sample_rate)
   1553      1.1  macallan 			break;
   1554      1.1  macallan 
   1555  1.9.2.1        ad 	if (CS4215_FREQ[rate].freq == 0)
   1556      1.1  macallan 		return (EINVAL);
   1557      1.1  macallan 
   1558      1.1  macallan 	/* set frequency */
   1559      1.9  macallan 	sc->sc_mm.c.bcontrol[1] &= ~0x38;
   1560  1.9.2.1        ad 	sc->sc_mm.c.bcontrol[1] |= CS4215_FREQ[rate].csval;
   1561      1.9  macallan 	sc->sc_mm.c.bcontrol[2] &= ~0x70;
   1562  1.9.2.1        ad 	sc->sc_mm.c.bcontrol[2] |= CS4215_FREQ[rate].xtal;
   1563      1.1  macallan 
   1564  1.9.2.1        ad 	switch (p->encoding) {
   1565      1.1  macallan 	case AUDIO_ENCODING_ULAW:
   1566      1.9  macallan 		sc->sc_mm.c.bcontrol[1] &= ~3;
   1567      1.9  macallan 		sc->sc_mm.c.bcontrol[1] |= CS4215_DFR_ULAW;
   1568      1.1  macallan 		break;
   1569      1.1  macallan 	case AUDIO_ENCODING_ALAW:
   1570      1.9  macallan 		sc->sc_mm.c.bcontrol[1] &= ~3;
   1571      1.9  macallan 		sc->sc_mm.c.bcontrol[1] |= CS4215_DFR_ALAW;
   1572      1.1  macallan 		break;
   1573      1.1  macallan 	case AUDIO_ENCODING_ULINEAR:
   1574      1.9  macallan 		sc->sc_mm.c.bcontrol[1] &= ~3;
   1575  1.9.2.1        ad 		if (p->precision == 8) {
   1576      1.9  macallan 			sc->sc_mm.c.bcontrol[1] |= CS4215_DFR_LINEAR8;
   1577      1.1  macallan 		} else {
   1578      1.9  macallan 			sc->sc_mm.c.bcontrol[1] |= CS4215_DFR_LINEAR16;
   1579      1.1  macallan 		}
   1580      1.1  macallan 		break;
   1581      1.1  macallan 	case AUDIO_ENCODING_SLINEAR_BE:
   1582  1.9.2.1        ad 	case AUDIO_ENCODING_SLINEAR:
   1583      1.9  macallan 		sc->sc_mm.c.bcontrol[1] &= ~3;
   1584      1.9  macallan 		sc->sc_mm.c.bcontrol[1] |= CS4215_DFR_LINEAR16;
   1585      1.1  macallan 		break;
   1586      1.1  macallan 	}
   1587      1.1  macallan 
   1588  1.9.2.1        ad 	switch (p->channels) {
   1589      1.1  macallan 	case 1:
   1590      1.9  macallan 		sc->sc_mm.c.bcontrol[1] &= ~CS4215_DFR_STEREO;
   1591      1.1  macallan 		break;
   1592      1.1  macallan 	case 2:
   1593      1.9  macallan 		sc->sc_mm.c.bcontrol[1] |= CS4215_DFR_STEREO;
   1594      1.1  macallan 		break;
   1595      1.1  macallan 	}
   1596      1.1  macallan 
   1597      1.1  macallan 	return (0);
   1598      1.1  macallan }
   1599      1.1  macallan 
   1600  1.9.2.1        ad static int
   1601      1.1  macallan dbri_round_blocksize(void *hdl, int bs, int mode,
   1602      1.1  macallan 			const audio_params_t *param)
   1603      1.1  macallan {
   1604      1.1  macallan 
   1605      1.1  macallan 	/* DBRI DMA segment size, rounded town to 32bit alignment */
   1606      1.5     blymn 	return 0x1ffc;
   1607      1.1  macallan }
   1608      1.1  macallan 
   1609  1.9.2.1        ad static int
   1610      1.1  macallan dbri_halt_output(void *hdl)
   1611      1.1  macallan {
   1612      1.1  macallan 	struct dbri_softc *sc = hdl;
   1613      1.1  macallan 
   1614  1.9.2.2        ad 	sc->sc_playing = 0;
   1615      1.1  macallan 	pipe_reset(sc, 4);
   1616      1.1  macallan 	return (0);
   1617      1.1  macallan }
   1618      1.1  macallan 
   1619  1.9.2.1        ad static int
   1620      1.1  macallan dbri_getdev(void *hdl, struct audio_device *ret)
   1621      1.1  macallan {
   1622      1.1  macallan 
   1623      1.1  macallan 	*ret = dbri_device;
   1624      1.1  macallan 	return (0);
   1625      1.1  macallan }
   1626      1.1  macallan 
   1627  1.9.2.1        ad static int
   1628      1.1  macallan dbri_set_port(void *hdl, mixer_ctrl_t *mc)
   1629      1.1  macallan {
   1630      1.1  macallan 	struct dbri_softc *sc = hdl;
   1631      1.1  macallan 	int latt = sc->sc_latt, ratt = sc->sc_ratt;
   1632      1.1  macallan 
   1633      1.1  macallan 	switch (mc->dev) {
   1634      1.1  macallan 	    case DBRI_VOL_OUTPUT:	/* master volume */
   1635      1.1  macallan 		latt = (latt & 0xc0) | (63 -
   1636      1.1  macallan 		    min(mc->un.value.level[AUDIO_MIXER_LEVEL_LEFT] >> 2, 63));
   1637      1.5     blymn 		ratt = (ratt & 0xc0) | (63 -
   1638      1.5     blymn 		    min(mc->un.value.level[AUDIO_MIXER_LEVEL_RIGHT] >> 2, 63));
   1639      1.1  macallan 		break;
   1640      1.1  macallan 	    case DBRI_ENABLE_MONO:	/* built-in speaker */
   1641      1.1  macallan 	    	if (mc->un.ord == 1) {
   1642      1.1  macallan 			ratt |= CS4215_SE;
   1643      1.1  macallan 		} else
   1644      1.1  macallan 			ratt &= ~CS4215_SE;
   1645      1.1  macallan 		break;
   1646      1.1  macallan 	    case DBRI_ENABLE_HEADPHONE:	/* headphones output */
   1647      1.1  macallan 	    	if (mc->un.ord == 1) {
   1648      1.1  macallan 			latt |= CS4215_HE;
   1649      1.1  macallan 		} else
   1650      1.1  macallan 			latt &= ~CS4215_HE;
   1651      1.1  macallan 		break;
   1652      1.1  macallan 	    case DBRI_ENABLE_LINE:	/* line out */
   1653      1.1  macallan 	    	if (mc->un.ord == 1) {
   1654      1.1  macallan 			latt |= CS4215_LE;
   1655      1.1  macallan 		} else
   1656      1.1  macallan 			latt &= ~CS4215_LE;
   1657      1.1  macallan 		break;
   1658  1.9.2.2        ad 	    case DBRI_VOL_MONITOR:
   1659  1.9.2.2        ad 		if (mc->un.value.level[AUDIO_MIXER_LEVEL_LEFT] ==
   1660  1.9.2.2        ad 		    sc->sc_monitor)
   1661  1.9.2.2        ad 			return 0;
   1662  1.9.2.2        ad 		sc->sc_monitor = mc->un.value.level[AUDIO_MIXER_LEVEL_LEFT];
   1663  1.9.2.2        ad 		break;
   1664  1.9.2.2        ad 	    case DBRI_INPUT_GAIN:
   1665  1.9.2.2        ad 		sc->sc_linp = mc->un.value.level[AUDIO_MIXER_LEVEL_LEFT];
   1666  1.9.2.2        ad 		sc->sc_rinp = mc->un.value.level[AUDIO_MIXER_LEVEL_RIGHT];
   1667  1.9.2.2        ad 		break;
   1668  1.9.2.2        ad 	    case DBRI_INPUT_SELECT:
   1669  1.9.2.2        ad 	    	if (mc->un.mask == sc->sc_input)
   1670  1.9.2.2        ad 	    		return 0;
   1671  1.9.2.2        ad 	    	sc->sc_input =  mc->un.mask;
   1672  1.9.2.2        ad 	    	break;
   1673      1.1  macallan 	}
   1674      1.5     blymn 
   1675      1.1  macallan 	sc->sc_latt = latt;
   1676      1.1  macallan 	sc->sc_ratt = ratt;
   1677      1.1  macallan 
   1678      1.1  macallan 	mmcodec_setgain(sc, 0);
   1679      1.1  macallan 
   1680      1.1  macallan 	return (0);
   1681      1.1  macallan }
   1682      1.1  macallan 
   1683  1.9.2.1        ad static int
   1684      1.1  macallan dbri_get_port(void *hdl, mixer_ctrl_t *mc)
   1685      1.1  macallan {
   1686      1.1  macallan 	struct dbri_softc *sc = hdl;
   1687      1.1  macallan 
   1688      1.1  macallan 	switch (mc->dev) {
   1689      1.1  macallan 	    case DBRI_VOL_OUTPUT:	/* master volume */
   1690      1.5     blymn 		mc->un.value.level[AUDIO_MIXER_LEVEL_LEFT] =
   1691      1.1  macallan 		    (63 - (sc->sc_latt & 0x3f)) << 2;
   1692      1.1  macallan 		mc->un.value.level[AUDIO_MIXER_LEVEL_RIGHT] =
   1693      1.1  macallan 		    (63 - (sc->sc_ratt & 0x3f)) << 2;
   1694      1.1  macallan 		return (0);
   1695      1.1  macallan 	    case DBRI_ENABLE_MONO:	/* built-in speaker */
   1696      1.1  macallan 	    	mc->un.ord = (sc->sc_ratt & CS4215_SE) ? 1 : 0;
   1697      1.1  macallan 		return 0;
   1698      1.1  macallan 	    case DBRI_ENABLE_HEADPHONE:	/* headphones output */
   1699      1.1  macallan 	    	mc->un.ord = (sc->sc_latt & CS4215_HE) ? 1 : 0;
   1700      1.1  macallan 		return 0;
   1701      1.1  macallan 	    case DBRI_ENABLE_LINE:	/* line out */
   1702      1.1  macallan 	    	mc->un.ord = (sc->sc_latt & CS4215_LE) ? 1 : 0;
   1703      1.1  macallan 		return 0;
   1704  1.9.2.2        ad 	    case DBRI_VOL_MONITOR:
   1705  1.9.2.2        ad 		mc->un.value.level[AUDIO_MIXER_LEVEL_LEFT] = sc->sc_monitor;
   1706  1.9.2.2        ad 		return 0;
   1707  1.9.2.2        ad 	    case DBRI_INPUT_GAIN:
   1708  1.9.2.2        ad 		mc->un.value.level[AUDIO_MIXER_LEVEL_LEFT] = sc->sc_linp;
   1709  1.9.2.2        ad 		mc->un.value.level[AUDIO_MIXER_LEVEL_RIGHT] = sc->sc_rinp;
   1710  1.9.2.2        ad 		return 0;
   1711  1.9.2.2        ad 	    case DBRI_INPUT_SELECT:
   1712  1.9.2.2        ad 	    	mc->un.mask = sc->sc_input;
   1713  1.9.2.2        ad 	    	return 0;
   1714      1.1  macallan 	}
   1715      1.1  macallan 	return (EINVAL);
   1716      1.1  macallan }
   1717      1.1  macallan 
   1718  1.9.2.1        ad static int
   1719      1.1  macallan dbri_query_devinfo(void *hdl, mixer_devinfo_t *di)
   1720      1.1  macallan {
   1721      1.1  macallan 
   1722      1.1  macallan 	switch (di->index) {
   1723      1.1  macallan 	case DBRI_MONITOR_CLASS:
   1724      1.1  macallan 		di->mixer_class = DBRI_MONITOR_CLASS;
   1725      1.1  macallan 		strcpy(di->label.name, AudioCmonitor);
   1726      1.1  macallan 		di->type = AUDIO_MIXER_CLASS;
   1727      1.1  macallan 		di->next = di->prev = AUDIO_MIXER_LAST;
   1728      1.1  macallan 		return 0;
   1729  1.9.2.2        ad 	case DBRI_OUTPUT_CLASS:
   1730  1.9.2.2        ad 		di->mixer_class = DBRI_OUTPUT_CLASS;
   1731  1.9.2.2        ad 		strcpy(di->label.name, AudioCoutputs);
   1732  1.9.2.2        ad 		di->type = AUDIO_MIXER_CLASS;
   1733  1.9.2.2        ad 		di->next = di->prev = AUDIO_MIXER_LAST;
   1734  1.9.2.2        ad 		return 0;
   1735  1.9.2.2        ad 	case DBRI_INPUT_CLASS:
   1736  1.9.2.2        ad 		di->mixer_class = DBRI_INPUT_CLASS;
   1737  1.9.2.2        ad 		strcpy(di->label.name, AudioCinputs);
   1738  1.9.2.2        ad 		di->type = AUDIO_MIXER_CLASS;
   1739  1.9.2.2        ad 		di->next = di->prev = AUDIO_MIXER_LAST;
   1740  1.9.2.2        ad 		return 0;
   1741      1.1  macallan 	case DBRI_VOL_OUTPUT:	/* master volume */
   1742  1.9.2.2        ad 		di->mixer_class = DBRI_OUTPUT_CLASS;
   1743      1.1  macallan 		di->next = di->prev = AUDIO_MIXER_LAST;
   1744      1.1  macallan 		strcpy(di->label.name, AudioNmaster);
   1745      1.1  macallan 		di->type = AUDIO_MIXER_VALUE;
   1746      1.1  macallan 		di->un.v.num_channels = 2;
   1747      1.1  macallan 		strcpy(di->un.v.units.name, AudioNvolume);
   1748      1.1  macallan 		return (0);
   1749  1.9.2.2        ad 	case DBRI_INPUT_GAIN:	/* input gain */
   1750  1.9.2.2        ad 		di->mixer_class = DBRI_INPUT_CLASS;
   1751  1.9.2.2        ad 		di->next = di->prev = AUDIO_MIXER_LAST;
   1752  1.9.2.2        ad 		strcpy(di->label.name, AudioNrecord);
   1753  1.9.2.2        ad 		di->type = AUDIO_MIXER_VALUE;
   1754  1.9.2.2        ad 		di->un.v.num_channels = 2;
   1755  1.9.2.2        ad 		strcpy(di->un.v.units.name, AudioNvolume);
   1756  1.9.2.2        ad 		return (0);
   1757  1.9.2.2        ad 	case DBRI_VOL_MONITOR:	/* monitor volume */
   1758      1.1  macallan 		di->mixer_class = DBRI_MONITOR_CLASS;
   1759      1.1  macallan 		di->next = di->prev = AUDIO_MIXER_LAST;
   1760  1.9.2.2        ad 		strcpy(di->label.name, AudioNmonitor);
   1761  1.9.2.2        ad 		di->type = AUDIO_MIXER_VALUE;
   1762  1.9.2.2        ad 		di->un.v.num_channels = 1;
   1763  1.9.2.2        ad 		strcpy(di->un.v.units.name, AudioNvolume);
   1764  1.9.2.2        ad 		return (0);
   1765  1.9.2.2        ad 	case DBRI_ENABLE_MONO:	/* built-in speaker */
   1766  1.9.2.2        ad 		di->mixer_class = DBRI_OUTPUT_CLASS;
   1767  1.9.2.2        ad 		di->next = di->prev = AUDIO_MIXER_LAST;
   1768      1.1  macallan 		strcpy(di->label.name, AudioNmono);
   1769      1.1  macallan 		di->type = AUDIO_MIXER_ENUM;
   1770      1.1  macallan 		di->un.e.num_mem = 2;
   1771      1.1  macallan 		strcpy(di->un.e.member[0].label.name, AudioNoff);
   1772      1.1  macallan 		di->un.e.member[0].ord = 0;
   1773      1.1  macallan 		strcpy(di->un.e.member[1].label.name, AudioNon);
   1774      1.1  macallan 		di->un.e.member[1].ord = 1;
   1775      1.1  macallan 		return (0);
   1776      1.1  macallan 	case DBRI_ENABLE_HEADPHONE:	/* headphones output */
   1777  1.9.2.2        ad 		di->mixer_class = DBRI_OUTPUT_CLASS;
   1778      1.1  macallan 		di->next = di->prev = AUDIO_MIXER_LAST;
   1779      1.1  macallan 		strcpy(di->label.name, AudioNheadphone);
   1780      1.1  macallan 		di->type = AUDIO_MIXER_ENUM;
   1781      1.1  macallan 		di->un.e.num_mem = 2;
   1782      1.1  macallan 		strcpy(di->un.e.member[0].label.name, AudioNoff);
   1783      1.1  macallan 		di->un.e.member[0].ord = 0;
   1784      1.1  macallan 		strcpy(di->un.e.member[1].label.name, AudioNon);
   1785      1.1  macallan 		di->un.e.member[1].ord = 1;
   1786      1.1  macallan 		return (0);
   1787      1.1  macallan 	case DBRI_ENABLE_LINE:	/* line out */
   1788  1.9.2.2        ad 		di->mixer_class = DBRI_OUTPUT_CLASS;
   1789      1.1  macallan 		di->next = di->prev = AUDIO_MIXER_LAST;
   1790      1.1  macallan 		strcpy(di->label.name, AudioNline);
   1791      1.1  macallan 		di->type = AUDIO_MIXER_ENUM;
   1792      1.1  macallan 		di->un.e.num_mem = 2;
   1793      1.1  macallan 		strcpy(di->un.e.member[0].label.name, AudioNoff);
   1794      1.1  macallan 		di->un.e.member[0].ord = 0;
   1795      1.1  macallan 		strcpy(di->un.e.member[1].label.name, AudioNon);
   1796      1.1  macallan 		di->un.e.member[1].ord = 1;
   1797      1.1  macallan 		return (0);
   1798  1.9.2.2        ad 	case DBRI_INPUT_SELECT:
   1799  1.9.2.2        ad 		di->mixer_class = DBRI_INPUT_CLASS;
   1800  1.9.2.2        ad 		strcpy(di->label.name, AudioNsource);
   1801  1.9.2.2        ad 		di->type = AUDIO_MIXER_SET;
   1802  1.9.2.2        ad 		di->prev = di->next = AUDIO_MIXER_LAST;
   1803  1.9.2.2        ad 		di->un.s.num_mem = 2;
   1804  1.9.2.2        ad 		strcpy(di->un.s.member[0].label.name, AudioNline);
   1805  1.9.2.2        ad 		di->un.s.member[0].mask = 1 << 0;
   1806  1.9.2.2        ad 		strcpy(di->un.s.member[1].label.name, AudioNmicrophone);
   1807  1.9.2.2        ad 		di->un.s.member[1].mask = 1 << 1;
   1808  1.9.2.2        ad 		return 0;
   1809      1.1  macallan 	}
   1810      1.5     blymn 
   1811      1.1  macallan 	return (ENXIO);
   1812      1.1  macallan }
   1813      1.1  macallan 
   1814  1.9.2.1        ad static size_t
   1815      1.1  macallan dbri_round_buffersize(void *hdl, int dir, size_t bufsize)
   1816      1.1  macallan {
   1817      1.1  macallan #ifdef DBRI_BIG_BUFFER
   1818      1.1  macallan 	return 16*0x1ffc;	/* use ~128KB buffer */
   1819      1.1  macallan #else
   1820      1.1  macallan 	return bufsize;
   1821      1.1  macallan #endif
   1822      1.1  macallan }
   1823      1.1  macallan 
   1824  1.9.2.1        ad static int
   1825      1.1  macallan dbri_get_props(void *hdl)
   1826      1.1  macallan {
   1827      1.1  macallan 
   1828  1.9.2.1        ad 	return AUDIO_PROP_MMAP;
   1829      1.1  macallan }
   1830      1.1  macallan 
   1831  1.9.2.1        ad static int
   1832      1.1  macallan dbri_trigger_output(void *hdl, void *start, void *end, int blksize,
   1833      1.1  macallan 		    void (*intr)(void *), void *intrarg,
   1834      1.1  macallan 		    const struct audio_params *param)
   1835      1.1  macallan {
   1836      1.1  macallan 	struct dbri_softc *sc = hdl;
   1837      1.1  macallan 	unsigned long count, current, num;
   1838      1.1  macallan 
   1839      1.8       mrg 	count = (unsigned long)(((char *)end - (char *)start));
   1840      1.1  macallan 	num = count / blksize;
   1841      1.5     blymn 
   1842  1.9.2.1        ad 	DPRINTF("trigger_output(%lx %lx) : %d %ld %ld\n",
   1843      1.1  macallan 	    (unsigned long)intr,
   1844  1.9.2.1        ad 	    (unsigned long)intrarg, blksize, count, num);
   1845      1.4  macallan 
   1846      1.1  macallan 	sc->sc_params = *param;
   1847      1.1  macallan 
   1848      1.1  macallan 	mmcodec_setcontrol(sc);
   1849      1.1  macallan 	mmcodec_init_data(sc);
   1850      1.1  macallan 	current = 0;
   1851      1.5     blymn 	while ((current < sc->sc_desc_used) &&
   1852      1.5     blymn 	    (sc->sc_desc[current].buf != start))
   1853      1.1  macallan 	    	current++;
   1854      1.5     blymn 
   1855      1.1  macallan 	if (current < sc->sc_desc_used) {
   1856      1.1  macallan 		setup_ring(sc, 4, current, num, blksize, intr, intrarg);
   1857  1.9.2.2        ad 		sc->sc_playing = 1;
   1858      1.1  macallan 		return 0;
   1859      1.1  macallan 	}
   1860      1.1  macallan 	return EINVAL;
   1861      1.1  macallan }
   1862      1.1  macallan 
   1863  1.9.2.2        ad static int
   1864  1.9.2.2        ad dbri_halt_input(void *cookie)
   1865  1.9.2.2        ad {
   1866  1.9.2.2        ad 	return 0;
   1867  1.9.2.2        ad }
   1868  1.9.2.2        ad 
   1869  1.9.2.2        ad static int
   1870  1.9.2.2        ad dbri_trigger_input(void *hdl, void *start, void *end, int blksize,
   1871  1.9.2.2        ad 		    void (*intr)(void *), void *intrarg,
   1872  1.9.2.2        ad 		    const struct audio_params *param)
   1873  1.9.2.2        ad {
   1874  1.9.2.2        ad #if notyet
   1875  1.9.2.2        ad 	struct dbri_softc *sc = hdl;
   1876  1.9.2.2        ad 	unsigned long count, current, num;
   1877  1.9.2.2        ad 
   1878  1.9.2.2        ad 	count = (unsigned long)(((char *)end - (char *)start));
   1879  1.9.2.2        ad 	num = count / blksize;
   1880  1.9.2.2        ad 
   1881  1.9.2.2        ad 	DPRINTF("trigger_input(%lx %lx) : %d %ld %ld\n",
   1882  1.9.2.2        ad 	    (unsigned long)intr,
   1883  1.9.2.2        ad 	    (unsigned long)intrarg, blksize, count, num);
   1884  1.9.2.2        ad 
   1885  1.9.2.2        ad 	sc->sc_params = *param;
   1886  1.9.2.2        ad 
   1887  1.9.2.2        ad 	mmcodec_setcontrol(sc);
   1888  1.9.2.2        ad 	mmcodec_init_data(sc);
   1889  1.9.2.2        ad 	current = 0;
   1890  1.9.2.2        ad 	while ((current < sc->sc_desc_used) &&
   1891  1.9.2.2        ad 	    (sc->sc_desc[current].buf != start))
   1892  1.9.2.2        ad 	    	current++;
   1893  1.9.2.2        ad 
   1894  1.9.2.2        ad 	if (current < sc->sc_desc_used) {
   1895  1.9.2.2        ad 		setup_ring(sc, 4, current, num, blksize, intr, intrarg);
   1896  1.9.2.2        ad 		return 0;
   1897  1.9.2.2        ad 	}
   1898  1.9.2.2        ad #endif
   1899  1.9.2.2        ad 	return EINVAL;
   1900  1.9.2.2        ad }
   1901  1.9.2.2        ad 
   1902  1.9.2.2        ad 
   1903  1.9.2.1        ad static u_int32_t
   1904      1.1  macallan reverse_bytes(u_int32_t b, int len)
   1905      1.1  macallan {
   1906      1.1  macallan 	switch (len) {
   1907      1.1  macallan 	case 32:
   1908      1.1  macallan 		b = ((b & 0xffff0000) >> 16) | ((b & 0x0000ffff) << 16);
   1909      1.1  macallan 	case 16:
   1910      1.1  macallan 		b = ((b & 0xff00ff00) >>  8) | ((b & 0x00ff00ff) <<  8);
   1911      1.1  macallan 	case 8:
   1912      1.1  macallan 		b = ((b & 0xf0f0f0f0) >>  4) | ((b & 0x0f0f0f0f) <<  4);
   1913      1.1  macallan 	case 4:
   1914      1.1  macallan 		b = ((b & 0xcccccccc) >>  2) | ((b & 0x33333333) <<  2);
   1915      1.1  macallan 	case 2:
   1916      1.1  macallan 		b = ((b & 0xaaaaaaaa) >>  1) | ((b & 0x55555555) <<  1);
   1917      1.1  macallan 	case 1:
   1918      1.1  macallan 	case 0:
   1919      1.1  macallan 		break;
   1920      1.1  macallan 	default:
   1921  1.9.2.1        ad 		DPRINTF("reverse_bytes: unsupported length\n");
   1922      1.1  macallan 	};
   1923      1.1  macallan 
   1924      1.1  macallan 	return (b);
   1925      1.1  macallan }
   1926      1.1  macallan 
   1927      1.1  macallan static void
   1928      1.1  macallan *dbri_malloc(void *v, int dir, size_t s, struct malloc_type *mt, int flags)
   1929      1.1  macallan {
   1930      1.1  macallan 	struct dbri_softc *sc = v;
   1931      1.1  macallan 	struct dbri_desc *dd = &sc->sc_desc[sc->sc_desc_used];
   1932      1.1  macallan 	int rseg;
   1933      1.5     blymn 
   1934      1.5     blymn 	if (bus_dmamap_create(sc->sc_dmat, s, 1, s, 0, BUS_DMA_NOWAIT,
   1935      1.1  macallan 	    &dd->dmamap) == 0) {
   1936      1.1  macallan 		if (bus_dmamem_alloc(sc->sc_dmat, s, 0, 0, &dd->dmaseg,
   1937      1.1  macallan 		    1, &rseg, BUS_DMA_NOWAIT) == 0) {
   1938      1.1  macallan 			if (bus_dmamem_map(sc->sc_dmat, &dd->dmaseg, rseg, s,
   1939      1.5     blymn 			    &dd->buf, BUS_DMA_NOWAIT|BUS_DMA_COHERENT) == 0) {
   1940      1.1  macallan 				if (dd->buf!=NULL) {
   1941      1.5     blymn 					if (bus_dmamap_load(sc->sc_dmat,
   1942      1.5     blymn 					    dd->dmamap, dd->buf, s, NULL,
   1943      1.1  macallan 					    BUS_DMA_NOWAIT) == 0) {
   1944      1.1  macallan 						dd->len = s;
   1945      1.1  macallan 						dd->busy = 0;
   1946      1.1  macallan 						dd->callback = NULL;
   1947      1.5     blymn 						dd->dmabase =
   1948      1.1  macallan 						 dd->dmamap->dm_segs[0].ds_addr;
   1949  1.9.2.1        ad 						DPRINTF("dbri_malloc: using buffer %d\n",
   1950  1.9.2.1        ad 						    sc->sc_desc_used);
   1951      1.1  macallan 						sc->sc_desc_used++;
   1952      1.1  macallan 						return dd->buf;
   1953      1.1  macallan 					} else
   1954  1.9.2.1        ad 						aprint_error("dbri_malloc: load failed\n");
   1955      1.1  macallan 				} else
   1956  1.9.2.1        ad 					aprint_error("dbri_malloc: map returned NULL\n");
   1957      1.1  macallan 			} else
   1958  1.9.2.1        ad 				aprint_error("dbri_malloc: map failed\n");
   1959      1.1  macallan 			bus_dmamem_free(sc->sc_dmat, &dd->dmaseg, rseg);
   1960      1.1  macallan 		} else
   1961  1.9.2.1        ad 			aprint_error("dbri_malloc: malloc() failed\n");
   1962      1.1  macallan 		bus_dmamap_destroy(sc->sc_dmat, dd->dmamap);
   1963      1.1  macallan 	} else
   1964  1.9.2.1        ad 		aprint_error("dbri_malloc: bus_dmamap_create() failed\n");
   1965      1.1  macallan 	return NULL;
   1966      1.1  macallan }
   1967      1.1  macallan 
   1968      1.1  macallan static void
   1969      1.1  macallan dbri_free(void *v, void *p, struct malloc_type *mt)
   1970      1.1  macallan {
   1971      1.1  macallan 	free(p, mt);
   1972      1.1  macallan }
   1973      1.1  macallan 
   1974      1.1  macallan static paddr_t
   1975      1.1  macallan dbri_mappage(void *v, void *mem, off_t off, int prot)
   1976      1.1  macallan {
   1977      1.1  macallan 	struct dbri_softc *sc = v;;
   1978      1.1  macallan 	int current;
   1979      1.5     blymn 
   1980      1.1  macallan 	if (off < 0)
   1981      1.1  macallan 		return -1;
   1982      1.5     blymn 
   1983      1.1  macallan 	current = 0;
   1984      1.5     blymn 	while ((current < sc->sc_desc_used) &&
   1985      1.5     blymn 	    (sc->sc_desc[current].buf != mem))
   1986      1.1  macallan 	    	current++;
   1987      1.5     blymn 
   1988      1.1  macallan 	if (current < sc->sc_desc_used) {
   1989      1.5     blymn 		return bus_dmamem_mmap(sc->sc_dmat,
   1990      1.1  macallan 		    &sc->sc_desc[current].dmaseg, 1, off, prot, BUS_DMA_WAITOK);
   1991      1.1  macallan 	}
   1992      1.5     blymn 
   1993      1.1  macallan 	return -1;
   1994      1.1  macallan }
   1995      1.1  macallan 
   1996      1.4  macallan static int
   1997      1.4  macallan dbri_open(void *cookie, int flags)
   1998      1.4  macallan {
   1999      1.4  macallan 	struct dbri_softc *sc = cookie;
   2000      1.5     blymn 
   2001      1.4  macallan 	dbri_bring_up(sc);
   2002  1.9.2.2        ad 	sc->sc_open = 1;
   2003      1.4  macallan 	return 0;
   2004      1.4  macallan }
   2005      1.4  macallan 
   2006      1.4  macallan static void
   2007      1.4  macallan dbri_close(void *cookie)
   2008      1.4  macallan {
   2009      1.4  macallan 	struct dbri_softc *sc = cookie;
   2010      1.5     blymn 
   2011  1.9.2.2        ad 	sc->sc_open = 0;
   2012      1.4  macallan 	dbri_set_power(sc, 0);
   2013      1.4  macallan }
   2014      1.4  macallan 
   2015      1.4  macallan static void
   2016      1.4  macallan dbri_powerhook(int why, void *cookie)
   2017      1.4  macallan {
   2018      1.4  macallan 	struct dbri_softc *sc = cookie;
   2019      1.5     blymn 
   2020  1.9.2.2        ad 	if (why == sc->sc_pmgrstate)
   2021  1.9.2.2        ad 		return;
   2022  1.9.2.2        ad 
   2023      1.4  macallan 	switch(why)
   2024      1.4  macallan 	{
   2025      1.4  macallan 		case PWR_SUSPEND:
   2026      1.4  macallan 			dbri_set_power(sc, 0);
   2027      1.4  macallan 			break;
   2028      1.4  macallan 		case PWR_RESUME:
   2029  1.9.2.2        ad 			DPRINTF("resume: %d\n", sc->sc_open);
   2030  1.9.2.2        ad 			sc->sc_pmgrstate = PWR_RESUME;
   2031  1.9.2.2        ad 			if (sc->sc_open == 1) {
   2032  1.9.2.2        ad 				dbri_bring_up(sc);
   2033  1.9.2.2        ad 				if (sc->sc_playing) {
   2034  1.9.2.2        ad 					volatile u_int32_t *cmd;
   2035  1.9.2.2        ad 					int s;
   2036  1.9.2.2        ad 
   2037  1.9.2.2        ad 					s = splaudio();
   2038  1.9.2.2        ad 					cmd = dbri_command_lock(sc);
   2039  1.9.2.2        ad 					*(cmd++) = DBRI_CMD(DBRI_COMMAND_SDP,
   2040  1.9.2.2        ad 					    0, sc->sc_pipe[4].sdp |
   2041  1.9.2.2        ad 					    DBRI_SDP_VALID_POINTER |
   2042  1.9.2.2        ad 					    DBRI_SDP_EVERY | DBRI_SDP_CLEAR);
   2043  1.9.2.2        ad 					*(cmd++) = sc->sc_dmabase +
   2044  1.9.2.2        ad 					    dbri_dma_off(desc, 0);
   2045  1.9.2.2        ad 					dbri_command_send(sc, cmd);
   2046  1.9.2.2        ad 					splx(s);
   2047  1.9.2.2        ad 				}
   2048  1.9.2.2        ad 			}
   2049      1.4  macallan 			break;
   2050  1.9.2.2        ad 		default:
   2051  1.9.2.2        ad 			return;
   2052      1.4  macallan 	}
   2053  1.9.2.2        ad 	sc->sc_pmgrstate = why;
   2054      1.4  macallan }
   2055      1.5     blymn 
   2056      1.4  macallan #endif /* NAUDIO > 0 */
   2057