dbri.c revision 1.1
1 /* $NetBSD: dbri.c,v 1.1 2005/07/16 18:58:50 macallan Exp $ */ 2 3 /* 4 * Copyright (c) 2001, 2002 Jared D. McNeill <jmcneill (at) invisible.yi.org> 5 * Copyright (c) 2005 Michael Lorenz <macallan (at) netbsd.org> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Jared D. McNeill. 19 * 4. Neither the name of the author nor the names of any contributors may 20 * be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 */ 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: dbri.c,v 1.1 2005/07/16 18:58:50 macallan Exp $"); 39 40 #include "audio.h" 41 #if NAUDIO > 0 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/errno.h> 46 #include <sys/device.h> 47 #include <sys/malloc.h> 48 #include <sys/proc.h> 49 50 #include <machine/bus.h> 51 #include <machine/intr.h> 52 53 #include <dev/sbus/sbusvar.h> 54 #include <sparc/sparc/auxreg.h> 55 #include <machine/autoconf.h> 56 57 #include <sys/audioio.h> 58 #include <dev/audio_if.h> 59 #include <dev/auconv.h> 60 61 #include <dev/ic/cs4215reg.h> 62 #include <dev/ic/cs4215var.h> 63 #include <dev/sbus/dbrireg.h> 64 #include <dev/sbus/dbrivar.h> 65 66 #define DBRI_ROM_NAME_PREFIX "SUNW,DBRI" 67 68 #define DBRI_BIG_BUFFER 69 70 static const char *dbri_supported[] = { 71 "e", 72 "s3", 73 "" 74 }; 75 76 enum ms { 77 CHImaster, 78 CHIslave 79 }; 80 81 enum io { 82 PIPEinput, 83 PIPEoutput 84 }; 85 86 /* 87 * Function prototypes 88 */ 89 90 /* softc stuff */ 91 static void dbri_attach_sbus(struct device *, struct device *, void *); 92 static int dbri_match_sbus(struct device *, struct cfdata *, void *); 93 94 static void dbri_config_interrupts(struct device *); 95 96 /* interrupt handler */ 97 static int dbri_intr(void *); 98 99 /* supporting subroutines */ 100 static int dbri_init(struct dbri_softc *); 101 static int dbri_reset(struct dbri_softc *); 102 static volatile u_int32_t *dbri_command_lock(struct dbri_softc *); 103 static void dbri_command_send(struct dbri_softc *, volatile u_int32_t *); 104 static void dbri_process_interrupt_buffer(struct dbri_softc *); 105 static void dbri_process_interrupt(struct dbri_softc *, int32_t); 106 107 /* mmcodec subroutines */ 108 static int mmcodec_init(struct dbri_softc *); 109 static void mmcodec_init_data(struct dbri_softc *); 110 static void mmcodec_pipe_init(struct dbri_softc *); 111 static void mmcodec_default(struct dbri_softc *); 112 static void mmcodec_setgain(struct dbri_softc *, int); 113 static int mmcodec_setcontrol(struct dbri_softc *); 114 115 /* chi subroutines */ 116 static void chi_reset(struct dbri_softc *, enum ms, int); 117 118 /* pipe subroutines */ 119 static void pipe_setup(struct dbri_softc *, int, int); 120 static void pipe_reset(struct dbri_softc *, int); 121 static void pipe_receive_fixed(struct dbri_softc *, int, 122 volatile u_int32_t *); 123 static void pipe_transmit_fixed(struct dbri_softc *, int, u_int32_t); 124 125 static void pipe_ts_link(struct dbri_softc *, int, enum io, int, int, int); 126 static int pipe_active(struct dbri_softc *, int); 127 128 /* audio(9) stuff */ 129 static int dbri_query_encoding(void *, struct audio_encoding *); 130 static int dbri_set_params(void *, int, int, struct audio_params *, 131 struct audio_params *,stream_filter_list_t *, stream_filter_list_t *); 132 static int dbri_round_blocksize(void *, int, int, const audio_params_t *); 133 static int dbri_halt_output(void *); 134 static int dbri_getdev(void *, struct audio_device *); 135 static int dbri_set_port(void *, mixer_ctrl_t *); 136 static int dbri_get_port(void *, mixer_ctrl_t *); 137 static int dbri_query_devinfo(void *, mixer_devinfo_t *); 138 static size_t dbri_round_buffersize(void *, int, size_t); 139 static int dbri_get_props(void *); 140 141 static void 142 setup_ring(struct dbri_softc *, int, int, int, int, void (*)(void *), void *); 143 144 static int dbri_trigger_output(void *, void *, void *, int, 145 void (*)(void *), void *, const struct audio_params *); 146 147 static void *dbri_malloc(void *, int, size_t, struct malloc_type *, int); 148 static void dbri_free(void *, void *, struct malloc_type *); 149 static paddr_t dbri_mappage(void *, void *, off_t, int); 150 151 /* stupid support routines */ 152 static u_int32_t reverse_bytes(u_int32_t, int); 153 154 struct audio_device dbri_device = { 155 "CS4215", 156 "", 157 "dbri" 158 }; 159 160 struct audio_hw_if dbri_hw_if = { 161 NULL, /*dbri_open,*/ 162 NULL, /*dbri_close,*/ 163 NULL, /* drain */ 164 dbri_query_encoding, 165 dbri_set_params, 166 dbri_round_blocksize, 167 NULL, /* commit_settings */ 168 NULL, /* init_output */ 169 NULL, /* init_input */ 170 NULL, /* start_output */ 171 NULL, /* start_input */ 172 dbri_halt_output, 173 NULL, /* halt_input */ 174 NULL, /* speaker_ctl */ 175 dbri_getdev, 176 NULL, /* setfd */ 177 dbri_set_port, 178 dbri_get_port, 179 dbri_query_devinfo, 180 dbri_malloc, 181 dbri_free, 182 dbri_round_buffersize, 183 dbri_mappage, 184 dbri_get_props, 185 dbri_trigger_output, 186 NULL /* trigger_input */ 187 }; 188 189 CFATTACH_DECL(dbri, sizeof(struct dbri_softc), 190 dbri_match_sbus, dbri_attach_sbus, NULL, NULL); 191 192 enum { 193 DBRI_MONITOR_CLASS, 194 DBRI_VOL_OUTPUT, 195 DBRI_ENABLE_MONO, 196 DBRI_ENABLE_HEADPHONE, 197 DBRI_ENABLE_LINE 198 /* 199 DBRI_INPUT_CLASS, 200 DBRI_RECORD_CLASS, 201 DBRI_INPUT_GAIN, 202 DBRI_INPUT_SELECT, 203 DBRI_ENUM_LAST 204 */ 205 }; 206 207 /* 208 * Autoconfig routines 209 */ 210 int 211 dbri_match_sbus(struct device *parent, struct cfdata *match, void *aux) 212 { 213 struct sbus_attach_args *sa = aux; 214 char *ver; 215 int i; 216 217 if (strncmp(DBRI_ROM_NAME_PREFIX, sa->sa_name, 9)) 218 return (0); 219 220 ver = &sa->sa_name[9]; 221 222 for (i = 0; dbri_supported[i][0] != '\0'; i++) 223 if (strcmp(dbri_supported[i], ver) == 0) 224 return (1); 225 226 return (0); 227 } 228 229 void 230 dbri_attach_sbus(struct device *parent, struct device *self, void *aux) 231 { 232 struct dbri_softc *sc = (struct dbri_softc *)self; 233 struct sbus_attach_args *sa = aux; 234 bus_space_handle_t ioh; 235 bus_size_t size; 236 int error, rseg, pwr; 237 char *ver = &sa->sa_name[9]; 238 239 sc->sc_iot = sa->sa_bustag; 240 sc->sc_dmat = sa->sa_dmatag; 241 242 pwr=prom_getpropint(sa->sa_node,"pwr-on-auxio",0); 243 if(pwr) { 244 /* we need to power up the device first */ 245 uint8_t auxregval = 0; 246 printf("\n%s: waiting to power up... ",self->dv_xname); 247 auxregval = *AUXIO4M_REG; 248 *AUXIO4M_REG = auxregval | (AUXIO4M_LED|4); 249 DELAY(1000); 250 printf("done\n"); /* more delay... */ 251 } else 252 printf(": rev %s\n", ver); 253 254 if (sa->sa_npromvaddrs) 255 ioh = (bus_space_handle_t)sa->sa_promvaddrs[0]; 256 else { 257 if (sbus_bus_map(sa->sa_bustag, sa->sa_slot, 258 sa->sa_offset, sa->sa_size, 259 BUS_SPACE_MAP_LINEAR, /*0,*/ &ioh) != 0) { 260 printf("%s @ sbus: cannot map registers\n", 261 self->dv_xname); 262 return; 263 } 264 } 265 266 sc->sc_ioh = ioh; 267 268 size = sizeof(struct dbri_dma); 269 270 /* get a DMA handle */ 271 if ((error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, 272 BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) { 273 printf("%s: DMA map create error %d\n", self->dv_xname, error); 274 return; 275 } 276 277 /* allocate DMA buffer */ 278 if ((error = bus_dmamem_alloc(sc->sc_dmat, size, 0, 0, &sc->sc_dmaseg, 279 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 280 printf("%s: DMA buffer alloc error %d\n", 281 self->dv_xname, error); 282 return; 283 } 284 285 /* map DMA buffer into CPU addressable space */ 286 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_dmaseg, rseg, size, 287 &sc->sc_membase, 288 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 289 printf("%s: DMA buffer map error %d\n", 290 self->dv_xname, error); 291 return; 292 } 293 294 /* load the buffer */ 295 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, 296 sc->sc_membase, size, NULL, 297 BUS_DMA_NOWAIT)) != 0) { 298 printf("%s: DMA buffer map load error %d\n", 299 self->dv_xname, error); 300 bus_dmamem_unmap(sc->sc_dmat, sc->sc_membase, size); 301 bus_dmamem_free(sc->sc_dmat, &sc->sc_dmaseg, rseg); 302 return; 303 } 304 305 /* map the registers into memory */ 306 307 sc->sc_dma = (struct dbri_dma *)sc->sc_membase; /* kernel virtual address of DMA buffer */ 308 sc->sc_dmabase = sc->sc_dmamap->dm_segs[0].ds_addr; /* physical address of DMA buffer */ 309 sc->sc_bufsiz = size; 310 311 sbus_establish(&sc->sc_sd, &sc->sc_dev); 312 313 bus_intr_establish(sa->sa_bustag, sa->sa_pri, IPL_AUDIO, /*0,*/ 314 dbri_intr, sc); 315 316 sc->sc_locked = 0; 317 sc->sc_desc_used = 0; 318 319 config_interrupts(self, &dbri_config_interrupts); 320 321 return; 322 } 323 324 void 325 dbri_config_interrupts(struct device *dev) 326 { 327 struct dbri_softc *sc = (struct dbri_softc *)dev; 328 dbri_init(sc); 329 mmcodec_init(sc); 330 /* Attach ourselves to the high level audio interface */ 331 audio_attach_mi(&dbri_hw_if, sc, &sc->sc_dev); 332 333 return; 334 } 335 336 int 337 dbri_intr(void *hdl) 338 { 339 struct dbri_softc *sc = hdl; 340 bus_space_tag_t iot = sc->sc_iot; 341 bus_space_handle_t ioh = sc->sc_ioh; 342 int x; 343 344 /* clear interrupt */ 345 x = bus_space_read_4(iot, ioh, DBRI_REG1); 346 if (x & (DBRI_MRR | DBRI_MLE | DBRI_LBG | DBRI_MBE)) { 347 u_int32_t tmp; 348 349 if (x & DBRI_MRR) 350 printf("%s: multiple ack error on sbus\n", 351 sc->sc_dev.dv_xname); 352 if (x & DBRI_MLE) 353 printf("%s: multiple late error on sbus\n", 354 sc->sc_dev.dv_xname); 355 if (x & DBRI_LBG) 356 printf("%s: lost bus grant on sbus\n", 357 sc->sc_dev.dv_xname); 358 if (x & DBRI_MBE) 359 printf("%s: burst error on sbus\n", 360 sc->sc_dev.dv_xname); 361 362 /* 363 * Some of these errors disable the chip's circuitry. 364 * Re-enable the circuitry and keep on going. 365 */ 366 367 tmp = bus_space_read_4(iot, ioh, DBRI_REG0); 368 tmp &= ~(DBRI_DISABLE_MASTER); 369 bus_space_write_4(iot, ioh, DBRI_REG0, tmp); 370 } 371 372 #if 0 373 if (!x & 1) /* XXX: DBRI_INTR_REQ */ 374 return (1); 375 #endif 376 377 dbri_process_interrupt_buffer(sc); 378 379 return (1); 380 } 381 382 int 383 dbri_init(struct dbri_softc *sc) 384 { 385 bus_space_tag_t iot = sc->sc_iot; 386 bus_space_handle_t ioh = sc->sc_ioh; 387 u_int32_t reg; 388 volatile u_int32_t *cmd; 389 bus_addr_t dmaaddr; 390 int n; 391 392 dbri_reset(sc); 393 394 cmd = dbri_command_lock(sc); 395 396 /* XXX: Initialize interrupt ring buffer */ 397 sc->sc_dma->intr[0] = (u_int32_t)sc->sc_dmabase + dbri_dma_off(intr, 0); 398 sc->sc_irqp = 1; 399 400 /* Initialize pipes */ 401 for (n = 0; n < DBRI_PIPE_MAX; n++) 402 sc->sc_pipe[n].desc = sc->sc_pipe[n].next = -1; 403 404 for(n=1;n<DBRI_INT_BLOCKS;n++) { 405 sc->sc_dma->intr[n]=0; 406 } 407 408 /* Disable all SBus bursts */ 409 /* XXX 16 byte bursts cause errors, the rest works */ 410 reg = bus_space_read_4(iot, ioh, DBRI_REG0); 411 /*reg &= ~(DBRI_BURST_4 | DBRI_BURST_8 | DBRI_BURST_16);*/ 412 reg |= (DBRI_BURST_4 | DBRI_BURST_8); 413 bus_space_write_4(iot, ioh, DBRI_REG0, reg); 414 415 /* setup interrupt queue */ 416 dmaaddr = (u_int32_t)sc->sc_dmabase + dbri_dma_off(intr, 0); 417 *(cmd++) = DBRI_CMD(DBRI_COMMAND_IIQ, 0, 0); 418 *(cmd++) = dmaaddr; 419 420 dbri_command_send(sc, cmd); 421 return (0); 422 } 423 424 int 425 dbri_reset(struct dbri_softc *sc) 426 { 427 int bail=0; 428 bus_space_tag_t iot = sc->sc_iot; 429 bus_space_handle_t ioh = sc->sc_ioh; 430 431 bus_space_write_4(iot, ioh, DBRI_REG0, DBRI_SOFT_RESET); 432 while ((bus_space_read_4(iot, ioh, DBRI_REG0) & DBRI_SOFT_RESET) && 433 (bail < 100000)) { 434 bail++; 435 delay(10); 436 } 437 if (bail == 100000) printf("%s: reset timed out\n",sc->sc_dev.dv_xname); 438 return (0); 439 } 440 441 volatile u_int32_t * 442 dbri_command_lock(struct dbri_softc *sc) 443 { 444 445 if (sc->sc_locked) 446 printf("%s: command buffer locked\n", sc->sc_dev.dv_xname); 447 448 sc->sc_locked++; 449 450 return (&sc->sc_dma->command[0]); 451 } 452 453 void 454 dbri_command_send(struct dbri_softc *sc, volatile u_int32_t *cmd) 455 { 456 bus_space_handle_t ioh = sc->sc_ioh; 457 bus_space_tag_t iot = sc->sc_iot; 458 int maxloops = 1000000; 459 int x; 460 461 x = splaudio(); 462 //x = splhigh(); 463 464 sc->sc_locked--; 465 466 if (sc->sc_locked != 0) { 467 printf("%s: command buffer improperly locked\n", 468 sc->sc_dev.dv_xname); 469 } else if ((cmd - &sc->sc_dma->command[0]) >= DBRI_NUM_COMMANDS - 1) { 470 printf("%s: command buffer overflow\n", sc->sc_dev.dv_xname); 471 } else { 472 *(cmd++) = DBRI_CMD(DBRI_COMMAND_PAUSE, 0, 0); 473 *(cmd++) = DBRI_CMD(DBRI_COMMAND_WAIT, 1, 0); 474 sc->sc_waitseen = 0; 475 bus_space_write_4(iot, ioh, DBRI_REG8, sc->sc_dmabase); 476 while ((--maxloops) > 0 && 477 (bus_space_read_4(iot, ioh, DBRI_REG0) 478 & DBRI_COMMAND_VALID)) { 479 bus_space_barrier(iot, ioh, DBRI_REG0, 4, 480 BUS_SPACE_BARRIER_READ); 481 delay(1000); 482 } 483 484 if (maxloops == 0) { 485 printf("%s: chip never completed command buffer\n", 486 sc->sc_dev.dv_xname); 487 } else { 488 #ifdef DBRI_DEBUG 489 printf("%s: command completed\n",sc->sc_dev.dv_xname); 490 #endif 491 while ((--maxloops) > 0 && (!sc->sc_waitseen)) 492 dbri_process_interrupt_buffer(sc); 493 if (maxloops == 0) { 494 printf("%s: chip never acked WAIT\n", 495 sc->sc_dev.dv_xname); 496 } 497 } 498 } 499 500 splx(x); 501 502 return; 503 } 504 505 void 506 dbri_process_interrupt_buffer(struct dbri_softc *sc) 507 { 508 int32_t i; 509 510 while ((i = sc->sc_dma->intr[sc->sc_irqp]) != 0) { 511 sc->sc_dma->intr[sc->sc_irqp] = 0; 512 sc->sc_irqp++; 513 514 if (sc->sc_irqp == DBRI_INT_BLOCKS) 515 sc->sc_irqp = 1; 516 else if ((sc->sc_irqp & (DBRI_INT_BLOCKS - 1)) == 0) 517 sc->sc_irqp++; 518 519 dbri_process_interrupt(sc, i); 520 } 521 522 return; 523 } 524 525 void 526 dbri_process_interrupt(struct dbri_softc *sc, int32_t i) 527 { 528 #if 0 529 const int liu_states[] = { 1, 0, 8, 3, 4, 5, 6, 7 }; 530 #endif 531 int val = DBRI_INTR_GETVAL(i); 532 int channel = DBRI_INTR_GETCHAN(i); 533 int command = DBRI_INTR_GETCMD(i); 534 int code = DBRI_INTR_GETCODE(i); 535 #if 0 536 int rval = DBRI_INTR_GETRVAL(i); 537 #endif 538 if (channel == DBRI_INTR_CMD && command == DBRI_COMMAND_WAIT) 539 sc->sc_waitseen++; 540 541 switch (code) { 542 case DBRI_INTR_XCMP: /* transmission complete */ 543 { 544 int td; 545 struct dbri_desc *dd; 546 547 td = sc->sc_pipe[channel].desc; 548 dd = &sc->sc_desc[td]; 549 550 if (dd->callback != NULL) 551 dd->callback(dd->callback_args); 552 break; 553 } 554 case DBRI_INTR_FXDT: /* fixed data change */ 555 #ifdef DBRI_DEBUG 556 printf("dbri_intr: Fixed data change (%d: %x)\n",channel,val); 557 #endif 558 if (sc->sc_pipe[channel].sdp & DBRI_SDP_MSB) 559 val = reverse_bytes(val, sc->sc_pipe[channel].length); 560 if (sc->sc_pipe[channel].prec) 561 *(sc->sc_pipe[channel].prec) = val; 562 #ifdef DBRI_DEBUG 563 printf("%s: wakeup %p\n", sc->sc_dev.dv_xname, sc); 564 #endif 565 #if 0 566 wakeup(sc); 567 #endif 568 break; 569 case DBRI_INTR_SBRI: 570 #ifdef DBRI_DEBUG 571 printf("dbri_intr: SBRI\n"); 572 #endif 573 break; 574 case DBRI_INTR_BRDY: 575 { 576 /* XXX no input (yet) */ 577 #if 0 578 int rd = sc->sc_pipe[channel].desc; 579 u_int32_t status; 580 581 printf("dbri_intr: BRDY\n"); 582 if (rd < 0 || rd >= DBRI_NUM_DESCRIPTORS) { 583 printf("%s: invalid rd on pipe\n", sc->sc_dev.dv_xname); 584 break; 585 } 586 587 sc->sc_desc[rd].busy = 0; 588 sc->sc_pipe[channel].desc = sc->sc_desc[rd].next; 589 status = sc->sc_dma->desc[rd].word1; 590 #endif 591 /* XXX: callback ??? */ 592 593 break; 594 } 595 case DBRI_INTR_UNDR: 596 { 597 volatile u_int32_t *cmd; 598 int td = sc->sc_pipe[channel].desc; 599 600 printf("%s: DBRI_INTR_UNDR\n", sc->sc_dev.dv_xname); 601 602 sc->sc_dma->desc[td].status = 0; 603 604 cmd = dbri_command_lock(sc); 605 *(cmd++) = DBRI_CMD(DBRI_COMMAND_SDP, 0, 606 sc->sc_pipe[channel].sdp | 607 DBRI_SDP_VALID_POINTER | 608 DBRI_SDP_CLEAR | 609 DBRI_SDP_2SAME); 610 *(cmd++) = sc->sc_dmabase + dbri_dma_off(desc, td); 611 dbri_command_send(sc, cmd); 612 break; 613 } 614 default: 615 #if 0 616 printf("%s: unknown interrupt code %d\n", 617 sc->sc_dev.dv_xname, code); 618 #endif 619 break; 620 } 621 622 return; 623 } 624 625 /* 626 * mmcodec stuff 627 */ 628 629 int 630 mmcodec_init(struct dbri_softc *sc) 631 { 632 bus_space_handle_t ioh = sc->sc_ioh; 633 bus_space_tag_t iot = sc->sc_iot; 634 u_int32_t reg2; 635 636 reg2 = bus_space_read_4(iot, ioh, DBRI_REG2); 637 #ifdef DBRI_DEBUG 638 printf("mmcodec_init: PIO reads %x\n",reg2); 639 #endif 640 if (reg2 & DBRI_PIO2) { 641 printf("%s: onboard CS4215 detected\n", 642 sc->sc_dev.dv_xname); 643 sc->sc_mm.onboard = 1; 644 } 645 646 if (reg2 & DBRI_PIO0) { 647 printf("%s: speakerbox detected\n", 648 sc->sc_dev.dv_xname); 649 sc->sc_mm.onboard = 0; 650 } 651 652 if ((reg2 & DBRI_PIO2) && (reg2 & DBRI_PIO0)) { 653 printf("%s: using speakerbox\n", 654 sc->sc_dev.dv_xname); 655 bus_space_write_4(iot, ioh, DBRI_REG2, DBRI_PIO2_ENABLE); 656 sc->sc_mm.onboard = 0; 657 } 658 659 if (!(reg2 & (DBRI_PIO0|DBRI_PIO2))) { 660 printf("%s: no mmcodec found\n", sc->sc_dev.dv_xname); 661 return -1; 662 } 663 664 sc->sc_version = 0xff; 665 666 mmcodec_pipe_init(sc); 667 mmcodec_default(sc); 668 669 sc->sc_mm.offset = sc->sc_mm.onboard ? 0 : 8; 670 671 if (mmcodec_setcontrol(sc) == -1 || sc->sc_version == 0xff) { 672 printf("%s: cs4215 probe failed at offset %d\n", 673 sc->sc_dev.dv_xname, sc->sc_mm.offset); 674 return (-1); 675 } 676 677 printf("%s: cs4215 ver %d found at offset %d\n", 678 sc->sc_dev.dv_xname, sc->sc_version & 0xf, sc->sc_mm.offset); 679 680 /* set some sane defaults for mmcodec_init_data */ 681 sc->sc_params.channels = 2; 682 sc->sc_params.precision = 16; 683 684 mmcodec_init_data(sc); 685 686 sc->sc_open = 0; 687 688 return (0); 689 } 690 691 void 692 mmcodec_init_data(struct dbri_softc *sc) 693 { 694 bus_space_tag_t iot = sc->sc_iot; 695 bus_space_handle_t ioh = sc->sc_ioh; 696 u_int32_t tmp; 697 int data_width; 698 699 tmp = bus_space_read_4(iot, ioh, DBRI_REG0); 700 tmp &= ~(DBRI_CHI_ACTIVATE); /* disable CHI */ 701 bus_space_write_4(iot, ioh, DBRI_REG0, tmp); 702 703 /* switch CS4215 to data mode - set PIO3 to 1 */ 704 tmp = DBRI_PIO_ENABLE_ALL | DBRI_PIO1 | DBRI_PIO3; 705 /* XXX */ 706 tmp |= (sc->sc_mm.onboard ? DBRI_PIO0 : DBRI_PIO2); 707 708 bus_space_write_4(iot, ioh, DBRI_REG2, tmp); 709 chi_reset(sc, CHIslave, 128); 710 711 data_width = sc->sc_params.channels 712 * sc->sc_params.precision; 713 pipe_ts_link(sc, 20, PIPEoutput, 16, 32, sc->sc_mm.offset + 32); 714 pipe_ts_link(sc, 4, PIPEoutput, 16, data_width, sc->sc_mm.offset); 715 pipe_ts_link(sc, 6, PIPEinput, 16, data_width, sc->sc_mm.offset); 716 pipe_ts_link(sc, 21, PIPEinput, 16, 16, sc->sc_mm.offset + 40); 717 718 mmcodec_setgain(sc, 0); 719 720 tmp = bus_space_read_4(iot, ioh, DBRI_REG0); 721 tmp |= DBRI_CHI_ACTIVATE; 722 bus_space_write_4(iot, ioh, DBRI_REG0, tmp); 723 724 return; 725 } 726 727 void 728 mmcodec_pipe_init(struct dbri_softc *sc) 729 { 730 731 pipe_setup(sc, 4, DBRI_SDP_MEM | DBRI_SDP_TO_SER | DBRI_SDP_MSB); 732 pipe_setup(sc, 20, DBRI_SDP_FIXED | DBRI_SDP_TO_SER | DBRI_SDP_MSB); 733 pipe_setup(sc, 6, DBRI_SDP_MEM | DBRI_SDP_FROM_SER | DBRI_SDP_MSB); 734 pipe_setup(sc, 21, DBRI_SDP_FIXED | DBRI_SDP_FROM_SER | DBRI_SDP_MSB); 735 736 pipe_setup(sc, 17, DBRI_SDP_FIXED | DBRI_SDP_TO_SER | DBRI_SDP_MSB); 737 pipe_setup(sc, 18, DBRI_SDP_FIXED | DBRI_SDP_FROM_SER | DBRI_SDP_MSB); 738 pipe_setup(sc, 19, DBRI_SDP_FIXED | DBRI_SDP_FROM_SER | DBRI_SDP_MSB); 739 740 sc->sc_mm.status = 0; 741 742 pipe_receive_fixed(sc, 18, &sc->sc_mm.status); 743 pipe_receive_fixed(sc, 19, &sc->sc_mm.version); 744 745 return; 746 } 747 748 void 749 mmcodec_default(struct dbri_softc *sc) 750 { 751 struct cs4215_state *mm = &sc->sc_mm; 752 753 /* 754 * no action, memory resetting only 755 * 756 * data time slots 5-8 757 * speaker, line and headphone enable. set gain to half. 758 * input is mic 759 */ 760 mm->data[0] = sc->sc_latt = 0x20 | CS4215_HE | CS4215_LE; 761 mm->data[1] = sc->sc_ratt = 0x20 | CS4215_SE; 762 mm->data[2] = CS4215_LG(0x08) | CS4215_IS | CS4215_PIO0 | CS4215_PIO1; 763 mm->data[3] = CS4215_RG(0x08) | CS4215_MA(0x0f); 764 765 /* 766 * control time slots 1-4 767 * 768 * 0: default I/O voltage scale 769 * 1: 8 bit ulaw, 8kHz, mono, high pass filter disabled 770 * 2: serial enable, CHI master, 128 bits per frame, clock 1 771 * 3: tests disabled 772 */ 773 mm->control[0] = CS4215_RSRVD_1 | CS4215_MLB; 774 mm->control[1] = CS4215_DFR_ULAW | CS4215_FREQ[0].csval; 775 mm->control[2] = CS4215_XCLK | CS4215_BSEL_128 | CS4215_FREQ[0].xtal; 776 mm->control[3] = 0; 777 778 return; 779 } 780 781 void 782 mmcodec_setgain(struct dbri_softc *sc, int mute) 783 { 784 if (mute) { 785 /* disable all outputs, max. attenuation */ 786 sc->sc_mm.data[0] = 63; 787 sc->sc_mm.data[1] = 63; 788 } else { 789 /* 790 * We should be setting the proper output here.. for now, 791 * use the speaker. Possible outputs: 792 * Headphones: 793 * data[0] |= CS4215_HE; 794 * Line out: 795 * data[0] |= CS4215_LE; 796 * Speaker: 797 * data[1] |= CS4215_SE; 798 */ 799 sc->sc_mm.data[0] = sc->sc_latt; 800 sc->sc_mm.data[1] = sc->sc_ratt; 801 } 802 803 pipe_transmit_fixed(sc, 20, *(u_int32_t *)__UNVOLATILE(sc->sc_mm.data)); 804 805 /* give the chip some time to execure the command */ 806 delay(250); 807 808 return; 809 } 810 811 int 812 mmcodec_setcontrol(struct dbri_softc *sc) 813 { 814 bus_space_tag_t iot = sc->sc_iot; 815 bus_space_handle_t ioh = sc->sc_ioh; 816 u_int32_t val; 817 u_int32_t tmp; 818 #if 1 819 int i; 820 #endif 821 822 /* 823 * Temporarily mute outputs and wait 125 us to make sure that it 824 * happens. This avoids clicking noises. 825 */ 826 mmcodec_setgain(sc, 1); 827 //DELAY(125); 828 829 /* enable control mode */ 830 val = DBRI_PIO_ENABLE_ALL | DBRI_PIO1; /* was PIO1 */ 831 832 /* XXX */ 833 val |= (sc->sc_mm.onboard ? DBRI_PIO0 : DBRI_PIO2); 834 835 bus_space_write_4(iot, ioh, DBRI_REG2, val); 836 837 DELAY(34); 838 839 /* 840 * in control mode, the cs4215 is the slave device, so the 841 * DBRI must act as the CHI master. 842 * 843 * in data mode, the cs4215 must be the CHI master to insure 844 * that the data stream is in sync with its codec 845 */ 846 tmp = bus_space_read_4(iot, ioh, DBRI_REG0); 847 tmp &= ~DBRI_COMMAND_CHI; 848 bus_space_write_4(iot, ioh, DBRI_REG0, tmp); 849 850 chi_reset(sc, CHImaster, 128); 851 852 /* control mode */ 853 pipe_ts_link(sc, 17, PIPEoutput, 16, 32, sc->sc_mm.offset); 854 pipe_ts_link(sc, 18, PIPEinput, 16, 8, sc->sc_mm.offset); 855 pipe_ts_link(sc, 19, PIPEinput, 16, 8, sc->sc_mm.offset + 48); 856 857 /* wait for the chip to echo back CLB as zero */ 858 sc->sc_mm.control[0] &= ~CS4215_CLB; 859 pipe_transmit_fixed(sc, 17, *(int *)__UNVOLATILE(sc->sc_mm.control)); 860 861 tmp = bus_space_read_4(iot, ioh, DBRI_REG0); 862 tmp |= DBRI_CHI_ACTIVATE; 863 bus_space_write_4(iot, ioh, DBRI_REG0, tmp); 864 865 #if 1 866 i = 1024; 867 while (((sc->sc_mm.status & 0xe4) != 0x20) && --i) { 868 delay(125); 869 } 870 871 if (i == 0) { 872 printf("%s: cs4215 didn't respond to CLB (0x%02x)\n", 873 sc->sc_dev.dv_xname, sc->sc_mm.status); 874 return (-1); 875 } 876 #else 877 while ((sc->sc_mm.status & 0xe4) != 0x20) { 878 printf("%s: tsleep %p\n", sc->sc_dev.dv_xname, sc); 879 tsleep(sc, PCATCH | PZERO, "dbrifxdt", 0); 880 } 881 #endif 882 883 /* copy the version information before it becomes unreadable again */ 884 sc->sc_version=sc->sc_mm.version; 885 886 /* terminate cs4215 control mode */ 887 sc->sc_mm.control[0] |= CS4215_CLB; 888 pipe_transmit_fixed(sc, 17, *(int *)__UNVOLATILE(sc->sc_mm.control)); 889 890 /* two frames of control info @ 8kHz frame rate = 250us delay */ 891 DELAY(250); 892 893 mmcodec_setgain(sc, 0); 894 895 return (0); 896 897 } 898 899 /* 900 * CHI combo 901 */ 902 void 903 chi_reset(struct dbri_softc *sc, enum ms ms, int bpf) 904 { 905 volatile u_int32_t *cmd; 906 int val; 907 int clockrate, divisor; 908 909 cmd = dbri_command_lock(sc); 910 911 /* set CHI anchor: pipe 16 */ 912 val = DBRI_DTS_VI | DBRI_DTS_INS | DBRI_DTS_PRVIN(16) | DBRI_PIPE(16); 913 *(cmd++) = DBRI_CMD(DBRI_COMMAND_DTS, 0, val); 914 *(cmd++) = DBRI_TS_ANCHOR | DBRI_TS_NEXT(16); 915 *(cmd++) = 0; 916 917 val = DBRI_DTS_VO | DBRI_DTS_INS | DBRI_DTS_PRVOUT(16) | DBRI_PIPE(16); 918 *(cmd++) = DBRI_CMD(DBRI_COMMAND_DTS, 0, val); 919 *(cmd++) = 0; 920 *(cmd++) = DBRI_TS_ANCHOR | DBRI_TS_NEXT(16); 921 922 sc->sc_pipe[16].sdp = 1; 923 sc->sc_pipe[16].next = 16; 924 sc->sc_chi_pipe_in = 16; 925 sc->sc_chi_pipe_out = 16; 926 927 switch (ms) { 928 case CHIslave: 929 *(cmd++) = DBRI_CMD(DBRI_COMMAND_CHI, 0, DBRI_CHI_CHICM(0)); 930 break; 931 case CHImaster: 932 clockrate = bpf * 8; 933 divisor = 12288 / clockrate; 934 935 if (divisor > 255 || divisor * clockrate != 12288) 936 printf("%s: illegal bits-per-frame %d\n", 937 sc->sc_dev.dv_xname, bpf); 938 939 *(cmd++) = DBRI_CMD(DBRI_COMMAND_CHI, 0, 940 DBRI_CHI_CHICM(divisor) | DBRI_CHI_FD | DBRI_CHI_BPF(bpf)); 941 break; 942 default: 943 printf("%s: unknown value for ms!\n", sc->sc_dev.dv_xname); 944 break; 945 } 946 947 sc->sc_chi_bpf = bpf; 948 949 /* CHI data mode */ 950 *(cmd++) = DBRI_CMD(DBRI_COMMAND_PAUSE, 0, 0); 951 *(cmd++) = DBRI_CMD(DBRI_COMMAND_CDM, 0, 952 DBRI_CDM_XCE | DBRI_CDM_XEN | DBRI_CDM_REN); 953 954 dbri_command_send(sc, cmd); 955 956 return; 957 } 958 959 /* 960 * pipe stuff 961 */ 962 void 963 pipe_setup(struct dbri_softc *sc, int pipe, int sdp) 964 { 965 #ifdef DBRI_DEBUG 966 printf("pipe setup: %d\n",pipe); 967 #endif 968 if (pipe < 0 || pipe >= DBRI_PIPE_MAX) { 969 printf("%s: illegal pipe number %d\n", sc->sc_dev.dv_xname, 970 pipe); 971 return; 972 } 973 974 if ((sdp & 0xf800) != sdp) 975 printf("%s: strange SDP value %d\n", sc->sc_dev.dv_xname, sdp); 976 977 if (DBRI_SDP_MODE(sdp) == DBRI_SDP_FIXED && 978 !(sdp & DBRI_SDP_TO_SER)) 979 sdp |= DBRI_SDP_CHANGE; 980 981 sdp |= DBRI_PIPE(pipe); 982 983 sc->sc_pipe[pipe].sdp = sdp; 984 sc->sc_pipe[pipe].desc = -1; 985 986 pipe_reset(sc, pipe); 987 988 return; 989 } 990 991 void 992 pipe_reset(struct dbri_softc *sc, int pipe) 993 { 994 struct dbri_desc *dd; 995 int sdp; 996 int desc; 997 volatile u_int32_t *cmd; 998 999 if (pipe < 0 || pipe >= DBRI_PIPE_MAX) { 1000 printf("%s: illegal pipe number %d\n", sc->sc_dev.dv_xname, 1001 pipe); 1002 return; 1003 } 1004 1005 sdp = sc->sc_pipe[pipe].sdp; 1006 if (sdp == 0) { 1007 printf("%s: can not reset uninitialized pipe %d\n", 1008 sc->sc_dev.dv_xname, pipe); 1009 return; 1010 } 1011 1012 cmd = dbri_command_lock(sc); 1013 *(cmd++) = DBRI_CMD(DBRI_COMMAND_SDP, 0, 1014 sdp | DBRI_SDP_CLEAR | DBRI_SDP_VALID_POINTER); 1015 *(cmd++) = 0; 1016 dbri_command_send(sc, cmd); 1017 1018 desc = sc->sc_pipe[pipe].desc; 1019 1020 dd = &sc->sc_desc[desc]; 1021 1022 dd->busy = 0; 1023 1024 #if 0 1025 if (dd->callback) 1026 (*dd->callback)(dd->callback_args); 1027 #endif 1028 1029 sc->sc_pipe[pipe].desc = -1; 1030 1031 return; 1032 } 1033 1034 void 1035 pipe_receive_fixed(struct dbri_softc *sc, int pipe, volatile u_int32_t *prec) 1036 { 1037 1038 if (pipe < DBRI_PIPE_MAX / 2 || pipe >= DBRI_PIPE_MAX) { 1039 printf("%s: illegal pipe number %d\n", sc->sc_dev.dv_xname, 1040 pipe); 1041 return; 1042 } 1043 1044 if (DBRI_SDP_MODE(sc->sc_pipe[pipe].sdp) != DBRI_SDP_FIXED) { 1045 printf("%s: non-fixed pipe %d\n", sc->sc_dev.dv_xname, 1046 pipe); 1047 return; 1048 } 1049 1050 if (sc->sc_pipe[pipe].sdp & DBRI_SDP_TO_SER) { 1051 printf("%s: can not receive on transmit pipe %d\b", 1052 sc->sc_dev.dv_xname, pipe); 1053 return; 1054 } 1055 1056 sc->sc_pipe[pipe].prec = prec; 1057 1058 return; 1059 } 1060 1061 void 1062 pipe_transmit_fixed(struct dbri_softc *sc, int pipe, u_int32_t data) 1063 { 1064 volatile u_int32_t *cmd; 1065 1066 if (pipe < DBRI_PIPE_MAX / 2 || pipe >= DBRI_PIPE_MAX) { 1067 printf("%s: illegal pipe number %d\n", sc->sc_dev.dv_xname, 1068 pipe); 1069 return; 1070 } 1071 1072 if (DBRI_SDP_MODE(sc->sc_pipe[pipe].sdp) == 0) { 1073 printf("%s: uninitialized pipe %d\n", sc->sc_dev.dv_xname, 1074 pipe); 1075 return; 1076 } 1077 1078 if (DBRI_SDP_MODE(sc->sc_pipe[pipe].sdp) != DBRI_SDP_FIXED) { 1079 printf("%s: non-fixed pipe %d\n", sc->sc_dev.dv_xname, pipe); 1080 return; 1081 } 1082 1083 if (!(sc->sc_pipe[pipe].sdp & DBRI_SDP_TO_SER)) { 1084 printf("%s: called on receive pipe %d\n", sc->sc_dev.dv_xname, 1085 pipe); 1086 return; 1087 } 1088 1089 if (sc->sc_pipe[pipe].sdp & DBRI_SDP_MSB) 1090 data = reverse_bytes(data, sc->sc_pipe[pipe].length); 1091 1092 cmd = dbri_command_lock(sc); 1093 *(cmd++) = DBRI_CMD(DBRI_COMMAND_SSP, 0, pipe); 1094 *(cmd++) = data; 1095 1096 dbri_command_send(sc, cmd); 1097 1098 return; 1099 } 1100 1101 void 1102 setup_ring(struct dbri_softc *sc, int pipe, int which, int num, int blksz, 1103 void (*callback)(void *), void *callback_args) 1104 { 1105 volatile u_int32_t *cmd; 1106 int x, i; 1107 int td; 1108 int td_first, td_last; 1109 bus_addr_t dmabuf, dmabase; 1110 struct dbri_desc *dd = &sc->sc_desc[which]; 1111 1112 td = 0; 1113 td_first = td_last = -1; 1114 1115 if (pipe < 0 || pipe >= DBRI_PIPE_MAX / 2) { 1116 printf("%s: illegal pipe number %d\n", sc->sc_dev.dv_xname, 1117 pipe); 1118 return; 1119 } 1120 1121 if (sc->sc_pipe[pipe].sdp == 0) { 1122 printf("%s: uninitialized pipe %d\n", sc->sc_dev.dv_xname, 1123 pipe); 1124 return; 1125 } 1126 1127 if (!(sc->sc_pipe[pipe].sdp & DBRI_SDP_TO_SER)) { 1128 printf("%s: called on receive pipe %d\n", 1129 sc->sc_dev.dv_xname, pipe); 1130 return; 1131 } 1132 1133 1134 dmabuf = dd->dmabase; 1135 dmabase = sc->sc_dmabase; 1136 td = 0; 1137 1138 for (i = 0; i < (num-1); i++) { 1139 1140 sc->sc_dma->desc[i].flags = TX_BCNT(blksz) 1141 | TX_EOF | TX_BINT; 1142 sc->sc_dma->desc[i].ba = dmabuf; 1143 sc->sc_dma->desc[i].nda = dmabase + dbri_dma_off(desc, i + 1); 1144 sc->sc_dma->desc[i].status = 0; 1145 1146 td_last = td; 1147 dmabuf += blksz; 1148 } 1149 1150 sc->sc_dma->desc[i].flags = TX_BCNT(blksz) | TX_EOF | TX_BINT; 1151 sc->sc_dma->desc[i].ba = dmabuf; 1152 sc->sc_dma->desc[i].nda = dmabase + dbri_dma_off(desc, 0); 1153 sc->sc_dma->desc[i].status = 0; 1154 1155 dd->callback = callback; //sc->intr; 1156 dd->callback_args = callback_args; //sc->intrarg; 1157 1158 x = splaudio(); 1159 1160 /* the pipe shouldn't be active */ 1161 if (pipe_active(sc, pipe)) { 1162 printf("pipe active (CDP)\n"); 1163 /* pipe is already active */ 1164 #if 0 1165 td_last = sc->sc_pipe[pipe].desc; 1166 while (sc->sc_desc[td_last].next != -1) 1167 td_last = sc->sc_desc[td_last].next; 1168 1169 sc->sc_desc[td_last].next = td_first; 1170 sc->sc_dma->desc[td_last].nda = 1171 sc->sc_dmabase + dbri_dma_off(desc, td_first); 1172 1173 cmd = dbri_command_lock(sc); 1174 *(cmd++) = DBRI_CMD(DBRI_COMMAND_CDP, 0, pipe); 1175 dbri_command_send(sc, cmd); 1176 #endif 1177 } else { 1178 /* 1179 * pipe isn't active - issue an SDP command to start our 1180 * chain of TDs running 1181 */ 1182 sc->sc_pipe[pipe].desc = which; 1183 cmd = dbri_command_lock(sc); 1184 *(cmd++) = DBRI_CMD(DBRI_COMMAND_SDP, 0, 1185 sc->sc_pipe[pipe].sdp | 1186 DBRI_SDP_VALID_POINTER | 1187 DBRI_SDP_EVERY | 1188 DBRI_SDP_CLEAR); 1189 *(cmd++) = sc->sc_dmabase + dbri_dma_off(desc, 0); 1190 dbri_command_send(sc, cmd); 1191 } 1192 1193 splx(x); 1194 1195 return; 1196 } 1197 1198 void 1199 pipe_ts_link(struct dbri_softc *sc, int pipe, enum io dir, int basepipe, 1200 int len, int cycle) 1201 { 1202 volatile u_int32_t *cmd; 1203 int prevpipe, nextpipe; 1204 int val; 1205 1206 if (pipe < 0 || pipe >= DBRI_PIPE_MAX || 1207 basepipe < 0 || basepipe >= DBRI_PIPE_MAX) { 1208 printf("%s: illegal pipe numbers (%d, %d)\n", 1209 sc->sc_dev.dv_xname, pipe, basepipe); 1210 return; 1211 } 1212 1213 if (sc->sc_pipe[pipe].sdp == 0 || sc->sc_pipe[basepipe].sdp == 0) { 1214 printf("%s: uninitialized pipe (%d, %d)\n", 1215 sc->sc_dev.dv_xname, pipe, basepipe); 1216 return; 1217 } 1218 1219 if (basepipe == 16 && dir == PIPEoutput && cycle == 0) 1220 cycle = sc->sc_chi_bpf; 1221 1222 if (basepipe == pipe) 1223 prevpipe = nextpipe = pipe; 1224 else { 1225 if (basepipe == 16) { 1226 if (dir == PIPEinput) { 1227 prevpipe = sc->sc_chi_pipe_in; 1228 } else { 1229 prevpipe = sc->sc_chi_pipe_out; 1230 } 1231 } else 1232 prevpipe = basepipe; 1233 1234 nextpipe = sc->sc_pipe[prevpipe].next; 1235 1236 while (sc->sc_pipe[nextpipe].cycle < cycle && 1237 sc->sc_pipe[nextpipe].next != basepipe) { 1238 prevpipe = nextpipe; 1239 nextpipe = sc->sc_pipe[nextpipe].next; 1240 } 1241 } 1242 1243 if (prevpipe == 16) { 1244 if (dir == PIPEinput) { 1245 sc->sc_chi_pipe_in = pipe; 1246 } else { 1247 sc->sc_chi_pipe_out = pipe; 1248 } 1249 } else 1250 sc->sc_pipe[prevpipe].next = pipe; 1251 1252 sc->sc_pipe[pipe].next = nextpipe; 1253 sc->sc_pipe[pipe].cycle = cycle; 1254 sc->sc_pipe[pipe].length = len; 1255 1256 cmd = dbri_command_lock(sc); 1257 1258 switch (dir) { 1259 case PIPEinput: 1260 val = DBRI_DTS_VI | DBRI_DTS_INS | DBRI_DTS_PRVIN(prevpipe); 1261 val |= pipe; 1262 *(cmd++) = DBRI_CMD(DBRI_COMMAND_DTS, 0, val); 1263 *(cmd++) = DBRI_TS_LEN(len) | DBRI_TS_CYCLE(cycle) | 1264 DBRI_TS_NEXT(nextpipe); 1265 *(cmd++) = 0; 1266 break; 1267 case PIPEoutput: 1268 val = DBRI_DTS_VO | DBRI_DTS_INS | DBRI_DTS_PRVOUT(prevpipe); 1269 val |= pipe; 1270 *(cmd++) = DBRI_CMD(DBRI_COMMAND_DTS, 0, val); 1271 *(cmd++) = 0; 1272 *(cmd++) = DBRI_TS_LEN(len) | DBRI_TS_CYCLE(cycle) | 1273 DBRI_TS_NEXT(nextpipe); 1274 break; 1275 default: 1276 printf("%s: should not have happened!\n", 1277 sc->sc_dev.dv_xname); 1278 break; 1279 } 1280 1281 dbri_command_send(sc, cmd); 1282 1283 return; 1284 } 1285 1286 int 1287 pipe_active(struct dbri_softc *sc, int pipe) 1288 { 1289 1290 return (sc->sc_pipe[pipe].desc != -1); 1291 } 1292 1293 /* 1294 * subroutines required to interface with audio(9) 1295 */ 1296 1297 int 1298 dbri_query_encoding(void *hdl, struct audio_encoding *ae) 1299 { 1300 1301 /* XXX we shouldn't claim we support LE samples */ 1302 switch (ae->index) { 1303 case 0: 1304 strcpy(ae->name, AudioEulinear); 1305 ae->encoding = AUDIO_ENCODING_ULINEAR; 1306 ae->precision = 8; 1307 ae->flags = AUDIO_ENCODINGFLAG_EMULATED; 1308 break; 1309 case 1: 1310 strcpy(ae->name, AudioEmulaw); 1311 ae->encoding = AUDIO_ENCODING_ULAW; 1312 ae->precision = 8; 1313 ae->flags = 0; 1314 break; 1315 case 2: 1316 strcpy(ae->name, AudioEalaw); 1317 ae->encoding = AUDIO_ENCODING_ALAW; 1318 ae->precision = 8; 1319 ae->flags = 0; 1320 break; 1321 case 3: 1322 strcpy(ae->name, AudioEslinear); 1323 ae->encoding = AUDIO_ENCODING_SLINEAR; 1324 ae->precision = 8; 1325 ae->flags = AUDIO_ENCODINGFLAG_EMULATED; 1326 break; 1327 case 4: 1328 strcpy(ae->name, AudioEslinear_le); 1329 ae->encoding = AUDIO_ENCODING_SLINEAR_LE; 1330 ae->precision = 16; 1331 ae->flags = AUDIO_ENCODINGFLAG_EMULATED; 1332 break; 1333 case 5: 1334 strcpy(ae->name, AudioEulinear_le); 1335 ae->encoding = AUDIO_ENCODING_ULINEAR_LE; 1336 ae->precision = 16; 1337 ae->flags = AUDIO_ENCODINGFLAG_EMULATED; 1338 break; 1339 case 6: 1340 strcpy(ae->name, AudioEslinear_be); 1341 ae->encoding = AUDIO_ENCODING_SLINEAR_BE; 1342 ae->precision = 16; 1343 ae->flags = 0; 1344 break; 1345 case 7: 1346 strcpy(ae->name, AudioEulinear_be); 1347 ae->encoding = AUDIO_ENCODING_ULINEAR_BE; 1348 ae->precision = 16; 1349 ae->flags = 0; 1350 break; 1351 default: 1352 return (EINVAL); 1353 } 1354 1355 return (0); 1356 } 1357 1358 /* 1359 * XXX: recording isn't supported - jmcneill 1360 */ 1361 int 1362 dbri_set_params(void *hdl, int setmode, int usemode, 1363 struct audio_params *play, struct audio_params *rec, 1364 stream_filter_list_t *pfil, stream_filter_list_t *rfil) 1365 { 1366 struct dbri_softc *sc = hdl; 1367 int i; 1368 1369 if ((play->precision != 8 && play->precision != 16) || 1370 (play->channels != 1 && play->channels != 2)) 1371 return (EINVAL); 1372 1373 for (i = 0; CS4215_FREQ[i].freq; i++) 1374 if (CS4215_FREQ[i].freq == play->sample_rate) 1375 break; 1376 1377 if (CS4215_FREQ[i].freq == 0) 1378 return (EINVAL); 1379 1380 /* set frequency */ 1381 sc->sc_mm.control[1] &= ~0x38; 1382 sc->sc_mm.control[1] |= CS4215_FREQ[i].csval; 1383 sc->sc_mm.control[2] &= ~0x70; 1384 sc->sc_mm.control[2] |= CS4215_FREQ[i].xtal; 1385 1386 /*play->factor = 1; 1387 play->sw_code = NULL;*/ 1388 1389 switch (play->encoding) { 1390 case AUDIO_ENCODING_ULAW: 1391 sc->sc_mm.control[1] &= ~3; 1392 sc->sc_mm.control[1] |= CS4215_DFR_ULAW; 1393 break; 1394 case AUDIO_ENCODING_ALAW: 1395 sc->sc_mm.control[1] &= ~3; 1396 sc->sc_mm.control[1] |= CS4215_DFR_ALAW; 1397 break; 1398 case AUDIO_ENCODING_SLINEAR_LE: 1399 case AUDIO_ENCODING_ULINEAR_LE: 1400 if (play->precision == 16) { 1401 /* XXX this surely needs some changes elsewhere */ 1402 /*play->sw_code = swap_bytes;*/ 1403 sc->sc_mm.control[1] &= ~3; 1404 sc->sc_mm.control[1] |= CS4215_DFR_LINEAR16; 1405 } 1406 break; 1407 case AUDIO_ENCODING_ULINEAR: 1408 case AUDIO_ENCODING_SLINEAR: 1409 sc->sc_mm.control[1] &= ~3; 1410 if (play->precision == 8) { 1411 sc->sc_mm.control[1] |= CS4215_DFR_LINEAR8; 1412 } else { 1413 sc->sc_mm.control[1] |= CS4215_DFR_LINEAR16; 1414 } 1415 break; 1416 case AUDIO_ENCODING_ULINEAR_BE: 1417 case AUDIO_ENCODING_SLINEAR_BE: 1418 sc->sc_mm.control[1] &= ~3; 1419 sc->sc_mm.control[1] |= CS4215_DFR_LINEAR16; 1420 break; 1421 } 1422 1423 switch (play->channels) { 1424 case 1: 1425 sc->sc_mm.control[1] &= ~CS4215_DFR_STEREO; 1426 break; 1427 case 2: 1428 sc->sc_mm.control[1] |= CS4215_DFR_STEREO; 1429 break; 1430 } 1431 1432 return (0); 1433 } 1434 1435 int 1436 dbri_round_blocksize(void *hdl, int bs, int mode, 1437 const audio_params_t *param) 1438 { 1439 1440 /* DBRI DMA segment size, rounded town to 32bit alignment */ 1441 return 0x1ffc; 1442 } 1443 1444 int 1445 dbri_halt_output(void *hdl) 1446 { 1447 struct dbri_softc *sc = hdl; 1448 1449 pipe_reset(sc, 4); 1450 1451 return (0); 1452 } 1453 1454 int 1455 dbri_getdev(void *hdl, struct audio_device *ret) 1456 { 1457 1458 *ret = dbri_device; 1459 return (0); 1460 } 1461 1462 int 1463 dbri_set_port(void *hdl, mixer_ctrl_t *mc) 1464 { 1465 struct dbri_softc *sc = hdl; 1466 int latt = sc->sc_latt, ratt = sc->sc_ratt; 1467 1468 switch (mc->dev) { 1469 case DBRI_VOL_OUTPUT: /* master volume */ 1470 latt = (latt & 0xc0) | (63 - 1471 min(mc->un.value.level[AUDIO_MIXER_LEVEL_LEFT] >> 2, 63)); 1472 ratt = (ratt & 0xc0) | (63 - 1473 min(mc->un.value.level[AUDIO_MIXER_LEVEL_RIGHT] >> 2, 63)); 1474 break; 1475 case DBRI_ENABLE_MONO: /* built-in speaker */ 1476 if (mc->un.ord == 1) { 1477 ratt |= CS4215_SE; 1478 } else 1479 ratt &= ~CS4215_SE; 1480 break; 1481 case DBRI_ENABLE_HEADPHONE: /* headphones output */ 1482 if (mc->un.ord == 1) { 1483 latt |= CS4215_HE; 1484 } else 1485 latt &= ~CS4215_HE; 1486 break; 1487 case DBRI_ENABLE_LINE: /* line out */ 1488 if (mc->un.ord == 1) { 1489 latt |= CS4215_LE; 1490 } else 1491 latt &= ~CS4215_LE; 1492 break; 1493 } 1494 1495 sc->sc_latt = latt; 1496 sc->sc_ratt = ratt; 1497 1498 /* no need to do that here - mmcodec_setgain does it anyway */ 1499 /*pipe_transmit_fixed(sc, 20, *(int *)__UNVOLATILE(sc->sc_mm.data));*/ 1500 1501 mmcodec_setgain(sc, 0); 1502 1503 return (0); 1504 } 1505 1506 int 1507 dbri_get_port(void *hdl, mixer_ctrl_t *mc) 1508 { 1509 struct dbri_softc *sc = hdl; 1510 1511 switch (mc->dev) { 1512 case DBRI_VOL_OUTPUT: /* master volume */ 1513 mc->un.value.level[AUDIO_MIXER_LEVEL_LEFT] = 1514 (63 - (sc->sc_latt & 0x3f)) << 2; 1515 mc->un.value.level[AUDIO_MIXER_LEVEL_RIGHT] = 1516 (63 - (sc->sc_ratt & 0x3f)) << 2; 1517 return (0); 1518 case DBRI_ENABLE_MONO: /* built-in speaker */ 1519 mc->un.ord = (sc->sc_ratt & CS4215_SE) ? 1 : 0; 1520 return 0; 1521 case DBRI_ENABLE_HEADPHONE: /* headphones output */ 1522 mc->un.ord = (sc->sc_latt & CS4215_HE) ? 1 : 0; 1523 return 0; 1524 case DBRI_ENABLE_LINE: /* line out */ 1525 mc->un.ord = (sc->sc_latt & CS4215_LE) ? 1 : 0; 1526 return 0; 1527 } 1528 return (EINVAL); 1529 } 1530 1531 int 1532 dbri_query_devinfo(void *hdl, mixer_devinfo_t *di) 1533 { 1534 1535 switch (di->index) { 1536 case DBRI_MONITOR_CLASS: 1537 di->mixer_class = DBRI_MONITOR_CLASS; 1538 strcpy(di->label.name, AudioCmonitor); 1539 di->type = AUDIO_MIXER_CLASS; 1540 di->next = di->prev = AUDIO_MIXER_LAST; 1541 return 0; 1542 case DBRI_VOL_OUTPUT: /* master volume */ 1543 di->mixer_class = DBRI_MONITOR_CLASS; 1544 di->next = di->prev = AUDIO_MIXER_LAST; 1545 strcpy(di->label.name, AudioNmaster); 1546 di->type = AUDIO_MIXER_VALUE; 1547 di->un.v.num_channels = 2; 1548 strcpy(di->un.v.units.name, AudioNvolume); 1549 return (0); 1550 case DBRI_ENABLE_MONO: /* built-in speaker */ 1551 di->mixer_class = DBRI_MONITOR_CLASS; 1552 di->next = di->prev = AUDIO_MIXER_LAST; 1553 strcpy(di->label.name, AudioNmono); 1554 di->type = AUDIO_MIXER_ENUM; 1555 di->un.e.num_mem = 2; 1556 strcpy(di->un.e.member[0].label.name, AudioNoff); 1557 di->un.e.member[0].ord = 0; 1558 strcpy(di->un.e.member[1].label.name, AudioNon); 1559 di->un.e.member[1].ord = 1; 1560 return (0); 1561 case DBRI_ENABLE_HEADPHONE: /* headphones output */ 1562 di->mixer_class = DBRI_MONITOR_CLASS; 1563 di->next = di->prev = AUDIO_MIXER_LAST; 1564 strcpy(di->label.name, AudioNheadphone); 1565 di->type = AUDIO_MIXER_ENUM; 1566 di->un.e.num_mem = 2; 1567 strcpy(di->un.e.member[0].label.name, AudioNoff); 1568 di->un.e.member[0].ord = 0; 1569 strcpy(di->un.e.member[1].label.name, AudioNon); 1570 di->un.e.member[1].ord = 1; 1571 return (0); 1572 case DBRI_ENABLE_LINE: /* line out */ 1573 di->mixer_class = DBRI_MONITOR_CLASS; 1574 di->next = di->prev = AUDIO_MIXER_LAST; 1575 strcpy(di->label.name, AudioNline); 1576 di->type = AUDIO_MIXER_ENUM; 1577 di->un.e.num_mem = 2; 1578 strcpy(di->un.e.member[0].label.name, AudioNoff); 1579 di->un.e.member[0].ord = 0; 1580 strcpy(di->un.e.member[1].label.name, AudioNon); 1581 di->un.e.member[1].ord = 1; 1582 return (0); 1583 } 1584 1585 return (ENXIO); 1586 } 1587 1588 size_t 1589 dbri_round_buffersize(void *hdl, int dir, size_t bufsize) 1590 { 1591 #ifdef DBRI_BIG_BUFFER 1592 return 16*0x1ffc; /* use ~128KB buffer */ 1593 #else 1594 return bufsize; 1595 #endif 1596 } 1597 1598 int 1599 dbri_get_props(void *hdl) 1600 { 1601 1602 return (AUDIO_PROP_MMAP/* | AUDIO_PROP_INDEPENDENT*/); 1603 //return (0); 1604 } 1605 1606 int 1607 dbri_trigger_output(void *hdl, void *start, void *end, int blksize, 1608 void (*intr)(void *), void *intrarg, 1609 const struct audio_params *param) 1610 { 1611 struct dbri_softc *sc = hdl; 1612 unsigned long count, current, num; 1613 1614 count = (unsigned long)(((caddr_t)end - (caddr_t)start)); 1615 num = count / blksize; 1616 #ifdef DBRI_DEBUG 1617 printf("trigger_output(%lx %lx) : %d %ld %ld\n", 1618 (unsigned long)intr, 1619 (unsigned long)intrarg, blksize, count, num); 1620 #endif 1621 sc->sc_params = *param; 1622 1623 mmcodec_setcontrol(sc); 1624 mmcodec_init_data(sc); 1625 current = 0; 1626 while ((current < sc->sc_desc_used) && 1627 (sc->sc_desc[current].buf != start)) 1628 current++; 1629 1630 if (current < sc->sc_desc_used) { 1631 setup_ring(sc, 4, current, num, blksize, intr, intrarg); 1632 return 0; 1633 } 1634 return EINVAL; 1635 } 1636 1637 u_int32_t 1638 reverse_bytes(u_int32_t b, int len) 1639 { 1640 switch (len) { 1641 case 32: 1642 b = ((b & 0xffff0000) >> 16) | ((b & 0x0000ffff) << 16); 1643 case 16: 1644 b = ((b & 0xff00ff00) >> 8) | ((b & 0x00ff00ff) << 8); 1645 case 8: 1646 b = ((b & 0xf0f0f0f0) >> 4) | ((b & 0x0f0f0f0f) << 4); 1647 case 4: 1648 b = ((b & 0xcccccccc) >> 2) | ((b & 0x33333333) << 2); 1649 case 2: 1650 b = ((b & 0xaaaaaaaa) >> 1) | ((b & 0x55555555) << 1); 1651 case 1: 1652 case 0: 1653 break; 1654 default: 1655 printf("reverse_bytes: unsupported length\n"); 1656 }; 1657 1658 return (b); 1659 } 1660 1661 static void 1662 *dbri_malloc(void *v, int dir, size_t s, struct malloc_type *mt, int flags) 1663 { 1664 struct dbri_softc *sc = v; 1665 struct dbri_desc *dd = &sc->sc_desc[sc->sc_desc_used]; 1666 int rseg; 1667 1668 if (bus_dmamap_create(sc->sc_dmat, s, 1, s, 0, BUS_DMA_NOWAIT, 1669 &dd->dmamap) == 0) { 1670 if (bus_dmamem_alloc(sc->sc_dmat, s, 0, 0, &dd->dmaseg, 1671 1, &rseg, BUS_DMA_NOWAIT) == 0) { 1672 if (bus_dmamem_map(sc->sc_dmat, &dd->dmaseg, rseg, s, 1673 &dd->buf, BUS_DMA_NOWAIT|BUS_DMA_COHERENT) == 0) { 1674 if (dd->buf!=NULL) { 1675 if (bus_dmamap_load(sc->sc_dmat, 1676 dd->dmamap, dd->buf, s, NULL, 1677 BUS_DMA_NOWAIT) == 0) { 1678 dd->len = s; 1679 dd->busy = 0; 1680 dd->callback = NULL; 1681 dd->dmabase = 1682 dd->dmamap->dm_segs[0].ds_addr; 1683 #ifdef DBRI_DEBUG 1684 printf("dbri_malloc: using buffer %d\n", 1685 sc->sc_desc_used); 1686 #endif 1687 sc->sc_desc_used++; 1688 return dd->buf; 1689 } else 1690 printf("dbri_malloc: load failed\n"); 1691 } else 1692 printf("dbri_malloc: map returned NULL\n"); 1693 } else 1694 printf("dbri_malloc: map failed\n"); 1695 bus_dmamem_free(sc->sc_dmat, &dd->dmaseg, rseg); 1696 } else 1697 printf("dbri_malloc: malloc() failed\n"); 1698 bus_dmamap_destroy(sc->sc_dmat, dd->dmamap); 1699 } else 1700 printf("dbri_malloc: bus_dmamap_create() failed\n"); 1701 return NULL; 1702 } 1703 1704 static void 1705 dbri_free(void *v, void *p, struct malloc_type *mt) 1706 { 1707 free(p, mt); 1708 } 1709 1710 static paddr_t 1711 dbri_mappage(void *v, void *mem, off_t off, int prot) 1712 { 1713 struct dbri_softc *sc = v;; 1714 int current; 1715 1716 if (off < 0) 1717 return -1; 1718 1719 current = 0; 1720 while ((current < sc->sc_desc_used) && 1721 (sc->sc_desc[current].buf != mem)) 1722 current++; 1723 1724 if (current < sc->sc_desc_used) { 1725 return bus_dmamem_mmap(sc->sc_dmat, 1726 &sc->sc_desc[current].dmaseg, 1, off, prot, BUS_DMA_WAITOK); 1727 } 1728 1729 return -1; 1730 } 1731 1732 #endif 1733
Indexes created Thu Sep 25 16:09:42 GMT 2025