dbri.c revision 1.13
1 /* $NetBSD: dbri.c,v 1.13 2007/03/14 05:40:35 macallan Exp $ */ 2 3 /* 4 * Copyright (C) 1997 Rudolf Koenig (rfkoenig (at) immd4.informatik.uni-erlangen.de) 5 * Copyright (c) 1998, 1999 Brent Baccala (baccala (at) freesoft.org) 6 * Copyright (c) 2001, 2002 Jared D. McNeill <jmcneill (at) netbsd.org> 7 * Copyright (c) 2005 Michael Lorenz <macallan (at) netbsd.org> 8 * All rights reserved. 9 * 10 * This driver is losely based on a Linux driver written by Rudolf Koenig and 11 * Brent Baccala who kindly gave their permission to use their code in a 12 * BSD-licensed driver. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions 16 * are met: 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in the 21 * documentation and/or other materials provided with the distribution. 22 * 3. All advertising materials mentioning features or use of this software 23 * must display the following acknowledgement: 24 * This product includes software developed by Rudolf Koenig, Brent 25 * Baccala, Jared D. McNeill. 26 * 4. Neither the name of the author nor the names of any contributors may 27 * be used to endorse or promote products derived from this software 28 * without specific prior written permission. 29 * 30 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 31 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 33 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 36 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 37 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 38 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 39 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 40 * SUCH DAMAGE. 41 * 42 */ 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: dbri.c,v 1.13 2007/03/14 05:40:35 macallan Exp $"); 46 47 #include "audio.h" 48 #if NAUDIO > 0 49 50 #include <sys/param.h> 51 #include <sys/systm.h> 52 #include <sys/errno.h> 53 #include <sys/device.h> 54 #include <sys/malloc.h> 55 #include <sys/proc.h> 56 57 #include <machine/bus.h> 58 #include <machine/intr.h> 59 60 #include <dev/sbus/sbusvar.h> 61 #include <sparc/sparc/auxreg.h> 62 #include <machine/autoconf.h> 63 64 #include <sys/audioio.h> 65 #include <dev/audio_if.h> 66 #include <dev/auconv.h> 67 68 #include <dev/ic/cs4215reg.h> 69 #include <dev/ic/cs4215var.h> 70 #include <dev/sbus/dbrireg.h> 71 #include <dev/sbus/dbrivar.h> 72 73 #include "opt_sbus_dbri.h" 74 75 #define DBRI_ROM_NAME_PREFIX "SUNW,DBRI" 76 77 #ifdef DBRI_DEBUG 78 # define DPRINTF aprint_normal 79 #else 80 # define DPRINTF while (0) printf 81 #endif 82 83 static const char *dbri_supported[] = { 84 "e", 85 "s3", 86 "" 87 }; 88 89 enum ms { 90 CHImaster, 91 CHIslave 92 }; 93 94 enum io { 95 PIPEinput, 96 PIPEoutput 97 }; 98 99 /* 100 * Function prototypes 101 */ 102 103 /* softc stuff */ 104 static void dbri_attach_sbus(struct device *, struct device *, void *); 105 static int dbri_match_sbus(struct device *, struct cfdata *, void *); 106 107 static void dbri_config_interrupts(struct device *); 108 109 /* interrupt handler */ 110 static int dbri_intr(void *); 111 112 /* supporting subroutines */ 113 static int dbri_init(struct dbri_softc *); 114 static int dbri_reset(struct dbri_softc *); 115 static volatile u_int32_t *dbri_command_lock(struct dbri_softc *); 116 static void dbri_command_send(struct dbri_softc *, volatile u_int32_t *); 117 static void dbri_process_interrupt_buffer(struct dbri_softc *); 118 static void dbri_process_interrupt(struct dbri_softc *, int32_t); 119 120 /* mmcodec subroutines */ 121 static int mmcodec_init(struct dbri_softc *); 122 static void mmcodec_init_data(struct dbri_softc *); 123 static void mmcodec_pipe_init(struct dbri_softc *); 124 static void mmcodec_default(struct dbri_softc *); 125 static void mmcodec_setgain(struct dbri_softc *, int); 126 static int mmcodec_setcontrol(struct dbri_softc *); 127 128 /* chi subroutines */ 129 static void chi_reset(struct dbri_softc *, enum ms, int); 130 131 /* pipe subroutines */ 132 static void pipe_setup(struct dbri_softc *, int, int); 133 static void pipe_reset(struct dbri_softc *, int); 134 static void pipe_receive_fixed(struct dbri_softc *, int, 135 volatile u_int32_t *); 136 static void pipe_transmit_fixed(struct dbri_softc *, int, u_int32_t); 137 138 static void pipe_ts_link(struct dbri_softc *, int, enum io, int, int, int); 139 static int pipe_active(struct dbri_softc *, int); 140 141 /* audio(9) stuff */ 142 static int dbri_query_encoding(void *, struct audio_encoding *); 143 static int dbri_set_params(void *, int, int, struct audio_params *, 144 struct audio_params *,stream_filter_list_t *, stream_filter_list_t *); 145 static int dbri_round_blocksize(void *, int, int, const audio_params_t *); 146 static int dbri_halt_output(void *); 147 static int dbri_halt_input(void *); 148 static int dbri_getdev(void *, struct audio_device *); 149 static int dbri_set_port(void *, mixer_ctrl_t *); 150 static int dbri_get_port(void *, mixer_ctrl_t *); 151 static int dbri_query_devinfo(void *, mixer_devinfo_t *); 152 static size_t dbri_round_buffersize(void *, int, size_t); 153 static int dbri_get_props(void *); 154 static int dbri_open(void *, int); 155 static void dbri_close(void *); 156 157 static void setup_ring(struct dbri_softc *, int, int, int, int, 158 void (*)(void *), void *); 159 160 static int dbri_trigger_output(void *, void *, void *, int, 161 void (*)(void *), void *, const struct audio_params *); 162 static int dbri_trigger_input(void *, void *, void *, int, 163 void (*)(void *), void *, const struct audio_params *); 164 165 static void *dbri_malloc(void *, int, size_t, struct malloc_type *, int); 166 static void dbri_free(void *, void *, struct malloc_type *); 167 static paddr_t dbri_mappage(void *, void *, off_t, int); 168 static void dbri_set_power(struct dbri_softc *, int); 169 static void dbri_bring_up(struct dbri_softc *); 170 static void dbri_powerhook(int, void *); 171 172 /* stupid support routines */ 173 static u_int32_t reverse_bytes(u_int32_t, int); 174 175 struct audio_device dbri_device = { 176 "CS4215", 177 "", 178 "dbri" 179 }; 180 181 struct audio_hw_if dbri_hw_if = { 182 dbri_open, 183 dbri_close, 184 NULL, /* drain */ 185 dbri_query_encoding, 186 dbri_set_params, 187 dbri_round_blocksize, 188 NULL, /* commit_settings */ 189 NULL, /* init_output */ 190 NULL, /* init_input */ 191 NULL, /* start_output */ 192 NULL, /* start_input */ 193 dbri_halt_output, 194 dbri_halt_input, 195 NULL, /* speaker_ctl */ 196 dbri_getdev, 197 NULL, /* setfd */ 198 dbri_set_port, 199 dbri_get_port, 200 dbri_query_devinfo, 201 dbri_malloc, 202 dbri_free, 203 dbri_round_buffersize, 204 dbri_mappage, 205 dbri_get_props, 206 dbri_trigger_output, 207 dbri_trigger_input 208 }; 209 210 CFATTACH_DECL(dbri, sizeof(struct dbri_softc), 211 dbri_match_sbus, dbri_attach_sbus, NULL, NULL); 212 213 #define DBRI_NFORMATS 7 214 static const struct audio_format dbri_formats[DBRI_NFORMATS] = { 215 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_SLINEAR_BE, 16, 16, 216 2, AUFMT_STEREO, 8, {8000, 9600, 11025, 16000, 22050, 32000, 44100, 48000}}, 217 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_ULAW, 8, 8, 218 2, AUFMT_STEREO, 8, {8000, 9600, 11025, 16000, 22050, 32000, 44100, 48000}}, 219 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_ALAW, 8, 8, 220 2, AUFMT_STEREO, 8, {8000, 9600, 11025, 16000, 22050, 32000, 44100, 48000}}, 221 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_ULINEAR, 8, 8, 222 2, AUFMT_STEREO, 8, {8000, 9600, 11025, 16000, 22050, 32000, 44100, 48000}}, 223 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_ULAW, 8, 8, 224 1, AUFMT_STEREO, 8, {8000, 9600, 11025, 16000, 22050, 32000, 44100, 48000}}, 225 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_ALAW, 8, 8, 226 1, AUFMT_STEREO, 8, {8000, 9600, 11025, 16000, 22050, 32000, 44100, 48000}}, 227 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_ULINEAR, 8, 8, 228 1, AUFMT_STEREO, 8, {8000, 9600, 11025, 16000, 22050, 32000, 44100, 48000}}, 229 }; 230 231 enum { 232 DBRI_OUTPUT_CLASS, 233 DBRI_VOL_OUTPUT, 234 DBRI_ENABLE_MONO, 235 DBRI_ENABLE_HEADPHONE, 236 DBRI_ENABLE_LINE, 237 DBRI_MONITOR_CLASS, 238 DBRI_VOL_MONITOR, 239 DBRI_INPUT_CLASS, 240 DBRI_INPUT_GAIN, 241 DBRI_INPUT_SELECT, 242 DBRI_RECORD_CLASS, 243 DBRI_ENUM_LAST 244 }; 245 246 /* 247 * Autoconfig routines 248 */ 249 static int 250 dbri_match_sbus(struct device *parent, struct cfdata *match, void *aux) 251 { 252 struct sbus_attach_args *sa = aux; 253 char *ver; 254 int i; 255 256 if (strncmp(DBRI_ROM_NAME_PREFIX, sa->sa_name, 9)) 257 return (0); 258 259 ver = &sa->sa_name[9]; 260 261 for (i = 0; dbri_supported[i][0] != '\0'; i++) 262 if (strcmp(dbri_supported[i], ver) == 0) 263 return (1); 264 265 return (0); 266 } 267 268 static void 269 dbri_attach_sbus(struct device *parent, struct device *self, void *aux) 270 { 271 struct dbri_softc *sc = (struct dbri_softc *)self; 272 struct sbus_attach_args *sa = aux; 273 bus_space_handle_t ioh; 274 bus_size_t size; 275 int error, rseg, pwr; 276 char *ver = &sa->sa_name[9]; 277 278 sc->sc_iot = sa->sa_bustag; 279 sc->sc_dmat = sa->sa_dmatag; 280 sc->sc_powerstate = PWR_RESUME; 281 282 pwr = prom_getpropint(sa->sa_node,"pwr-on-auxio",0); 283 aprint_normal(": rev %s\n", ver); 284 285 if (pwr) { 286 /* 287 * we can control DBRI power via auxio and we're initially 288 * powered down 289 */ 290 291 sc->sc_have_powerctl = 1; 292 sc->sc_powerstate = 0; 293 dbri_set_power(sc, 1); 294 powerhook_establish(self->dv_xname, dbri_powerhook, sc); 295 } else { 296 /* we can't control power so we're always up */ 297 sc->sc_have_powerctl = 0; 298 sc->sc_powerstate = 1; 299 } 300 301 if (sa->sa_npromvaddrs) 302 ioh = (bus_space_handle_t)sa->sa_promvaddrs[0]; 303 else { 304 if (sbus_bus_map(sa->sa_bustag, sa->sa_slot, 305 sa->sa_offset, sa->sa_size, 306 BUS_SPACE_MAP_LINEAR, /*0,*/ &ioh) != 0) { 307 aprint_error("%s @ sbus: cannot map registers\n", 308 self->dv_xname); 309 return; 310 } 311 } 312 313 sc->sc_ioh = ioh; 314 315 size = sizeof(struct dbri_dma); 316 317 /* get a DMA handle */ 318 if ((error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, 319 BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) { 320 aprint_error("%s: DMA map create error %d\n", self->dv_xname, error); 321 return; 322 } 323 324 /* allocate DMA buffer */ 325 if ((error = bus_dmamem_alloc(sc->sc_dmat, size, 0, 0, &sc->sc_dmaseg, 326 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 327 aprint_error("%s: DMA buffer alloc error %d\n", 328 self->dv_xname, error); 329 return; 330 } 331 332 /* map DMA buffer into CPU addressable space */ 333 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_dmaseg, rseg, size, 334 &sc->sc_membase, 335 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 336 aprint_error("%s: DMA buffer map error %d\n", 337 self->dv_xname, error); 338 return; 339 } 340 341 /* load the buffer */ 342 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, 343 sc->sc_membase, size, NULL, 344 BUS_DMA_NOWAIT)) != 0) { 345 aprint_error("%s: DMA buffer map load error %d\n", 346 self->dv_xname, error); 347 bus_dmamem_unmap(sc->sc_dmat, sc->sc_membase, size); 348 bus_dmamem_free(sc->sc_dmat, &sc->sc_dmaseg, rseg); 349 return; 350 } 351 352 /* map the registers into memory */ 353 354 /* kernel virtual address of DMA buffer */ 355 sc->sc_dma = (struct dbri_dma *)sc->sc_membase; 356 /* physical address of DMA buffer */ 357 sc->sc_dmabase = sc->sc_dmamap->dm_segs[0].ds_addr; 358 sc->sc_bufsiz = size; 359 360 sbus_establish(&sc->sc_sd, &sc->sc_dev); 361 362 bus_intr_establish(sa->sa_bustag, sa->sa_pri, IPL_AUDIO, dbri_intr, 363 sc); 364 365 sc->sc_locked = 0; 366 sc->sc_desc_used = 0; 367 sc->sc_open = 0; 368 sc->sc_playing = 0; 369 sc->sc_pmgrstate = PWR_RESUME; 370 config_interrupts(self, &dbri_config_interrupts); 371 372 return; 373 } 374 375 /* 376 * lowlevel routine to switch power for the DBRI chip 377 */ 378 static void 379 dbri_set_power(struct dbri_softc *sc, int state) 380 { 381 int s; 382 383 if (sc->sc_have_powerctl == 0) 384 return; 385 if (sc->sc_powerstate == state) 386 return; 387 388 if (state) { 389 DPRINTF("%s: waiting to power up... ", sc->sc_dev.dv_xname); 390 s = splhigh(); 391 *AUXIO4M_REG |= (AUXIO4M_MMX); 392 splx(s); 393 delay(10000); 394 DPRINTF("done (%02x)\n", *AUXIO4M_REG); 395 } else { 396 DPRINTF("%s: powering down\n", sc->sc_dev.dv_xname); 397 s = splhigh(); 398 *AUXIO4M_REG &= ~AUXIO4M_MMX; 399 splx(s); 400 DPRINTF("done (%02x})\n", *AUXIO4M_REG); 401 } 402 sc->sc_powerstate = state; 403 } 404 405 /* 406 * power up and re-initialize the chip 407 */ 408 static void 409 dbri_bring_up(struct dbri_softc *sc) 410 { 411 412 if (sc->sc_have_powerctl == 0) 413 return; 414 if (sc->sc_powerstate == 1) 415 return; 416 417 /* ok, we really need to do something */ 418 dbri_set_power(sc, 1); 419 420 /* 421 * re-initialize the chip but skip all the probing, don't overwrite 422 * any other settings either 423 */ 424 dbri_init(sc); 425 mmcodec_setgain(sc, 1); 426 mmcodec_pipe_init(sc); 427 mmcodec_init_data(sc); 428 mmcodec_setgain(sc, 0); 429 } 430 431 static void 432 dbri_config_interrupts(struct device *dev) 433 { 434 struct dbri_softc *sc = (struct dbri_softc *)dev; 435 436 dbri_init(sc); 437 mmcodec_init(sc); 438 439 /* Attach ourselves to the high level audio interface */ 440 audio_attach_mi(&dbri_hw_if, sc, &sc->sc_dev); 441 442 /* power down until open() */ 443 dbri_set_power(sc, 0); 444 return; 445 } 446 447 static int 448 dbri_intr(void *hdl) 449 { 450 struct dbri_softc *sc = hdl; 451 bus_space_tag_t iot = sc->sc_iot; 452 bus_space_handle_t ioh = sc->sc_ioh; 453 int x; 454 455 /* clear interrupt */ 456 x = bus_space_read_4(iot, ioh, DBRI_REG1); 457 if (x & (DBRI_MRR | DBRI_MLE | DBRI_LBG | DBRI_MBE)) { 458 u_int32_t tmp; 459 460 if (x & DBRI_MRR) 461 aprint_debug("%s: multiple ack error on sbus\n", 462 sc->sc_dev.dv_xname); 463 if (x & DBRI_MLE) 464 aprint_debug("%s: multiple late error on sbus\n", 465 sc->sc_dev.dv_xname); 466 if (x & DBRI_LBG) 467 aprint_debug("%s: lost bus grant on sbus\n", 468 sc->sc_dev.dv_xname); 469 if (x & DBRI_MBE) 470 aprint_debug("%s: burst error on sbus\n", 471 sc->sc_dev.dv_xname); 472 473 /* 474 * Some of these errors disable the chip's circuitry. 475 * Re-enable the circuitry and keep on going. 476 */ 477 478 tmp = bus_space_read_4(iot, ioh, DBRI_REG0); 479 tmp &= ~(DBRI_DISABLE_MASTER); 480 bus_space_write_4(iot, ioh, DBRI_REG0, tmp); 481 } 482 483 #if 0 484 if (!x & 1) /* XXX: DBRI_INTR_REQ */ 485 return (1); 486 #endif 487 488 dbri_process_interrupt_buffer(sc); 489 490 return (1); 491 } 492 493 static int 494 dbri_init(struct dbri_softc *sc) 495 { 496 bus_space_tag_t iot = sc->sc_iot; 497 bus_space_handle_t ioh = sc->sc_ioh; 498 u_int32_t reg; 499 volatile u_int32_t *cmd; 500 bus_addr_t dmaaddr; 501 int n; 502 503 dbri_reset(sc); 504 505 cmd = dbri_command_lock(sc); 506 507 /* XXX: Initialize interrupt ring buffer */ 508 sc->sc_dma->intr[0] = (u_int32_t)sc->sc_dmabase + dbri_dma_off(intr, 0); 509 sc->sc_irqp = 1; 510 511 /* Initialize pipes */ 512 for (n = 0; n < DBRI_PIPE_MAX; n++) 513 sc->sc_pipe[n].desc = sc->sc_pipe[n].next = -1; 514 515 for (n = 1; n < DBRI_INT_BLOCKS; n++) { 516 sc->sc_dma->intr[n] = 0; 517 } 518 519 /* Disable all SBus bursts */ 520 /* XXX 16 byte bursts cause errors, the rest works */ 521 reg = bus_space_read_4(iot, ioh, DBRI_REG0); 522 523 /*reg &= ~(DBRI_BURST_4 | DBRI_BURST_8 | DBRI_BURST_16);*/ 524 reg |= (DBRI_BURST_4 | DBRI_BURST_8); 525 bus_space_write_4(iot, ioh, DBRI_REG0, reg); 526 527 /* setup interrupt queue */ 528 dmaaddr = (u_int32_t)sc->sc_dmabase + dbri_dma_off(intr, 0); 529 *(cmd++) = DBRI_CMD(DBRI_COMMAND_IIQ, 0, 0); 530 *(cmd++) = dmaaddr; 531 532 dbri_command_send(sc, cmd); 533 return (0); 534 } 535 536 static int 537 dbri_reset(struct dbri_softc *sc) 538 { 539 int bail = 0; 540 541 bus_space_tag_t iot = sc->sc_iot; 542 bus_space_handle_t ioh = sc->sc_ioh; 543 544 bus_space_write_4(iot, ioh, DBRI_REG0, DBRI_SOFT_RESET); 545 while ((bus_space_read_4(iot, ioh, DBRI_REG0) & DBRI_SOFT_RESET) && 546 (bail < 100000)) { 547 bail++; 548 delay(10); 549 } 550 if (bail == 100000) aprint_error("%s: reset timed out\n", 551 sc->sc_dev.dv_xname); 552 return (0); 553 } 554 555 static volatile u_int32_t * 556 dbri_command_lock(struct dbri_softc *sc) 557 { 558 559 if (sc->sc_locked) 560 aprint_debug("%s: command buffer locked\n", sc->sc_dev.dv_xname); 561 562 sc->sc_locked++; 563 564 return (&sc->sc_dma->command[0]); 565 } 566 567 static void 568 dbri_command_send(struct dbri_softc *sc, volatile u_int32_t *cmd) 569 { 570 bus_space_handle_t ioh = sc->sc_ioh; 571 bus_space_tag_t iot = sc->sc_iot; 572 int maxloops = 1000000; 573 int x; 574 575 x = splaudio(); 576 577 sc->sc_locked--; 578 579 if (sc->sc_locked != 0) { 580 aprint_error("%s: command buffer improperly locked\n", 581 sc->sc_dev.dv_xname); 582 } else if ((cmd - &sc->sc_dma->command[0]) >= DBRI_NUM_COMMANDS - 1) { 583 aprint_error("%s: command buffer overflow\n", sc->sc_dev.dv_xname); 584 } else { 585 *(cmd++) = DBRI_CMD(DBRI_COMMAND_PAUSE, 0, 0); 586 *(cmd++) = DBRI_CMD(DBRI_COMMAND_WAIT, 1, 0); 587 sc->sc_waitseen = 0; 588 bus_space_write_4(iot, ioh, DBRI_REG8, sc->sc_dmabase); 589 while ((--maxloops) > 0 && 590 (bus_space_read_4(iot, ioh, DBRI_REG0) 591 & DBRI_COMMAND_VALID)) { 592 bus_space_barrier(iot, ioh, DBRI_REG0, 4, 593 BUS_SPACE_BARRIER_READ); 594 delay(1000); 595 } 596 597 if (maxloops == 0) { 598 aprint_error("%s: chip never completed command buffer\n", 599 sc->sc_dev.dv_xname); 600 } else { 601 602 DPRINTF("%s: command completed\n", 603 sc->sc_dev.dv_xname); 604 605 while ((--maxloops) > 0 && (!sc->sc_waitseen)) 606 dbri_process_interrupt_buffer(sc); 607 if (maxloops == 0) { 608 aprint_error("%s: chip never acked WAIT\n", 609 sc->sc_dev.dv_xname); 610 } 611 } 612 } 613 614 splx(x); 615 616 return; 617 } 618 619 static void 620 dbri_process_interrupt_buffer(struct dbri_softc *sc) 621 { 622 int32_t i; 623 624 while ((i = sc->sc_dma->intr[sc->sc_irqp]) != 0) { 625 sc->sc_dma->intr[sc->sc_irqp] = 0; 626 sc->sc_irqp++; 627 628 if (sc->sc_irqp == DBRI_INT_BLOCKS) 629 sc->sc_irqp = 1; 630 else if ((sc->sc_irqp & (DBRI_INT_BLOCKS - 1)) == 0) 631 sc->sc_irqp++; 632 633 dbri_process_interrupt(sc, i); 634 } 635 636 return; 637 } 638 639 static void 640 dbri_process_interrupt(struct dbri_softc *sc, int32_t i) 641 { 642 #if 0 643 const int liu_states[] = { 1, 0, 8, 3, 4, 5, 6, 7 }; 644 #endif 645 int val = DBRI_INTR_GETVAL(i); 646 int channel = DBRI_INTR_GETCHAN(i); 647 int command = DBRI_INTR_GETCMD(i); 648 int code = DBRI_INTR_GETCODE(i); 649 #if 0 650 int rval = DBRI_INTR_GETRVAL(i); 651 #endif 652 if (channel == DBRI_INTR_CMD && command == DBRI_COMMAND_WAIT) 653 sc->sc_waitseen++; 654 655 switch (code) { 656 case DBRI_INTR_XCMP: /* transmission complete */ 657 { 658 int td; 659 struct dbri_desc *dd; 660 661 td = sc->sc_pipe[channel].desc; 662 dd = &sc->sc_desc[td]; 663 664 if (dd->callback != NULL) 665 dd->callback(dd->callback_args); 666 break; 667 } 668 case DBRI_INTR_FXDT: /* fixed data change */ 669 DPRINTF("dbri_intr: Fixed data change (%d: %x)\n", channel, 670 val); 671 672 if (sc->sc_pipe[channel].sdp & DBRI_SDP_MSB) 673 val = reverse_bytes(val, sc->sc_pipe[channel].length); 674 if (sc->sc_pipe[channel].prec) 675 *(sc->sc_pipe[channel].prec) = val; 676 #ifndef DBRI_SPIN 677 DPRINTF("%s: wakeup %p\n", sc->sc_dev.dv_xname, sc); 678 wakeup(sc); 679 #endif 680 break; 681 case DBRI_INTR_SBRI: 682 DPRINTF("dbri_intr: SBRI\n"); 683 break; 684 case DBRI_INTR_BRDY: 685 { 686 /* XXX no input (yet) */ 687 #if 0 688 int rd = sc->sc_pipe[channel].desc; 689 u_int32_t status; 690 691 DPRINTF("dbri_intr: BRDY\n"); 692 if (rd < 0 || rd >= DBRI_NUM_DESCRIPTORS) { 693 aprint_error("%s: invalid rd on pipe\n", 694 sc->sc_dev.dv_xname); 695 break; 696 } 697 698 sc->sc_desc[rd].busy = 0; 699 sc->sc_pipe[channel].desc = sc->sc_desc[rd].next; 700 status = sc->sc_dma->desc[rd].word1; 701 #endif 702 /* XXX: callback ??? */ 703 704 break; 705 } 706 case DBRI_INTR_UNDR: 707 { 708 volatile u_int32_t *cmd; 709 int td = sc->sc_pipe[channel].desc; 710 711 DPRINTF("%s: DBRI_INTR_UNDR\n", sc->sc_dev.dv_xname); 712 713 sc->sc_dma->desc[td].status = 0; 714 715 cmd = dbri_command_lock(sc); 716 *(cmd++) = DBRI_CMD(DBRI_COMMAND_SDP, 0, 717 sc->sc_pipe[channel].sdp | 718 DBRI_SDP_VALID_POINTER | 719 DBRI_SDP_CLEAR | 720 DBRI_SDP_2SAME); 721 *(cmd++) = sc->sc_dmabase + dbri_dma_off(desc, td); 722 dbri_command_send(sc, cmd); 723 break; 724 } 725 case DBRI_INTR_CMDI: 726 break; 727 default: 728 729 DPRINTF("%s: unknown interrupt code %d\n", 730 sc->sc_dev.dv_xname, code); 731 break; 732 } 733 734 return; 735 } 736 737 /* 738 * mmcodec stuff 739 */ 740 741 static int 742 mmcodec_init(struct dbri_softc *sc) 743 { 744 bus_space_handle_t ioh = sc->sc_ioh; 745 bus_space_tag_t iot = sc->sc_iot; 746 u_int32_t reg2; 747 int bail; 748 749 reg2 = bus_space_read_4(iot, ioh, DBRI_REG2); 750 DPRINTF("mmcodec_init: PIO reads %x\n", reg2); 751 752 if (reg2 & DBRI_PIO2) { 753 aprint_normal("%s: onboard CS4215 detected\n", 754 sc->sc_dev.dv_xname); 755 sc->sc_mm.onboard = 1; 756 } 757 758 if (reg2 & DBRI_PIO0) { 759 aprint_normal("%s: speakerbox detected\n", 760 sc->sc_dev.dv_xname); 761 sc->sc_mm.onboard = 0; 762 } 763 764 if ((reg2 & DBRI_PIO2) && (reg2 & DBRI_PIO0)) { 765 aprint_normal("%s: using speakerbox\n", 766 sc->sc_dev.dv_xname); 767 bus_space_write_4(iot, ioh, DBRI_REG2, DBRI_PIO2_ENABLE); 768 sc->sc_mm.onboard = 0; 769 } 770 771 if (!(reg2 & (DBRI_PIO0|DBRI_PIO2))) { 772 aprint_normal("%s: no mmcodec found\n", sc->sc_dev.dv_xname); 773 return -1; 774 } 775 776 sc->sc_version = 0xff; 777 778 mmcodec_pipe_init(sc); 779 mmcodec_default(sc); 780 781 sc->sc_mm.offset = sc->sc_mm.onboard ? 0 : 8; 782 783 /* 784 * mmcodec_setcontrol() sometimes fails right after powerup 785 * so we just try again until we either get a useful response or run 786 * out of time 787 */ 788 bail = 0; 789 while (mmcodec_setcontrol(sc) == -1 || sc->sc_version == 0xff) { 790 791 bail++; 792 if (bail > 100) { 793 DPRINTF("%s: cs4215 probe failed at offset %d\n", 794 sc->sc_dev.dv_xname, sc->sc_mm.offset); 795 return (-1); 796 } 797 delay(10000); 798 } 799 800 aprint_normal("%s: cs4215 ver %d found at offset %d\n", 801 sc->sc_dev.dv_xname, sc->sc_version & 0xf, sc->sc_mm.offset); 802 803 /* set some sane defaults for mmcodec_init_data */ 804 sc->sc_params.channels = 2; 805 sc->sc_params.precision = 16; 806 807 mmcodec_init_data(sc); 808 809 return (0); 810 } 811 812 static void 813 mmcodec_init_data(struct dbri_softc *sc) 814 { 815 bus_space_tag_t iot = sc->sc_iot; 816 bus_space_handle_t ioh = sc->sc_ioh; 817 u_int32_t tmp; 818 int data_width; 819 820 tmp = bus_space_read_4(iot, ioh, DBRI_REG0); 821 tmp &= ~(DBRI_CHI_ACTIVATE); /* disable CHI */ 822 bus_space_write_4(iot, ioh, DBRI_REG0, tmp); 823 824 /* switch CS4215 to data mode - set PIO3 to 1 */ 825 tmp = DBRI_PIO_ENABLE_ALL | DBRI_PIO1 | DBRI_PIO3; 826 827 /* XXX */ 828 tmp |= (sc->sc_mm.onboard ? DBRI_PIO0 : DBRI_PIO2); 829 830 bus_space_write_4(iot, ioh, DBRI_REG2, tmp); 831 chi_reset(sc, CHIslave, 128); 832 833 data_width = sc->sc_params.channels * sc->sc_params.precision; 834 pipe_ts_link(sc, 20, PIPEoutput, 16, 32, sc->sc_mm.offset + 32); 835 pipe_ts_link(sc, 4, PIPEoutput, 16, data_width, sc->sc_mm.offset); 836 pipe_ts_link(sc, 6, PIPEinput, 16, data_width, sc->sc_mm.offset); 837 pipe_ts_link(sc, 21, PIPEinput, 16, 16, sc->sc_mm.offset + 40); 838 839 mmcodec_setgain(sc, 0); 840 841 tmp = bus_space_read_4(iot, ioh, DBRI_REG0); 842 tmp |= DBRI_CHI_ACTIVATE; 843 bus_space_write_4(iot, ioh, DBRI_REG0, tmp); 844 845 return; 846 } 847 848 static void 849 mmcodec_pipe_init(struct dbri_softc *sc) 850 { 851 852 pipe_setup(sc, 4, DBRI_SDP_MEM | DBRI_SDP_TO_SER | DBRI_SDP_MSB); 853 pipe_setup(sc, 20, DBRI_SDP_FIXED | DBRI_SDP_TO_SER | DBRI_SDP_MSB); 854 pipe_setup(sc, 6, DBRI_SDP_MEM | DBRI_SDP_FROM_SER | DBRI_SDP_MSB); 855 pipe_setup(sc, 21, DBRI_SDP_FIXED | DBRI_SDP_FROM_SER | DBRI_SDP_MSB); 856 857 pipe_setup(sc, 17, DBRI_SDP_FIXED | DBRI_SDP_TO_SER | DBRI_SDP_MSB); 858 pipe_setup(sc, 18, DBRI_SDP_FIXED | DBRI_SDP_FROM_SER | DBRI_SDP_MSB); 859 pipe_setup(sc, 19, DBRI_SDP_FIXED | DBRI_SDP_FROM_SER | DBRI_SDP_MSB); 860 861 sc->sc_mm.status = 0; 862 863 pipe_receive_fixed(sc, 18, &sc->sc_mm.status); 864 pipe_receive_fixed(sc, 19, &sc->sc_mm.version); 865 866 return; 867 } 868 869 static void 870 mmcodec_default(struct dbri_softc *sc) 871 { 872 struct cs4215_state *mm = &sc->sc_mm; 873 874 /* 875 * no action, memory resetting only 876 * 877 * data time slots 5-8 878 * speaker, line and headphone enable. set gain to half. 879 * input is mic 880 */ 881 mm->d.bdata[0] = sc->sc_latt = 0x20 | CS4215_HE | CS4215_LE; 882 mm->d.bdata[1] = sc->sc_ratt = 0x20 | CS4215_SE; 883 sc->sc_linp = 128; 884 sc->sc_rinp = 128; 885 sc->sc_monitor = 0; 886 sc->sc_input = 1; /* line */ 887 mm->d.bdata[2] = (CS4215_LG((sc->sc_linp >> 4)) & 0x0f) | 888 ((sc->sc_input == 2) ? CS4215_IS : 0) | CS4215_PIO0 | CS4215_PIO1; 889 mm->d.bdata[3] = (CS4215_RG((sc->sc_rinp >> 4) & 0x0f)) | 890 CS4215_MA(15 - ((sc->sc_monitor >> 4) & 0x0f)); 891 892 893 /* 894 * control time slots 1-4 895 * 896 * 0: default I/O voltage scale 897 * 1: 8 bit ulaw, 8kHz, mono, high pass filter disabled 898 * 2: serial enable, CHI master, 128 bits per frame, clock 1 899 * 3: tests disabled 900 */ 901 mm->c.bcontrol[0] = CS4215_RSRVD_1 | CS4215_MLB; 902 mm->c.bcontrol[1] = CS4215_DFR_ULAW | CS4215_FREQ[0].csval; 903 mm->c.bcontrol[2] = CS4215_XCLK | CS4215_BSEL_128 | CS4215_FREQ[0].xtal; 904 mm->c.bcontrol[3] = 0; 905 906 return; 907 } 908 909 static void 910 mmcodec_setgain(struct dbri_softc *sc, int mute) 911 { 912 if (mute) { 913 /* disable all outputs, max. attenuation */ 914 sc->sc_mm.d.bdata[0] = sc->sc_latt | 63; 915 sc->sc_mm.d.bdata[1] = sc->sc_ratt | 63; 916 } else { 917 918 sc->sc_mm.d.bdata[0] = sc->sc_latt; 919 sc->sc_mm.d.bdata[1] = sc->sc_ratt; 920 } 921 922 /* input stuff */ 923 sc->sc_mm.d.bdata[2] = CS4215_LG((sc->sc_linp >> 4) & 0x0f) | 924 ((sc->sc_input == 2) ? CS4215_IS : 0) | CS4215_PIO0 | CS4215_PIO1; 925 sc->sc_mm.d.bdata[3] = (CS4215_RG((sc->sc_rinp >> 4)) & 0x0f) | 926 (CS4215_MA(15 - ((sc->sc_monitor >> 4) & 0x0f))); 927 928 if (sc->sc_powerstate == 0) 929 return; 930 pipe_transmit_fixed(sc, 20, sc->sc_mm.d.ldata); 931 932 DPRINTF("mmcodec_setgain: %08x\n", sc->sc_mm.d.ldata); 933 /* give the chip some time to execute the command */ 934 delay(250); 935 936 return; 937 } 938 939 static int 940 mmcodec_setcontrol(struct dbri_softc *sc) 941 { 942 bus_space_tag_t iot = sc->sc_iot; 943 bus_space_handle_t ioh = sc->sc_ioh; 944 u_int32_t val; 945 u_int32_t tmp; 946 #if DBRI_SPIN 947 int i; 948 #endif 949 950 /* 951 * Temporarily mute outputs and wait 125 us to make sure that it 952 * happens. This avoids clicking noises. 953 */ 954 mmcodec_setgain(sc, 1); 955 delay(125); 956 957 /* enable control mode */ 958 val = DBRI_PIO_ENABLE_ALL | DBRI_PIO1; /* was PIO1 */ 959 960 /* XXX */ 961 val |= (sc->sc_mm.onboard ? DBRI_PIO0 : DBRI_PIO2); 962 963 bus_space_write_4(iot, ioh, DBRI_REG2, val); 964 965 delay(34); 966 967 /* 968 * in control mode, the cs4215 is the slave device, so the 969 * DBRI must act as the CHI master. 970 * 971 * in data mode, the cs4215 must be the CHI master to insure 972 * that the data stream is in sync with its codec 973 */ 974 tmp = bus_space_read_4(iot, ioh, DBRI_REG0); 975 tmp &= ~DBRI_COMMAND_CHI; 976 bus_space_write_4(iot, ioh, DBRI_REG0, tmp); 977 978 chi_reset(sc, CHImaster, 128); 979 980 /* control mode */ 981 pipe_ts_link(sc, 17, PIPEoutput, 16, 32, sc->sc_mm.offset); 982 pipe_ts_link(sc, 18, PIPEinput, 16, 8, sc->sc_mm.offset); 983 pipe_ts_link(sc, 19, PIPEinput, 16, 8, sc->sc_mm.offset + 48); 984 985 /* wait for the chip to echo back CLB as zero */ 986 sc->sc_mm.c.bcontrol[0] &= ~CS4215_CLB; 987 pipe_transmit_fixed(sc, 17, sc->sc_mm.c.lcontrol); 988 989 tmp = bus_space_read_4(iot, ioh, DBRI_REG0); 990 tmp |= DBRI_CHI_ACTIVATE; 991 bus_space_write_4(iot, ioh, DBRI_REG0, tmp); 992 993 #if DBRI_SPIN 994 i = 1024; 995 while (((sc->sc_mm.status & 0xe4) != 0x20) && --i) { 996 delay(125); 997 } 998 999 if (i == 0) { 1000 DPRINTF("%s: cs4215 didn't respond to CLB (0x%02x)\n", 1001 sc->sc_dev.dv_xname, sc->sc_mm.status); 1002 return (-1); 1003 } 1004 #else 1005 while ((sc->sc_mm.status & 0xe4) != 0x20) { 1006 DPRINTF("%s: tsleep %p\n", sc->sc_dev.dv_xname, sc); 1007 tsleep(sc, PCATCH | PZERO, "dbrifxdt", 0); 1008 } 1009 #endif 1010 1011 /* copy the version information before it becomes unreadable again */ 1012 sc->sc_version = sc->sc_mm.version; 1013 1014 /* terminate cs4215 control mode */ 1015 sc->sc_mm.c.bcontrol[0] |= CS4215_CLB; 1016 pipe_transmit_fixed(sc, 17, sc->sc_mm.c.lcontrol); 1017 1018 /* two frames of control info @ 8kHz frame rate = 250us delay */ 1019 delay(250); 1020 1021 mmcodec_setgain(sc, 0); 1022 1023 return (0); 1024 1025 } 1026 1027 /* 1028 * CHI combo 1029 */ 1030 static void 1031 chi_reset(struct dbri_softc *sc, enum ms ms, int bpf) 1032 { 1033 volatile u_int32_t *cmd; 1034 int val; 1035 int clockrate, divisor; 1036 1037 cmd = dbri_command_lock(sc); 1038 1039 /* set CHI anchor: pipe 16 */ 1040 val = DBRI_DTS_VI | DBRI_DTS_INS | DBRI_DTS_PRVIN(16) | DBRI_PIPE(16); 1041 *(cmd++) = DBRI_CMD(DBRI_COMMAND_DTS, 0, val); 1042 *(cmd++) = DBRI_TS_ANCHOR | DBRI_TS_NEXT(16); 1043 *(cmd++) = 0; 1044 1045 val = DBRI_DTS_VO | DBRI_DTS_INS | DBRI_DTS_PRVOUT(16) | DBRI_PIPE(16); 1046 *(cmd++) = DBRI_CMD(DBRI_COMMAND_DTS, 0, val); 1047 *(cmd++) = 0; 1048 *(cmd++) = DBRI_TS_ANCHOR | DBRI_TS_NEXT(16); 1049 1050 sc->sc_pipe[16].sdp = 1; 1051 sc->sc_pipe[16].next = 16; 1052 sc->sc_chi_pipe_in = 16; 1053 sc->sc_chi_pipe_out = 16; 1054 1055 switch (ms) { 1056 case CHIslave: 1057 *(cmd++) = DBRI_CMD(DBRI_COMMAND_CHI, 0, DBRI_CHI_CHICM(0)); 1058 break; 1059 case CHImaster: 1060 clockrate = bpf * 8; 1061 divisor = 12288 / clockrate; 1062 1063 if (divisor > 255 || divisor * clockrate != 12288) 1064 aprint_error("%s: illegal bits-per-frame %d\n", 1065 sc->sc_dev.dv_xname, bpf); 1066 1067 *(cmd++) = DBRI_CMD(DBRI_COMMAND_CHI, 0, 1068 DBRI_CHI_CHICM(divisor) | DBRI_CHI_FD | DBRI_CHI_BPF(bpf)); 1069 break; 1070 default: 1071 aprint_error("%s: unknown value for ms!\n", sc->sc_dev.dv_xname); 1072 break; 1073 } 1074 1075 sc->sc_chi_bpf = bpf; 1076 1077 /* CHI data mode */ 1078 *(cmd++) = DBRI_CMD(DBRI_COMMAND_PAUSE, 0, 0); 1079 *(cmd++) = DBRI_CMD(DBRI_COMMAND_CDM, 0, 1080 DBRI_CDM_XCE | DBRI_CDM_XEN | DBRI_CDM_REN); 1081 1082 dbri_command_send(sc, cmd); 1083 1084 return; 1085 } 1086 1087 /* 1088 * pipe stuff 1089 */ 1090 static void 1091 pipe_setup(struct dbri_softc *sc, int pipe, int sdp) 1092 { 1093 DPRINTF("pipe setup: %d\n", pipe); 1094 if (pipe < 0 || pipe >= DBRI_PIPE_MAX) { 1095 aprint_error("%s: illegal pipe number %d\n", sc->sc_dev.dv_xname, 1096 pipe); 1097 return; 1098 } 1099 1100 if ((sdp & 0xf800) != sdp) 1101 aprint_error("%s: strange SDP value %d\n", sc->sc_dev.dv_xname, sdp); 1102 1103 if (DBRI_SDP_MODE(sdp) == DBRI_SDP_FIXED && 1104 !(sdp & DBRI_SDP_TO_SER)) 1105 sdp |= DBRI_SDP_CHANGE; 1106 1107 sdp |= DBRI_PIPE(pipe); 1108 1109 sc->sc_pipe[pipe].sdp = sdp; 1110 sc->sc_pipe[pipe].desc = -1; 1111 1112 pipe_reset(sc, pipe); 1113 1114 return; 1115 } 1116 1117 static void 1118 pipe_reset(struct dbri_softc *sc, int pipe) 1119 { 1120 struct dbri_desc *dd; 1121 int sdp; 1122 int desc; 1123 volatile u_int32_t *cmd; 1124 1125 if (pipe < 0 || pipe >= DBRI_PIPE_MAX) { 1126 aprint_error("%s: illegal pipe number %d\n", sc->sc_dev.dv_xname, 1127 pipe); 1128 return; 1129 } 1130 1131 sdp = sc->sc_pipe[pipe].sdp; 1132 if (sdp == 0) { 1133 aprint_error("%s: can not reset uninitialized pipe %d\n", 1134 sc->sc_dev.dv_xname, pipe); 1135 return; 1136 } 1137 1138 cmd = dbri_command_lock(sc); 1139 *(cmd++) = DBRI_CMD(DBRI_COMMAND_SDP, 0, 1140 sdp | DBRI_SDP_CLEAR | DBRI_SDP_VALID_POINTER); 1141 *(cmd++) = 0; 1142 dbri_command_send(sc, cmd); 1143 1144 desc = sc->sc_pipe[pipe].desc; 1145 1146 dd = &sc->sc_desc[desc]; 1147 1148 dd->busy = 0; 1149 1150 #if 0 1151 if (dd->callback) 1152 (*dd->callback)(dd->callback_args); 1153 #endif 1154 1155 sc->sc_pipe[pipe].desc = -1; 1156 1157 return; 1158 } 1159 1160 static void 1161 pipe_receive_fixed(struct dbri_softc *sc, int pipe, volatile u_int32_t *prec) 1162 { 1163 1164 if (pipe < DBRI_PIPE_MAX / 2 || pipe >= DBRI_PIPE_MAX) { 1165 aprint_error("%s: illegal pipe number %d\n", 1166 sc->sc_dev.dv_xname, pipe); 1167 return; 1168 } 1169 1170 if (DBRI_SDP_MODE(sc->sc_pipe[pipe].sdp) != DBRI_SDP_FIXED) { 1171 aprint_error("%s: non-fixed pipe %d\n", sc->sc_dev.dv_xname, 1172 pipe); 1173 return; 1174 } 1175 1176 if (sc->sc_pipe[pipe].sdp & DBRI_SDP_TO_SER) { 1177 aprint_error("%s: can not receive on transmit pipe %d\b", 1178 sc->sc_dev.dv_xname, pipe); 1179 return; 1180 } 1181 1182 sc->sc_pipe[pipe].prec = prec; 1183 1184 return; 1185 } 1186 1187 static void 1188 pipe_transmit_fixed(struct dbri_softc *sc, int pipe, u_int32_t data) 1189 { 1190 volatile u_int32_t *cmd; 1191 1192 if (pipe < DBRI_PIPE_MAX / 2 || pipe >= DBRI_PIPE_MAX) { 1193 aprint_error("%s: illegal pipe number %d\n", 1194 sc->sc_dev.dv_xname, pipe); 1195 return; 1196 } 1197 1198 if (DBRI_SDP_MODE(sc->sc_pipe[pipe].sdp) == 0) { 1199 aprint_error("%s: uninitialized pipe %d\n", 1200 sc->sc_dev.dv_xname, pipe); 1201 return; 1202 } 1203 1204 if (DBRI_SDP_MODE(sc->sc_pipe[pipe].sdp) != DBRI_SDP_FIXED) { 1205 aprint_error("%s: non-fixed pipe %d\n", sc->sc_dev.dv_xname, 1206 pipe); 1207 return; 1208 } 1209 1210 if (!(sc->sc_pipe[pipe].sdp & DBRI_SDP_TO_SER)) { 1211 aprint_error("%s: called on receive pipe %d\n", 1212 sc->sc_dev.dv_xname, pipe); 1213 return; 1214 } 1215 1216 if (sc->sc_pipe[pipe].sdp & DBRI_SDP_MSB) 1217 data = reverse_bytes(data, sc->sc_pipe[pipe].length); 1218 1219 cmd = dbri_command_lock(sc); 1220 *(cmd++) = DBRI_CMD(DBRI_COMMAND_SSP, 0, pipe); 1221 *(cmd++) = data; 1222 1223 dbri_command_send(sc, cmd); 1224 1225 return; 1226 } 1227 1228 static void 1229 setup_ring(struct dbri_softc *sc, int pipe, int which, int num, int blksz, 1230 void (*callback)(void *), void *callback_args) 1231 { 1232 volatile u_int32_t *cmd; 1233 int x, i; 1234 int td; 1235 int td_first, td_last; 1236 bus_addr_t dmabuf, dmabase; 1237 struct dbri_desc *dd = &sc->sc_desc[which]; 1238 1239 td = 0; 1240 td_first = td_last = -1; 1241 1242 if (pipe < 0 || pipe >= DBRI_PIPE_MAX / 2) { 1243 aprint_error("%s: illegal pipe number %d\n", 1244 sc->sc_dev.dv_xname, pipe); 1245 return; 1246 } 1247 1248 if (sc->sc_pipe[pipe].sdp == 0) { 1249 aprint_error("%s: uninitialized pipe %d\n", 1250 sc->sc_dev.dv_xname, pipe); 1251 return; 1252 } 1253 1254 if (!(sc->sc_pipe[pipe].sdp & DBRI_SDP_TO_SER)) { 1255 aprint_error("%s: called on receive pipe %d\n", 1256 sc->sc_dev.dv_xname, pipe); 1257 return; 1258 } 1259 1260 1261 dmabuf = dd->dmabase; 1262 dmabase = sc->sc_dmabase; 1263 td = 0; 1264 1265 for (i = 0; i < (num-1); i++) { 1266 1267 sc->sc_dma->desc[i].flags = TX_BCNT(blksz) 1268 | TX_EOF | TX_BINT; 1269 sc->sc_dma->desc[i].ba = dmabuf; 1270 sc->sc_dma->desc[i].nda = dmabase + dbri_dma_off(desc, i + 1); 1271 sc->sc_dma->desc[i].status = 0; 1272 1273 td_last = td; 1274 dmabuf += blksz; 1275 } 1276 1277 sc->sc_dma->desc[i].flags = TX_BCNT(blksz) | TX_EOF | TX_BINT; 1278 sc->sc_dma->desc[i].ba = dmabuf; 1279 sc->sc_dma->desc[i].nda = dmabase + dbri_dma_off(desc, 0); 1280 sc->sc_dma->desc[i].status = 0; 1281 1282 dd->callback = callback; 1283 dd->callback_args = callback_args; 1284 1285 x = splaudio(); 1286 1287 /* the pipe shouldn't be active */ 1288 if (pipe_active(sc, pipe)) { 1289 aprint_error("pipe active (CDP)\n"); 1290 /* pipe is already active */ 1291 #if 0 1292 td_last = sc->sc_pipe[pipe].desc; 1293 while (sc->sc_desc[td_last].next != -1) 1294 td_last = sc->sc_desc[td_last].next; 1295 1296 sc->sc_desc[td_last].next = td_first; 1297 sc->sc_dma->desc[td_last].nda = 1298 sc->sc_dmabase + dbri_dma_off(desc, td_first); 1299 1300 cmd = dbri_command_lock(sc); 1301 *(cmd++) = DBRI_CMD(DBRI_COMMAND_CDP, 0, pipe); 1302 dbri_command_send(sc, cmd); 1303 #endif 1304 } else { 1305 /* 1306 * pipe isn't active - issue an SDP command to start our 1307 * chain of TDs running 1308 */ 1309 sc->sc_pipe[pipe].desc = which; 1310 cmd = dbri_command_lock(sc); 1311 *(cmd++) = DBRI_CMD(DBRI_COMMAND_SDP, 0, 1312 sc->sc_pipe[pipe].sdp | 1313 DBRI_SDP_VALID_POINTER | 1314 DBRI_SDP_EVERY | 1315 DBRI_SDP_CLEAR); 1316 *(cmd++) = sc->sc_dmabase + dbri_dma_off(desc, 0); 1317 dbri_command_send(sc, cmd); 1318 } 1319 1320 splx(x); 1321 1322 return; 1323 } 1324 1325 static void 1326 pipe_ts_link(struct dbri_softc *sc, int pipe, enum io dir, int basepipe, 1327 int len, int cycle) 1328 { 1329 volatile u_int32_t *cmd; 1330 int prevpipe, nextpipe; 1331 int val; 1332 1333 if (pipe < 0 || pipe >= DBRI_PIPE_MAX || 1334 basepipe < 0 || basepipe >= DBRI_PIPE_MAX) { 1335 aprint_error("%s: illegal pipe numbers (%d, %d)\n", 1336 sc->sc_dev.dv_xname, pipe, basepipe); 1337 return; 1338 } 1339 1340 if (sc->sc_pipe[pipe].sdp == 0 || sc->sc_pipe[basepipe].sdp == 0) { 1341 aprint_error("%s: uninitialized pipe (%d, %d)\n", 1342 sc->sc_dev.dv_xname, pipe, basepipe); 1343 return; 1344 } 1345 1346 if (basepipe == 16 && dir == PIPEoutput && cycle == 0) 1347 cycle = sc->sc_chi_bpf; 1348 1349 if (basepipe == pipe) 1350 prevpipe = nextpipe = pipe; 1351 else { 1352 if (basepipe == 16) { 1353 if (dir == PIPEinput) { 1354 prevpipe = sc->sc_chi_pipe_in; 1355 } else { 1356 prevpipe = sc->sc_chi_pipe_out; 1357 } 1358 } else 1359 prevpipe = basepipe; 1360 1361 nextpipe = sc->sc_pipe[prevpipe].next; 1362 1363 while (sc->sc_pipe[nextpipe].cycle < cycle && 1364 sc->sc_pipe[nextpipe].next != basepipe) { 1365 prevpipe = nextpipe; 1366 nextpipe = sc->sc_pipe[nextpipe].next; 1367 } 1368 } 1369 1370 if (prevpipe == 16) { 1371 if (dir == PIPEinput) { 1372 sc->sc_chi_pipe_in = pipe; 1373 } else { 1374 sc->sc_chi_pipe_out = pipe; 1375 } 1376 } else 1377 sc->sc_pipe[prevpipe].next = pipe; 1378 1379 sc->sc_pipe[pipe].next = nextpipe; 1380 sc->sc_pipe[pipe].cycle = cycle; 1381 sc->sc_pipe[pipe].length = len; 1382 1383 cmd = dbri_command_lock(sc); 1384 1385 switch (dir) { 1386 case PIPEinput: 1387 val = DBRI_DTS_VI | DBRI_DTS_INS | DBRI_DTS_PRVIN(prevpipe); 1388 val |= pipe; 1389 *(cmd++) = DBRI_CMD(DBRI_COMMAND_DTS, 0, val); 1390 *(cmd++) = DBRI_TS_LEN(len) | DBRI_TS_CYCLE(cycle) | 1391 DBRI_TS_NEXT(nextpipe); 1392 *(cmd++) = 0; 1393 break; 1394 case PIPEoutput: 1395 val = DBRI_DTS_VO | DBRI_DTS_INS | DBRI_DTS_PRVOUT(prevpipe); 1396 val |= pipe; 1397 *(cmd++) = DBRI_CMD(DBRI_COMMAND_DTS, 0, val); 1398 *(cmd++) = 0; 1399 *(cmd++) = DBRI_TS_LEN(len) | DBRI_TS_CYCLE(cycle) | 1400 DBRI_TS_NEXT(nextpipe); 1401 break; 1402 default: 1403 DPRINTF("%s: should not have happened!\n", 1404 sc->sc_dev.dv_xname); 1405 break; 1406 } 1407 1408 dbri_command_send(sc, cmd); 1409 1410 return; 1411 } 1412 1413 static int 1414 pipe_active(struct dbri_softc *sc, int pipe) 1415 { 1416 1417 return (sc->sc_pipe[pipe].desc != -1); 1418 } 1419 1420 /* 1421 * subroutines required to interface with audio(9) 1422 */ 1423 1424 static int 1425 dbri_query_encoding(void *hdl, struct audio_encoding *ae) 1426 { 1427 1428 switch (ae->index) { 1429 case 0: 1430 strcpy(ae->name, AudioEulinear); 1431 ae->encoding = AUDIO_ENCODING_ULINEAR; 1432 ae->precision = 8; 1433 ae->flags = 0; 1434 break; 1435 case 1: 1436 strcpy(ae->name, AudioEmulaw); 1437 ae->encoding = AUDIO_ENCODING_ULAW; 1438 ae->precision = 8; 1439 ae->flags = 0; 1440 break; 1441 case 2: 1442 strcpy(ae->name, AudioEalaw); 1443 ae->encoding = AUDIO_ENCODING_ALAW; 1444 ae->precision = 8; 1445 ae->flags = 0; 1446 break; 1447 case 3: 1448 strcpy(ae->name, AudioEslinear); 1449 ae->encoding = AUDIO_ENCODING_SLINEAR; 1450 ae->precision = 8; 1451 ae->flags = AUDIO_ENCODINGFLAG_EMULATED; 1452 break; 1453 case 4: 1454 strcpy(ae->name, AudioEslinear_le); 1455 ae->encoding = AUDIO_ENCODING_SLINEAR_LE; 1456 ae->precision = 16; 1457 ae->flags = AUDIO_ENCODINGFLAG_EMULATED; 1458 break; 1459 case 5: 1460 strcpy(ae->name, AudioEulinear_le); 1461 ae->encoding = AUDIO_ENCODING_ULINEAR_LE; 1462 ae->precision = 16; 1463 ae->flags = AUDIO_ENCODINGFLAG_EMULATED; 1464 break; 1465 case 6: 1466 strcpy(ae->name, AudioEslinear_be); 1467 ae->encoding = AUDIO_ENCODING_SLINEAR_BE; 1468 ae->precision = 16; 1469 ae->flags = 0; 1470 break; 1471 case 7: 1472 strcpy(ae->name, AudioEulinear_be); 1473 ae->encoding = AUDIO_ENCODING_ULINEAR_BE; 1474 ae->precision = 16; 1475 ae->flags = AUDIO_ENCODINGFLAG_EMULATED; 1476 break; 1477 case 8: 1478 strcpy(ae->name, AudioEslinear); 1479 ae->encoding = AUDIO_ENCODING_SLINEAR; 1480 ae->precision = 16; 1481 ae->flags = 0; 1482 break; 1483 default: 1484 return (EINVAL); 1485 } 1486 1487 return (0); 1488 } 1489 1490 /* 1491 * XXX: recording isn't supported - jmcneill 1492 */ 1493 static int 1494 dbri_set_params(void *hdl, int setmode, int usemode, 1495 struct audio_params *play, struct audio_params *rec, 1496 stream_filter_list_t *pfil, stream_filter_list_t *rfil) 1497 { 1498 struct dbri_softc *sc = hdl; 1499 int rate; 1500 audio_params_t *p = NULL; 1501 stream_filter_list_t *fil; 1502 int mode; 1503 1504 /* 1505 * This device only has one clock, so make the sample rates match. 1506 */ 1507 if (play->sample_rate != rec->sample_rate && 1508 usemode == (AUMODE_PLAY | AUMODE_RECORD)) { 1509 if (setmode == AUMODE_PLAY) { 1510 rec->sample_rate = play->sample_rate; 1511 setmode |= AUMODE_RECORD; 1512 } else if (setmode == AUMODE_RECORD) { 1513 play->sample_rate = rec->sample_rate; 1514 setmode |= AUMODE_PLAY; 1515 } else 1516 return EINVAL; 1517 } 1518 1519 for (mode = AUMODE_RECORD; mode != -1; 1520 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) { 1521 if ((setmode & mode) == 0) 1522 continue; 1523 1524 p = mode == AUMODE_PLAY ? play : rec; 1525 if (p->sample_rate < 4000 || p->sample_rate > 50000) { 1526 DPRINTF("dbri_set_params: invalid rate %d\n", 1527 p->sample_rate); 1528 return EINVAL; 1529 } 1530 1531 fil = mode == AUMODE_PLAY ? pfil : rfil; 1532 DPRINTF("enc: %d rate: %d prec: %d chan: %d\n", p->encoding, 1533 p->sample_rate, p->precision, p->channels); 1534 if (auconv_set_converter(dbri_formats, DBRI_NFORMATS, 1535 mode, p, true, fil) < 0) { 1536 DPRINTF("dbri_set_params: auconv_set_converter failed\n"); 1537 return EINVAL; 1538 } 1539 if (fil->req_size > 0) 1540 p = &fil->filters[0].param; 1541 } 1542 1543 if (p == NULL) { 1544 DPRINTF("dbri_set_params: no parameters to set\n"); 1545 return 0; 1546 } 1547 1548 DPRINTF("enc: %d rate: %d prec: %d chan: %d\n", p->encoding, 1549 p->sample_rate, p->precision, p->channels); 1550 1551 for (rate = 0; CS4215_FREQ[rate].freq; rate++) 1552 if (CS4215_FREQ[rate].freq == p->sample_rate) 1553 break; 1554 1555 if (CS4215_FREQ[rate].freq == 0) 1556 return (EINVAL); 1557 1558 /* set frequency */ 1559 sc->sc_mm.c.bcontrol[1] &= ~0x38; 1560 sc->sc_mm.c.bcontrol[1] |= CS4215_FREQ[rate].csval; 1561 sc->sc_mm.c.bcontrol[2] &= ~0x70; 1562 sc->sc_mm.c.bcontrol[2] |= CS4215_FREQ[rate].xtal; 1563 1564 switch (p->encoding) { 1565 case AUDIO_ENCODING_ULAW: 1566 sc->sc_mm.c.bcontrol[1] &= ~3; 1567 sc->sc_mm.c.bcontrol[1] |= CS4215_DFR_ULAW; 1568 break; 1569 case AUDIO_ENCODING_ALAW: 1570 sc->sc_mm.c.bcontrol[1] &= ~3; 1571 sc->sc_mm.c.bcontrol[1] |= CS4215_DFR_ALAW; 1572 break; 1573 case AUDIO_ENCODING_ULINEAR: 1574 sc->sc_mm.c.bcontrol[1] &= ~3; 1575 if (p->precision == 8) { 1576 sc->sc_mm.c.bcontrol[1] |= CS4215_DFR_LINEAR8; 1577 } else { 1578 sc->sc_mm.c.bcontrol[1] |= CS4215_DFR_LINEAR16; 1579 } 1580 break; 1581 case AUDIO_ENCODING_SLINEAR_BE: 1582 case AUDIO_ENCODING_SLINEAR: 1583 sc->sc_mm.c.bcontrol[1] &= ~3; 1584 sc->sc_mm.c.bcontrol[1] |= CS4215_DFR_LINEAR16; 1585 break; 1586 } 1587 1588 switch (p->channels) { 1589 case 1: 1590 sc->sc_mm.c.bcontrol[1] &= ~CS4215_DFR_STEREO; 1591 break; 1592 case 2: 1593 sc->sc_mm.c.bcontrol[1] |= CS4215_DFR_STEREO; 1594 break; 1595 } 1596 1597 return (0); 1598 } 1599 1600 static int 1601 dbri_round_blocksize(void *hdl, int bs, int mode, 1602 const audio_params_t *param) 1603 { 1604 1605 /* DBRI DMA segment size, rounded town to 32bit alignment */ 1606 return 0x1ffc; 1607 } 1608 1609 static int 1610 dbri_halt_output(void *hdl) 1611 { 1612 struct dbri_softc *sc = hdl; 1613 1614 sc->sc_playing = 0; 1615 pipe_reset(sc, 4); 1616 return (0); 1617 } 1618 1619 static int 1620 dbri_getdev(void *hdl, struct audio_device *ret) 1621 { 1622 1623 *ret = dbri_device; 1624 return (0); 1625 } 1626 1627 static int 1628 dbri_set_port(void *hdl, mixer_ctrl_t *mc) 1629 { 1630 struct dbri_softc *sc = hdl; 1631 int latt = sc->sc_latt, ratt = sc->sc_ratt; 1632 1633 switch (mc->dev) { 1634 case DBRI_VOL_OUTPUT: /* master volume */ 1635 latt = (latt & 0xc0) | (63 - 1636 min(mc->un.value.level[AUDIO_MIXER_LEVEL_LEFT] >> 2, 63)); 1637 ratt = (ratt & 0xc0) | (63 - 1638 min(mc->un.value.level[AUDIO_MIXER_LEVEL_RIGHT] >> 2, 63)); 1639 break; 1640 case DBRI_ENABLE_MONO: /* built-in speaker */ 1641 if (mc->un.ord == 1) { 1642 ratt |= CS4215_SE; 1643 } else 1644 ratt &= ~CS4215_SE; 1645 break; 1646 case DBRI_ENABLE_HEADPHONE: /* headphones output */ 1647 if (mc->un.ord == 1) { 1648 latt |= CS4215_HE; 1649 } else 1650 latt &= ~CS4215_HE; 1651 break; 1652 case DBRI_ENABLE_LINE: /* line out */ 1653 if (mc->un.ord == 1) { 1654 latt |= CS4215_LE; 1655 } else 1656 latt &= ~CS4215_LE; 1657 break; 1658 case DBRI_VOL_MONITOR: 1659 if (mc->un.value.level[AUDIO_MIXER_LEVEL_LEFT] == 1660 sc->sc_monitor) 1661 return 0; 1662 sc->sc_monitor = mc->un.value.level[AUDIO_MIXER_LEVEL_LEFT]; 1663 break; 1664 case DBRI_INPUT_GAIN: 1665 sc->sc_linp = mc->un.value.level[AUDIO_MIXER_LEVEL_LEFT]; 1666 sc->sc_rinp = mc->un.value.level[AUDIO_MIXER_LEVEL_RIGHT]; 1667 break; 1668 case DBRI_INPUT_SELECT: 1669 if (mc->un.mask == sc->sc_input) 1670 return 0; 1671 sc->sc_input = mc->un.mask; 1672 break; 1673 } 1674 1675 sc->sc_latt = latt; 1676 sc->sc_ratt = ratt; 1677 1678 mmcodec_setgain(sc, 0); 1679 1680 return (0); 1681 } 1682 1683 static int 1684 dbri_get_port(void *hdl, mixer_ctrl_t *mc) 1685 { 1686 struct dbri_softc *sc = hdl; 1687 1688 switch (mc->dev) { 1689 case DBRI_VOL_OUTPUT: /* master volume */ 1690 mc->un.value.level[AUDIO_MIXER_LEVEL_LEFT] = 1691 (63 - (sc->sc_latt & 0x3f)) << 2; 1692 mc->un.value.level[AUDIO_MIXER_LEVEL_RIGHT] = 1693 (63 - (sc->sc_ratt & 0x3f)) << 2; 1694 return (0); 1695 case DBRI_ENABLE_MONO: /* built-in speaker */ 1696 mc->un.ord = (sc->sc_ratt & CS4215_SE) ? 1 : 0; 1697 return 0; 1698 case DBRI_ENABLE_HEADPHONE: /* headphones output */ 1699 mc->un.ord = (sc->sc_latt & CS4215_HE) ? 1 : 0; 1700 return 0; 1701 case DBRI_ENABLE_LINE: /* line out */ 1702 mc->un.ord = (sc->sc_latt & CS4215_LE) ? 1 : 0; 1703 return 0; 1704 case DBRI_VOL_MONITOR: 1705 mc->un.value.level[AUDIO_MIXER_LEVEL_LEFT] = sc->sc_monitor; 1706 return 0; 1707 case DBRI_INPUT_GAIN: 1708 mc->un.value.level[AUDIO_MIXER_LEVEL_LEFT] = sc->sc_linp; 1709 mc->un.value.level[AUDIO_MIXER_LEVEL_RIGHT] = sc->sc_rinp; 1710 return 0; 1711 case DBRI_INPUT_SELECT: 1712 mc->un.mask = sc->sc_input; 1713 return 0; 1714 } 1715 return (EINVAL); 1716 } 1717 1718 static int 1719 dbri_query_devinfo(void *hdl, mixer_devinfo_t *di) 1720 { 1721 1722 switch (di->index) { 1723 case DBRI_MONITOR_CLASS: 1724 di->mixer_class = DBRI_MONITOR_CLASS; 1725 strcpy(di->label.name, AudioCmonitor); 1726 di->type = AUDIO_MIXER_CLASS; 1727 di->next = di->prev = AUDIO_MIXER_LAST; 1728 return 0; 1729 case DBRI_OUTPUT_CLASS: 1730 di->mixer_class = DBRI_OUTPUT_CLASS; 1731 strcpy(di->label.name, AudioCoutputs); 1732 di->type = AUDIO_MIXER_CLASS; 1733 di->next = di->prev = AUDIO_MIXER_LAST; 1734 return 0; 1735 case DBRI_INPUT_CLASS: 1736 di->mixer_class = DBRI_INPUT_CLASS; 1737 strcpy(di->label.name, AudioCinputs); 1738 di->type = AUDIO_MIXER_CLASS; 1739 di->next = di->prev = AUDIO_MIXER_LAST; 1740 return 0; 1741 case DBRI_VOL_OUTPUT: /* master volume */ 1742 di->mixer_class = DBRI_OUTPUT_CLASS; 1743 di->next = di->prev = AUDIO_MIXER_LAST; 1744 strcpy(di->label.name, AudioNmaster); 1745 di->type = AUDIO_MIXER_VALUE; 1746 di->un.v.num_channels = 2; 1747 strcpy(di->un.v.units.name, AudioNvolume); 1748 return (0); 1749 case DBRI_INPUT_GAIN: /* input gain */ 1750 di->mixer_class = DBRI_INPUT_CLASS; 1751 di->next = di->prev = AUDIO_MIXER_LAST; 1752 strcpy(di->label.name, AudioNrecord); 1753 di->type = AUDIO_MIXER_VALUE; 1754 di->un.v.num_channels = 2; 1755 strcpy(di->un.v.units.name, AudioNvolume); 1756 return (0); 1757 case DBRI_VOL_MONITOR: /* monitor volume */ 1758 di->mixer_class = DBRI_MONITOR_CLASS; 1759 di->next = di->prev = AUDIO_MIXER_LAST; 1760 strcpy(di->label.name, AudioNmonitor); 1761 di->type = AUDIO_MIXER_VALUE; 1762 di->un.v.num_channels = 1; 1763 strcpy(di->un.v.units.name, AudioNvolume); 1764 return (0); 1765 case DBRI_ENABLE_MONO: /* built-in speaker */ 1766 di->mixer_class = DBRI_OUTPUT_CLASS; 1767 di->next = di->prev = AUDIO_MIXER_LAST; 1768 strcpy(di->label.name, AudioNmono); 1769 di->type = AUDIO_MIXER_ENUM; 1770 di->un.e.num_mem = 2; 1771 strcpy(di->un.e.member[0].label.name, AudioNoff); 1772 di->un.e.member[0].ord = 0; 1773 strcpy(di->un.e.member[1].label.name, AudioNon); 1774 di->un.e.member[1].ord = 1; 1775 return (0); 1776 case DBRI_ENABLE_HEADPHONE: /* headphones output */ 1777 di->mixer_class = DBRI_OUTPUT_CLASS; 1778 di->next = di->prev = AUDIO_MIXER_LAST; 1779 strcpy(di->label.name, AudioNheadphone); 1780 di->type = AUDIO_MIXER_ENUM; 1781 di->un.e.num_mem = 2; 1782 strcpy(di->un.e.member[0].label.name, AudioNoff); 1783 di->un.e.member[0].ord = 0; 1784 strcpy(di->un.e.member[1].label.name, AudioNon); 1785 di->un.e.member[1].ord = 1; 1786 return (0); 1787 case DBRI_ENABLE_LINE: /* line out */ 1788 di->mixer_class = DBRI_OUTPUT_CLASS; 1789 di->next = di->prev = AUDIO_MIXER_LAST; 1790 strcpy(di->label.name, AudioNline); 1791 di->type = AUDIO_MIXER_ENUM; 1792 di->un.e.num_mem = 2; 1793 strcpy(di->un.e.member[0].label.name, AudioNoff); 1794 di->un.e.member[0].ord = 0; 1795 strcpy(di->un.e.member[1].label.name, AudioNon); 1796 di->un.e.member[1].ord = 1; 1797 return (0); 1798 case DBRI_INPUT_SELECT: 1799 di->mixer_class = DBRI_INPUT_CLASS; 1800 strcpy(di->label.name, AudioNsource); 1801 di->type = AUDIO_MIXER_SET; 1802 di->prev = di->next = AUDIO_MIXER_LAST; 1803 di->un.s.num_mem = 2; 1804 strcpy(di->un.s.member[0].label.name, AudioNline); 1805 di->un.s.member[0].mask = 1 << 0; 1806 strcpy(di->un.s.member[1].label.name, AudioNmicrophone); 1807 di->un.s.member[1].mask = 1 << 1; 1808 return 0; 1809 } 1810 1811 return (ENXIO); 1812 } 1813 1814 static size_t 1815 dbri_round_buffersize(void *hdl, int dir, size_t bufsize) 1816 { 1817 #ifdef DBRI_BIG_BUFFER 1818 return 16*0x1ffc; /* use ~128KB buffer */ 1819 #else 1820 return bufsize; 1821 #endif 1822 } 1823 1824 static int 1825 dbri_get_props(void *hdl) 1826 { 1827 1828 return AUDIO_PROP_MMAP; 1829 } 1830 1831 static int 1832 dbri_trigger_output(void *hdl, void *start, void *end, int blksize, 1833 void (*intr)(void *), void *intrarg, 1834 const struct audio_params *param) 1835 { 1836 struct dbri_softc *sc = hdl; 1837 unsigned long count, current, num; 1838 1839 count = (unsigned long)(((char *)end - (char *)start)); 1840 num = count / blksize; 1841 1842 DPRINTF("trigger_output(%lx %lx) : %d %ld %ld\n", 1843 (unsigned long)intr, 1844 (unsigned long)intrarg, blksize, count, num); 1845 1846 sc->sc_params = *param; 1847 1848 mmcodec_setcontrol(sc); 1849 mmcodec_init_data(sc); 1850 current = 0; 1851 while ((current < sc->sc_desc_used) && 1852 (sc->sc_desc[current].buf != start)) 1853 current++; 1854 1855 if (current < sc->sc_desc_used) { 1856 setup_ring(sc, 4, current, num, blksize, intr, intrarg); 1857 sc->sc_playing = 1; 1858 return 0; 1859 } 1860 return EINVAL; 1861 } 1862 1863 static int 1864 dbri_halt_input(void *cookie) 1865 { 1866 return 0; 1867 } 1868 1869 static int 1870 dbri_trigger_input(void *hdl, void *start, void *end, int blksize, 1871 void (*intr)(void *), void *intrarg, 1872 const struct audio_params *param) 1873 { 1874 #if notyet 1875 struct dbri_softc *sc = hdl; 1876 unsigned long count, current, num; 1877 1878 count = (unsigned long)(((char *)end - (char *)start)); 1879 num = count / blksize; 1880 1881 DPRINTF("trigger_input(%lx %lx) : %d %ld %ld\n", 1882 (unsigned long)intr, 1883 (unsigned long)intrarg, blksize, count, num); 1884 1885 sc->sc_params = *param; 1886 1887 mmcodec_setcontrol(sc); 1888 mmcodec_init_data(sc); 1889 current = 0; 1890 while ((current < sc->sc_desc_used) && 1891 (sc->sc_desc[current].buf != start)) 1892 current++; 1893 1894 if (current < sc->sc_desc_used) { 1895 setup_ring(sc, 4, current, num, blksize, intr, intrarg); 1896 return 0; 1897 } 1898 #endif 1899 return EINVAL; 1900 } 1901 1902 1903 static u_int32_t 1904 reverse_bytes(u_int32_t b, int len) 1905 { 1906 switch (len) { 1907 case 32: 1908 b = ((b & 0xffff0000) >> 16) | ((b & 0x0000ffff) << 16); 1909 case 16: 1910 b = ((b & 0xff00ff00) >> 8) | ((b & 0x00ff00ff) << 8); 1911 case 8: 1912 b = ((b & 0xf0f0f0f0) >> 4) | ((b & 0x0f0f0f0f) << 4); 1913 case 4: 1914 b = ((b & 0xcccccccc) >> 2) | ((b & 0x33333333) << 2); 1915 case 2: 1916 b = ((b & 0xaaaaaaaa) >> 1) | ((b & 0x55555555) << 1); 1917 case 1: 1918 case 0: 1919 break; 1920 default: 1921 DPRINTF("reverse_bytes: unsupported length\n"); 1922 }; 1923 1924 return (b); 1925 } 1926 1927 static void 1928 *dbri_malloc(void *v, int dir, size_t s, struct malloc_type *mt, int flags) 1929 { 1930 struct dbri_softc *sc = v; 1931 struct dbri_desc *dd = &sc->sc_desc[sc->sc_desc_used]; 1932 int rseg; 1933 1934 if (bus_dmamap_create(sc->sc_dmat, s, 1, s, 0, BUS_DMA_NOWAIT, 1935 &dd->dmamap) == 0) { 1936 if (bus_dmamem_alloc(sc->sc_dmat, s, 0, 0, &dd->dmaseg, 1937 1, &rseg, BUS_DMA_NOWAIT) == 0) { 1938 if (bus_dmamem_map(sc->sc_dmat, &dd->dmaseg, rseg, s, 1939 &dd->buf, BUS_DMA_NOWAIT|BUS_DMA_COHERENT) == 0) { 1940 if (dd->buf!=NULL) { 1941 if (bus_dmamap_load(sc->sc_dmat, 1942 dd->dmamap, dd->buf, s, NULL, 1943 BUS_DMA_NOWAIT) == 0) { 1944 dd->len = s; 1945 dd->busy = 0; 1946 dd->callback = NULL; 1947 dd->dmabase = 1948 dd->dmamap->dm_segs[0].ds_addr; 1949 DPRINTF("dbri_malloc: using buffer %d\n", 1950 sc->sc_desc_used); 1951 sc->sc_desc_used++; 1952 return dd->buf; 1953 } else 1954 aprint_error("dbri_malloc: load failed\n"); 1955 } else 1956 aprint_error("dbri_malloc: map returned NULL\n"); 1957 } else 1958 aprint_error("dbri_malloc: map failed\n"); 1959 bus_dmamem_free(sc->sc_dmat, &dd->dmaseg, rseg); 1960 } else 1961 aprint_error("dbri_malloc: malloc() failed\n"); 1962 bus_dmamap_destroy(sc->sc_dmat, dd->dmamap); 1963 } else 1964 aprint_error("dbri_malloc: bus_dmamap_create() failed\n"); 1965 return NULL; 1966 } 1967 1968 static void 1969 dbri_free(void *v, void *p, struct malloc_type *mt) 1970 { 1971 free(p, mt); 1972 } 1973 1974 static paddr_t 1975 dbri_mappage(void *v, void *mem, off_t off, int prot) 1976 { 1977 struct dbri_softc *sc = v;; 1978 int current; 1979 1980 if (off < 0) 1981 return -1; 1982 1983 current = 0; 1984 while ((current < sc->sc_desc_used) && 1985 (sc->sc_desc[current].buf != mem)) 1986 current++; 1987 1988 if (current < sc->sc_desc_used) { 1989 return bus_dmamem_mmap(sc->sc_dmat, 1990 &sc->sc_desc[current].dmaseg, 1, off, prot, BUS_DMA_WAITOK); 1991 } 1992 1993 return -1; 1994 } 1995 1996 static int 1997 dbri_open(void *cookie, int flags) 1998 { 1999 struct dbri_softc *sc = cookie; 2000 2001 dbri_bring_up(sc); 2002 sc->sc_open = 1; 2003 return 0; 2004 } 2005 2006 static void 2007 dbri_close(void *cookie) 2008 { 2009 struct dbri_softc *sc = cookie; 2010 2011 sc->sc_open = 0; 2012 dbri_set_power(sc, 0); 2013 } 2014 2015 static void 2016 dbri_powerhook(int why, void *cookie) 2017 { 2018 struct dbri_softc *sc = cookie; 2019 2020 if (why == sc->sc_pmgrstate) 2021 return; 2022 2023 switch(why) 2024 { 2025 case PWR_SUSPEND: 2026 dbri_set_power(sc, 0); 2027 break; 2028 case PWR_RESUME: 2029 DPRINTF("resume: %d\n", sc->sc_open); 2030 sc->sc_pmgrstate = PWR_RESUME; 2031 if (sc->sc_open == 1) { 2032 dbri_bring_up(sc); 2033 if (sc->sc_playing) { 2034 volatile u_int32_t *cmd; 2035 int s; 2036 2037 s = splaudio(); 2038 cmd = dbri_command_lock(sc); 2039 *(cmd++) = DBRI_CMD(DBRI_COMMAND_SDP, 2040 0, sc->sc_pipe[4].sdp | 2041 DBRI_SDP_VALID_POINTER | 2042 DBRI_SDP_EVERY | DBRI_SDP_CLEAR); 2043 *(cmd++) = sc->sc_dmabase + 2044 dbri_dma_off(desc, 0); 2045 dbri_command_send(sc, cmd); 2046 splx(s); 2047 } 2048 } 2049 break; 2050 default: 2051 return; 2052 } 2053 sc->sc_pmgrstate = why; 2054 } 2055 2056 #endif /* NAUDIO > 0 */ 2057
Indexes created Sat Sep 27 14:09:57 GMT 2025