dbri.c revision 1.16
1 /* $NetBSD: dbri.c,v 1.16 2007/10/19 12:01:10 ad Exp $ */ 2 3 /* 4 * Copyright (C) 1997 Rudolf Koenig (rfkoenig (at) immd4.informatik.uni-erlangen.de) 5 * Copyright (c) 1998, 1999 Brent Baccala (baccala (at) freesoft.org) 6 * Copyright (c) 2001, 2002 Jared D. McNeill <jmcneill (at) netbsd.org> 7 * Copyright (c) 2005, 2007 Michael Lorenz <macallan (at) netbsd.org> 8 * All rights reserved. 9 * 10 * This driver is losely based on a Linux driver written by Rudolf Koenig and 11 * Brent Baccala who kindly gave their permission to use their code in a 12 * BSD-licensed driver. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions 16 * are met: 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in the 21 * documentation and/or other materials provided with the distribution. 22 * 3. All advertising materials mentioning features or use of this software 23 * must display the following acknowledgement: 24 * This product includes software developed by Rudolf Koenig, Brent 25 * Baccala, Jared D. McNeill. 26 * 4. Neither the name of the author nor the names of any contributors may 27 * be used to endorse or promote products derived from this software 28 * without specific prior written permission. 29 * 30 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 31 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 33 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 36 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 37 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 38 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 39 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 40 * SUCH DAMAGE. 41 * 42 */ 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: dbri.c,v 1.16 2007/10/19 12:01:10 ad Exp $"); 46 47 #include "audio.h" 48 #if NAUDIO > 0 49 50 #include <sys/param.h> 51 #include <sys/systm.h> 52 #include <sys/errno.h> 53 #include <sys/device.h> 54 #include <sys/malloc.h> 55 #include <sys/proc.h> 56 #include <sys/kernel.h> 57 58 #include <sys/bus.h> 59 #include <sys/intr.h> 60 61 #include <dev/sbus/sbusvar.h> 62 #include <sparc/sparc/auxreg.h> 63 #include <machine/autoconf.h> 64 65 #include <sys/audioio.h> 66 #include <dev/audio_if.h> 67 #include <dev/auconv.h> 68 69 #include <dev/ic/cs4215reg.h> 70 #include <dev/ic/cs4215var.h> 71 #include <dev/sbus/dbrireg.h> 72 #include <dev/sbus/dbrivar.h> 73 74 #include "opt_sbus_dbri.h" 75 76 #define DBRI_ROM_NAME_PREFIX "SUNW,DBRI" 77 78 #ifdef DBRI_DEBUG 79 # define DPRINTF aprint_normal 80 #else 81 # define DPRINTF while (0) printf 82 #endif 83 84 static const char *dbri_supported[] = { 85 "e", 86 "s3", 87 "" 88 }; 89 90 enum ms { 91 CHImaster, 92 CHIslave 93 }; 94 95 enum io { 96 PIPEinput, 97 PIPEoutput 98 }; 99 100 /* 101 * Function prototypes 102 */ 103 104 /* softc stuff */ 105 static void dbri_attach_sbus(struct device *, struct device *, void *); 106 static int dbri_match_sbus(struct device *, struct cfdata *, void *); 107 108 static void dbri_config_interrupts(struct device *); 109 110 /* interrupt handler */ 111 static int dbri_intr(void *); 112 113 /* supporting subroutines */ 114 static int dbri_init(struct dbri_softc *); 115 static int dbri_reset(struct dbri_softc *); 116 static volatile u_int32_t *dbri_command_lock(struct dbri_softc *); 117 static void dbri_command_send(struct dbri_softc *, volatile u_int32_t *); 118 static void dbri_process_interrupt_buffer(struct dbri_softc *); 119 static void dbri_process_interrupt(struct dbri_softc *, int32_t); 120 121 /* mmcodec subroutines */ 122 static int mmcodec_init(struct dbri_softc *); 123 static void mmcodec_init_data(struct dbri_softc *); 124 static void mmcodec_pipe_init(struct dbri_softc *); 125 static void mmcodec_default(struct dbri_softc *); 126 static void mmcodec_setgain(struct dbri_softc *, int); 127 static int mmcodec_setcontrol(struct dbri_softc *); 128 129 /* chi subroutines */ 130 static void chi_reset(struct dbri_softc *, enum ms, int); 131 132 /* pipe subroutines */ 133 static void pipe_setup(struct dbri_softc *, int, int); 134 static void pipe_reset(struct dbri_softc *, int); 135 static void pipe_receive_fixed(struct dbri_softc *, int, 136 volatile u_int32_t *); 137 static void pipe_transmit_fixed(struct dbri_softc *, int, u_int32_t); 138 139 static void pipe_ts_link(struct dbri_softc *, int, enum io, int, int, int); 140 static int pipe_active(struct dbri_softc *, int); 141 142 /* audio(9) stuff */ 143 static int dbri_query_encoding(void *, struct audio_encoding *); 144 static int dbri_set_params(void *, int, int, struct audio_params *, 145 struct audio_params *,stream_filter_list_t *, stream_filter_list_t *); 146 static int dbri_round_blocksize(void *, int, int, const audio_params_t *); 147 static int dbri_halt_output(void *); 148 static int dbri_halt_input(void *); 149 static int dbri_getdev(void *, struct audio_device *); 150 static int dbri_set_port(void *, mixer_ctrl_t *); 151 static int dbri_get_port(void *, mixer_ctrl_t *); 152 static int dbri_query_devinfo(void *, mixer_devinfo_t *); 153 static size_t dbri_round_buffersize(void *, int, size_t); 154 static int dbri_get_props(void *); 155 static int dbri_open(void *, int); 156 static void dbri_close(void *); 157 158 static void setup_ring_xmit(struct dbri_softc *, int, int, int, int, 159 void (*)(void *), void *); 160 static void setup_ring_recv(struct dbri_softc *, int, int, int, int, 161 void (*)(void *), void *); 162 163 static int dbri_trigger_output(void *, void *, void *, int, 164 void (*)(void *), void *, const struct audio_params *); 165 static int dbri_trigger_input(void *, void *, void *, int, 166 void (*)(void *), void *, const struct audio_params *); 167 168 static void *dbri_malloc(void *, int, size_t, struct malloc_type *, int); 169 static void dbri_free(void *, void *, struct malloc_type *); 170 static paddr_t dbri_mappage(void *, void *, off_t, int); 171 static void dbri_set_power(struct dbri_softc *, int); 172 static void dbri_bring_up(struct dbri_softc *); 173 static void dbri_powerhook(int, void *); 174 175 /* stupid support routines */ 176 static u_int32_t reverse_bytes(u_int32_t, int); 177 178 struct audio_device dbri_device = { 179 "CS4215", 180 "", 181 "dbri" 182 }; 183 184 struct audio_hw_if dbri_hw_if = { 185 dbri_open, 186 dbri_close, 187 NULL, /* drain */ 188 dbri_query_encoding, 189 dbri_set_params, 190 dbri_round_blocksize, 191 NULL, /* commit_settings */ 192 NULL, /* init_output */ 193 NULL, /* init_input */ 194 NULL, /* start_output */ 195 NULL, /* start_input */ 196 dbri_halt_output, 197 dbri_halt_input, 198 NULL, /* speaker_ctl */ 199 dbri_getdev, 200 NULL, /* setfd */ 201 dbri_set_port, 202 dbri_get_port, 203 dbri_query_devinfo, 204 dbri_malloc, 205 dbri_free, 206 dbri_round_buffersize, 207 dbri_mappage, 208 dbri_get_props, 209 dbri_trigger_output, 210 dbri_trigger_input 211 }; 212 213 CFATTACH_DECL(dbri, sizeof(struct dbri_softc), 214 dbri_match_sbus, dbri_attach_sbus, NULL, NULL); 215 216 #define DBRI_NFORMATS 4 217 static const struct audio_format dbri_formats[DBRI_NFORMATS] = { 218 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_SLINEAR_BE, 16, 16, 219 2, AUFMT_STEREO, 8, {8000, 9600, 11025, 16000, 22050, 32000, 44100, 220 48000}}, 221 /* {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_ULAW, 8, 8, 222 2, AUFMT_STEREO, 8, {8000, 9600, 11025, 16000, 22050, 32000, 44100, 223 48000}}, 224 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_ALAW, 8, 8, 225 2, AUFMT_STEREO, 8, {8000, 9600, 11025, 16000, 22050, 32000, 44100, 226 48000}}, 227 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_ULINEAR, 8, 8, 228 2, AUFMT_STEREO, 8, {8000, 9600, 11025, 16000, 22050, 32000, 44100, 229 48000}},*/ 230 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_ULAW, 8, 8, 231 1, AUFMT_MONAURAL, 8, {8000, 9600, 11025, 16000, 22050, 32000, 44100, 232 48000}}, 233 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_ALAW, 8, 8, 234 1, AUFMT_MONAURAL, 8, {8000, 9600, 11025, 16000, 22050, 32000, 44100, 235 48000}}, 236 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_ULINEAR, 8, 8, 237 1, AUFMT_MONAURAL, 8, {8000, 9600, 11025, 16000, 22050, 32000, 44100, 238 48000}}, 239 }; 240 241 enum { 242 DBRI_OUTPUT_CLASS, 243 DBRI_VOL_OUTPUT, 244 DBRI_ENABLE_MONO, 245 DBRI_ENABLE_HEADPHONE, 246 DBRI_ENABLE_LINE, 247 DBRI_MONITOR_CLASS, 248 DBRI_VOL_MONITOR, 249 DBRI_INPUT_CLASS, 250 DBRI_INPUT_GAIN, 251 DBRI_INPUT_SELECT, 252 DBRI_RECORD_CLASS, 253 DBRI_ENUM_LAST 254 }; 255 256 /* 257 * Autoconfig routines 258 */ 259 static int 260 dbri_match_sbus(struct device *parent, struct cfdata *match, void *aux) 261 { 262 struct sbus_attach_args *sa = aux; 263 char *ver; 264 int i; 265 266 if (strncmp(DBRI_ROM_NAME_PREFIX, sa->sa_name, 9)) 267 return (0); 268 269 ver = &sa->sa_name[9]; 270 271 for (i = 0; dbri_supported[i][0] != '\0'; i++) 272 if (strcmp(dbri_supported[i], ver) == 0) 273 return (1); 274 275 return (0); 276 } 277 278 static void 279 dbri_attach_sbus(struct device *parent, struct device *self, void *aux) 280 { 281 struct dbri_softc *sc = (struct dbri_softc *)self; 282 struct sbus_attach_args *sa = aux; 283 bus_space_handle_t ioh; 284 bus_size_t size; 285 int error, rseg, pwr; 286 char *ver = &sa->sa_name[9]; 287 288 sc->sc_iot = sa->sa_bustag; 289 sc->sc_dmat = sa->sa_dmatag; 290 sc->sc_powerstate = 1; 291 292 pwr = prom_getpropint(sa->sa_node,"pwr-on-auxio",0); 293 aprint_normal(": rev %s\n", ver); 294 295 if (pwr) { 296 /* 297 * we can control DBRI power via auxio and we're initially 298 * powered down 299 */ 300 301 sc->sc_have_powerctl = 1; 302 sc->sc_powerstate = 0; 303 dbri_set_power(sc, 1); 304 powerhook_establish(self->dv_xname, dbri_powerhook, sc); 305 } else { 306 /* we can't control power so we're always up */ 307 sc->sc_have_powerctl = 0; 308 sc->sc_powerstate = 1; 309 } 310 311 if (sa->sa_npromvaddrs) 312 ioh = (bus_space_handle_t)sa->sa_promvaddrs[0]; 313 else { 314 if (sbus_bus_map(sa->sa_bustag, sa->sa_slot, 315 sa->sa_offset, sa->sa_size, 316 BUS_SPACE_MAP_LINEAR, /*0,*/ &ioh) != 0) { 317 aprint_error("%s @ sbus: cannot map registers\n", 318 self->dv_xname); 319 return; 320 } 321 } 322 323 sc->sc_ioh = ioh; 324 325 size = sizeof(struct dbri_dma); 326 327 /* get a DMA handle */ 328 if ((error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, 329 BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) { 330 aprint_error("%s: DMA map create error %d\n", self->dv_xname, 331 error); 332 return; 333 } 334 335 /* allocate DMA buffer */ 336 if ((error = bus_dmamem_alloc(sc->sc_dmat, size, 0, 0, &sc->sc_dmaseg, 337 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 338 aprint_error("%s: DMA buffer alloc error %d\n", 339 self->dv_xname, error); 340 return; 341 } 342 343 /* map DMA buffer into CPU addressable space */ 344 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_dmaseg, rseg, size, 345 &sc->sc_membase, 346 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 347 aprint_error("%s: DMA buffer map error %d\n", 348 self->dv_xname, error); 349 return; 350 } 351 352 /* load the buffer */ 353 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, 354 sc->sc_membase, size, NULL, 355 BUS_DMA_NOWAIT)) != 0) { 356 aprint_error("%s: DMA buffer map load error %d\n", 357 self->dv_xname, error); 358 bus_dmamem_unmap(sc->sc_dmat, sc->sc_membase, size); 359 bus_dmamem_free(sc->sc_dmat, &sc->sc_dmaseg, rseg); 360 return; 361 } 362 363 /* map the registers into memory */ 364 365 /* kernel virtual address of DMA buffer */ 366 sc->sc_dma = (struct dbri_dma *)sc->sc_membase; 367 /* physical address of DMA buffer */ 368 sc->sc_dmabase = sc->sc_dmamap->dm_segs[0].ds_addr; 369 sc->sc_bufsiz = size; 370 371 sbus_establish(&sc->sc_sd, &sc->sc_dev); 372 373 bus_intr_establish(sa->sa_bustag, sa->sa_pri, IPL_AUDIO, dbri_intr, 374 sc); 375 376 sc->sc_locked = 0; 377 sc->sc_desc_used = 0; 378 sc->sc_refcount = 0; 379 sc->sc_playing = 0; 380 sc->sc_recording = 0; 381 sc->sc_pmgrstate = PWR_RESUME; 382 config_interrupts(self, &dbri_config_interrupts); 383 384 return; 385 } 386 387 /* 388 * lowlevel routine to switch power for the DBRI chip 389 */ 390 static void 391 dbri_set_power(struct dbri_softc *sc, int state) 392 { 393 int s; 394 395 if (sc->sc_have_powerctl == 0) 396 return; 397 if (sc->sc_powerstate == state) 398 return; 399 400 if (state) { 401 DPRINTF("%s: waiting to power up... ", sc->sc_dev.dv_xname); 402 s = splhigh(); 403 *AUXIO4M_REG |= (AUXIO4M_MMX); 404 splx(s); 405 delay(10000); 406 DPRINTF("done (%02x)\n", *AUXIO4M_REG); 407 } else { 408 DPRINTF("%s: powering down\n", sc->sc_dev.dv_xname); 409 s = splhigh(); 410 *AUXIO4M_REG &= ~AUXIO4M_MMX; 411 splx(s); 412 DPRINTF("done (%02x})\n", *AUXIO4M_REG); 413 } 414 sc->sc_powerstate = state; 415 } 416 417 /* 418 * power up and re-initialize the chip 419 */ 420 static void 421 dbri_bring_up(struct dbri_softc *sc) 422 { 423 424 if (sc->sc_have_powerctl == 0) 425 return; 426 427 if (sc->sc_powerstate == 1) 428 return; 429 430 /* ok, we really need to do something */ 431 dbri_set_power(sc, 1); 432 433 /* 434 * re-initialize the chip but skip all the probing, don't overwrite 435 * any other settings either 436 */ 437 dbri_init(sc); 438 mmcodec_setgain(sc, 1); 439 mmcodec_pipe_init(sc); 440 mmcodec_init_data(sc); 441 mmcodec_setgain(sc, 0); 442 } 443 444 static void 445 dbri_config_interrupts(struct device *dev) 446 { 447 struct dbri_softc *sc = (struct dbri_softc *)dev; 448 449 dbri_init(sc); 450 mmcodec_init(sc); 451 452 /* Attach ourselves to the high level audio interface */ 453 audio_attach_mi(&dbri_hw_if, sc, &sc->sc_dev); 454 455 /* power down until open() */ 456 dbri_set_power(sc, 0); 457 return; 458 } 459 460 static int 461 dbri_intr(void *hdl) 462 { 463 struct dbri_softc *sc = hdl; 464 bus_space_tag_t iot = sc->sc_iot; 465 bus_space_handle_t ioh = sc->sc_ioh; 466 int x; 467 468 /* clear interrupt */ 469 x = bus_space_read_4(iot, ioh, DBRI_REG1); 470 if (x & (DBRI_MRR | DBRI_MLE | DBRI_LBG | DBRI_MBE)) { 471 u_int32_t tmp; 472 473 if (x & DBRI_MRR) 474 aprint_debug("%s: multiple ack error on sbus\n", 475 sc->sc_dev.dv_xname); 476 if (x & DBRI_MLE) 477 aprint_debug("%s: multiple late error on sbus\n", 478 sc->sc_dev.dv_xname); 479 if (x & DBRI_LBG) 480 aprint_debug("%s: lost bus grant on sbus\n", 481 sc->sc_dev.dv_xname); 482 if (x & DBRI_MBE) 483 aprint_debug("%s: burst error on sbus\n", 484 sc->sc_dev.dv_xname); 485 486 /* 487 * Some of these errors disable the chip's circuitry. 488 * Re-enable the circuitry and keep on going. 489 */ 490 491 tmp = bus_space_read_4(iot, ioh, DBRI_REG0); 492 tmp &= ~(DBRI_DISABLE_MASTER); 493 bus_space_write_4(iot, ioh, DBRI_REG0, tmp); 494 } 495 496 #if 0 497 if (!x & 1) /* XXX: DBRI_INTR_REQ */ 498 return (1); 499 #endif 500 501 dbri_process_interrupt_buffer(sc); 502 503 return (1); 504 } 505 506 static int 507 dbri_init(struct dbri_softc *sc) 508 { 509 bus_space_tag_t iot = sc->sc_iot; 510 bus_space_handle_t ioh = sc->sc_ioh; 511 u_int32_t reg; 512 volatile u_int32_t *cmd; 513 bus_addr_t dmaaddr; 514 int n; 515 516 dbri_reset(sc); 517 518 cmd = dbri_command_lock(sc); 519 520 /* XXX: Initialize interrupt ring buffer */ 521 sc->sc_dma->intr[0] = (u_int32_t)sc->sc_dmabase + dbri_dma_off(intr, 0); 522 sc->sc_irqp = 1; 523 524 /* Initialize pipes */ 525 for (n = 0; n < DBRI_PIPE_MAX; n++) 526 sc->sc_pipe[n].desc = sc->sc_pipe[n].next = -1; 527 528 for (n = 1; n < DBRI_INT_BLOCKS; n++) { 529 sc->sc_dma->intr[n] = 0; 530 } 531 532 /* Disable all SBus bursts */ 533 /* XXX 16 byte bursts cause errors, the rest works */ 534 reg = bus_space_read_4(iot, ioh, DBRI_REG0); 535 536 /*reg &= ~(DBRI_BURST_4 | DBRI_BURST_8 | DBRI_BURST_16);*/ 537 reg |= (DBRI_BURST_4 | DBRI_BURST_8); 538 bus_space_write_4(iot, ioh, DBRI_REG0, reg); 539 540 /* setup interrupt queue */ 541 dmaaddr = (u_int32_t)sc->sc_dmabase + dbri_dma_off(intr, 0); 542 *(cmd++) = DBRI_CMD(DBRI_COMMAND_IIQ, 0, 0); 543 *(cmd++) = dmaaddr; 544 545 dbri_command_send(sc, cmd); 546 return (0); 547 } 548 549 static int 550 dbri_reset(struct dbri_softc *sc) 551 { 552 int bail = 0; 553 554 bus_space_tag_t iot = sc->sc_iot; 555 bus_space_handle_t ioh = sc->sc_ioh; 556 557 bus_space_write_4(iot, ioh, DBRI_REG0, DBRI_SOFT_RESET); 558 while ((bus_space_read_4(iot, ioh, DBRI_REG0) & DBRI_SOFT_RESET) && 559 (bail < 100000)) { 560 bail++; 561 delay(10); 562 } 563 if (bail == 100000) aprint_error("%s: reset timed out\n", 564 sc->sc_dev.dv_xname); 565 return (0); 566 } 567 568 static volatile u_int32_t * 569 dbri_command_lock(struct dbri_softc *sc) 570 { 571 572 if (sc->sc_locked) 573 aprint_debug("%s: command buffer locked\n", 574 sc->sc_dev.dv_xname); 575 576 sc->sc_locked++; 577 578 return (&sc->sc_dma->command[0]); 579 } 580 581 static void 582 dbri_command_send(struct dbri_softc *sc, volatile u_int32_t *cmd) 583 { 584 bus_space_handle_t ioh = sc->sc_ioh; 585 bus_space_tag_t iot = sc->sc_iot; 586 int maxloops = 1000000; 587 int x; 588 589 x = splaudio(); 590 591 sc->sc_locked--; 592 593 if (sc->sc_locked != 0) { 594 aprint_error("%s: command buffer improperly locked\n", 595 sc->sc_dev.dv_xname); 596 } else if ((cmd - &sc->sc_dma->command[0]) >= DBRI_NUM_COMMANDS - 1) { 597 aprint_error("%s: command buffer overflow\n", 598 sc->sc_dev.dv_xname); 599 } else { 600 *(cmd++) = DBRI_CMD(DBRI_COMMAND_PAUSE, 0, 0); 601 *(cmd++) = DBRI_CMD(DBRI_COMMAND_WAIT, 1, 0); 602 sc->sc_waitseen = 0; 603 bus_space_write_4(iot, ioh, DBRI_REG8, sc->sc_dmabase); 604 while ((--maxloops) > 0 && 605 (bus_space_read_4(iot, ioh, DBRI_REG0) 606 & DBRI_COMMAND_VALID)) { 607 bus_space_barrier(iot, ioh, DBRI_REG0, 4, 608 BUS_SPACE_BARRIER_READ); 609 delay(1000); 610 } 611 612 if (maxloops == 0) { 613 aprint_error( 614 "%s: chip never completed command buffer\n", 615 sc->sc_dev.dv_xname); 616 } else { 617 618 DPRINTF("%s: command completed\n", 619 sc->sc_dev.dv_xname); 620 621 while ((--maxloops) > 0 && (!sc->sc_waitseen)) 622 dbri_process_interrupt_buffer(sc); 623 if (maxloops == 0) { 624 aprint_error("%s: chip never acked WAIT\n", 625 sc->sc_dev.dv_xname); 626 } 627 } 628 } 629 630 splx(x); 631 632 return; 633 } 634 635 static void 636 dbri_process_interrupt_buffer(struct dbri_softc *sc) 637 { 638 int32_t i; 639 640 while ((i = sc->sc_dma->intr[sc->sc_irqp]) != 0) { 641 sc->sc_dma->intr[sc->sc_irqp] = 0; 642 sc->sc_irqp++; 643 644 if (sc->sc_irqp == DBRI_INT_BLOCKS) 645 sc->sc_irqp = 1; 646 else if ((sc->sc_irqp & (DBRI_INT_BLOCKS - 1)) == 0) 647 sc->sc_irqp++; 648 649 dbri_process_interrupt(sc, i); 650 } 651 652 return; 653 } 654 655 static void 656 dbri_process_interrupt(struct dbri_softc *sc, int32_t i) 657 { 658 #if 0 659 const int liu_states[] = { 1, 0, 8, 3, 4, 5, 6, 7 }; 660 #endif 661 int val = DBRI_INTR_GETVAL(i); 662 int channel = DBRI_INTR_GETCHAN(i); 663 int command = DBRI_INTR_GETCMD(i); 664 int code = DBRI_INTR_GETCODE(i); 665 #if 0 666 int rval = DBRI_INTR_GETRVAL(i); 667 #endif 668 if (channel == DBRI_INTR_CMD && command == DBRI_COMMAND_WAIT) 669 sc->sc_waitseen++; 670 671 switch (code) { 672 case DBRI_INTR_XCMP: /* transmission complete */ 673 { 674 int td; 675 struct dbri_desc *dd; 676 677 td = sc->sc_pipe[channel].desc; 678 dd = &sc->sc_desc[td]; 679 680 if (dd->callback != NULL) { 681 dd->callback(dd->callback_args); 682 } else 683 DPRINTF("!"); 684 break; 685 } 686 case DBRI_INTR_FXDT: /* fixed data change */ 687 DPRINTF("dbri_intr: Fixed data change (%d: %x)\n", channel, 688 val); 689 #if 0 690 printf("reg: %08x\n", sc->sc_mm.status); 691 #endif 692 if (sc->sc_pipe[channel].sdp & DBRI_SDP_MSB) 693 val = reverse_bytes(val, sc->sc_pipe[channel].length); 694 if (sc->sc_pipe[channel].prec) 695 *(sc->sc_pipe[channel].prec) = val; 696 #ifndef DBRI_SPIN 697 DPRINTF("%s: wakeup %p\n", sc->sc_dev.dv_xname, sc); 698 wakeup(sc); 699 #endif 700 break; 701 case DBRI_INTR_SBRI: 702 DPRINTF("dbri_intr: SBRI\n"); 703 break; 704 case DBRI_INTR_BRDY: 705 { 706 int td; 707 struct dbri_desc *dd; 708 709 td = sc->sc_pipe[channel].desc; 710 dd = &sc->sc_desc[td]; 711 712 if (dd->callback != NULL) 713 dd->callback(dd->callback_args); 714 break; 715 } 716 case DBRI_INTR_UNDR: 717 { 718 volatile u_int32_t *cmd; 719 int td = sc->sc_pipe[channel].desc; 720 721 DPRINTF("%s: DBRI_INTR_UNDR\n", sc->sc_dev.dv_xname); 722 723 sc->sc_dma->xmit[td].status = 0; 724 725 cmd = dbri_command_lock(sc); 726 *(cmd++) = DBRI_CMD(DBRI_COMMAND_SDP, 0, 727 sc->sc_pipe[channel].sdp | 728 DBRI_SDP_VALID_POINTER | 729 DBRI_SDP_CLEAR | 730 DBRI_SDP_2SAME); 731 *(cmd++) = sc->sc_dmabase + dbri_dma_off(xmit, td); 732 dbri_command_send(sc, cmd); 733 break; 734 } 735 case DBRI_INTR_CMDI: 736 DPRINTF("ok"); 737 break; 738 default: 739 740 aprint_error("%s: unknown interrupt code %d\n", 741 sc->sc_dev.dv_xname, code); 742 break; 743 } 744 745 return; 746 } 747 748 /* 749 * mmcodec stuff 750 */ 751 752 static int 753 mmcodec_init(struct dbri_softc *sc) 754 { 755 bus_space_handle_t ioh = sc->sc_ioh; 756 bus_space_tag_t iot = sc->sc_iot; 757 u_int32_t reg2; 758 int bail; 759 760 reg2 = bus_space_read_4(iot, ioh, DBRI_REG2); 761 DPRINTF("mmcodec_init: PIO reads %x\n", reg2); 762 763 if (reg2 & DBRI_PIO2) { 764 aprint_normal("%s: onboard CS4215 detected\n", 765 sc->sc_dev.dv_xname); 766 sc->sc_mm.onboard = 1; 767 } 768 769 if (reg2 & DBRI_PIO0) { 770 aprint_normal("%s: speakerbox detected\n", 771 sc->sc_dev.dv_xname); 772 bus_space_write_4(iot, ioh, DBRI_REG2, DBRI_PIO2_ENABLE); 773 sc->sc_mm.onboard = 0; 774 } 775 776 if ((reg2 & DBRI_PIO2) && (reg2 & DBRI_PIO0)) { 777 aprint_normal("%s: using speakerbox\n", 778 sc->sc_dev.dv_xname); 779 bus_space_write_4(iot, ioh, DBRI_REG2, DBRI_PIO2_ENABLE); 780 sc->sc_mm.onboard = 0; 781 } 782 783 if (!(reg2 & (DBRI_PIO0|DBRI_PIO2))) { 784 aprint_normal("%s: no mmcodec found\n", sc->sc_dev.dv_xname); 785 return -1; 786 } 787 788 sc->sc_version = 0xff; 789 790 mmcodec_pipe_init(sc); 791 mmcodec_default(sc); 792 793 sc->sc_mm.offset = sc->sc_mm.onboard ? 0 : 8; 794 795 /* 796 * mmcodec_setcontrol() sometimes fails right after powerup 797 * so we just try again until we either get a useful response or run 798 * out of time 799 */ 800 bail = 0; 801 while (mmcodec_setcontrol(sc) == -1 || sc->sc_version == 0xff) { 802 803 bail++; 804 if (bail > 100) { 805 DPRINTF("%s: cs4215 probe failed at offset %d\n", 806 sc->sc_dev.dv_xname, sc->sc_mm.offset); 807 return (-1); 808 } 809 delay(10000); 810 } 811 812 aprint_normal("%s: cs4215 rev %c found at offset %d\n", 813 sc->sc_dev.dv_xname, 0x43 + (sc->sc_version & 0xf), sc->sc_mm.offset); 814 815 /* set some sane defaults for mmcodec_init_data */ 816 sc->sc_params.channels = 2; 817 sc->sc_params.precision = 16; 818 819 mmcodec_init_data(sc); 820 821 return (0); 822 } 823 824 static void 825 mmcodec_init_data(struct dbri_softc *sc) 826 { 827 bus_space_tag_t iot = sc->sc_iot; 828 bus_space_handle_t ioh = sc->sc_ioh; 829 u_int32_t tmp; 830 int data_width; 831 832 tmp = bus_space_read_4(iot, ioh, DBRI_REG0); 833 tmp &= ~(DBRI_CHI_ACTIVATE); /* disable CHI */ 834 bus_space_write_4(iot, ioh, DBRI_REG0, tmp); 835 836 /* switch CS4215 to data mode - set PIO3 to 1 */ 837 tmp = DBRI_PIO_ENABLE_ALL | DBRI_PIO1 | DBRI_PIO3; 838 839 /* XXX */ 840 tmp |= (sc->sc_mm.onboard ? DBRI_PIO0 : DBRI_PIO2); 841 842 bus_space_write_4(iot, ioh, DBRI_REG2, tmp); 843 chi_reset(sc, CHIslave, 128); 844 845 data_width = sc->sc_params.channels * sc->sc_params.precision; 846 847 if ((data_width != 32) && (data_width != 8)) 848 aprint_error("%s: data_width is %d\n", __func__, data_width); 849 850 pipe_ts_link(sc, 20, PIPEoutput, 16, 32, sc->sc_mm.offset + 32); 851 pipe_ts_link(sc, 4, PIPEoutput, 16, data_width, sc->sc_mm.offset); 852 pipe_ts_link(sc, 6, PIPEinput, 16, data_width, sc->sc_mm.offset); 853 pipe_ts_link(sc, 21, PIPEinput, 16, 32, sc->sc_mm.offset + 32); 854 855 pipe_receive_fixed(sc, 21, &sc->sc_mm.status); 856 857 mmcodec_setgain(sc, 0); 858 859 tmp = bus_space_read_4(iot, ioh, DBRI_REG0); 860 tmp |= DBRI_CHI_ACTIVATE; 861 bus_space_write_4(iot, ioh, DBRI_REG0, tmp); 862 863 return; 864 } 865 866 static void 867 mmcodec_pipe_init(struct dbri_softc *sc) 868 { 869 870 pipe_setup(sc, 4, DBRI_SDP_MEM | DBRI_SDP_TO_SER | DBRI_SDP_MSB); 871 pipe_setup(sc, 20, DBRI_SDP_FIXED | DBRI_SDP_TO_SER | DBRI_SDP_MSB); 872 pipe_setup(sc, 6, DBRI_SDP_MEM | DBRI_SDP_FROM_SER | DBRI_SDP_MSB); 873 pipe_setup(sc, 21, DBRI_SDP_FIXED | DBRI_SDP_FROM_SER | DBRI_SDP_MSB); 874 875 pipe_setup(sc, 17, DBRI_SDP_FIXED | DBRI_SDP_TO_SER | DBRI_SDP_MSB); 876 pipe_setup(sc, 18, DBRI_SDP_FIXED | DBRI_SDP_FROM_SER | DBRI_SDP_MSB); 877 pipe_setup(sc, 19, DBRI_SDP_FIXED | DBRI_SDP_FROM_SER | DBRI_SDP_MSB); 878 879 sc->sc_mm.status = 0; 880 881 pipe_receive_fixed(sc, 18, &sc->sc_mm.status); 882 pipe_receive_fixed(sc, 19, &sc->sc_mm.version); 883 884 return; 885 } 886 887 static void 888 mmcodec_default(struct dbri_softc *sc) 889 { 890 struct cs4215_state *mm = &sc->sc_mm; 891 892 /* 893 * no action, memory resetting only 894 * 895 * data time slots 5-8 896 * speaker, line and headphone enable. set gain to half. 897 * input is line 898 */ 899 mm->d.bdata[0] = sc->sc_latt = 0x20 | CS4215_HE | CS4215_LE; 900 mm->d.bdata[1] = sc->sc_ratt = 0x20 | CS4215_SE; 901 sc->sc_linp = 128; 902 sc->sc_rinp = 128; 903 sc->sc_monitor = 0; 904 sc->sc_input = 1; /* line */ 905 mm->d.bdata[2] = (CS4215_LG((sc->sc_linp >> 4)) & 0x0f) | 906 ((sc->sc_input == 2) ? CS4215_IS : 0) | CS4215_PIO0 | CS4215_PIO1; 907 mm->d.bdata[3] = (CS4215_RG((sc->sc_rinp >> 4) & 0x0f)) | 908 CS4215_MA(15 - ((sc->sc_monitor >> 4) & 0x0f)); 909 910 911 /* 912 * control time slots 1-4 913 * 914 * 0: default I/O voltage scale 915 * 1: 8 bit ulaw, 8kHz, mono, high pass filter disabled 916 * 2: serial enable, CHI master, 128 bits per frame, clock 1 917 * 3: tests disabled 918 */ 919 mm->c.bcontrol[0] = CS4215_RSRVD_1 | CS4215_MLB; 920 mm->c.bcontrol[1] = CS4215_DFR_ULAW | CS4215_FREQ[0].csval; 921 mm->c.bcontrol[2] = CS4215_XCLK | CS4215_BSEL_128 | CS4215_FREQ[0].xtal; 922 mm->c.bcontrol[3] = 0; 923 924 return; 925 } 926 927 static void 928 mmcodec_setgain(struct dbri_softc *sc, int mute) 929 { 930 if (mute) { 931 /* disable all outputs, max. attenuation */ 932 sc->sc_mm.d.bdata[0] = sc->sc_latt | 63; 933 sc->sc_mm.d.bdata[1] = sc->sc_ratt | 63; 934 } else { 935 936 sc->sc_mm.d.bdata[0] = sc->sc_latt; 937 sc->sc_mm.d.bdata[1] = sc->sc_ratt; 938 } 939 940 /* input stuff */ 941 sc->sc_mm.d.bdata[2] = CS4215_LG((sc->sc_linp >> 4) & 0x0f) | 942 ((sc->sc_input == 2) ? CS4215_IS : 0) | CS4215_PIO0 | CS4215_PIO1; 943 sc->sc_mm.d.bdata[3] = (CS4215_RG((sc->sc_rinp >> 4)) & 0x0f) | 944 (CS4215_MA(15 - ((sc->sc_monitor >> 4) & 0x0f))); 945 946 if (sc->sc_powerstate == 0) 947 return; 948 pipe_transmit_fixed(sc, 20, sc->sc_mm.d.ldata); 949 950 DPRINTF("mmcodec_setgain: %08x\n", sc->sc_mm.d.ldata); 951 /* give the chip some time to execute the command */ 952 delay(250); 953 954 return; 955 } 956 957 static int 958 mmcodec_setcontrol(struct dbri_softc *sc) 959 { 960 bus_space_tag_t iot = sc->sc_iot; 961 bus_space_handle_t ioh = sc->sc_ioh; 962 u_int32_t val; 963 u_int32_t tmp; 964 int bail = 0; 965 #if DBRI_SPIN 966 int i; 967 #endif 968 969 /* 970 * Temporarily mute outputs and wait 125 us to make sure that it 971 * happens. This avoids clicking noises. 972 */ 973 mmcodec_setgain(sc, 1); 974 delay(125); 975 976 bus_space_write_4(iot, ioh, DBRI_REG2, 0); 977 delay(125); 978 979 /* enable control mode */ 980 val = DBRI_PIO_ENABLE_ALL | DBRI_PIO1; /* was PIO1 */ 981 982 /* XXX */ 983 val |= (sc->sc_mm.onboard ? DBRI_PIO0 : DBRI_PIO2); 984 985 bus_space_write_4(iot, ioh, DBRI_REG2, val); 986 987 delay(34); 988 989 /* 990 * in control mode, the cs4215 is the slave device, so the 991 * DBRI must act as the CHI master. 992 * 993 * in data mode, the cs4215 must be the CHI master to insure 994 * that the data stream is in sync with its codec 995 */ 996 tmp = bus_space_read_4(iot, ioh, DBRI_REG0); 997 tmp &= ~DBRI_COMMAND_CHI; 998 bus_space_write_4(iot, ioh, DBRI_REG0, tmp); 999 1000 chi_reset(sc, CHImaster, 128); 1001 1002 /* control mode */ 1003 pipe_ts_link(sc, 17, PIPEoutput, 16, 32, sc->sc_mm.offset); 1004 pipe_ts_link(sc, 18, PIPEinput, 16, 8, sc->sc_mm.offset); 1005 pipe_ts_link(sc, 19, PIPEinput, 16, 8, sc->sc_mm.offset + 48); 1006 1007 /* wait for the chip to echo back CLB as zero */ 1008 sc->sc_mm.c.bcontrol[0] &= ~CS4215_CLB; 1009 pipe_transmit_fixed(sc, 17, sc->sc_mm.c.lcontrol); 1010 1011 tmp = bus_space_read_4(iot, ioh, DBRI_REG0); 1012 tmp |= DBRI_CHI_ACTIVATE; 1013 bus_space_write_4(iot, ioh, DBRI_REG0, tmp); 1014 1015 #if DBRI_SPIN 1016 i = 1024; 1017 while (((sc->sc_mm.status & 0xe4) != 0x20) && --i) { 1018 delay(125); 1019 } 1020 1021 if (i == 0) { 1022 DPRINTF("%s: cs4215 didn't respond to CLB (0x%02x)\n", 1023 sc->sc_dev.dv_xname, sc->sc_mm.status); 1024 return (-1); 1025 } 1026 #else 1027 while (((sc->sc_mm.status & 0xe4) != 0x20) && (bail < 10)) { 1028 DPRINTF("%s: tsleep %p\n", sc->sc_dev.dv_xname, sc); 1029 tsleep(sc, PCATCH | PZERO, "dbrifxdt", hz); 1030 bail++; 1031 } 1032 #endif 1033 if (bail >= 10) { 1034 DPRINTF("%s: switching to control mode timed out (%x %x)\n", 1035 sc->sc_dev.dv_xname, sc->sc_mm.status, 1036 bus_space_read_4(iot, ioh, DBRI_REG2)); 1037 return -1; 1038 } 1039 1040 /* copy the version information before it becomes unreadable again */ 1041 sc->sc_version = sc->sc_mm.version; 1042 1043 /* terminate cs4215 control mode */ 1044 sc->sc_mm.c.bcontrol[0] |= CS4215_CLB; 1045 pipe_transmit_fixed(sc, 17, sc->sc_mm.c.lcontrol); 1046 1047 /* two frames of control info @ 8kHz frame rate = 250us delay */ 1048 delay(250); 1049 1050 mmcodec_setgain(sc, 0); 1051 1052 return (0); 1053 1054 } 1055 1056 /* 1057 * CHI combo 1058 */ 1059 static void 1060 chi_reset(struct dbri_softc *sc, enum ms ms, int bpf) 1061 { 1062 volatile u_int32_t *cmd; 1063 int val; 1064 int clockrate, divisor; 1065 1066 cmd = dbri_command_lock(sc); 1067 1068 /* set CHI anchor: pipe 16 */ 1069 val = DBRI_DTS_VI | DBRI_DTS_INS | DBRI_DTS_PRVIN(16) | DBRI_PIPE(16); 1070 *(cmd++) = DBRI_CMD(DBRI_COMMAND_DTS, 0, val); 1071 *(cmd++) = DBRI_TS_ANCHOR | DBRI_TS_NEXT(16); 1072 *(cmd++) = 0; 1073 1074 val = DBRI_DTS_VO | DBRI_DTS_INS | DBRI_DTS_PRVOUT(16) | DBRI_PIPE(16); 1075 *(cmd++) = DBRI_CMD(DBRI_COMMAND_DTS, 0, val); 1076 *(cmd++) = 0; 1077 *(cmd++) = DBRI_TS_ANCHOR | DBRI_TS_NEXT(16); 1078 1079 sc->sc_pipe[16].sdp = 1; 1080 sc->sc_pipe[16].next = 16; 1081 sc->sc_chi_pipe_in = 16; 1082 sc->sc_chi_pipe_out = 16; 1083 1084 switch (ms) { 1085 case CHIslave: 1086 *(cmd++) = DBRI_CMD(DBRI_COMMAND_CHI, 0, DBRI_CHI_CHICM(0)); 1087 break; 1088 case CHImaster: 1089 clockrate = bpf * 8; 1090 divisor = 12288 / clockrate; 1091 1092 if (divisor > 255 || divisor * clockrate != 12288) 1093 aprint_error("%s: illegal bits-per-frame %d\n", 1094 sc->sc_dev.dv_xname, bpf); 1095 1096 *(cmd++) = DBRI_CMD(DBRI_COMMAND_CHI, 0, 1097 DBRI_CHI_CHICM(divisor) | DBRI_CHI_FD | DBRI_CHI_BPF(bpf)); 1098 break; 1099 default: 1100 aprint_error("%s: unknown value for ms!\n", 1101 sc->sc_dev.dv_xname); 1102 break; 1103 } 1104 1105 sc->sc_chi_bpf = bpf; 1106 1107 /* CHI data mode */ 1108 *(cmd++) = DBRI_CMD(DBRI_COMMAND_PAUSE, 0, 0); 1109 *(cmd++) = DBRI_CMD(DBRI_COMMAND_CDM, 0, 1110 DBRI_CDM_XCE | DBRI_CDM_XEN | DBRI_CDM_REN); 1111 1112 dbri_command_send(sc, cmd); 1113 1114 return; 1115 } 1116 1117 /* 1118 * pipe stuff 1119 */ 1120 static void 1121 pipe_setup(struct dbri_softc *sc, int pipe, int sdp) 1122 { 1123 DPRINTF("pipe setup: %d\n", pipe); 1124 if (pipe < 0 || pipe >= DBRI_PIPE_MAX) { 1125 aprint_error("%s: illegal pipe number %d\n", 1126 sc->sc_dev.dv_xname, pipe); 1127 return; 1128 } 1129 1130 if ((sdp & 0xf800) != sdp) 1131 aprint_error("%s: strange SDP value %d\n", sc->sc_dev.dv_xname, 1132 sdp); 1133 1134 if (DBRI_SDP_MODE(sdp) == DBRI_SDP_FIXED && 1135 !(sdp & DBRI_SDP_TO_SER)) 1136 sdp |= DBRI_SDP_CHANGE; 1137 1138 sdp |= DBRI_PIPE(pipe); 1139 1140 sc->sc_pipe[pipe].sdp = sdp; 1141 sc->sc_pipe[pipe].desc = -1; 1142 1143 pipe_reset(sc, pipe); 1144 1145 return; 1146 } 1147 1148 static void 1149 pipe_reset(struct dbri_softc *sc, int pipe) 1150 { 1151 struct dbri_desc *dd; 1152 int sdp; 1153 int desc; 1154 volatile u_int32_t *cmd; 1155 1156 if (pipe < 0 || pipe >= DBRI_PIPE_MAX) { 1157 aprint_error("%s: illegal pipe number %d\n", 1158 sc->sc_dev.dv_xname, pipe); 1159 return; 1160 } 1161 1162 sdp = sc->sc_pipe[pipe].sdp; 1163 if (sdp == 0) { 1164 aprint_error("%s: can not reset uninitialized pipe %d\n", 1165 sc->sc_dev.dv_xname, pipe); 1166 return; 1167 } 1168 1169 cmd = dbri_command_lock(sc); 1170 *(cmd++) = DBRI_CMD(DBRI_COMMAND_SDP, 0, 1171 sdp | DBRI_SDP_CLEAR | DBRI_SDP_VALID_POINTER); 1172 *(cmd++) = 0; 1173 dbri_command_send(sc, cmd); 1174 1175 desc = sc->sc_pipe[pipe].desc; 1176 1177 dd = &sc->sc_desc[desc]; 1178 1179 dd->busy = 0; 1180 1181 #if 0 1182 if (dd->callback) 1183 (*dd->callback)(dd->callback_args); 1184 #endif 1185 1186 sc->sc_pipe[pipe].desc = -1; 1187 1188 return; 1189 } 1190 1191 static void 1192 pipe_receive_fixed(struct dbri_softc *sc, int pipe, volatile u_int32_t *prec) 1193 { 1194 1195 if (pipe < DBRI_PIPE_MAX / 2 || pipe >= DBRI_PIPE_MAX) { 1196 aprint_error("%s: illegal pipe number %d\n", 1197 sc->sc_dev.dv_xname, pipe); 1198 return; 1199 } 1200 1201 if (DBRI_SDP_MODE(sc->sc_pipe[pipe].sdp) != DBRI_SDP_FIXED) { 1202 aprint_error("%s: non-fixed pipe %d\n", sc->sc_dev.dv_xname, 1203 pipe); 1204 return; 1205 } 1206 1207 if (sc->sc_pipe[pipe].sdp & DBRI_SDP_TO_SER) { 1208 aprint_error("%s: can not receive on transmit pipe %d\b", 1209 sc->sc_dev.dv_xname, pipe); 1210 return; 1211 } 1212 1213 sc->sc_pipe[pipe].prec = prec; 1214 1215 return; 1216 } 1217 1218 static void 1219 pipe_transmit_fixed(struct dbri_softc *sc, int pipe, u_int32_t data) 1220 { 1221 volatile u_int32_t *cmd; 1222 1223 if (pipe < DBRI_PIPE_MAX / 2 || pipe >= DBRI_PIPE_MAX) { 1224 aprint_error("%s: illegal pipe number %d\n", 1225 sc->sc_dev.dv_xname, pipe); 1226 return; 1227 } 1228 1229 if (DBRI_SDP_MODE(sc->sc_pipe[pipe].sdp) == 0) { 1230 aprint_error("%s: uninitialized pipe %d\n", 1231 sc->sc_dev.dv_xname, pipe); 1232 return; 1233 } 1234 1235 if (DBRI_SDP_MODE(sc->sc_pipe[pipe].sdp) != DBRI_SDP_FIXED) { 1236 aprint_error("%s: non-fixed pipe %d\n", sc->sc_dev.dv_xname, 1237 pipe); 1238 return; 1239 } 1240 1241 if (!(sc->sc_pipe[pipe].sdp & DBRI_SDP_TO_SER)) { 1242 aprint_error("%s: called on receive pipe %d\n", 1243 sc->sc_dev.dv_xname, pipe); 1244 return; 1245 } 1246 1247 if (sc->sc_pipe[pipe].sdp & DBRI_SDP_MSB) 1248 data = reverse_bytes(data, sc->sc_pipe[pipe].length); 1249 1250 cmd = dbri_command_lock(sc); 1251 *(cmd++) = DBRI_CMD(DBRI_COMMAND_SSP, 0, pipe); 1252 *(cmd++) = data; 1253 1254 dbri_command_send(sc, cmd); 1255 1256 return; 1257 } 1258 1259 static void 1260 setup_ring_xmit(struct dbri_softc *sc, int pipe, int which, int num, int blksz, 1261 void (*callback)(void *), void *callback_args) 1262 { 1263 volatile u_int32_t *cmd; 1264 int x, i; 1265 int td; 1266 int td_first, td_last; 1267 bus_addr_t dmabuf, dmabase; 1268 struct dbri_desc *dd = &sc->sc_desc[which]; 1269 1270 switch (pipe) { 1271 case 4: 1272 /* output, offset 0 */ 1273 break; 1274 default: 1275 aprint_error("%s: illegal pipe number (%d)\n", 1276 __func__, pipe); 1277 return; 1278 } 1279 1280 td = 0; 1281 td_first = td_last = -1; 1282 1283 if (sc->sc_pipe[pipe].sdp == 0) { 1284 aprint_error("%s: uninitialized pipe %d\n", 1285 sc->sc_dev.dv_xname, pipe); 1286 return; 1287 } 1288 1289 dmabuf = dd->dmabase; 1290 dmabase = sc->sc_dmabase; 1291 td = 0; 1292 1293 for (i = 0; i < (num - 1); i++) { 1294 1295 sc->sc_dma->xmit[i].flags = TX_BCNT(blksz) 1296 | TX_EOF | TX_BINT; 1297 sc->sc_dma->xmit[i].ba = dmabuf; 1298 sc->sc_dma->xmit[i].nda = dmabase + dbri_dma_off(xmit, i + 1); 1299 sc->sc_dma->xmit[i].status = 0; 1300 1301 td_last = td; 1302 dmabuf += blksz; 1303 } 1304 1305 sc->sc_dma->xmit[i].flags = TX_BCNT(blksz) | TX_EOF | TX_BINT; 1306 1307 sc->sc_dma->xmit[i].ba = dmabuf; 1308 sc->sc_dma->xmit[i].nda = dmabase + dbri_dma_off(xmit, 0); 1309 sc->sc_dma->xmit[i].status = 0; 1310 1311 dd->callback = callback; 1312 dd->callback_args = callback_args; 1313 1314 x = splaudio(); 1315 1316 /* the pipe shouldn't be active */ 1317 if (pipe_active(sc, pipe)) { 1318 aprint_error("pipe active (CDP)\n"); 1319 /* pipe is already active */ 1320 #if 0 1321 td_last = sc->sc_pipe[pipe].desc; 1322 while (sc->sc_desc[td_last].next != -1) 1323 td_last = sc->sc_desc[td_last].next; 1324 1325 sc->sc_desc[td_last].next = td_first; 1326 sc->sc_dma->desc[td_last].nda = 1327 sc->sc_dmabase + dbri_dma_off(desc, td_first); 1328 1329 cmd = dbri_command_lock(sc); 1330 *(cmd++) = DBRI_CMD(DBRI_COMMAND_CDP, 0, pipe); 1331 dbri_command_send(sc, cmd); 1332 #endif 1333 } else { 1334 /* 1335 * pipe isn't active - issue an SDP command to start our 1336 * chain of TDs running 1337 */ 1338 sc->sc_pipe[pipe].desc = which; 1339 cmd = dbri_command_lock(sc); 1340 *(cmd++) = DBRI_CMD(DBRI_COMMAND_SDP, 0, 1341 sc->sc_pipe[pipe].sdp | 1342 DBRI_SDP_VALID_POINTER | 1343 DBRI_SDP_EVERY | 1344 DBRI_SDP_CLEAR); 1345 *(cmd++) = sc->sc_dmabase + dbri_dma_off(xmit, 0); 1346 dbri_command_send(sc, cmd); 1347 DPRINTF("%s: starting DMA\n", __func__); 1348 } 1349 1350 splx(x); 1351 1352 return; 1353 } 1354 1355 static void 1356 setup_ring_recv(struct dbri_softc *sc, int pipe, int which, int num, int blksz, 1357 void (*callback)(void *), void *callback_args) 1358 { 1359 volatile u_int32_t *cmd; 1360 int x, i; 1361 int td_first, td_last; 1362 bus_addr_t dmabuf, dmabase; 1363 struct dbri_desc *dd = &sc->sc_desc[which]; 1364 1365 switch (pipe) { 1366 case 6: 1367 break; 1368 default: 1369 aprint_error("%s: illegal pipe number (%d)\n", 1370 __func__, pipe); 1371 return; 1372 } 1373 1374 td_first = td_last = -1; 1375 1376 if (sc->sc_pipe[pipe].sdp == 0) { 1377 aprint_error("%s: uninitialized pipe %d\n", 1378 sc->sc_dev.dv_xname, pipe); 1379 return; 1380 } 1381 1382 dmabuf = dd->dmabase; 1383 dmabase = sc->sc_dmabase; 1384 1385 for (i = 0; i < (num - 1); i++) { 1386 1387 sc->sc_dma->recv[i].flags = RX_BSIZE(blksz) | RX_FINAL; 1388 sc->sc_dma->recv[i].ba = dmabuf; 1389 sc->sc_dma->recv[i].nda = dmabase + dbri_dma_off(recv, i + 1); 1390 sc->sc_dma->recv[i].status = RX_EOF; 1391 1392 td_last = i; 1393 dmabuf += blksz; 1394 } 1395 1396 sc->sc_dma->recv[i].flags = RX_BSIZE(blksz) | RX_FINAL; 1397 1398 sc->sc_dma->recv[i].ba = dmabuf; 1399 sc->sc_dma->recv[i].nda = dmabase + dbri_dma_off(recv, 0); 1400 sc->sc_dma->recv[i].status = RX_EOF; 1401 1402 dd->callback = callback; 1403 dd->callback_args = callback_args; 1404 1405 x = splaudio(); 1406 1407 /* the pipe shouldn't be active */ 1408 if (pipe_active(sc, pipe)) { 1409 aprint_error("pipe active (CDP)\n"); 1410 /* pipe is already active */ 1411 #if 0 1412 td_last = sc->sc_pipe[pipe].desc; 1413 while (sc->sc_desc[td_last].next != -1) 1414 td_last = sc->sc_desc[td_last].next; 1415 1416 sc->sc_desc[td_last].next = td_first; 1417 sc->sc_dma->desc[td_last].nda = 1418 sc->sc_dmabase + dbri_dma_off(desc, td_first); 1419 1420 cmd = dbri_command_lock(sc); 1421 *(cmd++) = DBRI_CMD(DBRI_COMMAND_CDP, 0, pipe); 1422 dbri_command_send(sc, cmd); 1423 #endif 1424 } else { 1425 /* 1426 * pipe isn't active - issue an SDP command to start our 1427 * chain of TDs running 1428 */ 1429 sc->sc_pipe[pipe].desc = which; 1430 cmd = dbri_command_lock(sc); 1431 *(cmd++) = DBRI_CMD(DBRI_COMMAND_SDP, 0, 1432 sc->sc_pipe[pipe].sdp | 1433 DBRI_SDP_VALID_POINTER | 1434 DBRI_SDP_EVERY | 1435 DBRI_SDP_CLEAR); 1436 *(cmd++) = sc->sc_dmabase + dbri_dma_off(recv, 0); 1437 dbri_command_send(sc, cmd); 1438 DPRINTF("%s: starting DMA\n", __func__); 1439 } 1440 1441 splx(x); 1442 1443 return; 1444 } 1445 1446 static void 1447 pipe_ts_link(struct dbri_softc *sc, int pipe, enum io dir, int basepipe, 1448 int len, int cycle) 1449 { 1450 volatile u_int32_t *cmd; 1451 int prevpipe, nextpipe; 1452 int val; 1453 1454 DPRINTF("%s: %d\n", __func__, pipe); 1455 if (pipe < 0 || pipe >= DBRI_PIPE_MAX || 1456 basepipe < 0 || basepipe >= DBRI_PIPE_MAX) { 1457 aprint_error("%s: illegal pipe numbers (%d, %d)\n", 1458 sc->sc_dev.dv_xname, pipe, basepipe); 1459 return; 1460 } 1461 1462 if (sc->sc_pipe[pipe].sdp == 0 || sc->sc_pipe[basepipe].sdp == 0) { 1463 aprint_error("%s: uninitialized pipe (%d, %d)\n", 1464 sc->sc_dev.dv_xname, pipe, basepipe); 1465 return; 1466 } 1467 1468 if (basepipe == 16 && dir == PIPEoutput && cycle == 0) 1469 cycle = sc->sc_chi_bpf; 1470 1471 if (basepipe == pipe) 1472 prevpipe = nextpipe = pipe; 1473 else { 1474 if (basepipe == 16) { 1475 if (dir == PIPEinput) { 1476 prevpipe = sc->sc_chi_pipe_in; 1477 } else { 1478 prevpipe = sc->sc_chi_pipe_out; 1479 } 1480 } else 1481 prevpipe = basepipe; 1482 1483 nextpipe = sc->sc_pipe[prevpipe].next; 1484 1485 while (sc->sc_pipe[nextpipe].cycle < cycle && 1486 sc->sc_pipe[nextpipe].next != basepipe) { 1487 prevpipe = nextpipe; 1488 nextpipe = sc->sc_pipe[nextpipe].next; 1489 } 1490 } 1491 1492 if (prevpipe == 16) { 1493 if (dir == PIPEinput) { 1494 sc->sc_chi_pipe_in = pipe; 1495 } else { 1496 sc->sc_chi_pipe_out = pipe; 1497 } 1498 } else 1499 sc->sc_pipe[prevpipe].next = pipe; 1500 1501 sc->sc_pipe[pipe].next = nextpipe; 1502 sc->sc_pipe[pipe].cycle = cycle; 1503 sc->sc_pipe[pipe].length = len; 1504 1505 cmd = dbri_command_lock(sc); 1506 1507 switch (dir) { 1508 case PIPEinput: 1509 val = DBRI_DTS_VI | DBRI_DTS_INS | DBRI_DTS_PRVIN(prevpipe); 1510 val |= pipe; 1511 *(cmd++) = DBRI_CMD(DBRI_COMMAND_DTS, 0, val); 1512 *(cmd++) = DBRI_TS_LEN(len) | DBRI_TS_CYCLE(cycle) | 1513 DBRI_TS_NEXT(nextpipe); 1514 *(cmd++) = 0; 1515 break; 1516 case PIPEoutput: 1517 val = DBRI_DTS_VO | DBRI_DTS_INS | DBRI_DTS_PRVOUT(prevpipe); 1518 val |= pipe; 1519 *(cmd++) = DBRI_CMD(DBRI_COMMAND_DTS, 0, val); 1520 *(cmd++) = 0; 1521 *(cmd++) = DBRI_TS_LEN(len) | DBRI_TS_CYCLE(cycle) | 1522 DBRI_TS_NEXT(nextpipe); 1523 break; 1524 default: 1525 DPRINTF("%s: should not have happened!\n", 1526 sc->sc_dev.dv_xname); 1527 break; 1528 } 1529 1530 dbri_command_send(sc, cmd); 1531 1532 return; 1533 } 1534 1535 static int 1536 pipe_active(struct dbri_softc *sc, int pipe) 1537 { 1538 1539 return (sc->sc_pipe[pipe].desc != -1); 1540 } 1541 1542 /* 1543 * subroutines required to interface with audio(9) 1544 */ 1545 1546 static int 1547 dbri_query_encoding(void *hdl, struct audio_encoding *ae) 1548 { 1549 1550 switch (ae->index) { 1551 case 0: 1552 strcpy(ae->name, AudioEulinear); 1553 ae->encoding = AUDIO_ENCODING_ULINEAR; 1554 ae->precision = 8; 1555 ae->flags = 0; 1556 break; 1557 case 1: 1558 strcpy(ae->name, AudioEmulaw); 1559 ae->encoding = AUDIO_ENCODING_ULAW; 1560 ae->precision = 8; 1561 ae->flags = 0; 1562 break; 1563 case 2: 1564 strcpy(ae->name, AudioEalaw); 1565 ae->encoding = AUDIO_ENCODING_ALAW; 1566 ae->precision = 8; 1567 ae->flags = 0; 1568 break; 1569 case 3: 1570 strcpy(ae->name, AudioEslinear); 1571 ae->encoding = AUDIO_ENCODING_SLINEAR; 1572 ae->precision = 8; 1573 ae->flags = AUDIO_ENCODINGFLAG_EMULATED; 1574 break; 1575 case 4: 1576 strcpy(ae->name, AudioEslinear_le); 1577 ae->encoding = AUDIO_ENCODING_SLINEAR_LE; 1578 ae->precision = 16; 1579 ae->flags = AUDIO_ENCODINGFLAG_EMULATED; 1580 break; 1581 case 5: 1582 strcpy(ae->name, AudioEulinear_le); 1583 ae->encoding = AUDIO_ENCODING_ULINEAR_LE; 1584 ae->precision = 16; 1585 ae->flags = AUDIO_ENCODINGFLAG_EMULATED; 1586 break; 1587 case 6: 1588 strcpy(ae->name, AudioEslinear_be); 1589 ae->encoding = AUDIO_ENCODING_SLINEAR_BE; 1590 ae->precision = 16; 1591 ae->flags = 0; 1592 break; 1593 case 7: 1594 strcpy(ae->name, AudioEulinear_be); 1595 ae->encoding = AUDIO_ENCODING_ULINEAR_BE; 1596 ae->precision = 16; 1597 ae->flags = AUDIO_ENCODINGFLAG_EMULATED; 1598 break; 1599 case 8: 1600 strcpy(ae->name, AudioEslinear); 1601 ae->encoding = AUDIO_ENCODING_SLINEAR; 1602 ae->precision = 16; 1603 ae->flags = 0; 1604 break; 1605 default: 1606 return (EINVAL); 1607 } 1608 1609 return (0); 1610 } 1611 1612 static int 1613 dbri_set_params(void *hdl, int setmode, int usemode, 1614 struct audio_params *play, struct audio_params *rec, 1615 stream_filter_list_t *pfil, stream_filter_list_t *rfil) 1616 { 1617 struct dbri_softc *sc = hdl; 1618 int rate; 1619 audio_params_t *p = NULL; 1620 stream_filter_list_t *fil; 1621 int mode; 1622 1623 /* 1624 * This device only has one clock, so make the sample rates match. 1625 */ 1626 if (play->sample_rate != rec->sample_rate && 1627 usemode == (AUMODE_PLAY | AUMODE_RECORD)) { 1628 if (setmode == AUMODE_PLAY) { 1629 rec->sample_rate = play->sample_rate; 1630 setmode |= AUMODE_RECORD; 1631 } else if (setmode == AUMODE_RECORD) { 1632 play->sample_rate = rec->sample_rate; 1633 setmode |= AUMODE_PLAY; 1634 } else 1635 return EINVAL; 1636 } 1637 1638 for (mode = AUMODE_RECORD; mode != -1; 1639 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) { 1640 if ((setmode & mode) == 0) 1641 continue; 1642 1643 p = mode == AUMODE_PLAY ? play : rec; 1644 if (p->sample_rate < 4000 || p->sample_rate > 50000) { 1645 DPRINTF("dbri_set_params: invalid rate %d\n", 1646 p->sample_rate); 1647 return EINVAL; 1648 } 1649 1650 fil = mode == AUMODE_PLAY ? pfil : rfil; 1651 DPRINTF("requested enc: %d rate: %d prec: %d chan: %d\n", p->encoding, 1652 p->sample_rate, p->precision, p->channels); 1653 if (auconv_set_converter(dbri_formats, DBRI_NFORMATS, 1654 mode, p, true, fil) < 0) { 1655 aprint_debug("dbri_set_params: auconv_set_converter failed\n"); 1656 return EINVAL; 1657 } 1658 if (fil->req_size > 0) 1659 p = &fil->filters[0].param; 1660 } 1661 1662 if (p == NULL) { 1663 DPRINTF("dbri_set_params: no parameters to set\n"); 1664 return 0; 1665 } 1666 1667 DPRINTF("native enc: %d rate: %d prec: %d chan: %d\n", p->encoding, 1668 p->sample_rate, p->precision, p->channels); 1669 1670 for (rate = 0; CS4215_FREQ[rate].freq; rate++) 1671 if (CS4215_FREQ[rate].freq == p->sample_rate) 1672 break; 1673 1674 if (CS4215_FREQ[rate].freq == 0) 1675 return (EINVAL); 1676 1677 /* set frequency */ 1678 sc->sc_mm.c.bcontrol[1] &= ~0x38; 1679 sc->sc_mm.c.bcontrol[1] |= CS4215_FREQ[rate].csval; 1680 sc->sc_mm.c.bcontrol[2] &= ~0x70; 1681 sc->sc_mm.c.bcontrol[2] |= CS4215_FREQ[rate].xtal; 1682 1683 switch (p->encoding) { 1684 case AUDIO_ENCODING_ULAW: 1685 sc->sc_mm.c.bcontrol[1] &= ~3; 1686 sc->sc_mm.c.bcontrol[1] |= CS4215_DFR_ULAW; 1687 break; 1688 case AUDIO_ENCODING_ALAW: 1689 sc->sc_mm.c.bcontrol[1] &= ~3; 1690 sc->sc_mm.c.bcontrol[1] |= CS4215_DFR_ALAW; 1691 break; 1692 case AUDIO_ENCODING_ULINEAR: 1693 sc->sc_mm.c.bcontrol[1] &= ~3; 1694 if (p->precision == 8) { 1695 sc->sc_mm.c.bcontrol[1] |= CS4215_DFR_LINEAR8; 1696 } else { 1697 sc->sc_mm.c.bcontrol[1] |= CS4215_DFR_LINEAR16; 1698 } 1699 break; 1700 case AUDIO_ENCODING_SLINEAR_BE: 1701 case AUDIO_ENCODING_SLINEAR: 1702 sc->sc_mm.c.bcontrol[1] &= ~3; 1703 sc->sc_mm.c.bcontrol[1] |= CS4215_DFR_LINEAR16; 1704 break; 1705 } 1706 1707 switch (p->channels) { 1708 case 1: 1709 sc->sc_mm.c.bcontrol[1] &= ~CS4215_DFR_STEREO; 1710 break; 1711 case 2: 1712 sc->sc_mm.c.bcontrol[1] |= CS4215_DFR_STEREO; 1713 break; 1714 } 1715 1716 return (0); 1717 } 1718 1719 static int 1720 dbri_round_blocksize(void *hdl, int bs, int mode, 1721 const audio_params_t *param) 1722 { 1723 1724 /* DBRI DMA segment size, rounded down to 32bit alignment */ 1725 return 0x1ffc; 1726 } 1727 1728 static int 1729 dbri_halt_output(void *hdl) 1730 { 1731 struct dbri_softc *sc = hdl; 1732 1733 if (!sc->sc_playing) 1734 return 0; 1735 1736 sc->sc_playing = 0; 1737 pipe_reset(sc, 4); 1738 return (0); 1739 } 1740 1741 static int 1742 dbri_getdev(void *hdl, struct audio_device *ret) 1743 { 1744 1745 *ret = dbri_device; 1746 return (0); 1747 } 1748 1749 static int 1750 dbri_set_port(void *hdl, mixer_ctrl_t *mc) 1751 { 1752 struct dbri_softc *sc = hdl; 1753 int latt = sc->sc_latt, ratt = sc->sc_ratt; 1754 1755 switch (mc->dev) { 1756 case DBRI_VOL_OUTPUT: /* master volume */ 1757 latt = (latt & 0xc0) | (63 - 1758 min(mc->un.value.level[AUDIO_MIXER_LEVEL_LEFT] >> 2, 63)); 1759 ratt = (ratt & 0xc0) | (63 - 1760 min(mc->un.value.level[AUDIO_MIXER_LEVEL_RIGHT] >> 2, 63)); 1761 break; 1762 case DBRI_ENABLE_MONO: /* built-in speaker */ 1763 if (mc->un.ord == 1) { 1764 ratt |= CS4215_SE; 1765 } else 1766 ratt &= ~CS4215_SE; 1767 break; 1768 case DBRI_ENABLE_HEADPHONE: /* headphones output */ 1769 if (mc->un.ord == 1) { 1770 latt |= CS4215_HE; 1771 } else 1772 latt &= ~CS4215_HE; 1773 break; 1774 case DBRI_ENABLE_LINE: /* line out */ 1775 if (mc->un.ord == 1) { 1776 latt |= CS4215_LE; 1777 } else 1778 latt &= ~CS4215_LE; 1779 break; 1780 case DBRI_VOL_MONITOR: 1781 if (mc->un.value.level[AUDIO_MIXER_LEVEL_LEFT] == 1782 sc->sc_monitor) 1783 return 0; 1784 sc->sc_monitor = mc->un.value.level[AUDIO_MIXER_LEVEL_LEFT]; 1785 break; 1786 case DBRI_INPUT_GAIN: 1787 sc->sc_linp = mc->un.value.level[AUDIO_MIXER_LEVEL_LEFT]; 1788 sc->sc_rinp = mc->un.value.level[AUDIO_MIXER_LEVEL_RIGHT]; 1789 break; 1790 case DBRI_INPUT_SELECT: 1791 if (mc->un.mask == sc->sc_input) 1792 return 0; 1793 sc->sc_input = mc->un.mask; 1794 break; 1795 } 1796 1797 sc->sc_latt = latt; 1798 sc->sc_ratt = ratt; 1799 1800 mmcodec_setgain(sc, 0); 1801 1802 return (0); 1803 } 1804 1805 static int 1806 dbri_get_port(void *hdl, mixer_ctrl_t *mc) 1807 { 1808 struct dbri_softc *sc = hdl; 1809 1810 switch (mc->dev) { 1811 case DBRI_VOL_OUTPUT: /* master volume */ 1812 mc->un.value.level[AUDIO_MIXER_LEVEL_LEFT] = 1813 (63 - (sc->sc_latt & 0x3f)) << 2; 1814 mc->un.value.level[AUDIO_MIXER_LEVEL_RIGHT] = 1815 (63 - (sc->sc_ratt & 0x3f)) << 2; 1816 return (0); 1817 case DBRI_ENABLE_MONO: /* built-in speaker */ 1818 mc->un.ord = (sc->sc_ratt & CS4215_SE) ? 1 : 0; 1819 return 0; 1820 case DBRI_ENABLE_HEADPHONE: /* headphones output */ 1821 mc->un.ord = (sc->sc_latt & CS4215_HE) ? 1 : 0; 1822 return 0; 1823 case DBRI_ENABLE_LINE: /* line out */ 1824 mc->un.ord = (sc->sc_latt & CS4215_LE) ? 1 : 0; 1825 return 0; 1826 case DBRI_VOL_MONITOR: 1827 mc->un.value.level[AUDIO_MIXER_LEVEL_LEFT] = sc->sc_monitor; 1828 return 0; 1829 case DBRI_INPUT_GAIN: 1830 mc->un.value.level[AUDIO_MIXER_LEVEL_LEFT] = sc->sc_linp; 1831 mc->un.value.level[AUDIO_MIXER_LEVEL_RIGHT] = sc->sc_rinp; 1832 return 0; 1833 case DBRI_INPUT_SELECT: 1834 mc->un.mask = sc->sc_input; 1835 return 0; 1836 } 1837 return (EINVAL); 1838 } 1839 1840 static int 1841 dbri_query_devinfo(void *hdl, mixer_devinfo_t *di) 1842 { 1843 1844 switch (di->index) { 1845 case DBRI_MONITOR_CLASS: 1846 di->mixer_class = DBRI_MONITOR_CLASS; 1847 strcpy(di->label.name, AudioCmonitor); 1848 di->type = AUDIO_MIXER_CLASS; 1849 di->next = di->prev = AUDIO_MIXER_LAST; 1850 return 0; 1851 case DBRI_OUTPUT_CLASS: 1852 di->mixer_class = DBRI_OUTPUT_CLASS; 1853 strcpy(di->label.name, AudioCoutputs); 1854 di->type = AUDIO_MIXER_CLASS; 1855 di->next = di->prev = AUDIO_MIXER_LAST; 1856 return 0; 1857 case DBRI_INPUT_CLASS: 1858 di->mixer_class = DBRI_INPUT_CLASS; 1859 strcpy(di->label.name, AudioCinputs); 1860 di->type = AUDIO_MIXER_CLASS; 1861 di->next = di->prev = AUDIO_MIXER_LAST; 1862 return 0; 1863 case DBRI_VOL_OUTPUT: /* master volume */ 1864 di->mixer_class = DBRI_OUTPUT_CLASS; 1865 di->next = di->prev = AUDIO_MIXER_LAST; 1866 strcpy(di->label.name, AudioNmaster); 1867 di->type = AUDIO_MIXER_VALUE; 1868 di->un.v.num_channels = 2; 1869 strcpy(di->un.v.units.name, AudioNvolume); 1870 return (0); 1871 case DBRI_INPUT_GAIN: /* input gain */ 1872 di->mixer_class = DBRI_INPUT_CLASS; 1873 di->next = di->prev = AUDIO_MIXER_LAST; 1874 strcpy(di->label.name, AudioNrecord); 1875 di->type = AUDIO_MIXER_VALUE; 1876 di->un.v.num_channels = 2; 1877 strcpy(di->un.v.units.name, AudioNvolume); 1878 return (0); 1879 case DBRI_VOL_MONITOR: /* monitor volume */ 1880 di->mixer_class = DBRI_MONITOR_CLASS; 1881 di->next = di->prev = AUDIO_MIXER_LAST; 1882 strcpy(di->label.name, AudioNmonitor); 1883 di->type = AUDIO_MIXER_VALUE; 1884 di->un.v.num_channels = 1; 1885 strcpy(di->un.v.units.name, AudioNvolume); 1886 return (0); 1887 case DBRI_ENABLE_MONO: /* built-in speaker */ 1888 di->mixer_class = DBRI_OUTPUT_CLASS; 1889 di->next = di->prev = AUDIO_MIXER_LAST; 1890 strcpy(di->label.name, AudioNmono); 1891 di->type = AUDIO_MIXER_ENUM; 1892 di->un.e.num_mem = 2; 1893 strcpy(di->un.e.member[0].label.name, AudioNoff); 1894 di->un.e.member[0].ord = 0; 1895 strcpy(di->un.e.member[1].label.name, AudioNon); 1896 di->un.e.member[1].ord = 1; 1897 return (0); 1898 case DBRI_ENABLE_HEADPHONE: /* headphones output */ 1899 di->mixer_class = DBRI_OUTPUT_CLASS; 1900 di->next = di->prev = AUDIO_MIXER_LAST; 1901 strcpy(di->label.name, AudioNheadphone); 1902 di->type = AUDIO_MIXER_ENUM; 1903 di->un.e.num_mem = 2; 1904 strcpy(di->un.e.member[0].label.name, AudioNoff); 1905 di->un.e.member[0].ord = 0; 1906 strcpy(di->un.e.member[1].label.name, AudioNon); 1907 di->un.e.member[1].ord = 1; 1908 return (0); 1909 case DBRI_ENABLE_LINE: /* line out */ 1910 di->mixer_class = DBRI_OUTPUT_CLASS; 1911 di->next = di->prev = AUDIO_MIXER_LAST; 1912 strcpy(di->label.name, AudioNline); 1913 di->type = AUDIO_MIXER_ENUM; 1914 di->un.e.num_mem = 2; 1915 strcpy(di->un.e.member[0].label.name, AudioNoff); 1916 di->un.e.member[0].ord = 0; 1917 strcpy(di->un.e.member[1].label.name, AudioNon); 1918 di->un.e.member[1].ord = 1; 1919 return (0); 1920 case DBRI_INPUT_SELECT: 1921 di->mixer_class = DBRI_INPUT_CLASS; 1922 strcpy(di->label.name, AudioNsource); 1923 di->type = AUDIO_MIXER_SET; 1924 di->prev = di->next = AUDIO_MIXER_LAST; 1925 di->un.s.num_mem = 2; 1926 strcpy(di->un.s.member[0].label.name, AudioNline); 1927 di->un.s.member[0].mask = 1 << 0; 1928 strcpy(di->un.s.member[1].label.name, AudioNmicrophone); 1929 di->un.s.member[1].mask = 1 << 1; 1930 return 0; 1931 } 1932 1933 return (ENXIO); 1934 } 1935 1936 static size_t 1937 dbri_round_buffersize(void *hdl, int dir, size_t bufsize) 1938 { 1939 #ifdef DBRI_BIG_BUFFER 1940 return 16*0x1ffc; /* use ~128KB buffer */ 1941 #else 1942 return bufsize; 1943 #endif 1944 } 1945 1946 static int 1947 dbri_get_props(void *hdl) 1948 { 1949 1950 return AUDIO_PROP_MMAP | AUDIO_PROP_FULLDUPLEX; 1951 } 1952 1953 static int 1954 dbri_trigger_output(void *hdl, void *start, void *end, int blksize, 1955 void (*intr)(void *), void *intrarg, 1956 const struct audio_params *param) 1957 { 1958 struct dbri_softc *sc = hdl; 1959 unsigned long count, num; 1960 1961 if (sc->sc_playing) 1962 return 0; 1963 1964 count = (unsigned long)(((char *)end - (char *)start)); 1965 num = count / blksize; 1966 1967 DPRINTF("trigger_output(%lx %lx) : %d %ld %ld\n", 1968 (unsigned long)intr, 1969 (unsigned long)intrarg, blksize, count, num); 1970 1971 sc->sc_params = *param; 1972 1973 if (sc->sc_recording == 0) { 1974 /* do not muck with the codec when it's already in use */ 1975 if (mmcodec_setcontrol(sc) != 0) 1976 return -1; 1977 mmcodec_init_data(sc); 1978 } 1979 1980 /* 1981 * always use DMA descriptor 0 for output 1982 * no need to allocate them dynamically since we only ever have 1983 * exactly one input stream and exactly one output stream 1984 */ 1985 setup_ring_xmit(sc, 4, 0, num, blksize, intr, intrarg); 1986 sc->sc_playing = 1; 1987 return 0; 1988 } 1989 1990 static int 1991 dbri_halt_input(void *cookie) 1992 { 1993 struct dbri_softc *sc = cookie; 1994 1995 if (!sc->sc_recording) 1996 return 0; 1997 1998 sc->sc_recording = 0; 1999 pipe_reset(sc, 6); 2000 return 0; 2001 } 2002 2003 static int 2004 dbri_trigger_input(void *hdl, void *start, void *end, int blksize, 2005 void (*intr)(void *), void *intrarg, 2006 const struct audio_params *param) 2007 { 2008 struct dbri_softc *sc = hdl; 2009 unsigned long count, num; 2010 2011 if (sc->sc_recording) 2012 return 0; 2013 2014 count = (unsigned long)(((char *)end - (char *)start)); 2015 num = count / blksize; 2016 2017 DPRINTF("trigger_input(%lx %lx) : %d %ld %ld\n", 2018 (unsigned long)intr, 2019 (unsigned long)intrarg, blksize, count, num); 2020 2021 sc->sc_params = *param; 2022 2023 if (sc->sc_playing == 0) { 2024 2025 /* 2026 * we don't support different parameters for playing and 2027 * recording anyway so don't bother whacking the codec if 2028 * it's already set up 2029 */ 2030 mmcodec_setcontrol(sc); 2031 mmcodec_init_data(sc); 2032 } 2033 2034 sc->sc_recording = 1; 2035 setup_ring_recv(sc, 6, 1, num, blksize, intr, intrarg); 2036 return 0; 2037 } 2038 2039 2040 static u_int32_t 2041 reverse_bytes(u_int32_t b, int len) 2042 { 2043 switch (len) { 2044 case 32: 2045 b = ((b & 0xffff0000) >> 16) | ((b & 0x0000ffff) << 16); 2046 case 16: 2047 b = ((b & 0xff00ff00) >> 8) | ((b & 0x00ff00ff) << 8); 2048 case 8: 2049 b = ((b & 0xf0f0f0f0) >> 4) | ((b & 0x0f0f0f0f) << 4); 2050 case 4: 2051 b = ((b & 0xcccccccc) >> 2) | ((b & 0x33333333) << 2); 2052 case 2: 2053 b = ((b & 0xaaaaaaaa) >> 1) | ((b & 0x55555555) << 1); 2054 case 1: 2055 case 0: 2056 break; 2057 default: 2058 DPRINTF("reverse_bytes: unsupported length\n"); 2059 }; 2060 2061 return (b); 2062 } 2063 2064 static void * 2065 dbri_malloc(void *v, int dir, size_t s, struct malloc_type *mt, int flags) 2066 { 2067 struct dbri_softc *sc = v; 2068 struct dbri_desc *dd = &sc->sc_desc[sc->sc_desc_used]; 2069 int rseg; 2070 2071 if (bus_dmamap_create(sc->sc_dmat, s, 1, s, 0, BUS_DMA_NOWAIT, 2072 &dd->dmamap) == 0) { 2073 if (bus_dmamem_alloc(sc->sc_dmat, s, 0, 0, &dd->dmaseg, 2074 1, &rseg, BUS_DMA_NOWAIT) == 0) { 2075 if (bus_dmamem_map(sc->sc_dmat, &dd->dmaseg, rseg, s, 2076 &dd->buf, BUS_DMA_NOWAIT|BUS_DMA_COHERENT) == 0) { 2077 if (dd->buf != NULL) { 2078 if (bus_dmamap_load(sc->sc_dmat, 2079 dd->dmamap, dd->buf, s, NULL, 2080 BUS_DMA_NOWAIT) == 0) { 2081 dd->len = s; 2082 dd->busy = 0; 2083 dd->callback = NULL; 2084 dd->dmabase = 2085 dd->dmamap->dm_segs[0].ds_addr; 2086 DPRINTF("dbri_malloc: using buffer %d %08x\n", 2087 sc->sc_desc_used, (uint32_t)dd->buf); 2088 sc->sc_desc_used++; 2089 return dd->buf; 2090 } else 2091 aprint_error("dbri_malloc: load failed\n"); 2092 } else 2093 aprint_error("dbri_malloc: map returned NULL\n"); 2094 } else 2095 aprint_error("dbri_malloc: map failed\n"); 2096 bus_dmamem_free(sc->sc_dmat, &dd->dmaseg, rseg); 2097 } else 2098 aprint_error("dbri_malloc: malloc() failed\n"); 2099 bus_dmamap_destroy(sc->sc_dmat, dd->dmamap); 2100 } else 2101 aprint_error("dbri_malloc: bus_dmamap_create() failed\n"); 2102 return NULL; 2103 } 2104 2105 static void 2106 dbri_free(void *v, void *p, struct malloc_type *mt) 2107 { 2108 free(p, mt); 2109 } 2110 2111 static paddr_t 2112 dbri_mappage(void *v, void *mem, off_t off, int prot) 2113 { 2114 struct dbri_softc *sc = v;; 2115 int current; 2116 2117 if (off < 0) 2118 return -1; 2119 2120 current = 0; 2121 while ((current < sc->sc_desc_used) && 2122 (sc->sc_desc[current].buf != mem)) 2123 current++; 2124 2125 if (current < sc->sc_desc_used) { 2126 return bus_dmamem_mmap(sc->sc_dmat, 2127 &sc->sc_desc[current].dmaseg, 1, off, prot, BUS_DMA_WAITOK); 2128 } 2129 2130 return -1; 2131 } 2132 2133 static int 2134 dbri_open(void *cookie, int flags) 2135 { 2136 struct dbri_softc *sc = cookie; 2137 2138 DPRINTF("%s: %d\n", __func__, sc->sc_refcount); 2139 2140 if (sc->sc_refcount == 0) 2141 dbri_bring_up(sc); 2142 2143 sc->sc_refcount++; 2144 2145 return 0; 2146 } 2147 2148 static void 2149 dbri_close(void *cookie) 2150 { 2151 struct dbri_softc *sc = cookie; 2152 2153 DPRINTF("%s: %d\n", __func__, sc->sc_refcount); 2154 2155 sc->sc_refcount--; 2156 KASSERT(sc->sc_refcount >= 0); 2157 if (sc->sc_refcount > 0) 2158 return; 2159 2160 dbri_set_power(sc, 0); 2161 sc->sc_playing = 0; 2162 sc->sc_recording = 0; 2163 } 2164 2165 static void 2166 dbri_powerhook(int why, void *cookie) 2167 { 2168 struct dbri_softc *sc = cookie; 2169 2170 if (why == sc->sc_pmgrstate) 2171 return; 2172 2173 switch(why) 2174 { 2175 case PWR_SUSPEND: 2176 dbri_set_power(sc, 0); 2177 break; 2178 case PWR_RESUME: 2179 if (sc->sc_powerstate != 0) 2180 break; 2181 aprint_verbose("resume: %d\n", sc->sc_refcount); 2182 sc->sc_pmgrstate = PWR_RESUME; 2183 if (sc->sc_playing) { 2184 volatile u_int32_t *cmd; 2185 int s; 2186 2187 dbri_bring_up(sc); 2188 s = splaudio(); 2189 cmd = dbri_command_lock(sc); 2190 *(cmd++) = DBRI_CMD(DBRI_COMMAND_SDP, 2191 0, sc->sc_pipe[4].sdp | 2192 DBRI_SDP_VALID_POINTER | 2193 DBRI_SDP_EVERY | DBRI_SDP_CLEAR); 2194 *(cmd++) = sc->sc_dmabase + 2195 dbri_dma_off(xmit, 0); 2196 dbri_command_send(sc, cmd); 2197 splx(s); 2198 } 2199 break; 2200 default: 2201 return; 2202 } 2203 sc->sc_pmgrstate = why; 2204 } 2205 2206 #endif /* NAUDIO > 0 */ 2207
Indexes created Thu Sep 25 08:09:54 GMT 2025