dbri.c revision 1.17
1 /* $NetBSD: dbri.c,v 1.17 2007/12/03 15:34:33 ad Exp $ */ 2 3 /* 4 * Copyright (C) 1997 Rudolf Koenig (rfkoenig (at) immd4.informatik.uni-erlangen.de) 5 * Copyright (c) 1998, 1999 Brent Baccala (baccala (at) freesoft.org) 6 * Copyright (c) 2001, 2002 Jared D. McNeill <jmcneill (at) netbsd.org> 7 * Copyright (c) 2005, 2007 Michael Lorenz <macallan (at) netbsd.org> 8 * All rights reserved. 9 * 10 * This driver is losely based on a Linux driver written by Rudolf Koenig and 11 * Brent Baccala who kindly gave their permission to use their code in a 12 * BSD-licensed driver. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions 16 * are met: 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in the 21 * documentation and/or other materials provided with the distribution. 22 * 3. All advertising materials mentioning features or use of this software 23 * must display the following acknowledgement: 24 * This product includes software developed by Rudolf Koenig, Brent 25 * Baccala, Jared D. McNeill. 26 * 4. Neither the name of the author nor the names of any contributors may 27 * be used to endorse or promote products derived from this software 28 * without specific prior written permission. 29 * 30 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 31 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 33 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 36 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 37 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 38 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 39 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 40 * SUCH DAMAGE. 41 * 42 */ 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: dbri.c,v 1.17 2007/12/03 15:34:33 ad Exp $"); 46 47 #include "audio.h" 48 #if NAUDIO > 0 49 50 #include <sys/param.h> 51 #include <sys/systm.h> 52 #include <sys/errno.h> 53 #include <sys/device.h> 54 #include <sys/malloc.h> 55 #include <sys/proc.h> 56 #include <sys/kernel.h> 57 #include <sys/bus.h> 58 #include <sys/intr.h> 59 60 #include <dev/sbus/sbusvar.h> 61 #include <sparc/sparc/auxreg.h> 62 #include <machine/autoconf.h> 63 64 #include <sys/audioio.h> 65 #include <dev/audio_if.h> 66 #include <dev/auconv.h> 67 68 #include <dev/ic/cs4215reg.h> 69 #include <dev/ic/cs4215var.h> 70 #include <dev/sbus/dbrireg.h> 71 #include <dev/sbus/dbrivar.h> 72 73 #include "opt_sbus_dbri.h" 74 75 #define DBRI_ROM_NAME_PREFIX "SUNW,DBRI" 76 77 #ifdef DBRI_DEBUG 78 # define DPRINTF aprint_normal 79 #else 80 # define DPRINTF while (0) printf 81 #endif 82 83 static const char *dbri_supported[] = { 84 "e", 85 "s3", 86 "" 87 }; 88 89 enum ms { 90 CHImaster, 91 CHIslave 92 }; 93 94 enum io { 95 PIPEinput, 96 PIPEoutput 97 }; 98 99 /* 100 * Function prototypes 101 */ 102 103 /* softc stuff */ 104 static void dbri_attach_sbus(struct device *, struct device *, void *); 105 static int dbri_match_sbus(struct device *, struct cfdata *, void *); 106 107 static void dbri_config_interrupts(struct device *); 108 109 /* interrupt handler */ 110 static int dbri_intr(void *); 111 static void dbri_softint(void *); 112 113 /* supporting subroutines */ 114 static int dbri_init(struct dbri_softc *); 115 static int dbri_reset(struct dbri_softc *); 116 static volatile u_int32_t *dbri_command_lock(struct dbri_softc *); 117 static void dbri_command_send(struct dbri_softc *, volatile u_int32_t *); 118 static void dbri_process_interrupt_buffer(struct dbri_softc *); 119 static void dbri_process_interrupt(struct dbri_softc *, int32_t); 120 121 /* mmcodec subroutines */ 122 static int mmcodec_init(struct dbri_softc *); 123 static void mmcodec_init_data(struct dbri_softc *); 124 static void mmcodec_pipe_init(struct dbri_softc *); 125 static void mmcodec_default(struct dbri_softc *); 126 static void mmcodec_setgain(struct dbri_softc *, int); 127 static int mmcodec_setcontrol(struct dbri_softc *); 128 129 /* chi subroutines */ 130 static void chi_reset(struct dbri_softc *, enum ms, int); 131 132 /* pipe subroutines */ 133 static void pipe_setup(struct dbri_softc *, int, int); 134 static void pipe_reset(struct dbri_softc *, int); 135 static void pipe_receive_fixed(struct dbri_softc *, int, 136 volatile u_int32_t *); 137 static void pipe_transmit_fixed(struct dbri_softc *, int, u_int32_t); 138 139 static void pipe_ts_link(struct dbri_softc *, int, enum io, int, int, int); 140 static int pipe_active(struct dbri_softc *, int); 141 142 /* audio(9) stuff */ 143 static int dbri_query_encoding(void *, struct audio_encoding *); 144 static int dbri_set_params(void *, int, int, struct audio_params *, 145 struct audio_params *,stream_filter_list_t *, stream_filter_list_t *); 146 static int dbri_round_blocksize(void *, int, int, const audio_params_t *); 147 static int dbri_halt_output(void *); 148 static int dbri_halt_input(void *); 149 static int dbri_getdev(void *, struct audio_device *); 150 static int dbri_set_port(void *, mixer_ctrl_t *); 151 static int dbri_get_port(void *, mixer_ctrl_t *); 152 static int dbri_query_devinfo(void *, mixer_devinfo_t *); 153 static size_t dbri_round_buffersize(void *, int, size_t); 154 static int dbri_get_props(void *); 155 static int dbri_open(void *, int); 156 static void dbri_close(void *); 157 158 static void setup_ring_xmit(struct dbri_softc *, int, int, int, int, 159 void (*)(void *), void *); 160 static void setup_ring_recv(struct dbri_softc *, int, int, int, int, 161 void (*)(void *), void *); 162 163 static int dbri_trigger_output(void *, void *, void *, int, 164 void (*)(void *), void *, const struct audio_params *); 165 static int dbri_trigger_input(void *, void *, void *, int, 166 void (*)(void *), void *, const struct audio_params *); 167 168 static void *dbri_malloc(void *, int, size_t, struct malloc_type *, int); 169 static void dbri_free(void *, void *, struct malloc_type *); 170 static paddr_t dbri_mappage(void *, void *, off_t, int); 171 static void dbri_set_power(struct dbri_softc *, int); 172 static void dbri_bring_up(struct dbri_softc *); 173 static void dbri_powerhook(int, void *); 174 175 /* stupid support routines */ 176 static u_int32_t reverse_bytes(u_int32_t, int); 177 178 struct audio_device dbri_device = { 179 "CS4215", 180 "", 181 "dbri" 182 }; 183 184 struct audio_hw_if dbri_hw_if = { 185 dbri_open, 186 dbri_close, 187 NULL, /* drain */ 188 dbri_query_encoding, 189 dbri_set_params, 190 dbri_round_blocksize, 191 NULL, /* commit_settings */ 192 NULL, /* init_output */ 193 NULL, /* init_input */ 194 NULL, /* start_output */ 195 NULL, /* start_input */ 196 dbri_halt_output, 197 dbri_halt_input, 198 NULL, /* speaker_ctl */ 199 dbri_getdev, 200 NULL, /* setfd */ 201 dbri_set_port, 202 dbri_get_port, 203 dbri_query_devinfo, 204 dbri_malloc, 205 dbri_free, 206 dbri_round_buffersize, 207 dbri_mappage, 208 dbri_get_props, 209 dbri_trigger_output, 210 dbri_trigger_input 211 }; 212 213 CFATTACH_DECL(dbri, sizeof(struct dbri_softc), 214 dbri_match_sbus, dbri_attach_sbus, NULL, NULL); 215 216 #define DBRI_NFORMATS 4 217 static const struct audio_format dbri_formats[DBRI_NFORMATS] = { 218 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_SLINEAR_BE, 16, 16, 219 2, AUFMT_STEREO, 8, {8000, 9600, 11025, 16000, 22050, 32000, 44100, 220 48000}}, 221 /* {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_ULAW, 8, 8, 222 2, AUFMT_STEREO, 8, {8000, 9600, 11025, 16000, 22050, 32000, 44100, 223 48000}}, 224 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_ALAW, 8, 8, 225 2, AUFMT_STEREO, 8, {8000, 9600, 11025, 16000, 22050, 32000, 44100, 226 48000}}, 227 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_ULINEAR, 8, 8, 228 2, AUFMT_STEREO, 8, {8000, 9600, 11025, 16000, 22050, 32000, 44100, 229 48000}},*/ 230 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_ULAW, 8, 8, 231 1, AUFMT_MONAURAL, 8, {8000, 9600, 11025, 16000, 22050, 32000, 44100, 232 48000}}, 233 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_ALAW, 8, 8, 234 1, AUFMT_MONAURAL, 8, {8000, 9600, 11025, 16000, 22050, 32000, 44100, 235 48000}}, 236 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_ULINEAR, 8, 8, 237 1, AUFMT_MONAURAL, 8, {8000, 9600, 11025, 16000, 22050, 32000, 44100, 238 48000}}, 239 }; 240 241 enum { 242 DBRI_OUTPUT_CLASS, 243 DBRI_VOL_OUTPUT, 244 DBRI_ENABLE_MONO, 245 DBRI_ENABLE_HEADPHONE, 246 DBRI_ENABLE_LINE, 247 DBRI_MONITOR_CLASS, 248 DBRI_VOL_MONITOR, 249 DBRI_INPUT_CLASS, 250 DBRI_INPUT_GAIN, 251 DBRI_INPUT_SELECT, 252 DBRI_RECORD_CLASS, 253 DBRI_ENUM_LAST 254 }; 255 256 /* 257 * Autoconfig routines 258 */ 259 static int 260 dbri_match_sbus(struct device *parent, struct cfdata *match, void *aux) 261 { 262 struct sbus_attach_args *sa = aux; 263 char *ver; 264 int i; 265 266 if (strncmp(DBRI_ROM_NAME_PREFIX, sa->sa_name, 9)) 267 return (0); 268 269 ver = &sa->sa_name[9]; 270 271 for (i = 0; dbri_supported[i][0] != '\0'; i++) 272 if (strcmp(dbri_supported[i], ver) == 0) 273 return (1); 274 275 return (0); 276 } 277 278 static void 279 dbri_attach_sbus(struct device *parent, struct device *self, void *aux) 280 { 281 struct dbri_softc *sc = (struct dbri_softc *)self; 282 struct sbus_attach_args *sa = aux; 283 bus_space_handle_t ioh; 284 bus_size_t size; 285 int error, rseg, pwr, i; 286 char *ver = &sa->sa_name[9]; 287 288 sc->sc_iot = sa->sa_bustag; 289 sc->sc_dmat = sa->sa_dmatag; 290 sc->sc_powerstate = 1; 291 292 pwr = prom_getpropint(sa->sa_node,"pwr-on-auxio",0); 293 aprint_normal(": rev %s\n", ver); 294 295 if (pwr) { 296 /* 297 * we can control DBRI power via auxio and we're initially 298 * powered down 299 */ 300 301 sc->sc_have_powerctl = 1; 302 sc->sc_powerstate = 0; 303 dbri_set_power(sc, 1); 304 powerhook_establish(self->dv_xname, dbri_powerhook, sc); 305 } else { 306 /* we can't control power so we're always up */ 307 sc->sc_have_powerctl = 0; 308 sc->sc_powerstate = 1; 309 } 310 311 for (i = 0; i < DBRI_NUM_DESCRIPTORS; i++) { 312 sc->sc_desc[i].softint = softint_establish(SOFTINT_SERIAL, 313 dbri_softint, &sc->sc_desc[i]); 314 } 315 316 if (sa->sa_npromvaddrs) 317 ioh = (bus_space_handle_t)sa->sa_promvaddrs[0]; 318 else { 319 if (sbus_bus_map(sa->sa_bustag, sa->sa_slot, 320 sa->sa_offset, sa->sa_size, 321 BUS_SPACE_MAP_LINEAR, /*0,*/ &ioh) != 0) { 322 aprint_error("%s @ sbus: cannot map registers\n", 323 self->dv_xname); 324 return; 325 } 326 } 327 328 sc->sc_ioh = ioh; 329 330 size = sizeof(struct dbri_dma); 331 332 /* get a DMA handle */ 333 if ((error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, 334 BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) { 335 aprint_error("%s: DMA map create error %d\n", self->dv_xname, 336 error); 337 return; 338 } 339 340 /* allocate DMA buffer */ 341 if ((error = bus_dmamem_alloc(sc->sc_dmat, size, 0, 0, &sc->sc_dmaseg, 342 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 343 aprint_error("%s: DMA buffer alloc error %d\n", 344 self->dv_xname, error); 345 return; 346 } 347 348 /* map DMA buffer into CPU addressable space */ 349 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_dmaseg, rseg, size, 350 &sc->sc_membase, 351 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 352 aprint_error("%s: DMA buffer map error %d\n", 353 self->dv_xname, error); 354 return; 355 } 356 357 /* load the buffer */ 358 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, 359 sc->sc_membase, size, NULL, 360 BUS_DMA_NOWAIT)) != 0) { 361 aprint_error("%s: DMA buffer map load error %d\n", 362 self->dv_xname, error); 363 bus_dmamem_unmap(sc->sc_dmat, sc->sc_membase, size); 364 bus_dmamem_free(sc->sc_dmat, &sc->sc_dmaseg, rseg); 365 return; 366 } 367 368 /* map the registers into memory */ 369 370 /* kernel virtual address of DMA buffer */ 371 sc->sc_dma = (struct dbri_dma *)sc->sc_membase; 372 /* physical address of DMA buffer */ 373 sc->sc_dmabase = sc->sc_dmamap->dm_segs[0].ds_addr; 374 sc->sc_bufsiz = size; 375 376 sbus_establish(&sc->sc_sd, &sc->sc_dev); 377 378 bus_intr_establish(sa->sa_bustag, sa->sa_pri, IPL_SCHED, dbri_intr, 379 sc); 380 381 sc->sc_locked = 0; 382 sc->sc_desc_used = 0; 383 sc->sc_refcount = 0; 384 sc->sc_playing = 0; 385 sc->sc_recording = 0; 386 sc->sc_pmgrstate = PWR_RESUME; 387 config_interrupts(self, &dbri_config_interrupts); 388 389 return; 390 } 391 392 /* 393 * lowlevel routine to switch power for the DBRI chip 394 */ 395 static void 396 dbri_set_power(struct dbri_softc *sc, int state) 397 { 398 int s; 399 400 if (sc->sc_have_powerctl == 0) 401 return; 402 if (sc->sc_powerstate == state) 403 return; 404 405 if (state) { 406 DPRINTF("%s: waiting to power up... ", sc->sc_dev.dv_xname); 407 s = splhigh(); 408 *AUXIO4M_REG |= (AUXIO4M_MMX); 409 splx(s); 410 delay(10000); 411 DPRINTF("done (%02x)\n", *AUXIO4M_REG); 412 } else { 413 DPRINTF("%s: powering down\n", sc->sc_dev.dv_xname); 414 s = splhigh(); 415 *AUXIO4M_REG &= ~AUXIO4M_MMX; 416 splx(s); 417 DPRINTF("done (%02x})\n", *AUXIO4M_REG); 418 } 419 sc->sc_powerstate = state; 420 } 421 422 /* 423 * power up and re-initialize the chip 424 */ 425 static void 426 dbri_bring_up(struct dbri_softc *sc) 427 { 428 429 if (sc->sc_have_powerctl == 0) 430 return; 431 432 if (sc->sc_powerstate == 1) 433 return; 434 435 /* ok, we really need to do something */ 436 dbri_set_power(sc, 1); 437 438 /* 439 * re-initialize the chip but skip all the probing, don't overwrite 440 * any other settings either 441 */ 442 dbri_init(sc); 443 mmcodec_setgain(sc, 1); 444 mmcodec_pipe_init(sc); 445 mmcodec_init_data(sc); 446 mmcodec_setgain(sc, 0); 447 } 448 449 static void 450 dbri_config_interrupts(struct device *dev) 451 { 452 struct dbri_softc *sc = (struct dbri_softc *)dev; 453 454 dbri_init(sc); 455 mmcodec_init(sc); 456 457 /* Attach ourselves to the high level audio interface */ 458 audio_attach_mi(&dbri_hw_if, sc, &sc->sc_dev); 459 460 /* power down until open() */ 461 dbri_set_power(sc, 0); 462 return; 463 } 464 465 static int 466 dbri_intr(void *hdl) 467 { 468 struct dbri_softc *sc = hdl; 469 bus_space_tag_t iot = sc->sc_iot; 470 bus_space_handle_t ioh = sc->sc_ioh; 471 int x; 472 473 /* clear interrupt */ 474 x = bus_space_read_4(iot, ioh, DBRI_REG1); 475 if (x & (DBRI_MRR | DBRI_MLE | DBRI_LBG | DBRI_MBE)) { 476 u_int32_t tmp; 477 478 if (x & DBRI_MRR) 479 aprint_debug("%s: multiple ack error on sbus\n", 480 sc->sc_dev.dv_xname); 481 if (x & DBRI_MLE) 482 aprint_debug("%s: multiple late error on sbus\n", 483 sc->sc_dev.dv_xname); 484 if (x & DBRI_LBG) 485 aprint_debug("%s: lost bus grant on sbus\n", 486 sc->sc_dev.dv_xname); 487 if (x & DBRI_MBE) 488 aprint_debug("%s: burst error on sbus\n", 489 sc->sc_dev.dv_xname); 490 491 /* 492 * Some of these errors disable the chip's circuitry. 493 * Re-enable the circuitry and keep on going. 494 */ 495 496 tmp = bus_space_read_4(iot, ioh, DBRI_REG0); 497 tmp &= ~(DBRI_DISABLE_MASTER); 498 bus_space_write_4(iot, ioh, DBRI_REG0, tmp); 499 } 500 501 #if 0 502 if (!x & 1) /* XXX: DBRI_INTR_REQ */ 503 return (1); 504 #endif 505 506 dbri_process_interrupt_buffer(sc); 507 508 return (1); 509 } 510 511 static void 512 dbri_softint(void *cookie) 513 { 514 struct dbri_desc *dd = cookie; 515 516 if (dd->callback != NULL) 517 dd->callback(dd->callback_args); 518 } 519 520 static int 521 dbri_init(struct dbri_softc *sc) 522 { 523 bus_space_tag_t iot = sc->sc_iot; 524 bus_space_handle_t ioh = sc->sc_ioh; 525 u_int32_t reg; 526 volatile u_int32_t *cmd; 527 bus_addr_t dmaaddr; 528 int n; 529 530 dbri_reset(sc); 531 532 cmd = dbri_command_lock(sc); 533 534 /* XXX: Initialize interrupt ring buffer */ 535 sc->sc_dma->intr[0] = (u_int32_t)sc->sc_dmabase + dbri_dma_off(intr, 0); 536 sc->sc_irqp = 1; 537 538 /* Initialize pipes */ 539 for (n = 0; n < DBRI_PIPE_MAX; n++) 540 sc->sc_pipe[n].desc = sc->sc_pipe[n].next = -1; 541 542 for (n = 1; n < DBRI_INT_BLOCKS; n++) { 543 sc->sc_dma->intr[n] = 0; 544 } 545 546 /* Disable all SBus bursts */ 547 /* XXX 16 byte bursts cause errors, the rest works */ 548 reg = bus_space_read_4(iot, ioh, DBRI_REG0); 549 550 /*reg &= ~(DBRI_BURST_4 | DBRI_BURST_8 | DBRI_BURST_16);*/ 551 reg |= (DBRI_BURST_4 | DBRI_BURST_8); 552 bus_space_write_4(iot, ioh, DBRI_REG0, reg); 553 554 /* setup interrupt queue */ 555 dmaaddr = (u_int32_t)sc->sc_dmabase + dbri_dma_off(intr, 0); 556 *(cmd++) = DBRI_CMD(DBRI_COMMAND_IIQ, 0, 0); 557 *(cmd++) = dmaaddr; 558 559 dbri_command_send(sc, cmd); 560 return (0); 561 } 562 563 static int 564 dbri_reset(struct dbri_softc *sc) 565 { 566 int bail = 0; 567 568 bus_space_tag_t iot = sc->sc_iot; 569 bus_space_handle_t ioh = sc->sc_ioh; 570 571 bus_space_write_4(iot, ioh, DBRI_REG0, DBRI_SOFT_RESET); 572 while ((bus_space_read_4(iot, ioh, DBRI_REG0) & DBRI_SOFT_RESET) && 573 (bail < 100000)) { 574 bail++; 575 delay(10); 576 } 577 if (bail == 100000) aprint_error("%s: reset timed out\n", 578 sc->sc_dev.dv_xname); 579 return (0); 580 } 581 582 static volatile u_int32_t * 583 dbri_command_lock(struct dbri_softc *sc) 584 { 585 586 if (sc->sc_locked) 587 aprint_debug("%s: command buffer locked\n", 588 sc->sc_dev.dv_xname); 589 590 sc->sc_locked++; 591 592 return (&sc->sc_dma->command[0]); 593 } 594 595 static void 596 dbri_command_send(struct dbri_softc *sc, volatile u_int32_t *cmd) 597 { 598 bus_space_handle_t ioh = sc->sc_ioh; 599 bus_space_tag_t iot = sc->sc_iot; 600 int maxloops = 1000000; 601 int x; 602 603 x = splsched(); 604 605 sc->sc_locked--; 606 607 if (sc->sc_locked != 0) { 608 aprint_error("%s: command buffer improperly locked\n", 609 sc->sc_dev.dv_xname); 610 } else if ((cmd - &sc->sc_dma->command[0]) >= DBRI_NUM_COMMANDS - 1) { 611 aprint_error("%s: command buffer overflow\n", 612 sc->sc_dev.dv_xname); 613 } else { 614 *(cmd++) = DBRI_CMD(DBRI_COMMAND_PAUSE, 0, 0); 615 *(cmd++) = DBRI_CMD(DBRI_COMMAND_WAIT, 1, 0); 616 sc->sc_waitseen = 0; 617 bus_space_write_4(iot, ioh, DBRI_REG8, sc->sc_dmabase); 618 while ((--maxloops) > 0 && 619 (bus_space_read_4(iot, ioh, DBRI_REG0) 620 & DBRI_COMMAND_VALID)) { 621 bus_space_barrier(iot, ioh, DBRI_REG0, 4, 622 BUS_SPACE_BARRIER_READ); 623 delay(1000); 624 } 625 626 if (maxloops == 0) { 627 aprint_error( 628 "%s: chip never completed command buffer\n", 629 sc->sc_dev.dv_xname); 630 } else { 631 632 DPRINTF("%s: command completed\n", 633 sc->sc_dev.dv_xname); 634 635 while ((--maxloops) > 0 && (!sc->sc_waitseen)) 636 dbri_process_interrupt_buffer(sc); 637 if (maxloops == 0) { 638 aprint_error("%s: chip never acked WAIT\n", 639 sc->sc_dev.dv_xname); 640 } 641 } 642 } 643 644 splx(x); 645 646 return; 647 } 648 649 static void 650 dbri_process_interrupt_buffer(struct dbri_softc *sc) 651 { 652 int32_t i; 653 654 while ((i = sc->sc_dma->intr[sc->sc_irqp]) != 0) { 655 sc->sc_dma->intr[sc->sc_irqp] = 0; 656 sc->sc_irqp++; 657 658 if (sc->sc_irqp == DBRI_INT_BLOCKS) 659 sc->sc_irqp = 1; 660 else if ((sc->sc_irqp & (DBRI_INT_BLOCKS - 1)) == 0) 661 sc->sc_irqp++; 662 663 dbri_process_interrupt(sc, i); 664 } 665 666 return; 667 } 668 669 static void 670 dbri_process_interrupt(struct dbri_softc *sc, int32_t i) 671 { 672 #if 0 673 const int liu_states[] = { 1, 0, 8, 3, 4, 5, 6, 7 }; 674 #endif 675 int val = DBRI_INTR_GETVAL(i); 676 int channel = DBRI_INTR_GETCHAN(i); 677 int command = DBRI_INTR_GETCMD(i); 678 int code = DBRI_INTR_GETCODE(i); 679 #if 0 680 int rval = DBRI_INTR_GETRVAL(i); 681 #endif 682 if (channel == DBRI_INTR_CMD && command == DBRI_COMMAND_WAIT) 683 sc->sc_waitseen++; 684 685 switch (code) { 686 case DBRI_INTR_XCMP: /* transmission complete */ 687 { 688 int td; 689 struct dbri_desc *dd; 690 691 td = sc->sc_pipe[channel].desc; 692 dd = &sc->sc_desc[td]; 693 694 if (dd->callback != NULL) 695 softint_schedule(dd->softint); 696 break; 697 } 698 case DBRI_INTR_FXDT: /* fixed data change */ 699 DPRINTF("dbri_intr: Fixed data change (%d: %x)\n", channel, 700 val); 701 #if 0 702 printf("reg: %08x\n", sc->sc_mm.status); 703 #endif 704 if (sc->sc_pipe[channel].sdp & DBRI_SDP_MSB) 705 val = reverse_bytes(val, sc->sc_pipe[channel].length); 706 if (sc->sc_pipe[channel].prec) 707 *(sc->sc_pipe[channel].prec) = val; 708 #ifndef DBRI_SPIN 709 DPRINTF("%s: wakeup %p\n", sc->sc_dev.dv_xname, sc); 710 wakeup(sc); 711 #endif 712 break; 713 case DBRI_INTR_SBRI: 714 DPRINTF("dbri_intr: SBRI\n"); 715 break; 716 case DBRI_INTR_BRDY: 717 { 718 int td; 719 struct dbri_desc *dd; 720 721 td = sc->sc_pipe[channel].desc; 722 dd = &sc->sc_desc[td]; 723 724 if (dd->callback != NULL) 725 softint_schedule(dd->softint); 726 break; 727 } 728 case DBRI_INTR_UNDR: 729 { 730 volatile u_int32_t *cmd; 731 int td = sc->sc_pipe[channel].desc; 732 733 DPRINTF("%s: DBRI_INTR_UNDR\n", sc->sc_dev.dv_xname); 734 735 sc->sc_dma->xmit[td].status = 0; 736 737 cmd = dbri_command_lock(sc); 738 *(cmd++) = DBRI_CMD(DBRI_COMMAND_SDP, 0, 739 sc->sc_pipe[channel].sdp | 740 DBRI_SDP_VALID_POINTER | 741 DBRI_SDP_CLEAR | 742 DBRI_SDP_2SAME); 743 *(cmd++) = sc->sc_dmabase + dbri_dma_off(xmit, td); 744 dbri_command_send(sc, cmd); 745 break; 746 } 747 case DBRI_INTR_CMDI: 748 DPRINTF("ok"); 749 break; 750 default: 751 752 aprint_error("%s: unknown interrupt code %d\n", 753 sc->sc_dev.dv_xname, code); 754 break; 755 } 756 757 return; 758 } 759 760 /* 761 * mmcodec stuff 762 */ 763 764 static int 765 mmcodec_init(struct dbri_softc *sc) 766 { 767 bus_space_handle_t ioh = sc->sc_ioh; 768 bus_space_tag_t iot = sc->sc_iot; 769 u_int32_t reg2; 770 int bail; 771 772 reg2 = bus_space_read_4(iot, ioh, DBRI_REG2); 773 DPRINTF("mmcodec_init: PIO reads %x\n", reg2); 774 775 if (reg2 & DBRI_PIO2) { 776 aprint_normal("%s: onboard CS4215 detected\n", 777 sc->sc_dev.dv_xname); 778 sc->sc_mm.onboard = 1; 779 } 780 781 if (reg2 & DBRI_PIO0) { 782 aprint_normal("%s: speakerbox detected\n", 783 sc->sc_dev.dv_xname); 784 bus_space_write_4(iot, ioh, DBRI_REG2, DBRI_PIO2_ENABLE); 785 sc->sc_mm.onboard = 0; 786 } 787 788 if ((reg2 & DBRI_PIO2) && (reg2 & DBRI_PIO0)) { 789 aprint_normal("%s: using speakerbox\n", 790 sc->sc_dev.dv_xname); 791 bus_space_write_4(iot, ioh, DBRI_REG2, DBRI_PIO2_ENABLE); 792 sc->sc_mm.onboard = 0; 793 } 794 795 if (!(reg2 & (DBRI_PIO0|DBRI_PIO2))) { 796 aprint_normal("%s: no mmcodec found\n", sc->sc_dev.dv_xname); 797 return -1; 798 } 799 800 sc->sc_version = 0xff; 801 802 mmcodec_pipe_init(sc); 803 mmcodec_default(sc); 804 805 sc->sc_mm.offset = sc->sc_mm.onboard ? 0 : 8; 806 807 /* 808 * mmcodec_setcontrol() sometimes fails right after powerup 809 * so we just try again until we either get a useful response or run 810 * out of time 811 */ 812 bail = 0; 813 while (mmcodec_setcontrol(sc) == -1 || sc->sc_version == 0xff) { 814 815 bail++; 816 if (bail > 100) { 817 DPRINTF("%s: cs4215 probe failed at offset %d\n", 818 sc->sc_dev.dv_xname, sc->sc_mm.offset); 819 return (-1); 820 } 821 delay(10000); 822 } 823 824 aprint_normal("%s: cs4215 rev %c found at offset %d\n", 825 sc->sc_dev.dv_xname, 0x43 + (sc->sc_version & 0xf), sc->sc_mm.offset); 826 827 /* set some sane defaults for mmcodec_init_data */ 828 sc->sc_params.channels = 2; 829 sc->sc_params.precision = 16; 830 831 mmcodec_init_data(sc); 832 833 return (0); 834 } 835 836 static void 837 mmcodec_init_data(struct dbri_softc *sc) 838 { 839 bus_space_tag_t iot = sc->sc_iot; 840 bus_space_handle_t ioh = sc->sc_ioh; 841 u_int32_t tmp; 842 int data_width; 843 844 tmp = bus_space_read_4(iot, ioh, DBRI_REG0); 845 tmp &= ~(DBRI_CHI_ACTIVATE); /* disable CHI */ 846 bus_space_write_4(iot, ioh, DBRI_REG0, tmp); 847 848 /* switch CS4215 to data mode - set PIO3 to 1 */ 849 tmp = DBRI_PIO_ENABLE_ALL | DBRI_PIO1 | DBRI_PIO3; 850 851 /* XXX */ 852 tmp |= (sc->sc_mm.onboard ? DBRI_PIO0 : DBRI_PIO2); 853 854 bus_space_write_4(iot, ioh, DBRI_REG2, tmp); 855 chi_reset(sc, CHIslave, 128); 856 857 data_width = sc->sc_params.channels * sc->sc_params.precision; 858 859 if ((data_width != 32) && (data_width != 8)) 860 aprint_error("%s: data_width is %d\n", __func__, data_width); 861 862 pipe_ts_link(sc, 20, PIPEoutput, 16, 32, sc->sc_mm.offset + 32); 863 pipe_ts_link(sc, 4, PIPEoutput, 16, data_width, sc->sc_mm.offset); 864 pipe_ts_link(sc, 6, PIPEinput, 16, data_width, sc->sc_mm.offset); 865 pipe_ts_link(sc, 21, PIPEinput, 16, 32, sc->sc_mm.offset + 32); 866 867 pipe_receive_fixed(sc, 21, &sc->sc_mm.status); 868 869 mmcodec_setgain(sc, 0); 870 871 tmp = bus_space_read_4(iot, ioh, DBRI_REG0); 872 tmp |= DBRI_CHI_ACTIVATE; 873 bus_space_write_4(iot, ioh, DBRI_REG0, tmp); 874 875 return; 876 } 877 878 static void 879 mmcodec_pipe_init(struct dbri_softc *sc) 880 { 881 882 pipe_setup(sc, 4, DBRI_SDP_MEM | DBRI_SDP_TO_SER | DBRI_SDP_MSB); 883 pipe_setup(sc, 20, DBRI_SDP_FIXED | DBRI_SDP_TO_SER | DBRI_SDP_MSB); 884 pipe_setup(sc, 6, DBRI_SDP_MEM | DBRI_SDP_FROM_SER | DBRI_SDP_MSB); 885 pipe_setup(sc, 21, DBRI_SDP_FIXED | DBRI_SDP_FROM_SER | DBRI_SDP_MSB); 886 887 pipe_setup(sc, 17, DBRI_SDP_FIXED | DBRI_SDP_TO_SER | DBRI_SDP_MSB); 888 pipe_setup(sc, 18, DBRI_SDP_FIXED | DBRI_SDP_FROM_SER | DBRI_SDP_MSB); 889 pipe_setup(sc, 19, DBRI_SDP_FIXED | DBRI_SDP_FROM_SER | DBRI_SDP_MSB); 890 891 sc->sc_mm.status = 0; 892 893 pipe_receive_fixed(sc, 18, &sc->sc_mm.status); 894 pipe_receive_fixed(sc, 19, &sc->sc_mm.version); 895 896 return; 897 } 898 899 static void 900 mmcodec_default(struct dbri_softc *sc) 901 { 902 struct cs4215_state *mm = &sc->sc_mm; 903 904 /* 905 * no action, memory resetting only 906 * 907 * data time slots 5-8 908 * speaker, line and headphone enable. set gain to half. 909 * input is line 910 */ 911 mm->d.bdata[0] = sc->sc_latt = 0x20 | CS4215_HE | CS4215_LE; 912 mm->d.bdata[1] = sc->sc_ratt = 0x20 | CS4215_SE; 913 sc->sc_linp = 128; 914 sc->sc_rinp = 128; 915 sc->sc_monitor = 0; 916 sc->sc_input = 1; /* line */ 917 mm->d.bdata[2] = (CS4215_LG((sc->sc_linp >> 4)) & 0x0f) | 918 ((sc->sc_input == 2) ? CS4215_IS : 0) | CS4215_PIO0 | CS4215_PIO1; 919 mm->d.bdata[3] = (CS4215_RG((sc->sc_rinp >> 4) & 0x0f)) | 920 CS4215_MA(15 - ((sc->sc_monitor >> 4) & 0x0f)); 921 922 923 /* 924 * control time slots 1-4 925 * 926 * 0: default I/O voltage scale 927 * 1: 8 bit ulaw, 8kHz, mono, high pass filter disabled 928 * 2: serial enable, CHI master, 128 bits per frame, clock 1 929 * 3: tests disabled 930 */ 931 mm->c.bcontrol[0] = CS4215_RSRVD_1 | CS4215_MLB; 932 mm->c.bcontrol[1] = CS4215_DFR_ULAW | CS4215_FREQ[0].csval; 933 mm->c.bcontrol[2] = CS4215_XCLK | CS4215_BSEL_128 | CS4215_FREQ[0].xtal; 934 mm->c.bcontrol[3] = 0; 935 936 return; 937 } 938 939 static void 940 mmcodec_setgain(struct dbri_softc *sc, int mute) 941 { 942 if (mute) { 943 /* disable all outputs, max. attenuation */ 944 sc->sc_mm.d.bdata[0] = sc->sc_latt | 63; 945 sc->sc_mm.d.bdata[1] = sc->sc_ratt | 63; 946 } else { 947 948 sc->sc_mm.d.bdata[0] = sc->sc_latt; 949 sc->sc_mm.d.bdata[1] = sc->sc_ratt; 950 } 951 952 /* input stuff */ 953 sc->sc_mm.d.bdata[2] = CS4215_LG((sc->sc_linp >> 4) & 0x0f) | 954 ((sc->sc_input == 2) ? CS4215_IS : 0) | CS4215_PIO0 | CS4215_PIO1; 955 sc->sc_mm.d.bdata[3] = (CS4215_RG((sc->sc_rinp >> 4)) & 0x0f) | 956 (CS4215_MA(15 - ((sc->sc_monitor >> 4) & 0x0f))); 957 958 if (sc->sc_powerstate == 0) 959 return; 960 pipe_transmit_fixed(sc, 20, sc->sc_mm.d.ldata); 961 962 DPRINTF("mmcodec_setgain: %08x\n", sc->sc_mm.d.ldata); 963 /* give the chip some time to execute the command */ 964 delay(250); 965 966 return; 967 } 968 969 static int 970 mmcodec_setcontrol(struct dbri_softc *sc) 971 { 972 bus_space_tag_t iot = sc->sc_iot; 973 bus_space_handle_t ioh = sc->sc_ioh; 974 u_int32_t val; 975 u_int32_t tmp; 976 int bail = 0; 977 #if DBRI_SPIN 978 int i; 979 #endif 980 981 /* 982 * Temporarily mute outputs and wait 125 us to make sure that it 983 * happens. This avoids clicking noises. 984 */ 985 mmcodec_setgain(sc, 1); 986 delay(125); 987 988 bus_space_write_4(iot, ioh, DBRI_REG2, 0); 989 delay(125); 990 991 /* enable control mode */ 992 val = DBRI_PIO_ENABLE_ALL | DBRI_PIO1; /* was PIO1 */ 993 994 /* XXX */ 995 val |= (sc->sc_mm.onboard ? DBRI_PIO0 : DBRI_PIO2); 996 997 bus_space_write_4(iot, ioh, DBRI_REG2, val); 998 999 delay(34); 1000 1001 /* 1002 * in control mode, the cs4215 is the slave device, so the 1003 * DBRI must act as the CHI master. 1004 * 1005 * in data mode, the cs4215 must be the CHI master to insure 1006 * that the data stream is in sync with its codec 1007 */ 1008 tmp = bus_space_read_4(iot, ioh, DBRI_REG0); 1009 tmp &= ~DBRI_COMMAND_CHI; 1010 bus_space_write_4(iot, ioh, DBRI_REG0, tmp); 1011 1012 chi_reset(sc, CHImaster, 128); 1013 1014 /* control mode */ 1015 pipe_ts_link(sc, 17, PIPEoutput, 16, 32, sc->sc_mm.offset); 1016 pipe_ts_link(sc, 18, PIPEinput, 16, 8, sc->sc_mm.offset); 1017 pipe_ts_link(sc, 19, PIPEinput, 16, 8, sc->sc_mm.offset + 48); 1018 1019 /* wait for the chip to echo back CLB as zero */ 1020 sc->sc_mm.c.bcontrol[0] &= ~CS4215_CLB; 1021 pipe_transmit_fixed(sc, 17, sc->sc_mm.c.lcontrol); 1022 1023 tmp = bus_space_read_4(iot, ioh, DBRI_REG0); 1024 tmp |= DBRI_CHI_ACTIVATE; 1025 bus_space_write_4(iot, ioh, DBRI_REG0, tmp); 1026 1027 #if DBRI_SPIN 1028 i = 1024; 1029 while (((sc->sc_mm.status & 0xe4) != 0x20) && --i) { 1030 delay(125); 1031 } 1032 1033 if (i == 0) { 1034 DPRINTF("%s: cs4215 didn't respond to CLB (0x%02x)\n", 1035 sc->sc_dev.dv_xname, sc->sc_mm.status); 1036 return (-1); 1037 } 1038 #else 1039 while (((sc->sc_mm.status & 0xe4) != 0x20) && (bail < 10)) { 1040 DPRINTF("%s: tsleep %p\n", sc->sc_dev.dv_xname, sc); 1041 tsleep(sc, PCATCH | PZERO, "dbrifxdt", hz); 1042 bail++; 1043 } 1044 #endif 1045 if (bail >= 10) { 1046 DPRINTF("%s: switching to control mode timed out (%x %x)\n", 1047 sc->sc_dev.dv_xname, sc->sc_mm.status, 1048 bus_space_read_4(iot, ioh, DBRI_REG2)); 1049 return -1; 1050 } 1051 1052 /* copy the version information before it becomes unreadable again */ 1053 sc->sc_version = sc->sc_mm.version; 1054 1055 /* terminate cs4215 control mode */ 1056 sc->sc_mm.c.bcontrol[0] |= CS4215_CLB; 1057 pipe_transmit_fixed(sc, 17, sc->sc_mm.c.lcontrol); 1058 1059 /* two frames of control info @ 8kHz frame rate = 250us delay */ 1060 delay(250); 1061 1062 mmcodec_setgain(sc, 0); 1063 1064 return (0); 1065 1066 } 1067 1068 /* 1069 * CHI combo 1070 */ 1071 static void 1072 chi_reset(struct dbri_softc *sc, enum ms ms, int bpf) 1073 { 1074 volatile u_int32_t *cmd; 1075 int val; 1076 int clockrate, divisor; 1077 1078 cmd = dbri_command_lock(sc); 1079 1080 /* set CHI anchor: pipe 16 */ 1081 val = DBRI_DTS_VI | DBRI_DTS_INS | DBRI_DTS_PRVIN(16) | DBRI_PIPE(16); 1082 *(cmd++) = DBRI_CMD(DBRI_COMMAND_DTS, 0, val); 1083 *(cmd++) = DBRI_TS_ANCHOR | DBRI_TS_NEXT(16); 1084 *(cmd++) = 0; 1085 1086 val = DBRI_DTS_VO | DBRI_DTS_INS | DBRI_DTS_PRVOUT(16) | DBRI_PIPE(16); 1087 *(cmd++) = DBRI_CMD(DBRI_COMMAND_DTS, 0, val); 1088 *(cmd++) = 0; 1089 *(cmd++) = DBRI_TS_ANCHOR | DBRI_TS_NEXT(16); 1090 1091 sc->sc_pipe[16].sdp = 1; 1092 sc->sc_pipe[16].next = 16; 1093 sc->sc_chi_pipe_in = 16; 1094 sc->sc_chi_pipe_out = 16; 1095 1096 switch (ms) { 1097 case CHIslave: 1098 *(cmd++) = DBRI_CMD(DBRI_COMMAND_CHI, 0, DBRI_CHI_CHICM(0)); 1099 break; 1100 case CHImaster: 1101 clockrate = bpf * 8; 1102 divisor = 12288 / clockrate; 1103 1104 if (divisor > 255 || divisor * clockrate != 12288) 1105 aprint_error("%s: illegal bits-per-frame %d\n", 1106 sc->sc_dev.dv_xname, bpf); 1107 1108 *(cmd++) = DBRI_CMD(DBRI_COMMAND_CHI, 0, 1109 DBRI_CHI_CHICM(divisor) | DBRI_CHI_FD | DBRI_CHI_BPF(bpf)); 1110 break; 1111 default: 1112 aprint_error("%s: unknown value for ms!\n", 1113 sc->sc_dev.dv_xname); 1114 break; 1115 } 1116 1117 sc->sc_chi_bpf = bpf; 1118 1119 /* CHI data mode */ 1120 *(cmd++) = DBRI_CMD(DBRI_COMMAND_PAUSE, 0, 0); 1121 *(cmd++) = DBRI_CMD(DBRI_COMMAND_CDM, 0, 1122 DBRI_CDM_XCE | DBRI_CDM_XEN | DBRI_CDM_REN); 1123 1124 dbri_command_send(sc, cmd); 1125 1126 return; 1127 } 1128 1129 /* 1130 * pipe stuff 1131 */ 1132 static void 1133 pipe_setup(struct dbri_softc *sc, int pipe, int sdp) 1134 { 1135 DPRINTF("pipe setup: %d\n", pipe); 1136 if (pipe < 0 || pipe >= DBRI_PIPE_MAX) { 1137 aprint_error("%s: illegal pipe number %d\n", 1138 sc->sc_dev.dv_xname, pipe); 1139 return; 1140 } 1141 1142 if ((sdp & 0xf800) != sdp) 1143 aprint_error("%s: strange SDP value %d\n", sc->sc_dev.dv_xname, 1144 sdp); 1145 1146 if (DBRI_SDP_MODE(sdp) == DBRI_SDP_FIXED && 1147 !(sdp & DBRI_SDP_TO_SER)) 1148 sdp |= DBRI_SDP_CHANGE; 1149 1150 sdp |= DBRI_PIPE(pipe); 1151 1152 sc->sc_pipe[pipe].sdp = sdp; 1153 sc->sc_pipe[pipe].desc = -1; 1154 1155 pipe_reset(sc, pipe); 1156 1157 return; 1158 } 1159 1160 static void 1161 pipe_reset(struct dbri_softc *sc, int pipe) 1162 { 1163 struct dbri_desc *dd; 1164 int sdp; 1165 int desc; 1166 volatile u_int32_t *cmd; 1167 1168 if (pipe < 0 || pipe >= DBRI_PIPE_MAX) { 1169 aprint_error("%s: illegal pipe number %d\n", 1170 sc->sc_dev.dv_xname, pipe); 1171 return; 1172 } 1173 1174 sdp = sc->sc_pipe[pipe].sdp; 1175 if (sdp == 0) { 1176 aprint_error("%s: can not reset uninitialized pipe %d\n", 1177 sc->sc_dev.dv_xname, pipe); 1178 return; 1179 } 1180 1181 cmd = dbri_command_lock(sc); 1182 *(cmd++) = DBRI_CMD(DBRI_COMMAND_SDP, 0, 1183 sdp | DBRI_SDP_CLEAR | DBRI_SDP_VALID_POINTER); 1184 *(cmd++) = 0; 1185 dbri_command_send(sc, cmd); 1186 1187 desc = sc->sc_pipe[pipe].desc; 1188 1189 dd = &sc->sc_desc[desc]; 1190 1191 dd->busy = 0; 1192 1193 #if 0 1194 if (dd->callback) 1195 softint_schedule(dd->softint); 1196 #endif 1197 1198 sc->sc_pipe[pipe].desc = -1; 1199 1200 return; 1201 } 1202 1203 static void 1204 pipe_receive_fixed(struct dbri_softc *sc, int pipe, volatile u_int32_t *prec) 1205 { 1206 1207 if (pipe < DBRI_PIPE_MAX / 2 || pipe >= DBRI_PIPE_MAX) { 1208 aprint_error("%s: illegal pipe number %d\n", 1209 sc->sc_dev.dv_xname, pipe); 1210 return; 1211 } 1212 1213 if (DBRI_SDP_MODE(sc->sc_pipe[pipe].sdp) != DBRI_SDP_FIXED) { 1214 aprint_error("%s: non-fixed pipe %d\n", sc->sc_dev.dv_xname, 1215 pipe); 1216 return; 1217 } 1218 1219 if (sc->sc_pipe[pipe].sdp & DBRI_SDP_TO_SER) { 1220 aprint_error("%s: can not receive on transmit pipe %d\b", 1221 sc->sc_dev.dv_xname, pipe); 1222 return; 1223 } 1224 1225 sc->sc_pipe[pipe].prec = prec; 1226 1227 return; 1228 } 1229 1230 static void 1231 pipe_transmit_fixed(struct dbri_softc *sc, int pipe, u_int32_t data) 1232 { 1233 volatile u_int32_t *cmd; 1234 1235 if (pipe < DBRI_PIPE_MAX / 2 || pipe >= DBRI_PIPE_MAX) { 1236 aprint_error("%s: illegal pipe number %d\n", 1237 sc->sc_dev.dv_xname, pipe); 1238 return; 1239 } 1240 1241 if (DBRI_SDP_MODE(sc->sc_pipe[pipe].sdp) == 0) { 1242 aprint_error("%s: uninitialized pipe %d\n", 1243 sc->sc_dev.dv_xname, pipe); 1244 return; 1245 } 1246 1247 if (DBRI_SDP_MODE(sc->sc_pipe[pipe].sdp) != DBRI_SDP_FIXED) { 1248 aprint_error("%s: non-fixed pipe %d\n", sc->sc_dev.dv_xname, 1249 pipe); 1250 return; 1251 } 1252 1253 if (!(sc->sc_pipe[pipe].sdp & DBRI_SDP_TO_SER)) { 1254 aprint_error("%s: called on receive pipe %d\n", 1255 sc->sc_dev.dv_xname, pipe); 1256 return; 1257 } 1258 1259 if (sc->sc_pipe[pipe].sdp & DBRI_SDP_MSB) 1260 data = reverse_bytes(data, sc->sc_pipe[pipe].length); 1261 1262 cmd = dbri_command_lock(sc); 1263 *(cmd++) = DBRI_CMD(DBRI_COMMAND_SSP, 0, pipe); 1264 *(cmd++) = data; 1265 1266 dbri_command_send(sc, cmd); 1267 1268 return; 1269 } 1270 1271 static void 1272 setup_ring_xmit(struct dbri_softc *sc, int pipe, int which, int num, int blksz, 1273 void (*callback)(void *), void *callback_args) 1274 { 1275 volatile u_int32_t *cmd; 1276 int x, i; 1277 int td; 1278 int td_first, td_last; 1279 bus_addr_t dmabuf, dmabase; 1280 struct dbri_desc *dd = &sc->sc_desc[which]; 1281 1282 switch (pipe) { 1283 case 4: 1284 /* output, offset 0 */ 1285 break; 1286 default: 1287 aprint_error("%s: illegal pipe number (%d)\n", 1288 __func__, pipe); 1289 return; 1290 } 1291 1292 td = 0; 1293 td_first = td_last = -1; 1294 1295 if (sc->sc_pipe[pipe].sdp == 0) { 1296 aprint_error("%s: uninitialized pipe %d\n", 1297 sc->sc_dev.dv_xname, pipe); 1298 return; 1299 } 1300 1301 dmabuf = dd->dmabase; 1302 dmabase = sc->sc_dmabase; 1303 td = 0; 1304 1305 for (i = 0; i < (num - 1); i++) { 1306 1307 sc->sc_dma->xmit[i].flags = TX_BCNT(blksz) 1308 | TX_EOF | TX_BINT; 1309 sc->sc_dma->xmit[i].ba = dmabuf; 1310 sc->sc_dma->xmit[i].nda = dmabase + dbri_dma_off(xmit, i + 1); 1311 sc->sc_dma->xmit[i].status = 0; 1312 1313 td_last = td; 1314 dmabuf += blksz; 1315 } 1316 1317 sc->sc_dma->xmit[i].flags = TX_BCNT(blksz) | TX_EOF | TX_BINT; 1318 1319 sc->sc_dma->xmit[i].ba = dmabuf; 1320 sc->sc_dma->xmit[i].nda = dmabase + dbri_dma_off(xmit, 0); 1321 sc->sc_dma->xmit[i].status = 0; 1322 1323 dd->callback = callback; 1324 dd->callback_args = callback_args; 1325 1326 x = splsched(); 1327 1328 /* the pipe shouldn't be active */ 1329 if (pipe_active(sc, pipe)) { 1330 aprint_error("pipe active (CDP)\n"); 1331 /* pipe is already active */ 1332 #if 0 1333 td_last = sc->sc_pipe[pipe].desc; 1334 while (sc->sc_desc[td_last].next != -1) 1335 td_last = sc->sc_desc[td_last].next; 1336 1337 sc->sc_desc[td_last].next = td_first; 1338 sc->sc_dma->desc[td_last].nda = 1339 sc->sc_dmabase + dbri_dma_off(desc, td_first); 1340 1341 cmd = dbri_command_lock(sc); 1342 *(cmd++) = DBRI_CMD(DBRI_COMMAND_CDP, 0, pipe); 1343 dbri_command_send(sc, cmd); 1344 #endif 1345 } else { 1346 /* 1347 * pipe isn't active - issue an SDP command to start our 1348 * chain of TDs running 1349 */ 1350 sc->sc_pipe[pipe].desc = which; 1351 cmd = dbri_command_lock(sc); 1352 *(cmd++) = DBRI_CMD(DBRI_COMMAND_SDP, 0, 1353 sc->sc_pipe[pipe].sdp | 1354 DBRI_SDP_VALID_POINTER | 1355 DBRI_SDP_EVERY | 1356 DBRI_SDP_CLEAR); 1357 *(cmd++) = sc->sc_dmabase + dbri_dma_off(xmit, 0); 1358 dbri_command_send(sc, cmd); 1359 DPRINTF("%s: starting DMA\n", __func__); 1360 } 1361 1362 splx(x); 1363 1364 return; 1365 } 1366 1367 static void 1368 setup_ring_recv(struct dbri_softc *sc, int pipe, int which, int num, int blksz, 1369 void (*callback)(void *), void *callback_args) 1370 { 1371 volatile u_int32_t *cmd; 1372 int x, i; 1373 int td_first, td_last; 1374 bus_addr_t dmabuf, dmabase; 1375 struct dbri_desc *dd = &sc->sc_desc[which]; 1376 1377 switch (pipe) { 1378 case 6: 1379 break; 1380 default: 1381 aprint_error("%s: illegal pipe number (%d)\n", 1382 __func__, pipe); 1383 return; 1384 } 1385 1386 td_first = td_last = -1; 1387 1388 if (sc->sc_pipe[pipe].sdp == 0) { 1389 aprint_error("%s: uninitialized pipe %d\n", 1390 sc->sc_dev.dv_xname, pipe); 1391 return; 1392 } 1393 1394 dmabuf = dd->dmabase; 1395 dmabase = sc->sc_dmabase; 1396 1397 for (i = 0; i < (num - 1); i++) { 1398 1399 sc->sc_dma->recv[i].flags = RX_BSIZE(blksz) | RX_FINAL; 1400 sc->sc_dma->recv[i].ba = dmabuf; 1401 sc->sc_dma->recv[i].nda = dmabase + dbri_dma_off(recv, i + 1); 1402 sc->sc_dma->recv[i].status = RX_EOF; 1403 1404 td_last = i; 1405 dmabuf += blksz; 1406 } 1407 1408 sc->sc_dma->recv[i].flags = RX_BSIZE(blksz) | RX_FINAL; 1409 1410 sc->sc_dma->recv[i].ba = dmabuf; 1411 sc->sc_dma->recv[i].nda = dmabase + dbri_dma_off(recv, 0); 1412 sc->sc_dma->recv[i].status = RX_EOF; 1413 1414 dd->callback = callback; 1415 dd->callback_args = callback_args; 1416 1417 x = splsched(); 1418 1419 /* the pipe shouldn't be active */ 1420 if (pipe_active(sc, pipe)) { 1421 aprint_error("pipe active (CDP)\n"); 1422 /* pipe is already active */ 1423 #if 0 1424 td_last = sc->sc_pipe[pipe].desc; 1425 while (sc->sc_desc[td_last].next != -1) 1426 td_last = sc->sc_desc[td_last].next; 1427 1428 sc->sc_desc[td_last].next = td_first; 1429 sc->sc_dma->desc[td_last].nda = 1430 sc->sc_dmabase + dbri_dma_off(desc, td_first); 1431 1432 cmd = dbri_command_lock(sc); 1433 *(cmd++) = DBRI_CMD(DBRI_COMMAND_CDP, 0, pipe); 1434 dbri_command_send(sc, cmd); 1435 #endif 1436 } else { 1437 /* 1438 * pipe isn't active - issue an SDP command to start our 1439 * chain of TDs running 1440 */ 1441 sc->sc_pipe[pipe].desc = which; 1442 cmd = dbri_command_lock(sc); 1443 *(cmd++) = DBRI_CMD(DBRI_COMMAND_SDP, 0, 1444 sc->sc_pipe[pipe].sdp | 1445 DBRI_SDP_VALID_POINTER | 1446 DBRI_SDP_EVERY | 1447 DBRI_SDP_CLEAR); 1448 *(cmd++) = sc->sc_dmabase + dbri_dma_off(recv, 0); 1449 dbri_command_send(sc, cmd); 1450 DPRINTF("%s: starting DMA\n", __func__); 1451 } 1452 1453 splx(x); 1454 1455 return; 1456 } 1457 1458 static void 1459 pipe_ts_link(struct dbri_softc *sc, int pipe, enum io dir, int basepipe, 1460 int len, int cycle) 1461 { 1462 volatile u_int32_t *cmd; 1463 int prevpipe, nextpipe; 1464 int val; 1465 1466 DPRINTF("%s: %d\n", __func__, pipe); 1467 if (pipe < 0 || pipe >= DBRI_PIPE_MAX || 1468 basepipe < 0 || basepipe >= DBRI_PIPE_MAX) { 1469 aprint_error("%s: illegal pipe numbers (%d, %d)\n", 1470 sc->sc_dev.dv_xname, pipe, basepipe); 1471 return; 1472 } 1473 1474 if (sc->sc_pipe[pipe].sdp == 0 || sc->sc_pipe[basepipe].sdp == 0) { 1475 aprint_error("%s: uninitialized pipe (%d, %d)\n", 1476 sc->sc_dev.dv_xname, pipe, basepipe); 1477 return; 1478 } 1479 1480 if (basepipe == 16 && dir == PIPEoutput && cycle == 0) 1481 cycle = sc->sc_chi_bpf; 1482 1483 if (basepipe == pipe) 1484 prevpipe = nextpipe = pipe; 1485 else { 1486 if (basepipe == 16) { 1487 if (dir == PIPEinput) { 1488 prevpipe = sc->sc_chi_pipe_in; 1489 } else { 1490 prevpipe = sc->sc_chi_pipe_out; 1491 } 1492 } else 1493 prevpipe = basepipe; 1494 1495 nextpipe = sc->sc_pipe[prevpipe].next; 1496 1497 while (sc->sc_pipe[nextpipe].cycle < cycle && 1498 sc->sc_pipe[nextpipe].next != basepipe) { 1499 prevpipe = nextpipe; 1500 nextpipe = sc->sc_pipe[nextpipe].next; 1501 } 1502 } 1503 1504 if (prevpipe == 16) { 1505 if (dir == PIPEinput) { 1506 sc->sc_chi_pipe_in = pipe; 1507 } else { 1508 sc->sc_chi_pipe_out = pipe; 1509 } 1510 } else 1511 sc->sc_pipe[prevpipe].next = pipe; 1512 1513 sc->sc_pipe[pipe].next = nextpipe; 1514 sc->sc_pipe[pipe].cycle = cycle; 1515 sc->sc_pipe[pipe].length = len; 1516 1517 cmd = dbri_command_lock(sc); 1518 1519 switch (dir) { 1520 case PIPEinput: 1521 val = DBRI_DTS_VI | DBRI_DTS_INS | DBRI_DTS_PRVIN(prevpipe); 1522 val |= pipe; 1523 *(cmd++) = DBRI_CMD(DBRI_COMMAND_DTS, 0, val); 1524 *(cmd++) = DBRI_TS_LEN(len) | DBRI_TS_CYCLE(cycle) | 1525 DBRI_TS_NEXT(nextpipe); 1526 *(cmd++) = 0; 1527 break; 1528 case PIPEoutput: 1529 val = DBRI_DTS_VO | DBRI_DTS_INS | DBRI_DTS_PRVOUT(prevpipe); 1530 val |= pipe; 1531 *(cmd++) = DBRI_CMD(DBRI_COMMAND_DTS, 0, val); 1532 *(cmd++) = 0; 1533 *(cmd++) = DBRI_TS_LEN(len) | DBRI_TS_CYCLE(cycle) | 1534 DBRI_TS_NEXT(nextpipe); 1535 break; 1536 default: 1537 DPRINTF("%s: should not have happened!\n", 1538 sc->sc_dev.dv_xname); 1539 break; 1540 } 1541 1542 dbri_command_send(sc, cmd); 1543 1544 return; 1545 } 1546 1547 static int 1548 pipe_active(struct dbri_softc *sc, int pipe) 1549 { 1550 1551 return (sc->sc_pipe[pipe].desc != -1); 1552 } 1553 1554 /* 1555 * subroutines required to interface with audio(9) 1556 */ 1557 1558 static int 1559 dbri_query_encoding(void *hdl, struct audio_encoding *ae) 1560 { 1561 1562 switch (ae->index) { 1563 case 0: 1564 strcpy(ae->name, AudioEulinear); 1565 ae->encoding = AUDIO_ENCODING_ULINEAR; 1566 ae->precision = 8; 1567 ae->flags = 0; 1568 break; 1569 case 1: 1570 strcpy(ae->name, AudioEmulaw); 1571 ae->encoding = AUDIO_ENCODING_ULAW; 1572 ae->precision = 8; 1573 ae->flags = 0; 1574 break; 1575 case 2: 1576 strcpy(ae->name, AudioEalaw); 1577 ae->encoding = AUDIO_ENCODING_ALAW; 1578 ae->precision = 8; 1579 ae->flags = 0; 1580 break; 1581 case 3: 1582 strcpy(ae->name, AudioEslinear); 1583 ae->encoding = AUDIO_ENCODING_SLINEAR; 1584 ae->precision = 8; 1585 ae->flags = AUDIO_ENCODINGFLAG_EMULATED; 1586 break; 1587 case 4: 1588 strcpy(ae->name, AudioEslinear_le); 1589 ae->encoding = AUDIO_ENCODING_SLINEAR_LE; 1590 ae->precision = 16; 1591 ae->flags = AUDIO_ENCODINGFLAG_EMULATED; 1592 break; 1593 case 5: 1594 strcpy(ae->name, AudioEulinear_le); 1595 ae->encoding = AUDIO_ENCODING_ULINEAR_LE; 1596 ae->precision = 16; 1597 ae->flags = AUDIO_ENCODINGFLAG_EMULATED; 1598 break; 1599 case 6: 1600 strcpy(ae->name, AudioEslinear_be); 1601 ae->encoding = AUDIO_ENCODING_SLINEAR_BE; 1602 ae->precision = 16; 1603 ae->flags = 0; 1604 break; 1605 case 7: 1606 strcpy(ae->name, AudioEulinear_be); 1607 ae->encoding = AUDIO_ENCODING_ULINEAR_BE; 1608 ae->precision = 16; 1609 ae->flags = AUDIO_ENCODINGFLAG_EMULATED; 1610 break; 1611 case 8: 1612 strcpy(ae->name, AudioEslinear); 1613 ae->encoding = AUDIO_ENCODING_SLINEAR; 1614 ae->precision = 16; 1615 ae->flags = 0; 1616 break; 1617 default: 1618 return (EINVAL); 1619 } 1620 1621 return (0); 1622 } 1623 1624 static int 1625 dbri_set_params(void *hdl, int setmode, int usemode, 1626 struct audio_params *play, struct audio_params *rec, 1627 stream_filter_list_t *pfil, stream_filter_list_t *rfil) 1628 { 1629 struct dbri_softc *sc = hdl; 1630 int rate; 1631 audio_params_t *p = NULL; 1632 stream_filter_list_t *fil; 1633 int mode; 1634 1635 /* 1636 * This device only has one clock, so make the sample rates match. 1637 */ 1638 if (play->sample_rate != rec->sample_rate && 1639 usemode == (AUMODE_PLAY | AUMODE_RECORD)) { 1640 if (setmode == AUMODE_PLAY) { 1641 rec->sample_rate = play->sample_rate; 1642 setmode |= AUMODE_RECORD; 1643 } else if (setmode == AUMODE_RECORD) { 1644 play->sample_rate = rec->sample_rate; 1645 setmode |= AUMODE_PLAY; 1646 } else 1647 return EINVAL; 1648 } 1649 1650 for (mode = AUMODE_RECORD; mode != -1; 1651 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) { 1652 if ((setmode & mode) == 0) 1653 continue; 1654 1655 p = mode == AUMODE_PLAY ? play : rec; 1656 if (p->sample_rate < 4000 || p->sample_rate > 50000) { 1657 DPRINTF("dbri_set_params: invalid rate %d\n", 1658 p->sample_rate); 1659 return EINVAL; 1660 } 1661 1662 fil = mode == AUMODE_PLAY ? pfil : rfil; 1663 DPRINTF("requested enc: %d rate: %d prec: %d chan: %d\n", p->encoding, 1664 p->sample_rate, p->precision, p->channels); 1665 if (auconv_set_converter(dbri_formats, DBRI_NFORMATS, 1666 mode, p, true, fil) < 0) { 1667 aprint_debug("dbri_set_params: auconv_set_converter failed\n"); 1668 return EINVAL; 1669 } 1670 if (fil->req_size > 0) 1671 p = &fil->filters[0].param; 1672 } 1673 1674 if (p == NULL) { 1675 DPRINTF("dbri_set_params: no parameters to set\n"); 1676 return 0; 1677 } 1678 1679 DPRINTF("native enc: %d rate: %d prec: %d chan: %d\n", p->encoding, 1680 p->sample_rate, p->precision, p->channels); 1681 1682 for (rate = 0; CS4215_FREQ[rate].freq; rate++) 1683 if (CS4215_FREQ[rate].freq == p->sample_rate) 1684 break; 1685 1686 if (CS4215_FREQ[rate].freq == 0) 1687 return (EINVAL); 1688 1689 /* set frequency */ 1690 sc->sc_mm.c.bcontrol[1] &= ~0x38; 1691 sc->sc_mm.c.bcontrol[1] |= CS4215_FREQ[rate].csval; 1692 sc->sc_mm.c.bcontrol[2] &= ~0x70; 1693 sc->sc_mm.c.bcontrol[2] |= CS4215_FREQ[rate].xtal; 1694 1695 switch (p->encoding) { 1696 case AUDIO_ENCODING_ULAW: 1697 sc->sc_mm.c.bcontrol[1] &= ~3; 1698 sc->sc_mm.c.bcontrol[1] |= CS4215_DFR_ULAW; 1699 break; 1700 case AUDIO_ENCODING_ALAW: 1701 sc->sc_mm.c.bcontrol[1] &= ~3; 1702 sc->sc_mm.c.bcontrol[1] |= CS4215_DFR_ALAW; 1703 break; 1704 case AUDIO_ENCODING_ULINEAR: 1705 sc->sc_mm.c.bcontrol[1] &= ~3; 1706 if (p->precision == 8) { 1707 sc->sc_mm.c.bcontrol[1] |= CS4215_DFR_LINEAR8; 1708 } else { 1709 sc->sc_mm.c.bcontrol[1] |= CS4215_DFR_LINEAR16; 1710 } 1711 break; 1712 case AUDIO_ENCODING_SLINEAR_BE: 1713 case AUDIO_ENCODING_SLINEAR: 1714 sc->sc_mm.c.bcontrol[1] &= ~3; 1715 sc->sc_mm.c.bcontrol[1] |= CS4215_DFR_LINEAR16; 1716 break; 1717 } 1718 1719 switch (p->channels) { 1720 case 1: 1721 sc->sc_mm.c.bcontrol[1] &= ~CS4215_DFR_STEREO; 1722 break; 1723 case 2: 1724 sc->sc_mm.c.bcontrol[1] |= CS4215_DFR_STEREO; 1725 break; 1726 } 1727 1728 return (0); 1729 } 1730 1731 static int 1732 dbri_round_blocksize(void *hdl, int bs, int mode, 1733 const audio_params_t *param) 1734 { 1735 1736 /* DBRI DMA segment size, rounded down to 32bit alignment */ 1737 return 0x1ffc; 1738 } 1739 1740 static int 1741 dbri_halt_output(void *hdl) 1742 { 1743 struct dbri_softc *sc = hdl; 1744 1745 if (!sc->sc_playing) 1746 return 0; 1747 1748 sc->sc_playing = 0; 1749 pipe_reset(sc, 4); 1750 return (0); 1751 } 1752 1753 static int 1754 dbri_getdev(void *hdl, struct audio_device *ret) 1755 { 1756 1757 *ret = dbri_device; 1758 return (0); 1759 } 1760 1761 static int 1762 dbri_set_port(void *hdl, mixer_ctrl_t *mc) 1763 { 1764 struct dbri_softc *sc = hdl; 1765 int latt = sc->sc_latt, ratt = sc->sc_ratt; 1766 1767 switch (mc->dev) { 1768 case DBRI_VOL_OUTPUT: /* master volume */ 1769 latt = (latt & 0xc0) | (63 - 1770 min(mc->un.value.level[AUDIO_MIXER_LEVEL_LEFT] >> 2, 63)); 1771 ratt = (ratt & 0xc0) | (63 - 1772 min(mc->un.value.level[AUDIO_MIXER_LEVEL_RIGHT] >> 2, 63)); 1773 break; 1774 case DBRI_ENABLE_MONO: /* built-in speaker */ 1775 if (mc->un.ord == 1) { 1776 ratt |= CS4215_SE; 1777 } else 1778 ratt &= ~CS4215_SE; 1779 break; 1780 case DBRI_ENABLE_HEADPHONE: /* headphones output */ 1781 if (mc->un.ord == 1) { 1782 latt |= CS4215_HE; 1783 } else 1784 latt &= ~CS4215_HE; 1785 break; 1786 case DBRI_ENABLE_LINE: /* line out */ 1787 if (mc->un.ord == 1) { 1788 latt |= CS4215_LE; 1789 } else 1790 latt &= ~CS4215_LE; 1791 break; 1792 case DBRI_VOL_MONITOR: 1793 if (mc->un.value.level[AUDIO_MIXER_LEVEL_LEFT] == 1794 sc->sc_monitor) 1795 return 0; 1796 sc->sc_monitor = mc->un.value.level[AUDIO_MIXER_LEVEL_LEFT]; 1797 break; 1798 case DBRI_INPUT_GAIN: 1799 sc->sc_linp = mc->un.value.level[AUDIO_MIXER_LEVEL_LEFT]; 1800 sc->sc_rinp = mc->un.value.level[AUDIO_MIXER_LEVEL_RIGHT]; 1801 break; 1802 case DBRI_INPUT_SELECT: 1803 if (mc->un.mask == sc->sc_input) 1804 return 0; 1805 sc->sc_input = mc->un.mask; 1806 break; 1807 } 1808 1809 sc->sc_latt = latt; 1810 sc->sc_ratt = ratt; 1811 1812 mmcodec_setgain(sc, 0); 1813 1814 return (0); 1815 } 1816 1817 static int 1818 dbri_get_port(void *hdl, mixer_ctrl_t *mc) 1819 { 1820 struct dbri_softc *sc = hdl; 1821 1822 switch (mc->dev) { 1823 case DBRI_VOL_OUTPUT: /* master volume */ 1824 mc->un.value.level[AUDIO_MIXER_LEVEL_LEFT] = 1825 (63 - (sc->sc_latt & 0x3f)) << 2; 1826 mc->un.value.level[AUDIO_MIXER_LEVEL_RIGHT] = 1827 (63 - (sc->sc_ratt & 0x3f)) << 2; 1828 return (0); 1829 case DBRI_ENABLE_MONO: /* built-in speaker */ 1830 mc->un.ord = (sc->sc_ratt & CS4215_SE) ? 1 : 0; 1831 return 0; 1832 case DBRI_ENABLE_HEADPHONE: /* headphones output */ 1833 mc->un.ord = (sc->sc_latt & CS4215_HE) ? 1 : 0; 1834 return 0; 1835 case DBRI_ENABLE_LINE: /* line out */ 1836 mc->un.ord = (sc->sc_latt & CS4215_LE) ? 1 : 0; 1837 return 0; 1838 case DBRI_VOL_MONITOR: 1839 mc->un.value.level[AUDIO_MIXER_LEVEL_LEFT] = sc->sc_monitor; 1840 return 0; 1841 case DBRI_INPUT_GAIN: 1842 mc->un.value.level[AUDIO_MIXER_LEVEL_LEFT] = sc->sc_linp; 1843 mc->un.value.level[AUDIO_MIXER_LEVEL_RIGHT] = sc->sc_rinp; 1844 return 0; 1845 case DBRI_INPUT_SELECT: 1846 mc->un.mask = sc->sc_input; 1847 return 0; 1848 } 1849 return (EINVAL); 1850 } 1851 1852 static int 1853 dbri_query_devinfo(void *hdl, mixer_devinfo_t *di) 1854 { 1855 1856 switch (di->index) { 1857 case DBRI_MONITOR_CLASS: 1858 di->mixer_class = DBRI_MONITOR_CLASS; 1859 strcpy(di->label.name, AudioCmonitor); 1860 di->type = AUDIO_MIXER_CLASS; 1861 di->next = di->prev = AUDIO_MIXER_LAST; 1862 return 0; 1863 case DBRI_OUTPUT_CLASS: 1864 di->mixer_class = DBRI_OUTPUT_CLASS; 1865 strcpy(di->label.name, AudioCoutputs); 1866 di->type = AUDIO_MIXER_CLASS; 1867 di->next = di->prev = AUDIO_MIXER_LAST; 1868 return 0; 1869 case DBRI_INPUT_CLASS: 1870 di->mixer_class = DBRI_INPUT_CLASS; 1871 strcpy(di->label.name, AudioCinputs); 1872 di->type = AUDIO_MIXER_CLASS; 1873 di->next = di->prev = AUDIO_MIXER_LAST; 1874 return 0; 1875 case DBRI_VOL_OUTPUT: /* master volume */ 1876 di->mixer_class = DBRI_OUTPUT_CLASS; 1877 di->next = di->prev = AUDIO_MIXER_LAST; 1878 strcpy(di->label.name, AudioNmaster); 1879 di->type = AUDIO_MIXER_VALUE; 1880 di->un.v.num_channels = 2; 1881 strcpy(di->un.v.units.name, AudioNvolume); 1882 return (0); 1883 case DBRI_INPUT_GAIN: /* input gain */ 1884 di->mixer_class = DBRI_INPUT_CLASS; 1885 di->next = di->prev = AUDIO_MIXER_LAST; 1886 strcpy(di->label.name, AudioNrecord); 1887 di->type = AUDIO_MIXER_VALUE; 1888 di->un.v.num_channels = 2; 1889 strcpy(di->un.v.units.name, AudioNvolume); 1890 return (0); 1891 case DBRI_VOL_MONITOR: /* monitor volume */ 1892 di->mixer_class = DBRI_MONITOR_CLASS; 1893 di->next = di->prev = AUDIO_MIXER_LAST; 1894 strcpy(di->label.name, AudioNmonitor); 1895 di->type = AUDIO_MIXER_VALUE; 1896 di->un.v.num_channels = 1; 1897 strcpy(di->un.v.units.name, AudioNvolume); 1898 return (0); 1899 case DBRI_ENABLE_MONO: /* built-in speaker */ 1900 di->mixer_class = DBRI_OUTPUT_CLASS; 1901 di->next = di->prev = AUDIO_MIXER_LAST; 1902 strcpy(di->label.name, AudioNmono); 1903 di->type = AUDIO_MIXER_ENUM; 1904 di->un.e.num_mem = 2; 1905 strcpy(di->un.e.member[0].label.name, AudioNoff); 1906 di->un.e.member[0].ord = 0; 1907 strcpy(di->un.e.member[1].label.name, AudioNon); 1908 di->un.e.member[1].ord = 1; 1909 return (0); 1910 case DBRI_ENABLE_HEADPHONE: /* headphones output */ 1911 di->mixer_class = DBRI_OUTPUT_CLASS; 1912 di->next = di->prev = AUDIO_MIXER_LAST; 1913 strcpy(di->label.name, AudioNheadphone); 1914 di->type = AUDIO_MIXER_ENUM; 1915 di->un.e.num_mem = 2; 1916 strcpy(di->un.e.member[0].label.name, AudioNoff); 1917 di->un.e.member[0].ord = 0; 1918 strcpy(di->un.e.member[1].label.name, AudioNon); 1919 di->un.e.member[1].ord = 1; 1920 return (0); 1921 case DBRI_ENABLE_LINE: /* line out */ 1922 di->mixer_class = DBRI_OUTPUT_CLASS; 1923 di->next = di->prev = AUDIO_MIXER_LAST; 1924 strcpy(di->label.name, AudioNline); 1925 di->type = AUDIO_MIXER_ENUM; 1926 di->un.e.num_mem = 2; 1927 strcpy(di->un.e.member[0].label.name, AudioNoff); 1928 di->un.e.member[0].ord = 0; 1929 strcpy(di->un.e.member[1].label.name, AudioNon); 1930 di->un.e.member[1].ord = 1; 1931 return (0); 1932 case DBRI_INPUT_SELECT: 1933 di->mixer_class = DBRI_INPUT_CLASS; 1934 strcpy(di->label.name, AudioNsource); 1935 di->type = AUDIO_MIXER_SET; 1936 di->prev = di->next = AUDIO_MIXER_LAST; 1937 di->un.s.num_mem = 2; 1938 strcpy(di->un.s.member[0].label.name, AudioNline); 1939 di->un.s.member[0].mask = 1 << 0; 1940 strcpy(di->un.s.member[1].label.name, AudioNmicrophone); 1941 di->un.s.member[1].mask = 1 << 1; 1942 return 0; 1943 } 1944 1945 return (ENXIO); 1946 } 1947 1948 static size_t 1949 dbri_round_buffersize(void *hdl, int dir, size_t bufsize) 1950 { 1951 #ifdef DBRI_BIG_BUFFER 1952 return 16*0x1ffc; /* use ~128KB buffer */ 1953 #else 1954 return bufsize; 1955 #endif 1956 } 1957 1958 static int 1959 dbri_get_props(void *hdl) 1960 { 1961 1962 return AUDIO_PROP_MMAP | AUDIO_PROP_FULLDUPLEX; 1963 } 1964 1965 static int 1966 dbri_trigger_output(void *hdl, void *start, void *end, int blksize, 1967 void (*intr)(void *), void *intrarg, 1968 const struct audio_params *param) 1969 { 1970 struct dbri_softc *sc = hdl; 1971 unsigned long count, num; 1972 1973 if (sc->sc_playing) 1974 return 0; 1975 1976 count = (unsigned long)(((char *)end - (char *)start)); 1977 num = count / blksize; 1978 1979 DPRINTF("trigger_output(%lx %lx) : %d %ld %ld\n", 1980 (unsigned long)intr, 1981 (unsigned long)intrarg, blksize, count, num); 1982 1983 sc->sc_params = *param; 1984 1985 if (sc->sc_recording == 0) { 1986 /* do not muck with the codec when it's already in use */ 1987 if (mmcodec_setcontrol(sc) != 0) 1988 return -1; 1989 mmcodec_init_data(sc); 1990 } 1991 1992 /* 1993 * always use DMA descriptor 0 for output 1994 * no need to allocate them dynamically since we only ever have 1995 * exactly one input stream and exactly one output stream 1996 */ 1997 setup_ring_xmit(sc, 4, 0, num, blksize, intr, intrarg); 1998 sc->sc_playing = 1; 1999 return 0; 2000 } 2001 2002 static int 2003 dbri_halt_input(void *cookie) 2004 { 2005 struct dbri_softc *sc = cookie; 2006 2007 if (!sc->sc_recording) 2008 return 0; 2009 2010 sc->sc_recording = 0; 2011 pipe_reset(sc, 6); 2012 return 0; 2013 } 2014 2015 static int 2016 dbri_trigger_input(void *hdl, void *start, void *end, int blksize, 2017 void (*intr)(void *), void *intrarg, 2018 const struct audio_params *param) 2019 { 2020 struct dbri_softc *sc = hdl; 2021 unsigned long count, num; 2022 2023 if (sc->sc_recording) 2024 return 0; 2025 2026 count = (unsigned long)(((char *)end - (char *)start)); 2027 num = count / blksize; 2028 2029 DPRINTF("trigger_input(%lx %lx) : %d %ld %ld\n", 2030 (unsigned long)intr, 2031 (unsigned long)intrarg, blksize, count, num); 2032 2033 sc->sc_params = *param; 2034 2035 if (sc->sc_playing == 0) { 2036 2037 /* 2038 * we don't support different parameters for playing and 2039 * recording anyway so don't bother whacking the codec if 2040 * it's already set up 2041 */ 2042 mmcodec_setcontrol(sc); 2043 mmcodec_init_data(sc); 2044 } 2045 2046 sc->sc_recording = 1; 2047 setup_ring_recv(sc, 6, 1, num, blksize, intr, intrarg); 2048 return 0; 2049 } 2050 2051 2052 static u_int32_t 2053 reverse_bytes(u_int32_t b, int len) 2054 { 2055 switch (len) { 2056 case 32: 2057 b = ((b & 0xffff0000) >> 16) | ((b & 0x0000ffff) << 16); 2058 case 16: 2059 b = ((b & 0xff00ff00) >> 8) | ((b & 0x00ff00ff) << 8); 2060 case 8: 2061 b = ((b & 0xf0f0f0f0) >> 4) | ((b & 0x0f0f0f0f) << 4); 2062 case 4: 2063 b = ((b & 0xcccccccc) >> 2) | ((b & 0x33333333) << 2); 2064 case 2: 2065 b = ((b & 0xaaaaaaaa) >> 1) | ((b & 0x55555555) << 1); 2066 case 1: 2067 case 0: 2068 break; 2069 default: 2070 DPRINTF("reverse_bytes: unsupported length\n"); 2071 }; 2072 2073 return (b); 2074 } 2075 2076 static void * 2077 dbri_malloc(void *v, int dir, size_t s, struct malloc_type *mt, int flags) 2078 { 2079 struct dbri_softc *sc = v; 2080 struct dbri_desc *dd = &sc->sc_desc[sc->sc_desc_used]; 2081 int rseg; 2082 2083 if (bus_dmamap_create(sc->sc_dmat, s, 1, s, 0, BUS_DMA_NOWAIT, 2084 &dd->dmamap) == 0) { 2085 if (bus_dmamem_alloc(sc->sc_dmat, s, 0, 0, &dd->dmaseg, 2086 1, &rseg, BUS_DMA_NOWAIT) == 0) { 2087 if (bus_dmamem_map(sc->sc_dmat, &dd->dmaseg, rseg, s, 2088 &dd->buf, BUS_DMA_NOWAIT|BUS_DMA_COHERENT) == 0) { 2089 if (dd->buf != NULL) { 2090 if (bus_dmamap_load(sc->sc_dmat, 2091 dd->dmamap, dd->buf, s, NULL, 2092 BUS_DMA_NOWAIT) == 0) { 2093 dd->len = s; 2094 dd->busy = 0; 2095 dd->callback = NULL; 2096 dd->dmabase = 2097 dd->dmamap->dm_segs[0].ds_addr; 2098 DPRINTF("dbri_malloc: using buffer %d %08x\n", 2099 sc->sc_desc_used, (uint32_t)dd->buf); 2100 sc->sc_desc_used++; 2101 return dd->buf; 2102 } else 2103 aprint_error("dbri_malloc: load failed\n"); 2104 } else 2105 aprint_error("dbri_malloc: map returned NULL\n"); 2106 } else 2107 aprint_error("dbri_malloc: map failed\n"); 2108 bus_dmamem_free(sc->sc_dmat, &dd->dmaseg, rseg); 2109 } else 2110 aprint_error("dbri_malloc: malloc() failed\n"); 2111 bus_dmamap_destroy(sc->sc_dmat, dd->dmamap); 2112 } else 2113 aprint_error("dbri_malloc: bus_dmamap_create() failed\n"); 2114 return NULL; 2115 } 2116 2117 static void 2118 dbri_free(void *v, void *p, struct malloc_type *mt) 2119 { 2120 free(p, mt); 2121 } 2122 2123 static paddr_t 2124 dbri_mappage(void *v, void *mem, off_t off, int prot) 2125 { 2126 struct dbri_softc *sc = v;; 2127 int current; 2128 2129 if (off < 0) 2130 return -1; 2131 2132 current = 0; 2133 while ((current < sc->sc_desc_used) && 2134 (sc->sc_desc[current].buf != mem)) 2135 current++; 2136 2137 if (current < sc->sc_desc_used) { 2138 return bus_dmamem_mmap(sc->sc_dmat, 2139 &sc->sc_desc[current].dmaseg, 1, off, prot, BUS_DMA_WAITOK); 2140 } 2141 2142 return -1; 2143 } 2144 2145 static int 2146 dbri_open(void *cookie, int flags) 2147 { 2148 struct dbri_softc *sc = cookie; 2149 2150 DPRINTF("%s: %d\n", __func__, sc->sc_refcount); 2151 2152 if (sc->sc_refcount == 0) 2153 dbri_bring_up(sc); 2154 2155 sc->sc_refcount++; 2156 2157 return 0; 2158 } 2159 2160 static void 2161 dbri_close(void *cookie) 2162 { 2163 struct dbri_softc *sc = cookie; 2164 2165 DPRINTF("%s: %d\n", __func__, sc->sc_refcount); 2166 2167 sc->sc_refcount--; 2168 KASSERT(sc->sc_refcount >= 0); 2169 if (sc->sc_refcount > 0) 2170 return; 2171 2172 dbri_set_power(sc, 0); 2173 sc->sc_playing = 0; 2174 sc->sc_recording = 0; 2175 } 2176 2177 static void 2178 dbri_powerhook(int why, void *cookie) 2179 { 2180 struct dbri_softc *sc = cookie; 2181 2182 if (why == sc->sc_pmgrstate) 2183 return; 2184 2185 switch(why) 2186 { 2187 case PWR_SUSPEND: 2188 dbri_set_power(sc, 0); 2189 break; 2190 case PWR_RESUME: 2191 if (sc->sc_powerstate != 0) 2192 break; 2193 aprint_verbose("resume: %d\n", sc->sc_refcount); 2194 sc->sc_pmgrstate = PWR_RESUME; 2195 if (sc->sc_playing) { 2196 volatile u_int32_t *cmd; 2197 int s; 2198 2199 dbri_bring_up(sc); 2200 s = splsched(); 2201 cmd = dbri_command_lock(sc); 2202 *(cmd++) = DBRI_CMD(DBRI_COMMAND_SDP, 2203 0, sc->sc_pipe[4].sdp | 2204 DBRI_SDP_VALID_POINTER | 2205 DBRI_SDP_EVERY | DBRI_SDP_CLEAR); 2206 *(cmd++) = sc->sc_dmabase + 2207 dbri_dma_off(xmit, 0); 2208 dbri_command_send(sc, cmd); 2209 splx(s); 2210 } 2211 break; 2212 default: 2213 return; 2214 } 2215 sc->sc_pmgrstate = why; 2216 } 2217 2218 #endif /* NAUDIO > 0 */ 2219
Indexes created Fri Sep 26 08:10:20 GMT 2025