dbri.c revision 1.18
1 /* $NetBSD: dbri.c,v 1.18 2008/04/05 18:35:31 cegger Exp $ */ 2 3 /* 4 * Copyright (C) 1997 Rudolf Koenig (rfkoenig (at) immd4.informatik.uni-erlangen.de) 5 * Copyright (c) 1998, 1999 Brent Baccala (baccala (at) freesoft.org) 6 * Copyright (c) 2001, 2002 Jared D. McNeill <jmcneill (at) netbsd.org> 7 * Copyright (c) 2005, 2007 Michael Lorenz <macallan (at) netbsd.org> 8 * All rights reserved. 9 * 10 * This driver is losely based on a Linux driver written by Rudolf Koenig and 11 * Brent Baccala who kindly gave their permission to use their code in a 12 * BSD-licensed driver. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions 16 * are met: 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in the 21 * documentation and/or other materials provided with the distribution. 22 * 3. All advertising materials mentioning features or use of this software 23 * must display the following acknowledgement: 24 * This product includes software developed by Rudolf Koenig, Brent 25 * Baccala, Jared D. McNeill. 26 * 4. Neither the name of the author nor the names of any contributors may 27 * be used to endorse or promote products derived from this software 28 * without specific prior written permission. 29 * 30 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 31 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 33 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 36 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 37 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 38 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 39 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 40 * SUCH DAMAGE. 41 * 42 */ 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: dbri.c,v 1.18 2008/04/05 18:35:31 cegger Exp $"); 46 47 #include "audio.h" 48 #if NAUDIO > 0 49 50 #include <sys/param.h> 51 #include <sys/systm.h> 52 #include <sys/errno.h> 53 #include <sys/device.h> 54 #include <sys/malloc.h> 55 #include <sys/proc.h> 56 #include <sys/kernel.h> 57 #include <sys/bus.h> 58 #include <sys/intr.h> 59 60 #include <dev/sbus/sbusvar.h> 61 #include <sparc/sparc/auxreg.h> 62 #include <machine/autoconf.h> 63 64 #include <sys/audioio.h> 65 #include <dev/audio_if.h> 66 #include <dev/auconv.h> 67 68 #include <dev/ic/cs4215reg.h> 69 #include <dev/ic/cs4215var.h> 70 #include <dev/sbus/dbrireg.h> 71 #include <dev/sbus/dbrivar.h> 72 73 #include "opt_sbus_dbri.h" 74 75 #define DBRI_ROM_NAME_PREFIX "SUNW,DBRI" 76 77 #ifdef DBRI_DEBUG 78 # define DPRINTF aprint_normal 79 #else 80 # define DPRINTF while (0) printf 81 #endif 82 83 static const char *dbri_supported[] = { 84 "e", 85 "s3", 86 "" 87 }; 88 89 enum ms { 90 CHImaster, 91 CHIslave 92 }; 93 94 enum io { 95 PIPEinput, 96 PIPEoutput 97 }; 98 99 /* 100 * Function prototypes 101 */ 102 103 /* softc stuff */ 104 static void dbri_attach_sbus(struct device *, struct device *, void *); 105 static int dbri_match_sbus(struct device *, struct cfdata *, void *); 106 107 static void dbri_config_interrupts(struct device *); 108 109 /* interrupt handler */ 110 static int dbri_intr(void *); 111 static void dbri_softint(void *); 112 113 /* supporting subroutines */ 114 static int dbri_init(struct dbri_softc *); 115 static int dbri_reset(struct dbri_softc *); 116 static volatile u_int32_t *dbri_command_lock(struct dbri_softc *); 117 static void dbri_command_send(struct dbri_softc *, volatile u_int32_t *); 118 static void dbri_process_interrupt_buffer(struct dbri_softc *); 119 static void dbri_process_interrupt(struct dbri_softc *, int32_t); 120 121 /* mmcodec subroutines */ 122 static int mmcodec_init(struct dbri_softc *); 123 static void mmcodec_init_data(struct dbri_softc *); 124 static void mmcodec_pipe_init(struct dbri_softc *); 125 static void mmcodec_default(struct dbri_softc *); 126 static void mmcodec_setgain(struct dbri_softc *, int); 127 static int mmcodec_setcontrol(struct dbri_softc *); 128 129 /* chi subroutines */ 130 static void chi_reset(struct dbri_softc *, enum ms, int); 131 132 /* pipe subroutines */ 133 static void pipe_setup(struct dbri_softc *, int, int); 134 static void pipe_reset(struct dbri_softc *, int); 135 static void pipe_receive_fixed(struct dbri_softc *, int, 136 volatile u_int32_t *); 137 static void pipe_transmit_fixed(struct dbri_softc *, int, u_int32_t); 138 139 static void pipe_ts_link(struct dbri_softc *, int, enum io, int, int, int); 140 static int pipe_active(struct dbri_softc *, int); 141 142 /* audio(9) stuff */ 143 static int dbri_query_encoding(void *, struct audio_encoding *); 144 static int dbri_set_params(void *, int, int, struct audio_params *, 145 struct audio_params *,stream_filter_list_t *, stream_filter_list_t *); 146 static int dbri_round_blocksize(void *, int, int, const audio_params_t *); 147 static int dbri_halt_output(void *); 148 static int dbri_halt_input(void *); 149 static int dbri_getdev(void *, struct audio_device *); 150 static int dbri_set_port(void *, mixer_ctrl_t *); 151 static int dbri_get_port(void *, mixer_ctrl_t *); 152 static int dbri_query_devinfo(void *, mixer_devinfo_t *); 153 static size_t dbri_round_buffersize(void *, int, size_t); 154 static int dbri_get_props(void *); 155 static int dbri_open(void *, int); 156 static void dbri_close(void *); 157 158 static void setup_ring_xmit(struct dbri_softc *, int, int, int, int, 159 void (*)(void *), void *); 160 static void setup_ring_recv(struct dbri_softc *, int, int, int, int, 161 void (*)(void *), void *); 162 163 static int dbri_trigger_output(void *, void *, void *, int, 164 void (*)(void *), void *, const struct audio_params *); 165 static int dbri_trigger_input(void *, void *, void *, int, 166 void (*)(void *), void *, const struct audio_params *); 167 168 static void *dbri_malloc(void *, int, size_t, struct malloc_type *, int); 169 static void dbri_free(void *, void *, struct malloc_type *); 170 static paddr_t dbri_mappage(void *, void *, off_t, int); 171 static void dbri_set_power(struct dbri_softc *, int); 172 static void dbri_bring_up(struct dbri_softc *); 173 static void dbri_powerhook(int, void *); 174 175 /* stupid support routines */ 176 static u_int32_t reverse_bytes(u_int32_t, int); 177 178 struct audio_device dbri_device = { 179 "CS4215", 180 "", 181 "dbri" 182 }; 183 184 struct audio_hw_if dbri_hw_if = { 185 dbri_open, 186 dbri_close, 187 NULL, /* drain */ 188 dbri_query_encoding, 189 dbri_set_params, 190 dbri_round_blocksize, 191 NULL, /* commit_settings */ 192 NULL, /* init_output */ 193 NULL, /* init_input */ 194 NULL, /* start_output */ 195 NULL, /* start_input */ 196 dbri_halt_output, 197 dbri_halt_input, 198 NULL, /* speaker_ctl */ 199 dbri_getdev, 200 NULL, /* setfd */ 201 dbri_set_port, 202 dbri_get_port, 203 dbri_query_devinfo, 204 dbri_malloc, 205 dbri_free, 206 dbri_round_buffersize, 207 dbri_mappage, 208 dbri_get_props, 209 dbri_trigger_output, 210 dbri_trigger_input 211 }; 212 213 CFATTACH_DECL(dbri, sizeof(struct dbri_softc), 214 dbri_match_sbus, dbri_attach_sbus, NULL, NULL); 215 216 #define DBRI_NFORMATS 4 217 static const struct audio_format dbri_formats[DBRI_NFORMATS] = { 218 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_SLINEAR_BE, 16, 16, 219 2, AUFMT_STEREO, 8, {8000, 9600, 11025, 16000, 22050, 32000, 44100, 220 48000}}, 221 /* {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_ULAW, 8, 8, 222 2, AUFMT_STEREO, 8, {8000, 9600, 11025, 16000, 22050, 32000, 44100, 223 48000}}, 224 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_ALAW, 8, 8, 225 2, AUFMT_STEREO, 8, {8000, 9600, 11025, 16000, 22050, 32000, 44100, 226 48000}}, 227 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_ULINEAR, 8, 8, 228 2, AUFMT_STEREO, 8, {8000, 9600, 11025, 16000, 22050, 32000, 44100, 229 48000}},*/ 230 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_ULAW, 8, 8, 231 1, AUFMT_MONAURAL, 8, {8000, 9600, 11025, 16000, 22050, 32000, 44100, 232 48000}}, 233 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_ALAW, 8, 8, 234 1, AUFMT_MONAURAL, 8, {8000, 9600, 11025, 16000, 22050, 32000, 44100, 235 48000}}, 236 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_ULINEAR, 8, 8, 237 1, AUFMT_MONAURAL, 8, {8000, 9600, 11025, 16000, 22050, 32000, 44100, 238 48000}}, 239 }; 240 241 enum { 242 DBRI_OUTPUT_CLASS, 243 DBRI_VOL_OUTPUT, 244 DBRI_ENABLE_MONO, 245 DBRI_ENABLE_HEADPHONE, 246 DBRI_ENABLE_LINE, 247 DBRI_MONITOR_CLASS, 248 DBRI_VOL_MONITOR, 249 DBRI_INPUT_CLASS, 250 DBRI_INPUT_GAIN, 251 DBRI_INPUT_SELECT, 252 DBRI_RECORD_CLASS, 253 DBRI_ENUM_LAST 254 }; 255 256 /* 257 * Autoconfig routines 258 */ 259 static int 260 dbri_match_sbus(struct device *parent, struct cfdata *match, void *aux) 261 { 262 struct sbus_attach_args *sa = aux; 263 char *ver; 264 int i; 265 266 if (strncmp(DBRI_ROM_NAME_PREFIX, sa->sa_name, 9)) 267 return (0); 268 269 ver = &sa->sa_name[9]; 270 271 for (i = 0; dbri_supported[i][0] != '\0'; i++) 272 if (strcmp(dbri_supported[i], ver) == 0) 273 return (1); 274 275 return (0); 276 } 277 278 static void 279 dbri_attach_sbus(struct device *parent, struct device *self, void *aux) 280 { 281 struct dbri_softc *sc = (struct dbri_softc *)self; 282 struct sbus_attach_args *sa = aux; 283 bus_space_handle_t ioh; 284 bus_size_t size; 285 int error, rseg, pwr, i; 286 char *ver = &sa->sa_name[9]; 287 288 sc->sc_iot = sa->sa_bustag; 289 sc->sc_dmat = sa->sa_dmatag; 290 sc->sc_powerstate = 1; 291 292 pwr = prom_getpropint(sa->sa_node,"pwr-on-auxio",0); 293 aprint_normal(": rev %s\n", ver); 294 295 if (pwr) { 296 /* 297 * we can control DBRI power via auxio and we're initially 298 * powered down 299 */ 300 301 sc->sc_have_powerctl = 1; 302 sc->sc_powerstate = 0; 303 dbri_set_power(sc, 1); 304 powerhook_establish(device_xname(self), dbri_powerhook, sc); 305 } else { 306 /* we can't control power so we're always up */ 307 sc->sc_have_powerctl = 0; 308 sc->sc_powerstate = 1; 309 } 310 311 for (i = 0; i < DBRI_NUM_DESCRIPTORS; i++) { 312 sc->sc_desc[i].softint = softint_establish(SOFTINT_SERIAL, 313 dbri_softint, &sc->sc_desc[i]); 314 } 315 316 if (sa->sa_npromvaddrs) 317 ioh = (bus_space_handle_t)sa->sa_promvaddrs[0]; 318 else { 319 if (sbus_bus_map(sa->sa_bustag, sa->sa_slot, 320 sa->sa_offset, sa->sa_size, 321 BUS_SPACE_MAP_LINEAR, /*0,*/ &ioh) != 0) { 322 aprint_error("%s @ sbus: cannot map registers\n", 323 device_xname(self)); 324 return; 325 } 326 } 327 328 sc->sc_ioh = ioh; 329 330 size = sizeof(struct dbri_dma); 331 332 /* get a DMA handle */ 333 if ((error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, 334 BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) { 335 aprint_error_dev(self, "DMA map create error %d\n", 336 error); 337 return; 338 } 339 340 /* allocate DMA buffer */ 341 if ((error = bus_dmamem_alloc(sc->sc_dmat, size, 0, 0, &sc->sc_dmaseg, 342 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 343 aprint_error_dev(self, "DMA buffer alloc error %d\n", 344 error); 345 return; 346 } 347 348 /* map DMA buffer into CPU addressable space */ 349 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_dmaseg, rseg, size, 350 &sc->sc_membase, 351 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 352 aprint_error_dev(self, "DMA buffer map error %d\n", 353 error); 354 return; 355 } 356 357 /* load the buffer */ 358 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, 359 sc->sc_membase, size, NULL, 360 BUS_DMA_NOWAIT)) != 0) { 361 aprint_error_dev(self, "DMA buffer map load error %d\n", 362 error); 363 bus_dmamem_unmap(sc->sc_dmat, sc->sc_membase, size); 364 bus_dmamem_free(sc->sc_dmat, &sc->sc_dmaseg, rseg); 365 return; 366 } 367 368 /* map the registers into memory */ 369 370 /* kernel virtual address of DMA buffer */ 371 sc->sc_dma = (struct dbri_dma *)sc->sc_membase; 372 /* physical address of DMA buffer */ 373 sc->sc_dmabase = sc->sc_dmamap->dm_segs[0].ds_addr; 374 sc->sc_bufsiz = size; 375 376 sbus_establish(&sc->sc_sd, &sc->sc_dev); 377 378 bus_intr_establish(sa->sa_bustag, sa->sa_pri, IPL_SCHED, dbri_intr, 379 sc); 380 381 sc->sc_locked = 0; 382 sc->sc_desc_used = 0; 383 sc->sc_refcount = 0; 384 sc->sc_playing = 0; 385 sc->sc_recording = 0; 386 sc->sc_pmgrstate = PWR_RESUME; 387 config_interrupts(self, &dbri_config_interrupts); 388 389 return; 390 } 391 392 /* 393 * lowlevel routine to switch power for the DBRI chip 394 */ 395 static void 396 dbri_set_power(struct dbri_softc *sc, int state) 397 { 398 int s; 399 400 if (sc->sc_have_powerctl == 0) 401 return; 402 if (sc->sc_powerstate == state) 403 return; 404 405 if (state) { 406 DPRINTF("%s: waiting to power up... ", device_xname(&sc->sc_dev)); 407 s = splhigh(); 408 *AUXIO4M_REG |= (AUXIO4M_MMX); 409 splx(s); 410 delay(10000); 411 DPRINTF("done (%02x)\n", *AUXIO4M_REG); 412 } else { 413 DPRINTF("%s: powering down\n", device_xname(&sc->sc_dev)); 414 s = splhigh(); 415 *AUXIO4M_REG &= ~AUXIO4M_MMX; 416 splx(s); 417 DPRINTF("done (%02x})\n", *AUXIO4M_REG); 418 } 419 sc->sc_powerstate = state; 420 } 421 422 /* 423 * power up and re-initialize the chip 424 */ 425 static void 426 dbri_bring_up(struct dbri_softc *sc) 427 { 428 429 if (sc->sc_have_powerctl == 0) 430 return; 431 432 if (sc->sc_powerstate == 1) 433 return; 434 435 /* ok, we really need to do something */ 436 dbri_set_power(sc, 1); 437 438 /* 439 * re-initialize the chip but skip all the probing, don't overwrite 440 * any other settings either 441 */ 442 dbri_init(sc); 443 mmcodec_setgain(sc, 1); 444 mmcodec_pipe_init(sc); 445 mmcodec_init_data(sc); 446 mmcodec_setgain(sc, 0); 447 } 448 449 static void 450 dbri_config_interrupts(struct device *dev) 451 { 452 struct dbri_softc *sc = (struct dbri_softc *)dev; 453 454 dbri_init(sc); 455 mmcodec_init(sc); 456 457 /* Attach ourselves to the high level audio interface */ 458 audio_attach_mi(&dbri_hw_if, sc, &sc->sc_dev); 459 460 /* power down until open() */ 461 dbri_set_power(sc, 0); 462 return; 463 } 464 465 static int 466 dbri_intr(void *hdl) 467 { 468 struct dbri_softc *sc = hdl; 469 bus_space_tag_t iot = sc->sc_iot; 470 bus_space_handle_t ioh = sc->sc_ioh; 471 int x; 472 473 /* clear interrupt */ 474 x = bus_space_read_4(iot, ioh, DBRI_REG1); 475 if (x & (DBRI_MRR | DBRI_MLE | DBRI_LBG | DBRI_MBE)) { 476 u_int32_t tmp; 477 478 if (x & DBRI_MRR) 479 aprint_debug_dev(&sc->sc_dev, "multiple ack error on sbus\n"); 480 if (x & DBRI_MLE) 481 aprint_debug_dev(&sc->sc_dev, "multiple late error on sbus\n"); 482 if (x & DBRI_LBG) 483 aprint_debug_dev(&sc->sc_dev, "lost bus grant on sbus\n"); 484 if (x & DBRI_MBE) 485 aprint_debug_dev(&sc->sc_dev, "burst error on sbus\n"); 486 487 /* 488 * Some of these errors disable the chip's circuitry. 489 * Re-enable the circuitry and keep on going. 490 */ 491 492 tmp = bus_space_read_4(iot, ioh, DBRI_REG0); 493 tmp &= ~(DBRI_DISABLE_MASTER); 494 bus_space_write_4(iot, ioh, DBRI_REG0, tmp); 495 } 496 497 #if 0 498 if (!x & 1) /* XXX: DBRI_INTR_REQ */ 499 return (1); 500 #endif 501 502 dbri_process_interrupt_buffer(sc); 503 504 return (1); 505 } 506 507 static void 508 dbri_softint(void *cookie) 509 { 510 struct dbri_desc *dd = cookie; 511 512 if (dd->callback != NULL) 513 dd->callback(dd->callback_args); 514 } 515 516 static int 517 dbri_init(struct dbri_softc *sc) 518 { 519 bus_space_tag_t iot = sc->sc_iot; 520 bus_space_handle_t ioh = sc->sc_ioh; 521 u_int32_t reg; 522 volatile u_int32_t *cmd; 523 bus_addr_t dmaaddr; 524 int n; 525 526 dbri_reset(sc); 527 528 cmd = dbri_command_lock(sc); 529 530 /* XXX: Initialize interrupt ring buffer */ 531 sc->sc_dma->intr[0] = (u_int32_t)sc->sc_dmabase + dbri_dma_off(intr, 0); 532 sc->sc_irqp = 1; 533 534 /* Initialize pipes */ 535 for (n = 0; n < DBRI_PIPE_MAX; n++) 536 sc->sc_pipe[n].desc = sc->sc_pipe[n].next = -1; 537 538 for (n = 1; n < DBRI_INT_BLOCKS; n++) { 539 sc->sc_dma->intr[n] = 0; 540 } 541 542 /* Disable all SBus bursts */ 543 /* XXX 16 byte bursts cause errors, the rest works */ 544 reg = bus_space_read_4(iot, ioh, DBRI_REG0); 545 546 /*reg &= ~(DBRI_BURST_4 | DBRI_BURST_8 | DBRI_BURST_16);*/ 547 reg |= (DBRI_BURST_4 | DBRI_BURST_8); 548 bus_space_write_4(iot, ioh, DBRI_REG0, reg); 549 550 /* setup interrupt queue */ 551 dmaaddr = (u_int32_t)sc->sc_dmabase + dbri_dma_off(intr, 0); 552 *(cmd++) = DBRI_CMD(DBRI_COMMAND_IIQ, 0, 0); 553 *(cmd++) = dmaaddr; 554 555 dbri_command_send(sc, cmd); 556 return (0); 557 } 558 559 static int 560 dbri_reset(struct dbri_softc *sc) 561 { 562 int bail = 0; 563 564 bus_space_tag_t iot = sc->sc_iot; 565 bus_space_handle_t ioh = sc->sc_ioh; 566 567 bus_space_write_4(iot, ioh, DBRI_REG0, DBRI_SOFT_RESET); 568 while ((bus_space_read_4(iot, ioh, DBRI_REG0) & DBRI_SOFT_RESET) && 569 (bail < 100000)) { 570 bail++; 571 delay(10); 572 } 573 if (bail == 100000) 574 aprint_error_dev(&sc->sc_dev, "reset timed out\n"); 575 return (0); 576 } 577 578 static volatile u_int32_t * 579 dbri_command_lock(struct dbri_softc *sc) 580 { 581 582 if (sc->sc_locked) 583 aprint_debug_dev(&sc->sc_dev, "command buffer locked\n"); 584 585 sc->sc_locked++; 586 587 return (&sc->sc_dma->command[0]); 588 } 589 590 static void 591 dbri_command_send(struct dbri_softc *sc, volatile u_int32_t *cmd) 592 { 593 bus_space_handle_t ioh = sc->sc_ioh; 594 bus_space_tag_t iot = sc->sc_iot; 595 int maxloops = 1000000; 596 int x; 597 598 x = splsched(); 599 600 sc->sc_locked--; 601 602 if (sc->sc_locked != 0) { 603 aprint_error_dev(&sc->sc_dev, "command buffer improperly locked\n"); 604 } else if ((cmd - &sc->sc_dma->command[0]) >= DBRI_NUM_COMMANDS - 1) { 605 aprint_error_dev(&sc->sc_dev, "command buffer overflow\n"); 606 } else { 607 *(cmd++) = DBRI_CMD(DBRI_COMMAND_PAUSE, 0, 0); 608 *(cmd++) = DBRI_CMD(DBRI_COMMAND_WAIT, 1, 0); 609 sc->sc_waitseen = 0; 610 bus_space_write_4(iot, ioh, DBRI_REG8, sc->sc_dmabase); 611 while ((--maxloops) > 0 && 612 (bus_space_read_4(iot, ioh, DBRI_REG0) 613 & DBRI_COMMAND_VALID)) { 614 bus_space_barrier(iot, ioh, DBRI_REG0, 4, 615 BUS_SPACE_BARRIER_READ); 616 delay(1000); 617 } 618 619 if (maxloops == 0) { 620 aprint_error_dev(&sc->sc_dev, 621 "chip never completed command buffer\n"); 622 } else { 623 624 DPRINTF("%s: command completed\n", 625 device_xname(&sc->sc_dev)); 626 627 while ((--maxloops) > 0 && (!sc->sc_waitseen)) 628 dbri_process_interrupt_buffer(sc); 629 if (maxloops == 0) { 630 aprint_error_dev(&sc->sc_dev, "chip never acked WAIT\n"); 631 } 632 } 633 } 634 635 splx(x); 636 637 return; 638 } 639 640 static void 641 dbri_process_interrupt_buffer(struct dbri_softc *sc) 642 { 643 int32_t i; 644 645 while ((i = sc->sc_dma->intr[sc->sc_irqp]) != 0) { 646 sc->sc_dma->intr[sc->sc_irqp] = 0; 647 sc->sc_irqp++; 648 649 if (sc->sc_irqp == DBRI_INT_BLOCKS) 650 sc->sc_irqp = 1; 651 else if ((sc->sc_irqp & (DBRI_INT_BLOCKS - 1)) == 0) 652 sc->sc_irqp++; 653 654 dbri_process_interrupt(sc, i); 655 } 656 657 return; 658 } 659 660 static void 661 dbri_process_interrupt(struct dbri_softc *sc, int32_t i) 662 { 663 #if 0 664 const int liu_states[] = { 1, 0, 8, 3, 4, 5, 6, 7 }; 665 #endif 666 int val = DBRI_INTR_GETVAL(i); 667 int channel = DBRI_INTR_GETCHAN(i); 668 int command = DBRI_INTR_GETCMD(i); 669 int code = DBRI_INTR_GETCODE(i); 670 #if 0 671 int rval = DBRI_INTR_GETRVAL(i); 672 #endif 673 if (channel == DBRI_INTR_CMD && command == DBRI_COMMAND_WAIT) 674 sc->sc_waitseen++; 675 676 switch (code) { 677 case DBRI_INTR_XCMP: /* transmission complete */ 678 { 679 int td; 680 struct dbri_desc *dd; 681 682 td = sc->sc_pipe[channel].desc; 683 dd = &sc->sc_desc[td]; 684 685 if (dd->callback != NULL) 686 softint_schedule(dd->softint); 687 break; 688 } 689 case DBRI_INTR_FXDT: /* fixed data change */ 690 DPRINTF("dbri_intr: Fixed data change (%d: %x)\n", channel, 691 val); 692 #if 0 693 printf("reg: %08x\n", sc->sc_mm.status); 694 #endif 695 if (sc->sc_pipe[channel].sdp & DBRI_SDP_MSB) 696 val = reverse_bytes(val, sc->sc_pipe[channel].length); 697 if (sc->sc_pipe[channel].prec) 698 *(sc->sc_pipe[channel].prec) = val; 699 #ifndef DBRI_SPIN 700 DPRINTF("%s: wakeup %p\n", device_xname(&sc->sc_dev), sc); 701 wakeup(sc); 702 #endif 703 break; 704 case DBRI_INTR_SBRI: 705 DPRINTF("dbri_intr: SBRI\n"); 706 break; 707 case DBRI_INTR_BRDY: 708 { 709 int td; 710 struct dbri_desc *dd; 711 712 td = sc->sc_pipe[channel].desc; 713 dd = &sc->sc_desc[td]; 714 715 if (dd->callback != NULL) 716 softint_schedule(dd->softint); 717 break; 718 } 719 case DBRI_INTR_UNDR: 720 { 721 volatile u_int32_t *cmd; 722 int td = sc->sc_pipe[channel].desc; 723 724 DPRINTF("%s: DBRI_INTR_UNDR\n", device_xname(&sc->sc_dev)); 725 726 sc->sc_dma->xmit[td].status = 0; 727 728 cmd = dbri_command_lock(sc); 729 *(cmd++) = DBRI_CMD(DBRI_COMMAND_SDP, 0, 730 sc->sc_pipe[channel].sdp | 731 DBRI_SDP_VALID_POINTER | 732 DBRI_SDP_CLEAR | 733 DBRI_SDP_2SAME); 734 *(cmd++) = sc->sc_dmabase + dbri_dma_off(xmit, td); 735 dbri_command_send(sc, cmd); 736 break; 737 } 738 case DBRI_INTR_CMDI: 739 DPRINTF("ok"); 740 break; 741 default: 742 743 aprint_error_dev(&sc->sc_dev, "unknown interrupt code %d\n", 744 code); 745 break; 746 } 747 748 return; 749 } 750 751 /* 752 * mmcodec stuff 753 */ 754 755 static int 756 mmcodec_init(struct dbri_softc *sc) 757 { 758 bus_space_handle_t ioh = sc->sc_ioh; 759 bus_space_tag_t iot = sc->sc_iot; 760 u_int32_t reg2; 761 int bail; 762 763 reg2 = bus_space_read_4(iot, ioh, DBRI_REG2); 764 DPRINTF("mmcodec_init: PIO reads %x\n", reg2); 765 766 if (reg2 & DBRI_PIO2) { 767 aprint_normal_dev(&sc->sc_dev, " onboard CS4215 detected\n"); 768 sc->sc_mm.onboard = 1; 769 } 770 771 if (reg2 & DBRI_PIO0) { 772 aprint_normal_dev(&sc->sc_dev, "speakerbox detected\n"); 773 bus_space_write_4(iot, ioh, DBRI_REG2, DBRI_PIO2_ENABLE); 774 sc->sc_mm.onboard = 0; 775 } 776 777 if ((reg2 & DBRI_PIO2) && (reg2 & DBRI_PIO0)) { 778 aprint_normal_dev(&sc->sc_dev, "using speakerbox\n"); 779 bus_space_write_4(iot, ioh, DBRI_REG2, DBRI_PIO2_ENABLE); 780 sc->sc_mm.onboard = 0; 781 } 782 783 if (!(reg2 & (DBRI_PIO0|DBRI_PIO2))) { 784 aprint_normal_dev(&sc->sc_dev, "no mmcodec found\n"); 785 return -1; 786 } 787 788 sc->sc_version = 0xff; 789 790 mmcodec_pipe_init(sc); 791 mmcodec_default(sc); 792 793 sc->sc_mm.offset = sc->sc_mm.onboard ? 0 : 8; 794 795 /* 796 * mmcodec_setcontrol() sometimes fails right after powerup 797 * so we just try again until we either get a useful response or run 798 * out of time 799 */ 800 bail = 0; 801 while (mmcodec_setcontrol(sc) == -1 || sc->sc_version == 0xff) { 802 803 bail++; 804 if (bail > 100) { 805 DPRINTF("%s: cs4215 probe failed at offset %d\n", 806 device_xname(&sc->sc_dev), sc->sc_mm.offset); 807 return (-1); 808 } 809 delay(10000); 810 } 811 812 aprint_normal_dev(&sc->sc_dev, "cs4215 rev %c found at offset %d\n", 813 0x43 + (sc->sc_version & 0xf), sc->sc_mm.offset); 814 815 /* set some sane defaults for mmcodec_init_data */ 816 sc->sc_params.channels = 2; 817 sc->sc_params.precision = 16; 818 819 mmcodec_init_data(sc); 820 821 return (0); 822 } 823 824 static void 825 mmcodec_init_data(struct dbri_softc *sc) 826 { 827 bus_space_tag_t iot = sc->sc_iot; 828 bus_space_handle_t ioh = sc->sc_ioh; 829 u_int32_t tmp; 830 int data_width; 831 832 tmp = bus_space_read_4(iot, ioh, DBRI_REG0); 833 tmp &= ~(DBRI_CHI_ACTIVATE); /* disable CHI */ 834 bus_space_write_4(iot, ioh, DBRI_REG0, tmp); 835 836 /* switch CS4215 to data mode - set PIO3 to 1 */ 837 tmp = DBRI_PIO_ENABLE_ALL | DBRI_PIO1 | DBRI_PIO3; 838 839 /* XXX */ 840 tmp |= (sc->sc_mm.onboard ? DBRI_PIO0 : DBRI_PIO2); 841 842 bus_space_write_4(iot, ioh, DBRI_REG2, tmp); 843 chi_reset(sc, CHIslave, 128); 844 845 data_width = sc->sc_params.channels * sc->sc_params.precision; 846 847 if ((data_width != 32) && (data_width != 8)) 848 aprint_error("%s: data_width is %d\n", __func__, data_width); 849 850 pipe_ts_link(sc, 20, PIPEoutput, 16, 32, sc->sc_mm.offset + 32); 851 pipe_ts_link(sc, 4, PIPEoutput, 16, data_width, sc->sc_mm.offset); 852 pipe_ts_link(sc, 6, PIPEinput, 16, data_width, sc->sc_mm.offset); 853 pipe_ts_link(sc, 21, PIPEinput, 16, 32, sc->sc_mm.offset + 32); 854 855 pipe_receive_fixed(sc, 21, &sc->sc_mm.status); 856 857 mmcodec_setgain(sc, 0); 858 859 tmp = bus_space_read_4(iot, ioh, DBRI_REG0); 860 tmp |= DBRI_CHI_ACTIVATE; 861 bus_space_write_4(iot, ioh, DBRI_REG0, tmp); 862 863 return; 864 } 865 866 static void 867 mmcodec_pipe_init(struct dbri_softc *sc) 868 { 869 870 pipe_setup(sc, 4, DBRI_SDP_MEM | DBRI_SDP_TO_SER | DBRI_SDP_MSB); 871 pipe_setup(sc, 20, DBRI_SDP_FIXED | DBRI_SDP_TO_SER | DBRI_SDP_MSB); 872 pipe_setup(sc, 6, DBRI_SDP_MEM | DBRI_SDP_FROM_SER | DBRI_SDP_MSB); 873 pipe_setup(sc, 21, DBRI_SDP_FIXED | DBRI_SDP_FROM_SER | DBRI_SDP_MSB); 874 875 pipe_setup(sc, 17, DBRI_SDP_FIXED | DBRI_SDP_TO_SER | DBRI_SDP_MSB); 876 pipe_setup(sc, 18, DBRI_SDP_FIXED | DBRI_SDP_FROM_SER | DBRI_SDP_MSB); 877 pipe_setup(sc, 19, DBRI_SDP_FIXED | DBRI_SDP_FROM_SER | DBRI_SDP_MSB); 878 879 sc->sc_mm.status = 0; 880 881 pipe_receive_fixed(sc, 18, &sc->sc_mm.status); 882 pipe_receive_fixed(sc, 19, &sc->sc_mm.version); 883 884 return; 885 } 886 887 static void 888 mmcodec_default(struct dbri_softc *sc) 889 { 890 struct cs4215_state *mm = &sc->sc_mm; 891 892 /* 893 * no action, memory resetting only 894 * 895 * data time slots 5-8 896 * speaker, line and headphone enable. set gain to half. 897 * input is line 898 */ 899 mm->d.bdata[0] = sc->sc_latt = 0x20 | CS4215_HE | CS4215_LE; 900 mm->d.bdata[1] = sc->sc_ratt = 0x20 | CS4215_SE; 901 sc->sc_linp = 128; 902 sc->sc_rinp = 128; 903 sc->sc_monitor = 0; 904 sc->sc_input = 1; /* line */ 905 mm->d.bdata[2] = (CS4215_LG((sc->sc_linp >> 4)) & 0x0f) | 906 ((sc->sc_input == 2) ? CS4215_IS : 0) | CS4215_PIO0 | CS4215_PIO1; 907 mm->d.bdata[3] = (CS4215_RG((sc->sc_rinp >> 4) & 0x0f)) | 908 CS4215_MA(15 - ((sc->sc_monitor >> 4) & 0x0f)); 909 910 911 /* 912 * control time slots 1-4 913 * 914 * 0: default I/O voltage scale 915 * 1: 8 bit ulaw, 8kHz, mono, high pass filter disabled 916 * 2: serial enable, CHI master, 128 bits per frame, clock 1 917 * 3: tests disabled 918 */ 919 mm->c.bcontrol[0] = CS4215_RSRVD_1 | CS4215_MLB; 920 mm->c.bcontrol[1] = CS4215_DFR_ULAW | CS4215_FREQ[0].csval; 921 mm->c.bcontrol[2] = CS4215_XCLK | CS4215_BSEL_128 | CS4215_FREQ[0].xtal; 922 mm->c.bcontrol[3] = 0; 923 924 return; 925 } 926 927 static void 928 mmcodec_setgain(struct dbri_softc *sc, int mute) 929 { 930 if (mute) { 931 /* disable all outputs, max. attenuation */ 932 sc->sc_mm.d.bdata[0] = sc->sc_latt | 63; 933 sc->sc_mm.d.bdata[1] = sc->sc_ratt | 63; 934 } else { 935 936 sc->sc_mm.d.bdata[0] = sc->sc_latt; 937 sc->sc_mm.d.bdata[1] = sc->sc_ratt; 938 } 939 940 /* input stuff */ 941 sc->sc_mm.d.bdata[2] = CS4215_LG((sc->sc_linp >> 4) & 0x0f) | 942 ((sc->sc_input == 2) ? CS4215_IS : 0) | CS4215_PIO0 | CS4215_PIO1; 943 sc->sc_mm.d.bdata[3] = (CS4215_RG((sc->sc_rinp >> 4)) & 0x0f) | 944 (CS4215_MA(15 - ((sc->sc_monitor >> 4) & 0x0f))); 945 946 if (sc->sc_powerstate == 0) 947 return; 948 pipe_transmit_fixed(sc, 20, sc->sc_mm.d.ldata); 949 950 DPRINTF("mmcodec_setgain: %08x\n", sc->sc_mm.d.ldata); 951 /* give the chip some time to execute the command */ 952 delay(250); 953 954 return; 955 } 956 957 static int 958 mmcodec_setcontrol(struct dbri_softc *sc) 959 { 960 bus_space_tag_t iot = sc->sc_iot; 961 bus_space_handle_t ioh = sc->sc_ioh; 962 u_int32_t val; 963 u_int32_t tmp; 964 int bail = 0; 965 #if DBRI_SPIN 966 int i; 967 #endif 968 969 /* 970 * Temporarily mute outputs and wait 125 us to make sure that it 971 * happens. This avoids clicking noises. 972 */ 973 mmcodec_setgain(sc, 1); 974 delay(125); 975 976 bus_space_write_4(iot, ioh, DBRI_REG2, 0); 977 delay(125); 978 979 /* enable control mode */ 980 val = DBRI_PIO_ENABLE_ALL | DBRI_PIO1; /* was PIO1 */ 981 982 /* XXX */ 983 val |= (sc->sc_mm.onboard ? DBRI_PIO0 : DBRI_PIO2); 984 985 bus_space_write_4(iot, ioh, DBRI_REG2, val); 986 987 delay(34); 988 989 /* 990 * in control mode, the cs4215 is the slave device, so the 991 * DBRI must act as the CHI master. 992 * 993 * in data mode, the cs4215 must be the CHI master to insure 994 * that the data stream is in sync with its codec 995 */ 996 tmp = bus_space_read_4(iot, ioh, DBRI_REG0); 997 tmp &= ~DBRI_COMMAND_CHI; 998 bus_space_write_4(iot, ioh, DBRI_REG0, tmp); 999 1000 chi_reset(sc, CHImaster, 128); 1001 1002 /* control mode */ 1003 pipe_ts_link(sc, 17, PIPEoutput, 16, 32, sc->sc_mm.offset); 1004 pipe_ts_link(sc, 18, PIPEinput, 16, 8, sc->sc_mm.offset); 1005 pipe_ts_link(sc, 19, PIPEinput, 16, 8, sc->sc_mm.offset + 48); 1006 1007 /* wait for the chip to echo back CLB as zero */ 1008 sc->sc_mm.c.bcontrol[0] &= ~CS4215_CLB; 1009 pipe_transmit_fixed(sc, 17, sc->sc_mm.c.lcontrol); 1010 1011 tmp = bus_space_read_4(iot, ioh, DBRI_REG0); 1012 tmp |= DBRI_CHI_ACTIVATE; 1013 bus_space_write_4(iot, ioh, DBRI_REG0, tmp); 1014 1015 #if DBRI_SPIN 1016 i = 1024; 1017 while (((sc->sc_mm.status & 0xe4) != 0x20) && --i) { 1018 delay(125); 1019 } 1020 1021 if (i == 0) { 1022 DPRINTF("%s: cs4215 didn't respond to CLB (0x%02x)\n", 1023 device_xname(&sc->sc_dev), sc->sc_mm.status); 1024 return (-1); 1025 } 1026 #else 1027 while (((sc->sc_mm.status & 0xe4) != 0x20) && (bail < 10)) { 1028 DPRINTF("%s: tsleep %p\n", device_xname(&sc->sc_dev), sc); 1029 tsleep(sc, PCATCH | PZERO, "dbrifxdt", hz); 1030 bail++; 1031 } 1032 #endif 1033 if (bail >= 10) { 1034 DPRINTF("%s: switching to control mode timed out (%x %x)\n", 1035 device_xname(&sc->sc_dev), sc->sc_mm.status, 1036 bus_space_read_4(iot, ioh, DBRI_REG2)); 1037 return -1; 1038 } 1039 1040 /* copy the version information before it becomes unreadable again */ 1041 sc->sc_version = sc->sc_mm.version; 1042 1043 /* terminate cs4215 control mode */ 1044 sc->sc_mm.c.bcontrol[0] |= CS4215_CLB; 1045 pipe_transmit_fixed(sc, 17, sc->sc_mm.c.lcontrol); 1046 1047 /* two frames of control info @ 8kHz frame rate = 250us delay */ 1048 delay(250); 1049 1050 mmcodec_setgain(sc, 0); 1051 1052 return (0); 1053 1054 } 1055 1056 /* 1057 * CHI combo 1058 */ 1059 static void 1060 chi_reset(struct dbri_softc *sc, enum ms ms, int bpf) 1061 { 1062 volatile u_int32_t *cmd; 1063 int val; 1064 int clockrate, divisor; 1065 1066 cmd = dbri_command_lock(sc); 1067 1068 /* set CHI anchor: pipe 16 */ 1069 val = DBRI_DTS_VI | DBRI_DTS_INS | DBRI_DTS_PRVIN(16) | DBRI_PIPE(16); 1070 *(cmd++) = DBRI_CMD(DBRI_COMMAND_DTS, 0, val); 1071 *(cmd++) = DBRI_TS_ANCHOR | DBRI_TS_NEXT(16); 1072 *(cmd++) = 0; 1073 1074 val = DBRI_DTS_VO | DBRI_DTS_INS | DBRI_DTS_PRVOUT(16) | DBRI_PIPE(16); 1075 *(cmd++) = DBRI_CMD(DBRI_COMMAND_DTS, 0, val); 1076 *(cmd++) = 0; 1077 *(cmd++) = DBRI_TS_ANCHOR | DBRI_TS_NEXT(16); 1078 1079 sc->sc_pipe[16].sdp = 1; 1080 sc->sc_pipe[16].next = 16; 1081 sc->sc_chi_pipe_in = 16; 1082 sc->sc_chi_pipe_out = 16; 1083 1084 switch (ms) { 1085 case CHIslave: 1086 *(cmd++) = DBRI_CMD(DBRI_COMMAND_CHI, 0, DBRI_CHI_CHICM(0)); 1087 break; 1088 case CHImaster: 1089 clockrate = bpf * 8; 1090 divisor = 12288 / clockrate; 1091 1092 if (divisor > 255 || divisor * clockrate != 12288) 1093 aprint_error_dev(&sc->sc_dev, "illegal bits-per-frame %d\n", 1094 bpf); 1095 1096 *(cmd++) = DBRI_CMD(DBRI_COMMAND_CHI, 0, 1097 DBRI_CHI_CHICM(divisor) | DBRI_CHI_FD | DBRI_CHI_BPF(bpf)); 1098 break; 1099 default: 1100 aprint_error_dev(&sc->sc_dev, "unknown value for ms!\n"); 1101 break; 1102 } 1103 1104 sc->sc_chi_bpf = bpf; 1105 1106 /* CHI data mode */ 1107 *(cmd++) = DBRI_CMD(DBRI_COMMAND_PAUSE, 0, 0); 1108 *(cmd++) = DBRI_CMD(DBRI_COMMAND_CDM, 0, 1109 DBRI_CDM_XCE | DBRI_CDM_XEN | DBRI_CDM_REN); 1110 1111 dbri_command_send(sc, cmd); 1112 1113 return; 1114 } 1115 1116 /* 1117 * pipe stuff 1118 */ 1119 static void 1120 pipe_setup(struct dbri_softc *sc, int pipe, int sdp) 1121 { 1122 DPRINTF("pipe setup: %d\n", pipe); 1123 if (pipe < 0 || pipe >= DBRI_PIPE_MAX) { 1124 aprint_error_dev(&sc->sc_dev, "illegal pipe number %d\n", 1125 pipe); 1126 return; 1127 } 1128 1129 if ((sdp & 0xf800) != sdp) 1130 aprint_error_dev(&sc->sc_dev, "strange SDP value %d\n", 1131 sdp); 1132 1133 if (DBRI_SDP_MODE(sdp) == DBRI_SDP_FIXED && 1134 !(sdp & DBRI_SDP_TO_SER)) 1135 sdp |= DBRI_SDP_CHANGE; 1136 1137 sdp |= DBRI_PIPE(pipe); 1138 1139 sc->sc_pipe[pipe].sdp = sdp; 1140 sc->sc_pipe[pipe].desc = -1; 1141 1142 pipe_reset(sc, pipe); 1143 1144 return; 1145 } 1146 1147 static void 1148 pipe_reset(struct dbri_softc *sc, int pipe) 1149 { 1150 struct dbri_desc *dd; 1151 int sdp; 1152 int desc; 1153 volatile u_int32_t *cmd; 1154 1155 if (pipe < 0 || pipe >= DBRI_PIPE_MAX) { 1156 aprint_error_dev(&sc->sc_dev, "illegal pipe number %d\n", 1157 pipe); 1158 return; 1159 } 1160 1161 sdp = sc->sc_pipe[pipe].sdp; 1162 if (sdp == 0) { 1163 aprint_error_dev(&sc->sc_dev, "can not reset uninitialized pipe %d\n", 1164 pipe); 1165 return; 1166 } 1167 1168 cmd = dbri_command_lock(sc); 1169 *(cmd++) = DBRI_CMD(DBRI_COMMAND_SDP, 0, 1170 sdp | DBRI_SDP_CLEAR | DBRI_SDP_VALID_POINTER); 1171 *(cmd++) = 0; 1172 dbri_command_send(sc, cmd); 1173 1174 desc = sc->sc_pipe[pipe].desc; 1175 1176 dd = &sc->sc_desc[desc]; 1177 1178 dd->busy = 0; 1179 1180 #if 0 1181 if (dd->callback) 1182 softint_schedule(dd->softint); 1183 #endif 1184 1185 sc->sc_pipe[pipe].desc = -1; 1186 1187 return; 1188 } 1189 1190 static void 1191 pipe_receive_fixed(struct dbri_softc *sc, int pipe, volatile u_int32_t *prec) 1192 { 1193 1194 if (pipe < DBRI_PIPE_MAX / 2 || pipe >= DBRI_PIPE_MAX) { 1195 aprint_error_dev(&sc->sc_dev, "illegal pipe number %d\n", 1196 pipe); 1197 return; 1198 } 1199 1200 if (DBRI_SDP_MODE(sc->sc_pipe[pipe].sdp) != DBRI_SDP_FIXED) { 1201 aprint_error_dev(&sc->sc_dev, "non-fixed pipe %d\n", 1202 pipe); 1203 return; 1204 } 1205 1206 if (sc->sc_pipe[pipe].sdp & DBRI_SDP_TO_SER) { 1207 aprint_error_dev(&sc->sc_dev, "can not receive on transmit pipe %d\b", 1208 pipe); 1209 return; 1210 } 1211 1212 sc->sc_pipe[pipe].prec = prec; 1213 1214 return; 1215 } 1216 1217 static void 1218 pipe_transmit_fixed(struct dbri_softc *sc, int pipe, u_int32_t data) 1219 { 1220 volatile u_int32_t *cmd; 1221 1222 if (pipe < DBRI_PIPE_MAX / 2 || pipe >= DBRI_PIPE_MAX) { 1223 aprint_error_dev(&sc->sc_dev, "illegal pipe number %d\n", 1224 pipe); 1225 return; 1226 } 1227 1228 if (DBRI_SDP_MODE(sc->sc_pipe[pipe].sdp) == 0) { 1229 aprint_error_dev(&sc->sc_dev, "uninitialized pipe %d\n", 1230 pipe); 1231 return; 1232 } 1233 1234 if (DBRI_SDP_MODE(sc->sc_pipe[pipe].sdp) != DBRI_SDP_FIXED) { 1235 aprint_error_dev(&sc->sc_dev, "non-fixed pipe %d\n", 1236 pipe); 1237 return; 1238 } 1239 1240 if (!(sc->sc_pipe[pipe].sdp & DBRI_SDP_TO_SER)) { 1241 aprint_error_dev(&sc->sc_dev, "called on receive pipe %d\n", 1242 pipe); 1243 return; 1244 } 1245 1246 if (sc->sc_pipe[pipe].sdp & DBRI_SDP_MSB) 1247 data = reverse_bytes(data, sc->sc_pipe[pipe].length); 1248 1249 cmd = dbri_command_lock(sc); 1250 *(cmd++) = DBRI_CMD(DBRI_COMMAND_SSP, 0, pipe); 1251 *(cmd++) = data; 1252 1253 dbri_command_send(sc, cmd); 1254 1255 return; 1256 } 1257 1258 static void 1259 setup_ring_xmit(struct dbri_softc *sc, int pipe, int which, int num, int blksz, 1260 void (*callback)(void *), void *callback_args) 1261 { 1262 volatile u_int32_t *cmd; 1263 int x, i; 1264 int td; 1265 int td_first, td_last; 1266 bus_addr_t dmabuf, dmabase; 1267 struct dbri_desc *dd = &sc->sc_desc[which]; 1268 1269 switch (pipe) { 1270 case 4: 1271 /* output, offset 0 */ 1272 break; 1273 default: 1274 aprint_error("%s: illegal pipe number (%d)\n", 1275 __func__, pipe); 1276 return; 1277 } 1278 1279 td = 0; 1280 td_first = td_last = -1; 1281 1282 if (sc->sc_pipe[pipe].sdp == 0) { 1283 aprint_error_dev(&sc->sc_dev, "uninitialized pipe %d\n", 1284 pipe); 1285 return; 1286 } 1287 1288 dmabuf = dd->dmabase; 1289 dmabase = sc->sc_dmabase; 1290 td = 0; 1291 1292 for (i = 0; i < (num - 1); i++) { 1293 1294 sc->sc_dma->xmit[i].flags = TX_BCNT(blksz) 1295 | TX_EOF | TX_BINT; 1296 sc->sc_dma->xmit[i].ba = dmabuf; 1297 sc->sc_dma->xmit[i].nda = dmabase + dbri_dma_off(xmit, i + 1); 1298 sc->sc_dma->xmit[i].status = 0; 1299 1300 td_last = td; 1301 dmabuf += blksz; 1302 } 1303 1304 sc->sc_dma->xmit[i].flags = TX_BCNT(blksz) | TX_EOF | TX_BINT; 1305 1306 sc->sc_dma->xmit[i].ba = dmabuf; 1307 sc->sc_dma->xmit[i].nda = dmabase + dbri_dma_off(xmit, 0); 1308 sc->sc_dma->xmit[i].status = 0; 1309 1310 dd->callback = callback; 1311 dd->callback_args = callback_args; 1312 1313 x = splsched(); 1314 1315 /* the pipe shouldn't be active */ 1316 if (pipe_active(sc, pipe)) { 1317 aprint_error("pipe active (CDP)\n"); 1318 /* pipe is already active */ 1319 #if 0 1320 td_last = sc->sc_pipe[pipe].desc; 1321 while (sc->sc_desc[td_last].next != -1) 1322 td_last = sc->sc_desc[td_last].next; 1323 1324 sc->sc_desc[td_last].next = td_first; 1325 sc->sc_dma->desc[td_last].nda = 1326 sc->sc_dmabase + dbri_dma_off(desc, td_first); 1327 1328 cmd = dbri_command_lock(sc); 1329 *(cmd++) = DBRI_CMD(DBRI_COMMAND_CDP, 0, pipe); 1330 dbri_command_send(sc, cmd); 1331 #endif 1332 } else { 1333 /* 1334 * pipe isn't active - issue an SDP command to start our 1335 * chain of TDs running 1336 */ 1337 sc->sc_pipe[pipe].desc = which; 1338 cmd = dbri_command_lock(sc); 1339 *(cmd++) = DBRI_CMD(DBRI_COMMAND_SDP, 0, 1340 sc->sc_pipe[pipe].sdp | 1341 DBRI_SDP_VALID_POINTER | 1342 DBRI_SDP_EVERY | 1343 DBRI_SDP_CLEAR); 1344 *(cmd++) = sc->sc_dmabase + dbri_dma_off(xmit, 0); 1345 dbri_command_send(sc, cmd); 1346 DPRINTF("%s: starting DMA\n", __func__); 1347 } 1348 1349 splx(x); 1350 1351 return; 1352 } 1353 1354 static void 1355 setup_ring_recv(struct dbri_softc *sc, int pipe, int which, int num, int blksz, 1356 void (*callback)(void *), void *callback_args) 1357 { 1358 volatile u_int32_t *cmd; 1359 int x, i; 1360 int td_first, td_last; 1361 bus_addr_t dmabuf, dmabase; 1362 struct dbri_desc *dd = &sc->sc_desc[which]; 1363 1364 switch (pipe) { 1365 case 6: 1366 break; 1367 default: 1368 aprint_error("%s: illegal pipe number (%d)\n", 1369 __func__, pipe); 1370 return; 1371 } 1372 1373 td_first = td_last = -1; 1374 1375 if (sc->sc_pipe[pipe].sdp == 0) { 1376 aprint_error_dev(&sc->sc_dev, "uninitialized pipe %d\n", 1377 pipe); 1378 return; 1379 } 1380 1381 dmabuf = dd->dmabase; 1382 dmabase = sc->sc_dmabase; 1383 1384 for (i = 0; i < (num - 1); i++) { 1385 1386 sc->sc_dma->recv[i].flags = RX_BSIZE(blksz) | RX_FINAL; 1387 sc->sc_dma->recv[i].ba = dmabuf; 1388 sc->sc_dma->recv[i].nda = dmabase + dbri_dma_off(recv, i + 1); 1389 sc->sc_dma->recv[i].status = RX_EOF; 1390 1391 td_last = i; 1392 dmabuf += blksz; 1393 } 1394 1395 sc->sc_dma->recv[i].flags = RX_BSIZE(blksz) | RX_FINAL; 1396 1397 sc->sc_dma->recv[i].ba = dmabuf; 1398 sc->sc_dma->recv[i].nda = dmabase + dbri_dma_off(recv, 0); 1399 sc->sc_dma->recv[i].status = RX_EOF; 1400 1401 dd->callback = callback; 1402 dd->callback_args = callback_args; 1403 1404 x = splsched(); 1405 1406 /* the pipe shouldn't be active */ 1407 if (pipe_active(sc, pipe)) { 1408 aprint_error("pipe active (CDP)\n"); 1409 /* pipe is already active */ 1410 #if 0 1411 td_last = sc->sc_pipe[pipe].desc; 1412 while (sc->sc_desc[td_last].next != -1) 1413 td_last = sc->sc_desc[td_last].next; 1414 1415 sc->sc_desc[td_last].next = td_first; 1416 sc->sc_dma->desc[td_last].nda = 1417 sc->sc_dmabase + dbri_dma_off(desc, td_first); 1418 1419 cmd = dbri_command_lock(sc); 1420 *(cmd++) = DBRI_CMD(DBRI_COMMAND_CDP, 0, pipe); 1421 dbri_command_send(sc, cmd); 1422 #endif 1423 } else { 1424 /* 1425 * pipe isn't active - issue an SDP command to start our 1426 * chain of TDs running 1427 */ 1428 sc->sc_pipe[pipe].desc = which; 1429 cmd = dbri_command_lock(sc); 1430 *(cmd++) = DBRI_CMD(DBRI_COMMAND_SDP, 0, 1431 sc->sc_pipe[pipe].sdp | 1432 DBRI_SDP_VALID_POINTER | 1433 DBRI_SDP_EVERY | 1434 DBRI_SDP_CLEAR); 1435 *(cmd++) = sc->sc_dmabase + dbri_dma_off(recv, 0); 1436 dbri_command_send(sc, cmd); 1437 DPRINTF("%s: starting DMA\n", __func__); 1438 } 1439 1440 splx(x); 1441 1442 return; 1443 } 1444 1445 static void 1446 pipe_ts_link(struct dbri_softc *sc, int pipe, enum io dir, int basepipe, 1447 int len, int cycle) 1448 { 1449 volatile u_int32_t *cmd; 1450 int prevpipe, nextpipe; 1451 int val; 1452 1453 DPRINTF("%s: %d\n", __func__, pipe); 1454 if (pipe < 0 || pipe >= DBRI_PIPE_MAX || 1455 basepipe < 0 || basepipe >= DBRI_PIPE_MAX) { 1456 aprint_error_dev(&sc->sc_dev, "illegal pipe numbers (%d, %d)\n", 1457 pipe, basepipe); 1458 return; 1459 } 1460 1461 if (sc->sc_pipe[pipe].sdp == 0 || sc->sc_pipe[basepipe].sdp == 0) { 1462 aprint_error_dev(&sc->sc_dev, "uninitialized pipe (%d, %d)\n", 1463 pipe, basepipe); 1464 return; 1465 } 1466 1467 if (basepipe == 16 && dir == PIPEoutput && cycle == 0) 1468 cycle = sc->sc_chi_bpf; 1469 1470 if (basepipe == pipe) 1471 prevpipe = nextpipe = pipe; 1472 else { 1473 if (basepipe == 16) { 1474 if (dir == PIPEinput) { 1475 prevpipe = sc->sc_chi_pipe_in; 1476 } else { 1477 prevpipe = sc->sc_chi_pipe_out; 1478 } 1479 } else 1480 prevpipe = basepipe; 1481 1482 nextpipe = sc->sc_pipe[prevpipe].next; 1483 1484 while (sc->sc_pipe[nextpipe].cycle < cycle && 1485 sc->sc_pipe[nextpipe].next != basepipe) { 1486 prevpipe = nextpipe; 1487 nextpipe = sc->sc_pipe[nextpipe].next; 1488 } 1489 } 1490 1491 if (prevpipe == 16) { 1492 if (dir == PIPEinput) { 1493 sc->sc_chi_pipe_in = pipe; 1494 } else { 1495 sc->sc_chi_pipe_out = pipe; 1496 } 1497 } else 1498 sc->sc_pipe[prevpipe].next = pipe; 1499 1500 sc->sc_pipe[pipe].next = nextpipe; 1501 sc->sc_pipe[pipe].cycle = cycle; 1502 sc->sc_pipe[pipe].length = len; 1503 1504 cmd = dbri_command_lock(sc); 1505 1506 switch (dir) { 1507 case PIPEinput: 1508 val = DBRI_DTS_VI | DBRI_DTS_INS | DBRI_DTS_PRVIN(prevpipe); 1509 val |= pipe; 1510 *(cmd++) = DBRI_CMD(DBRI_COMMAND_DTS, 0, val); 1511 *(cmd++) = DBRI_TS_LEN(len) | DBRI_TS_CYCLE(cycle) | 1512 DBRI_TS_NEXT(nextpipe); 1513 *(cmd++) = 0; 1514 break; 1515 case PIPEoutput: 1516 val = DBRI_DTS_VO | DBRI_DTS_INS | DBRI_DTS_PRVOUT(prevpipe); 1517 val |= pipe; 1518 *(cmd++) = DBRI_CMD(DBRI_COMMAND_DTS, 0, val); 1519 *(cmd++) = 0; 1520 *(cmd++) = DBRI_TS_LEN(len) | DBRI_TS_CYCLE(cycle) | 1521 DBRI_TS_NEXT(nextpipe); 1522 break; 1523 default: 1524 DPRINTF("%s: should not have happened!\n", 1525 device_xname(&sc->sc_dev)); 1526 break; 1527 } 1528 1529 dbri_command_send(sc, cmd); 1530 1531 return; 1532 } 1533 1534 static int 1535 pipe_active(struct dbri_softc *sc, int pipe) 1536 { 1537 1538 return (sc->sc_pipe[pipe].desc != -1); 1539 } 1540 1541 /* 1542 * subroutines required to interface with audio(9) 1543 */ 1544 1545 static int 1546 dbri_query_encoding(void *hdl, struct audio_encoding *ae) 1547 { 1548 1549 switch (ae->index) { 1550 case 0: 1551 strcpy(ae->name, AudioEulinear); 1552 ae->encoding = AUDIO_ENCODING_ULINEAR; 1553 ae->precision = 8; 1554 ae->flags = 0; 1555 break; 1556 case 1: 1557 strcpy(ae->name, AudioEmulaw); 1558 ae->encoding = AUDIO_ENCODING_ULAW; 1559 ae->precision = 8; 1560 ae->flags = 0; 1561 break; 1562 case 2: 1563 strcpy(ae->name, AudioEalaw); 1564 ae->encoding = AUDIO_ENCODING_ALAW; 1565 ae->precision = 8; 1566 ae->flags = 0; 1567 break; 1568 case 3: 1569 strcpy(ae->name, AudioEslinear); 1570 ae->encoding = AUDIO_ENCODING_SLINEAR; 1571 ae->precision = 8; 1572 ae->flags = AUDIO_ENCODINGFLAG_EMULATED; 1573 break; 1574 case 4: 1575 strcpy(ae->name, AudioEslinear_le); 1576 ae->encoding = AUDIO_ENCODING_SLINEAR_LE; 1577 ae->precision = 16; 1578 ae->flags = AUDIO_ENCODINGFLAG_EMULATED; 1579 break; 1580 case 5: 1581 strcpy(ae->name, AudioEulinear_le); 1582 ae->encoding = AUDIO_ENCODING_ULINEAR_LE; 1583 ae->precision = 16; 1584 ae->flags = AUDIO_ENCODINGFLAG_EMULATED; 1585 break; 1586 case 6: 1587 strcpy(ae->name, AudioEslinear_be); 1588 ae->encoding = AUDIO_ENCODING_SLINEAR_BE; 1589 ae->precision = 16; 1590 ae->flags = 0; 1591 break; 1592 case 7: 1593 strcpy(ae->name, AudioEulinear_be); 1594 ae->encoding = AUDIO_ENCODING_ULINEAR_BE; 1595 ae->precision = 16; 1596 ae->flags = AUDIO_ENCODINGFLAG_EMULATED; 1597 break; 1598 case 8: 1599 strcpy(ae->name, AudioEslinear); 1600 ae->encoding = AUDIO_ENCODING_SLINEAR; 1601 ae->precision = 16; 1602 ae->flags = 0; 1603 break; 1604 default: 1605 return (EINVAL); 1606 } 1607 1608 return (0); 1609 } 1610 1611 static int 1612 dbri_set_params(void *hdl, int setmode, int usemode, 1613 struct audio_params *play, struct audio_params *rec, 1614 stream_filter_list_t *pfil, stream_filter_list_t *rfil) 1615 { 1616 struct dbri_softc *sc = hdl; 1617 int rate; 1618 audio_params_t *p = NULL; 1619 stream_filter_list_t *fil; 1620 int mode; 1621 1622 /* 1623 * This device only has one clock, so make the sample rates match. 1624 */ 1625 if (play->sample_rate != rec->sample_rate && 1626 usemode == (AUMODE_PLAY | AUMODE_RECORD)) { 1627 if (setmode == AUMODE_PLAY) { 1628 rec->sample_rate = play->sample_rate; 1629 setmode |= AUMODE_RECORD; 1630 } else if (setmode == AUMODE_RECORD) { 1631 play->sample_rate = rec->sample_rate; 1632 setmode |= AUMODE_PLAY; 1633 } else 1634 return EINVAL; 1635 } 1636 1637 for (mode = AUMODE_RECORD; mode != -1; 1638 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) { 1639 if ((setmode & mode) == 0) 1640 continue; 1641 1642 p = mode == AUMODE_PLAY ? play : rec; 1643 if (p->sample_rate < 4000 || p->sample_rate > 50000) { 1644 DPRINTF("dbri_set_params: invalid rate %d\n", 1645 p->sample_rate); 1646 return EINVAL; 1647 } 1648 1649 fil = mode == AUMODE_PLAY ? pfil : rfil; 1650 DPRINTF("requested enc: %d rate: %d prec: %d chan: %d\n", p->encoding, 1651 p->sample_rate, p->precision, p->channels); 1652 if (auconv_set_converter(dbri_formats, DBRI_NFORMATS, 1653 mode, p, true, fil) < 0) { 1654 aprint_debug("dbri_set_params: auconv_set_converter failed\n"); 1655 return EINVAL; 1656 } 1657 if (fil->req_size > 0) 1658 p = &fil->filters[0].param; 1659 } 1660 1661 if (p == NULL) { 1662 DPRINTF("dbri_set_params: no parameters to set\n"); 1663 return 0; 1664 } 1665 1666 DPRINTF("native enc: %d rate: %d prec: %d chan: %d\n", p->encoding, 1667 p->sample_rate, p->precision, p->channels); 1668 1669 for (rate = 0; CS4215_FREQ[rate].freq; rate++) 1670 if (CS4215_FREQ[rate].freq == p->sample_rate) 1671 break; 1672 1673 if (CS4215_FREQ[rate].freq == 0) 1674 return (EINVAL); 1675 1676 /* set frequency */ 1677 sc->sc_mm.c.bcontrol[1] &= ~0x38; 1678 sc->sc_mm.c.bcontrol[1] |= CS4215_FREQ[rate].csval; 1679 sc->sc_mm.c.bcontrol[2] &= ~0x70; 1680 sc->sc_mm.c.bcontrol[2] |= CS4215_FREQ[rate].xtal; 1681 1682 switch (p->encoding) { 1683 case AUDIO_ENCODING_ULAW: 1684 sc->sc_mm.c.bcontrol[1] &= ~3; 1685 sc->sc_mm.c.bcontrol[1] |= CS4215_DFR_ULAW; 1686 break; 1687 case AUDIO_ENCODING_ALAW: 1688 sc->sc_mm.c.bcontrol[1] &= ~3; 1689 sc->sc_mm.c.bcontrol[1] |= CS4215_DFR_ALAW; 1690 break; 1691 case AUDIO_ENCODING_ULINEAR: 1692 sc->sc_mm.c.bcontrol[1] &= ~3; 1693 if (p->precision == 8) { 1694 sc->sc_mm.c.bcontrol[1] |= CS4215_DFR_LINEAR8; 1695 } else { 1696 sc->sc_mm.c.bcontrol[1] |= CS4215_DFR_LINEAR16; 1697 } 1698 break; 1699 case AUDIO_ENCODING_SLINEAR_BE: 1700 case AUDIO_ENCODING_SLINEAR: 1701 sc->sc_mm.c.bcontrol[1] &= ~3; 1702 sc->sc_mm.c.bcontrol[1] |= CS4215_DFR_LINEAR16; 1703 break; 1704 } 1705 1706 switch (p->channels) { 1707 case 1: 1708 sc->sc_mm.c.bcontrol[1] &= ~CS4215_DFR_STEREO; 1709 break; 1710 case 2: 1711 sc->sc_mm.c.bcontrol[1] |= CS4215_DFR_STEREO; 1712 break; 1713 } 1714 1715 return (0); 1716 } 1717 1718 static int 1719 dbri_round_blocksize(void *hdl, int bs, int mode, 1720 const audio_params_t *param) 1721 { 1722 1723 /* DBRI DMA segment size, rounded down to 32bit alignment */ 1724 return 0x1ffc; 1725 } 1726 1727 static int 1728 dbri_halt_output(void *hdl) 1729 { 1730 struct dbri_softc *sc = hdl; 1731 1732 if (!sc->sc_playing) 1733 return 0; 1734 1735 sc->sc_playing = 0; 1736 pipe_reset(sc, 4); 1737 return (0); 1738 } 1739 1740 static int 1741 dbri_getdev(void *hdl, struct audio_device *ret) 1742 { 1743 1744 *ret = dbri_device; 1745 return (0); 1746 } 1747 1748 static int 1749 dbri_set_port(void *hdl, mixer_ctrl_t *mc) 1750 { 1751 struct dbri_softc *sc = hdl; 1752 int latt = sc->sc_latt, ratt = sc->sc_ratt; 1753 1754 switch (mc->dev) { 1755 case DBRI_VOL_OUTPUT: /* master volume */ 1756 latt = (latt & 0xc0) | (63 - 1757 min(mc->un.value.level[AUDIO_MIXER_LEVEL_LEFT] >> 2, 63)); 1758 ratt = (ratt & 0xc0) | (63 - 1759 min(mc->un.value.level[AUDIO_MIXER_LEVEL_RIGHT] >> 2, 63)); 1760 break; 1761 case DBRI_ENABLE_MONO: /* built-in speaker */ 1762 if (mc->un.ord == 1) { 1763 ratt |= CS4215_SE; 1764 } else 1765 ratt &= ~CS4215_SE; 1766 break; 1767 case DBRI_ENABLE_HEADPHONE: /* headphones output */ 1768 if (mc->un.ord == 1) { 1769 latt |= CS4215_HE; 1770 } else 1771 latt &= ~CS4215_HE; 1772 break; 1773 case DBRI_ENABLE_LINE: /* line out */ 1774 if (mc->un.ord == 1) { 1775 latt |= CS4215_LE; 1776 } else 1777 latt &= ~CS4215_LE; 1778 break; 1779 case DBRI_VOL_MONITOR: 1780 if (mc->un.value.level[AUDIO_MIXER_LEVEL_LEFT] == 1781 sc->sc_monitor) 1782 return 0; 1783 sc->sc_monitor = mc->un.value.level[AUDIO_MIXER_LEVEL_LEFT]; 1784 break; 1785 case DBRI_INPUT_GAIN: 1786 sc->sc_linp = mc->un.value.level[AUDIO_MIXER_LEVEL_LEFT]; 1787 sc->sc_rinp = mc->un.value.level[AUDIO_MIXER_LEVEL_RIGHT]; 1788 break; 1789 case DBRI_INPUT_SELECT: 1790 if (mc->un.mask == sc->sc_input) 1791 return 0; 1792 sc->sc_input = mc->un.mask; 1793 break; 1794 } 1795 1796 sc->sc_latt = latt; 1797 sc->sc_ratt = ratt; 1798 1799 mmcodec_setgain(sc, 0); 1800 1801 return (0); 1802 } 1803 1804 static int 1805 dbri_get_port(void *hdl, mixer_ctrl_t *mc) 1806 { 1807 struct dbri_softc *sc = hdl; 1808 1809 switch (mc->dev) { 1810 case DBRI_VOL_OUTPUT: /* master volume */ 1811 mc->un.value.level[AUDIO_MIXER_LEVEL_LEFT] = 1812 (63 - (sc->sc_latt & 0x3f)) << 2; 1813 mc->un.value.level[AUDIO_MIXER_LEVEL_RIGHT] = 1814 (63 - (sc->sc_ratt & 0x3f)) << 2; 1815 return (0); 1816 case DBRI_ENABLE_MONO: /* built-in speaker */ 1817 mc->un.ord = (sc->sc_ratt & CS4215_SE) ? 1 : 0; 1818 return 0; 1819 case DBRI_ENABLE_HEADPHONE: /* headphones output */ 1820 mc->un.ord = (sc->sc_latt & CS4215_HE) ? 1 : 0; 1821 return 0; 1822 case DBRI_ENABLE_LINE: /* line out */ 1823 mc->un.ord = (sc->sc_latt & CS4215_LE) ? 1 : 0; 1824 return 0; 1825 case DBRI_VOL_MONITOR: 1826 mc->un.value.level[AUDIO_MIXER_LEVEL_LEFT] = sc->sc_monitor; 1827 return 0; 1828 case DBRI_INPUT_GAIN: 1829 mc->un.value.level[AUDIO_MIXER_LEVEL_LEFT] = sc->sc_linp; 1830 mc->un.value.level[AUDIO_MIXER_LEVEL_RIGHT] = sc->sc_rinp; 1831 return 0; 1832 case DBRI_INPUT_SELECT: 1833 mc->un.mask = sc->sc_input; 1834 return 0; 1835 } 1836 return (EINVAL); 1837 } 1838 1839 static int 1840 dbri_query_devinfo(void *hdl, mixer_devinfo_t *di) 1841 { 1842 1843 switch (di->index) { 1844 case DBRI_MONITOR_CLASS: 1845 di->mixer_class = DBRI_MONITOR_CLASS; 1846 strcpy(di->label.name, AudioCmonitor); 1847 di->type = AUDIO_MIXER_CLASS; 1848 di->next = di->prev = AUDIO_MIXER_LAST; 1849 return 0; 1850 case DBRI_OUTPUT_CLASS: 1851 di->mixer_class = DBRI_OUTPUT_CLASS; 1852 strcpy(di->label.name, AudioCoutputs); 1853 di->type = AUDIO_MIXER_CLASS; 1854 di->next = di->prev = AUDIO_MIXER_LAST; 1855 return 0; 1856 case DBRI_INPUT_CLASS: 1857 di->mixer_class = DBRI_INPUT_CLASS; 1858 strcpy(di->label.name, AudioCinputs); 1859 di->type = AUDIO_MIXER_CLASS; 1860 di->next = di->prev = AUDIO_MIXER_LAST; 1861 return 0; 1862 case DBRI_VOL_OUTPUT: /* master volume */ 1863 di->mixer_class = DBRI_OUTPUT_CLASS; 1864 di->next = di->prev = AUDIO_MIXER_LAST; 1865 strcpy(di->label.name, AudioNmaster); 1866 di->type = AUDIO_MIXER_VALUE; 1867 di->un.v.num_channels = 2; 1868 strcpy(di->un.v.units.name, AudioNvolume); 1869 return (0); 1870 case DBRI_INPUT_GAIN: /* input gain */ 1871 di->mixer_class = DBRI_INPUT_CLASS; 1872 di->next = di->prev = AUDIO_MIXER_LAST; 1873 strcpy(di->label.name, AudioNrecord); 1874 di->type = AUDIO_MIXER_VALUE; 1875 di->un.v.num_channels = 2; 1876 strcpy(di->un.v.units.name, AudioNvolume); 1877 return (0); 1878 case DBRI_VOL_MONITOR: /* monitor volume */ 1879 di->mixer_class = DBRI_MONITOR_CLASS; 1880 di->next = di->prev = AUDIO_MIXER_LAST; 1881 strcpy(di->label.name, AudioNmonitor); 1882 di->type = AUDIO_MIXER_VALUE; 1883 di->un.v.num_channels = 1; 1884 strcpy(di->un.v.units.name, AudioNvolume); 1885 return (0); 1886 case DBRI_ENABLE_MONO: /* built-in speaker */ 1887 di->mixer_class = DBRI_OUTPUT_CLASS; 1888 di->next = di->prev = AUDIO_MIXER_LAST; 1889 strcpy(di->label.name, AudioNmono); 1890 di->type = AUDIO_MIXER_ENUM; 1891 di->un.e.num_mem = 2; 1892 strcpy(di->un.e.member[0].label.name, AudioNoff); 1893 di->un.e.member[0].ord = 0; 1894 strcpy(di->un.e.member[1].label.name, AudioNon); 1895 di->un.e.member[1].ord = 1; 1896 return (0); 1897 case DBRI_ENABLE_HEADPHONE: /* headphones output */ 1898 di->mixer_class = DBRI_OUTPUT_CLASS; 1899 di->next = di->prev = AUDIO_MIXER_LAST; 1900 strcpy(di->label.name, AudioNheadphone); 1901 di->type = AUDIO_MIXER_ENUM; 1902 di->un.e.num_mem = 2; 1903 strcpy(di->un.e.member[0].label.name, AudioNoff); 1904 di->un.e.member[0].ord = 0; 1905 strcpy(di->un.e.member[1].label.name, AudioNon); 1906 di->un.e.member[1].ord = 1; 1907 return (0); 1908 case DBRI_ENABLE_LINE: /* line out */ 1909 di->mixer_class = DBRI_OUTPUT_CLASS; 1910 di->next = di->prev = AUDIO_MIXER_LAST; 1911 strcpy(di->label.name, AudioNline); 1912 di->type = AUDIO_MIXER_ENUM; 1913 di->un.e.num_mem = 2; 1914 strcpy(di->un.e.member[0].label.name, AudioNoff); 1915 di->un.e.member[0].ord = 0; 1916 strcpy(di->un.e.member[1].label.name, AudioNon); 1917 di->un.e.member[1].ord = 1; 1918 return (0); 1919 case DBRI_INPUT_SELECT: 1920 di->mixer_class = DBRI_INPUT_CLASS; 1921 strcpy(di->label.name, AudioNsource); 1922 di->type = AUDIO_MIXER_SET; 1923 di->prev = di->next = AUDIO_MIXER_LAST; 1924 di->un.s.num_mem = 2; 1925 strcpy(di->un.s.member[0].label.name, AudioNline); 1926 di->un.s.member[0].mask = 1 << 0; 1927 strcpy(di->un.s.member[1].label.name, AudioNmicrophone); 1928 di->un.s.member[1].mask = 1 << 1; 1929 return 0; 1930 } 1931 1932 return (ENXIO); 1933 } 1934 1935 static size_t 1936 dbri_round_buffersize(void *hdl, int dir, size_t bufsize) 1937 { 1938 #ifdef DBRI_BIG_BUFFER 1939 return 16*0x1ffc; /* use ~128KB buffer */ 1940 #else 1941 return bufsize; 1942 #endif 1943 } 1944 1945 static int 1946 dbri_get_props(void *hdl) 1947 { 1948 1949 return AUDIO_PROP_MMAP | AUDIO_PROP_FULLDUPLEX; 1950 } 1951 1952 static int 1953 dbri_trigger_output(void *hdl, void *start, void *end, int blksize, 1954 void (*intr)(void *), void *intrarg, 1955 const struct audio_params *param) 1956 { 1957 struct dbri_softc *sc = hdl; 1958 unsigned long count, num; 1959 1960 if (sc->sc_playing) 1961 return 0; 1962 1963 count = (unsigned long)(((char *)end - (char *)start)); 1964 num = count / blksize; 1965 1966 DPRINTF("trigger_output(%lx %lx) : %d %ld %ld\n", 1967 (unsigned long)intr, 1968 (unsigned long)intrarg, blksize, count, num); 1969 1970 sc->sc_params = *param; 1971 1972 if (sc->sc_recording == 0) { 1973 /* do not muck with the codec when it's already in use */ 1974 if (mmcodec_setcontrol(sc) != 0) 1975 return -1; 1976 mmcodec_init_data(sc); 1977 } 1978 1979 /* 1980 * always use DMA descriptor 0 for output 1981 * no need to allocate them dynamically since we only ever have 1982 * exactly one input stream and exactly one output stream 1983 */ 1984 setup_ring_xmit(sc, 4, 0, num, blksize, intr, intrarg); 1985 sc->sc_playing = 1; 1986 return 0; 1987 } 1988 1989 static int 1990 dbri_halt_input(void *cookie) 1991 { 1992 struct dbri_softc *sc = cookie; 1993 1994 if (!sc->sc_recording) 1995 return 0; 1996 1997 sc->sc_recording = 0; 1998 pipe_reset(sc, 6); 1999 return 0; 2000 } 2001 2002 static int 2003 dbri_trigger_input(void *hdl, void *start, void *end, int blksize, 2004 void (*intr)(void *), void *intrarg, 2005 const struct audio_params *param) 2006 { 2007 struct dbri_softc *sc = hdl; 2008 unsigned long count, num; 2009 2010 if (sc->sc_recording) 2011 return 0; 2012 2013 count = (unsigned long)(((char *)end - (char *)start)); 2014 num = count / blksize; 2015 2016 DPRINTF("trigger_input(%lx %lx) : %d %ld %ld\n", 2017 (unsigned long)intr, 2018 (unsigned long)intrarg, blksize, count, num); 2019 2020 sc->sc_params = *param; 2021 2022 if (sc->sc_playing == 0) { 2023 2024 /* 2025 * we don't support different parameters for playing and 2026 * recording anyway so don't bother whacking the codec if 2027 * it's already set up 2028 */ 2029 mmcodec_setcontrol(sc); 2030 mmcodec_init_data(sc); 2031 } 2032 2033 sc->sc_recording = 1; 2034 setup_ring_recv(sc, 6, 1, num, blksize, intr, intrarg); 2035 return 0; 2036 } 2037 2038 2039 static u_int32_t 2040 reverse_bytes(u_int32_t b, int len) 2041 { 2042 switch (len) { 2043 case 32: 2044 b = ((b & 0xffff0000) >> 16) | ((b & 0x0000ffff) << 16); 2045 case 16: 2046 b = ((b & 0xff00ff00) >> 8) | ((b & 0x00ff00ff) << 8); 2047 case 8: 2048 b = ((b & 0xf0f0f0f0) >> 4) | ((b & 0x0f0f0f0f) << 4); 2049 case 4: 2050 b = ((b & 0xcccccccc) >> 2) | ((b & 0x33333333) << 2); 2051 case 2: 2052 b = ((b & 0xaaaaaaaa) >> 1) | ((b & 0x55555555) << 1); 2053 case 1: 2054 case 0: 2055 break; 2056 default: 2057 DPRINTF("reverse_bytes: unsupported length\n"); 2058 }; 2059 2060 return (b); 2061 } 2062 2063 static void * 2064 dbri_malloc(void *v, int dir, size_t s, struct malloc_type *mt, int flags) 2065 { 2066 struct dbri_softc *sc = v; 2067 struct dbri_desc *dd = &sc->sc_desc[sc->sc_desc_used]; 2068 int rseg; 2069 2070 if (bus_dmamap_create(sc->sc_dmat, s, 1, s, 0, BUS_DMA_NOWAIT, 2071 &dd->dmamap) == 0) { 2072 if (bus_dmamem_alloc(sc->sc_dmat, s, 0, 0, &dd->dmaseg, 2073 1, &rseg, BUS_DMA_NOWAIT) == 0) { 2074 if (bus_dmamem_map(sc->sc_dmat, &dd->dmaseg, rseg, s, 2075 &dd->buf, BUS_DMA_NOWAIT|BUS_DMA_COHERENT) == 0) { 2076 if (dd->buf != NULL) { 2077 if (bus_dmamap_load(sc->sc_dmat, 2078 dd->dmamap, dd->buf, s, NULL, 2079 BUS_DMA_NOWAIT) == 0) { 2080 dd->len = s; 2081 dd->busy = 0; 2082 dd->callback = NULL; 2083 dd->dmabase = 2084 dd->dmamap->dm_segs[0].ds_addr; 2085 DPRINTF("dbri_malloc: using buffer %d %08x\n", 2086 sc->sc_desc_used, (uint32_t)dd->buf); 2087 sc->sc_desc_used++; 2088 return dd->buf; 2089 } else 2090 aprint_error("dbri_malloc: load failed\n"); 2091 } else 2092 aprint_error("dbri_malloc: map returned NULL\n"); 2093 } else 2094 aprint_error("dbri_malloc: map failed\n"); 2095 bus_dmamem_free(sc->sc_dmat, &dd->dmaseg, rseg); 2096 } else 2097 aprint_error("dbri_malloc: malloc() failed\n"); 2098 bus_dmamap_destroy(sc->sc_dmat, dd->dmamap); 2099 } else 2100 aprint_error("dbri_malloc: bus_dmamap_create() failed\n"); 2101 return NULL; 2102 } 2103 2104 static void 2105 dbri_free(void *v, void *p, struct malloc_type *mt) 2106 { 2107 free(p, mt); 2108 } 2109 2110 static paddr_t 2111 dbri_mappage(void *v, void *mem, off_t off, int prot) 2112 { 2113 struct dbri_softc *sc = v;; 2114 int current; 2115 2116 if (off < 0) 2117 return -1; 2118 2119 current = 0; 2120 while ((current < sc->sc_desc_used) && 2121 (sc->sc_desc[current].buf != mem)) 2122 current++; 2123 2124 if (current < sc->sc_desc_used) { 2125 return bus_dmamem_mmap(sc->sc_dmat, 2126 &sc->sc_desc[current].dmaseg, 1, off, prot, BUS_DMA_WAITOK); 2127 } 2128 2129 return -1; 2130 } 2131 2132 static int 2133 dbri_open(void *cookie, int flags) 2134 { 2135 struct dbri_softc *sc = cookie; 2136 2137 DPRINTF("%s: %d\n", __func__, sc->sc_refcount); 2138 2139 if (sc->sc_refcount == 0) 2140 dbri_bring_up(sc); 2141 2142 sc->sc_refcount++; 2143 2144 return 0; 2145 } 2146 2147 static void 2148 dbri_close(void *cookie) 2149 { 2150 struct dbri_softc *sc = cookie; 2151 2152 DPRINTF("%s: %d\n", __func__, sc->sc_refcount); 2153 2154 sc->sc_refcount--; 2155 KASSERT(sc->sc_refcount >= 0); 2156 if (sc->sc_refcount > 0) 2157 return; 2158 2159 dbri_set_power(sc, 0); 2160 sc->sc_playing = 0; 2161 sc->sc_recording = 0; 2162 } 2163 2164 static void 2165 dbri_powerhook(int why, void *cookie) 2166 { 2167 struct dbri_softc *sc = cookie; 2168 2169 if (why == sc->sc_pmgrstate) 2170 return; 2171 2172 switch(why) 2173 { 2174 case PWR_SUSPEND: 2175 dbri_set_power(sc, 0); 2176 break; 2177 case PWR_RESUME: 2178 if (sc->sc_powerstate != 0) 2179 break; 2180 aprint_verbose("resume: %d\n", sc->sc_refcount); 2181 sc->sc_pmgrstate = PWR_RESUME; 2182 if (sc->sc_playing) { 2183 volatile u_int32_t *cmd; 2184 int s; 2185 2186 dbri_bring_up(sc); 2187 s = splsched(); 2188 cmd = dbri_command_lock(sc); 2189 *(cmd++) = DBRI_CMD(DBRI_COMMAND_SDP, 2190 0, sc->sc_pipe[4].sdp | 2191 DBRI_SDP_VALID_POINTER | 2192 DBRI_SDP_EVERY | DBRI_SDP_CLEAR); 2193 *(cmd++) = sc->sc_dmabase + 2194 dbri_dma_off(xmit, 0); 2195 dbri_command_send(sc, cmd); 2196 splx(s); 2197 } 2198 break; 2199 default: 2200 return; 2201 } 2202 sc->sc_pmgrstate = why; 2203 } 2204 2205 #endif /* NAUDIO > 0 */ 2206
Indexes created Fri Sep 26 20:09:58 GMT 2025