dbri.c revision 1.19
1 /* $NetBSD: dbri.c,v 1.19 2008/05/09 03:12:49 macallan Exp $ */ 2 3 /* 4 * Copyright (C) 1997 Rudolf Koenig (rfkoenig (at) immd4.informatik.uni-erlangen.de) 5 * Copyright (c) 1998, 1999 Brent Baccala (baccala (at) freesoft.org) 6 * Copyright (c) 2001, 2002 Jared D. McNeill <jmcneill (at) netbsd.org> 7 * Copyright (c) 2005 Michael Lorenz <macallan (at) netbsd.org> 8 * All rights reserved. 9 * 10 * This driver is losely based on a Linux driver written by Rudolf Koenig and 11 * Brent Baccala who kindly gave their permission to use their code in a 12 * BSD-licensed driver. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions 16 * are met: 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in the 21 * documentation and/or other materials provided with the distribution. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 28 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 29 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: dbri.c,v 1.19 2008/05/09 03:12:49 macallan Exp $"); 38 39 #include "audio.h" 40 #if NAUDIO > 0 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/errno.h> 45 #include <sys/device.h> 46 #include <sys/malloc.h> 47 #include <sys/proc.h> 48 #include <sys/kernel.h> 49 #include <sys/bus.h> 50 #include <sys/intr.h> 51 52 #include <dev/sbus/sbusvar.h> 53 #include <sparc/sparc/auxreg.h> 54 #include <machine/autoconf.h> 55 56 #include <sys/audioio.h> 57 #include <dev/audio_if.h> 58 #include <dev/auconv.h> 59 60 #include <dev/ic/cs4215reg.h> 61 #include <dev/ic/cs4215var.h> 62 #include <dev/sbus/dbrireg.h> 63 #include <dev/sbus/dbrivar.h> 64 65 #include "opt_sbus_dbri.h" 66 67 #define DBRI_ROM_NAME_PREFIX "SUNW,DBRI" 68 69 #ifdef DBRI_DEBUG 70 # define DPRINTF aprint_normal 71 #else 72 # define DPRINTF while (0) printf 73 #endif 74 75 static const char *dbri_supported[] = { 76 "e", 77 "s3", 78 "" 79 }; 80 81 enum ms { 82 CHImaster, 83 CHIslave 84 }; 85 86 enum io { 87 PIPEinput, 88 PIPEoutput 89 }; 90 91 /* 92 * Function prototypes 93 */ 94 95 /* softc stuff */ 96 static void dbri_attach_sbus(struct device *, struct device *, void *); 97 static int dbri_match_sbus(struct device *, struct cfdata *, void *); 98 99 static void dbri_config_interrupts(struct device *); 100 101 /* interrupt handler */ 102 static int dbri_intr(void *); 103 static void dbri_softint(void *); 104 105 /* supporting subroutines */ 106 static int dbri_init(struct dbri_softc *); 107 static int dbri_reset(struct dbri_softc *); 108 static volatile u_int32_t *dbri_command_lock(struct dbri_softc *); 109 static void dbri_command_send(struct dbri_softc *, volatile u_int32_t *); 110 static void dbri_process_interrupt_buffer(struct dbri_softc *); 111 static void dbri_process_interrupt(struct dbri_softc *, int32_t); 112 113 /* mmcodec subroutines */ 114 static int mmcodec_init(struct dbri_softc *); 115 static void mmcodec_init_data(struct dbri_softc *); 116 static void mmcodec_pipe_init(struct dbri_softc *); 117 static void mmcodec_default(struct dbri_softc *); 118 static void mmcodec_setgain(struct dbri_softc *, int); 119 static int mmcodec_setcontrol(struct dbri_softc *); 120 121 /* chi subroutines */ 122 static void chi_reset(struct dbri_softc *, enum ms, int); 123 124 /* pipe subroutines */ 125 static void pipe_setup(struct dbri_softc *, int, int); 126 static void pipe_reset(struct dbri_softc *, int); 127 static void pipe_receive_fixed(struct dbri_softc *, int, 128 volatile u_int32_t *); 129 static void pipe_transmit_fixed(struct dbri_softc *, int, u_int32_t); 130 131 static void pipe_ts_link(struct dbri_softc *, int, enum io, int, int, int); 132 static int pipe_active(struct dbri_softc *, int); 133 134 /* audio(9) stuff */ 135 static int dbri_query_encoding(void *, struct audio_encoding *); 136 static int dbri_set_params(void *, int, int, struct audio_params *, 137 struct audio_params *,stream_filter_list_t *, stream_filter_list_t *); 138 static int dbri_round_blocksize(void *, int, int, const audio_params_t *); 139 static int dbri_halt_output(void *); 140 static int dbri_halt_input(void *); 141 static int dbri_getdev(void *, struct audio_device *); 142 static int dbri_set_port(void *, mixer_ctrl_t *); 143 static int dbri_get_port(void *, mixer_ctrl_t *); 144 static int dbri_query_devinfo(void *, mixer_devinfo_t *); 145 static size_t dbri_round_buffersize(void *, int, size_t); 146 static int dbri_get_props(void *); 147 static int dbri_open(void *, int); 148 static void dbri_close(void *); 149 150 static void setup_ring_xmit(struct dbri_softc *, int, int, int, int, 151 void (*)(void *), void *); 152 static void setup_ring_recv(struct dbri_softc *, int, int, int, int, 153 void (*)(void *), void *); 154 155 static int dbri_trigger_output(void *, void *, void *, int, 156 void (*)(void *), void *, const struct audio_params *); 157 static int dbri_trigger_input(void *, void *, void *, int, 158 void (*)(void *), void *, const struct audio_params *); 159 160 static void *dbri_malloc(void *, int, size_t, struct malloc_type *, int); 161 static void dbri_free(void *, void *, struct malloc_type *); 162 static paddr_t dbri_mappage(void *, void *, off_t, int); 163 static void dbri_set_power(struct dbri_softc *, int); 164 static void dbri_bring_up(struct dbri_softc *); 165 static void dbri_powerhook(int, void *); 166 167 /* stupid support routines */ 168 static u_int32_t reverse_bytes(u_int32_t, int); 169 170 struct audio_device dbri_device = { 171 "CS4215", 172 "", 173 "dbri" 174 }; 175 176 struct audio_hw_if dbri_hw_if = { 177 dbri_open, 178 dbri_close, 179 NULL, /* drain */ 180 dbri_query_encoding, 181 dbri_set_params, 182 dbri_round_blocksize, 183 NULL, /* commit_settings */ 184 NULL, /* init_output */ 185 NULL, /* init_input */ 186 NULL, /* start_output */ 187 NULL, /* start_input */ 188 dbri_halt_output, 189 dbri_halt_input, 190 NULL, /* speaker_ctl */ 191 dbri_getdev, 192 NULL, /* setfd */ 193 dbri_set_port, 194 dbri_get_port, 195 dbri_query_devinfo, 196 dbri_malloc, 197 dbri_free, 198 dbri_round_buffersize, 199 dbri_mappage, 200 dbri_get_props, 201 dbri_trigger_output, 202 dbri_trigger_input 203 }; 204 205 CFATTACH_DECL(dbri, sizeof(struct dbri_softc), 206 dbri_match_sbus, dbri_attach_sbus, NULL, NULL); 207 208 #define DBRI_NFORMATS 4 209 static const struct audio_format dbri_formats[DBRI_NFORMATS] = { 210 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_SLINEAR_BE, 16, 16, 211 2, AUFMT_STEREO, 8, {8000, 9600, 11025, 16000, 22050, 32000, 44100, 212 48000}}, 213 /* {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_ULAW, 8, 8, 214 2, AUFMT_STEREO, 8, {8000, 9600, 11025, 16000, 22050, 32000, 44100, 215 48000}}, 216 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_ALAW, 8, 8, 217 2, AUFMT_STEREO, 8, {8000, 9600, 11025, 16000, 22050, 32000, 44100, 218 48000}}, 219 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_ULINEAR, 8, 8, 220 2, AUFMT_STEREO, 8, {8000, 9600, 11025, 16000, 22050, 32000, 44100, 221 48000}},*/ 222 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_ULAW, 8, 8, 223 1, AUFMT_MONAURAL, 8, {8000, 9600, 11025, 16000, 22050, 32000, 44100, 224 48000}}, 225 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_ALAW, 8, 8, 226 1, AUFMT_MONAURAL, 8, {8000, 9600, 11025, 16000, 22050, 32000, 44100, 227 48000}}, 228 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_ULINEAR, 8, 8, 229 1, AUFMT_MONAURAL, 8, {8000, 9600, 11025, 16000, 22050, 32000, 44100, 230 48000}}, 231 }; 232 233 enum { 234 DBRI_OUTPUT_CLASS, 235 DBRI_VOL_OUTPUT, 236 DBRI_ENABLE_MONO, 237 DBRI_ENABLE_HEADPHONE, 238 DBRI_ENABLE_LINE, 239 DBRI_MONITOR_CLASS, 240 DBRI_VOL_MONITOR, 241 DBRI_INPUT_CLASS, 242 DBRI_INPUT_GAIN, 243 DBRI_INPUT_SELECT, 244 DBRI_RECORD_CLASS, 245 DBRI_ENUM_LAST 246 }; 247 248 /* 249 * Autoconfig routines 250 */ 251 static int 252 dbri_match_sbus(struct device *parent, struct cfdata *match, void *aux) 253 { 254 struct sbus_attach_args *sa = aux; 255 char *ver; 256 int i; 257 258 if (strncmp(DBRI_ROM_NAME_PREFIX, sa->sa_name, 9)) 259 return (0); 260 261 ver = &sa->sa_name[9]; 262 263 for (i = 0; dbri_supported[i][0] != '\0'; i++) 264 if (strcmp(dbri_supported[i], ver) == 0) 265 return (1); 266 267 return (0); 268 } 269 270 static void 271 dbri_attach_sbus(struct device *parent, struct device *self, void *aux) 272 { 273 struct dbri_softc *sc = (struct dbri_softc *)self; 274 struct sbus_attach_args *sa = aux; 275 bus_space_handle_t ioh; 276 bus_size_t size; 277 int error, rseg, pwr, i; 278 char *ver = &sa->sa_name[9]; 279 280 sc->sc_iot = sa->sa_bustag; 281 sc->sc_dmat = sa->sa_dmatag; 282 sc->sc_powerstate = 1; 283 284 pwr = prom_getpropint(sa->sa_node,"pwr-on-auxio",0); 285 aprint_normal(": rev %s\n", ver); 286 287 if (pwr) { 288 /* 289 * we can control DBRI power via auxio and we're initially 290 * powered down 291 */ 292 293 sc->sc_have_powerctl = 1; 294 sc->sc_powerstate = 0; 295 dbri_set_power(sc, 1); 296 powerhook_establish(device_xname(self), dbri_powerhook, sc); 297 } else { 298 /* we can't control power so we're always up */ 299 sc->sc_have_powerctl = 0; 300 sc->sc_powerstate = 1; 301 } 302 303 for (i = 0; i < DBRI_NUM_DESCRIPTORS; i++) { 304 sc->sc_desc[i].softint = softint_establish(SOFTINT_SERIAL, 305 dbri_softint, &sc->sc_desc[i]); 306 } 307 308 if (sa->sa_npromvaddrs) 309 ioh = (bus_space_handle_t)sa->sa_promvaddrs[0]; 310 else { 311 if (sbus_bus_map(sa->sa_bustag, sa->sa_slot, 312 sa->sa_offset, sa->sa_size, 313 BUS_SPACE_MAP_LINEAR, /*0,*/ &ioh) != 0) { 314 aprint_error("%s @ sbus: cannot map registers\n", 315 device_xname(self)); 316 return; 317 } 318 } 319 320 sc->sc_ioh = ioh; 321 322 size = sizeof(struct dbri_dma); 323 324 /* get a DMA handle */ 325 if ((error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, 326 BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) { 327 aprint_error_dev(self, "DMA map create error %d\n", 328 error); 329 return; 330 } 331 332 /* allocate DMA buffer */ 333 if ((error = bus_dmamem_alloc(sc->sc_dmat, size, 0, 0, &sc->sc_dmaseg, 334 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 335 aprint_error_dev(self, "DMA buffer alloc error %d\n", 336 error); 337 return; 338 } 339 340 /* map DMA buffer into CPU addressable space */ 341 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_dmaseg, rseg, size, 342 &sc->sc_membase, 343 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 344 aprint_error_dev(self, "DMA buffer map error %d\n", 345 error); 346 return; 347 } 348 349 /* load the buffer */ 350 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, 351 sc->sc_membase, size, NULL, 352 BUS_DMA_NOWAIT)) != 0) { 353 aprint_error_dev(self, "DMA buffer map load error %d\n", 354 error); 355 bus_dmamem_unmap(sc->sc_dmat, sc->sc_membase, size); 356 bus_dmamem_free(sc->sc_dmat, &sc->sc_dmaseg, rseg); 357 return; 358 } 359 360 /* map the registers into memory */ 361 362 /* kernel virtual address of DMA buffer */ 363 sc->sc_dma = (struct dbri_dma *)sc->sc_membase; 364 /* physical address of DMA buffer */ 365 sc->sc_dmabase = sc->sc_dmamap->dm_segs[0].ds_addr; 366 sc->sc_bufsiz = size; 367 368 sbus_establish(&sc->sc_sd, &sc->sc_dev); 369 370 bus_intr_establish(sa->sa_bustag, sa->sa_pri, IPL_SCHED, dbri_intr, 371 sc); 372 373 sc->sc_locked = 0; 374 sc->sc_desc_used = 0; 375 sc->sc_refcount = 0; 376 sc->sc_playing = 0; 377 sc->sc_recording = 0; 378 sc->sc_pmgrstate = PWR_RESUME; 379 config_interrupts(self, &dbri_config_interrupts); 380 381 return; 382 } 383 384 /* 385 * lowlevel routine to switch power for the DBRI chip 386 */ 387 static void 388 dbri_set_power(struct dbri_softc *sc, int state) 389 { 390 int s; 391 392 if (sc->sc_have_powerctl == 0) 393 return; 394 if (sc->sc_powerstate == state) 395 return; 396 397 if (state) { 398 DPRINTF("%s: waiting to power up... ", device_xname(&sc->sc_dev)); 399 s = splhigh(); 400 *AUXIO4M_REG |= (AUXIO4M_MMX); 401 splx(s); 402 delay(10000); 403 DPRINTF("done (%02x)\n", *AUXIO4M_REG); 404 } else { 405 DPRINTF("%s: powering down\n", device_xname(&sc->sc_dev)); 406 s = splhigh(); 407 *AUXIO4M_REG &= ~AUXIO4M_MMX; 408 splx(s); 409 DPRINTF("done (%02x})\n", *AUXIO4M_REG); 410 } 411 sc->sc_powerstate = state; 412 } 413 414 /* 415 * power up and re-initialize the chip 416 */ 417 static void 418 dbri_bring_up(struct dbri_softc *sc) 419 { 420 421 if (sc->sc_have_powerctl == 0) 422 return; 423 424 if (sc->sc_powerstate == 1) 425 return; 426 427 /* ok, we really need to do something */ 428 dbri_set_power(sc, 1); 429 430 /* 431 * re-initialize the chip but skip all the probing, don't overwrite 432 * any other settings either 433 */ 434 dbri_init(sc); 435 mmcodec_setgain(sc, 1); 436 mmcodec_pipe_init(sc); 437 mmcodec_init_data(sc); 438 mmcodec_setgain(sc, 0); 439 } 440 441 static void 442 dbri_config_interrupts(struct device *dev) 443 { 444 struct dbri_softc *sc = (struct dbri_softc *)dev; 445 446 dbri_init(sc); 447 mmcodec_init(sc); 448 449 /* Attach ourselves to the high level audio interface */ 450 audio_attach_mi(&dbri_hw_if, sc, &sc->sc_dev); 451 452 /* power down until open() */ 453 dbri_set_power(sc, 0); 454 return; 455 } 456 457 static int 458 dbri_intr(void *hdl) 459 { 460 struct dbri_softc *sc = hdl; 461 bus_space_tag_t iot = sc->sc_iot; 462 bus_space_handle_t ioh = sc->sc_ioh; 463 int x; 464 465 /* clear interrupt */ 466 x = bus_space_read_4(iot, ioh, DBRI_REG1); 467 if (x & (DBRI_MRR | DBRI_MLE | DBRI_LBG | DBRI_MBE)) { 468 u_int32_t tmp; 469 470 if (x & DBRI_MRR) 471 aprint_debug_dev(&sc->sc_dev, "multiple ack error on sbus\n"); 472 if (x & DBRI_MLE) 473 aprint_debug_dev(&sc->sc_dev, "multiple late error on sbus\n"); 474 if (x & DBRI_LBG) 475 aprint_debug_dev(&sc->sc_dev, "lost bus grant on sbus\n"); 476 if (x & DBRI_MBE) 477 aprint_debug_dev(&sc->sc_dev, "burst error on sbus\n"); 478 479 /* 480 * Some of these errors disable the chip's circuitry. 481 * Re-enable the circuitry and keep on going. 482 */ 483 484 tmp = bus_space_read_4(iot, ioh, DBRI_REG0); 485 tmp &= ~(DBRI_DISABLE_MASTER); 486 bus_space_write_4(iot, ioh, DBRI_REG0, tmp); 487 } 488 489 #if 0 490 if (!x & 1) /* XXX: DBRI_INTR_REQ */ 491 return (1); 492 #endif 493 494 dbri_process_interrupt_buffer(sc); 495 496 return (1); 497 } 498 499 static void 500 dbri_softint(void *cookie) 501 { 502 struct dbri_desc *dd = cookie; 503 504 if (dd->callback != NULL) 505 dd->callback(dd->callback_args); 506 } 507 508 static int 509 dbri_init(struct dbri_softc *sc) 510 { 511 bus_space_tag_t iot = sc->sc_iot; 512 bus_space_handle_t ioh = sc->sc_ioh; 513 u_int32_t reg; 514 volatile u_int32_t *cmd; 515 bus_addr_t dmaaddr; 516 int n; 517 518 dbri_reset(sc); 519 520 cmd = dbri_command_lock(sc); 521 522 /* XXX: Initialize interrupt ring buffer */ 523 sc->sc_dma->intr[0] = (u_int32_t)sc->sc_dmabase + dbri_dma_off(intr, 0); 524 sc->sc_irqp = 1; 525 526 /* Initialize pipes */ 527 for (n = 0; n < DBRI_PIPE_MAX; n++) 528 sc->sc_pipe[n].desc = sc->sc_pipe[n].next = -1; 529 530 for (n = 1; n < DBRI_INT_BLOCKS; n++) { 531 sc->sc_dma->intr[n] = 0; 532 } 533 534 /* Disable all SBus bursts */ 535 /* XXX 16 byte bursts cause errors, the rest works */ 536 reg = bus_space_read_4(iot, ioh, DBRI_REG0); 537 538 /*reg &= ~(DBRI_BURST_4 | DBRI_BURST_8 | DBRI_BURST_16);*/ 539 reg |= (DBRI_BURST_4 | DBRI_BURST_8); 540 bus_space_write_4(iot, ioh, DBRI_REG0, reg); 541 542 /* setup interrupt queue */ 543 dmaaddr = (u_int32_t)sc->sc_dmabase + dbri_dma_off(intr, 0); 544 *(cmd++) = DBRI_CMD(DBRI_COMMAND_IIQ, 0, 0); 545 *(cmd++) = dmaaddr; 546 547 dbri_command_send(sc, cmd); 548 return (0); 549 } 550 551 static int 552 dbri_reset(struct dbri_softc *sc) 553 { 554 int bail = 0; 555 556 bus_space_tag_t iot = sc->sc_iot; 557 bus_space_handle_t ioh = sc->sc_ioh; 558 559 bus_space_write_4(iot, ioh, DBRI_REG0, DBRI_SOFT_RESET); 560 while ((bus_space_read_4(iot, ioh, DBRI_REG0) & DBRI_SOFT_RESET) && 561 (bail < 100000)) { 562 bail++; 563 delay(10); 564 } 565 if (bail == 100000) 566 aprint_error_dev(&sc->sc_dev, "reset timed out\n"); 567 return (0); 568 } 569 570 static volatile u_int32_t * 571 dbri_command_lock(struct dbri_softc *sc) 572 { 573 574 if (sc->sc_locked) 575 aprint_debug_dev(&sc->sc_dev, "command buffer locked\n"); 576 577 sc->sc_locked++; 578 579 return (&sc->sc_dma->command[0]); 580 } 581 582 static void 583 dbri_command_send(struct dbri_softc *sc, volatile u_int32_t *cmd) 584 { 585 bus_space_handle_t ioh = sc->sc_ioh; 586 bus_space_tag_t iot = sc->sc_iot; 587 int maxloops = 1000000; 588 int x; 589 590 x = splsched(); 591 592 sc->sc_locked--; 593 594 if (sc->sc_locked != 0) { 595 aprint_error_dev(&sc->sc_dev, "command buffer improperly locked\n"); 596 } else if ((cmd - &sc->sc_dma->command[0]) >= DBRI_NUM_COMMANDS - 1) { 597 aprint_error_dev(&sc->sc_dev, "command buffer overflow\n"); 598 } else { 599 *(cmd++) = DBRI_CMD(DBRI_COMMAND_PAUSE, 0, 0); 600 *(cmd++) = DBRI_CMD(DBRI_COMMAND_WAIT, 1, 0); 601 sc->sc_waitseen = 0; 602 bus_space_write_4(iot, ioh, DBRI_REG8, sc->sc_dmabase); 603 while ((--maxloops) > 0 && 604 (bus_space_read_4(iot, ioh, DBRI_REG0) 605 & DBRI_COMMAND_VALID)) { 606 bus_space_barrier(iot, ioh, DBRI_REG0, 4, 607 BUS_SPACE_BARRIER_READ); 608 delay(1000); 609 } 610 611 if (maxloops == 0) { 612 aprint_error_dev(&sc->sc_dev, 613 "chip never completed command buffer\n"); 614 } else { 615 616 DPRINTF("%s: command completed\n", 617 device_xname(&sc->sc_dev)); 618 619 while ((--maxloops) > 0 && (!sc->sc_waitseen)) 620 dbri_process_interrupt_buffer(sc); 621 if (maxloops == 0) { 622 aprint_error_dev(&sc->sc_dev, "chip never acked WAIT\n"); 623 } 624 } 625 } 626 627 splx(x); 628 629 return; 630 } 631 632 static void 633 dbri_process_interrupt_buffer(struct dbri_softc *sc) 634 { 635 int32_t i; 636 637 while ((i = sc->sc_dma->intr[sc->sc_irqp]) != 0) { 638 sc->sc_dma->intr[sc->sc_irqp] = 0; 639 sc->sc_irqp++; 640 641 if (sc->sc_irqp == DBRI_INT_BLOCKS) 642 sc->sc_irqp = 1; 643 else if ((sc->sc_irqp & (DBRI_INT_BLOCKS - 1)) == 0) 644 sc->sc_irqp++; 645 646 dbri_process_interrupt(sc, i); 647 } 648 649 return; 650 } 651 652 static void 653 dbri_process_interrupt(struct dbri_softc *sc, int32_t i) 654 { 655 #if 0 656 const int liu_states[] = { 1, 0, 8, 3, 4, 5, 6, 7 }; 657 #endif 658 int val = DBRI_INTR_GETVAL(i); 659 int channel = DBRI_INTR_GETCHAN(i); 660 int command = DBRI_INTR_GETCMD(i); 661 int code = DBRI_INTR_GETCODE(i); 662 #if 0 663 int rval = DBRI_INTR_GETRVAL(i); 664 #endif 665 if (channel == DBRI_INTR_CMD && command == DBRI_COMMAND_WAIT) 666 sc->sc_waitseen++; 667 668 switch (code) { 669 case DBRI_INTR_XCMP: /* transmission complete */ 670 { 671 int td; 672 struct dbri_desc *dd; 673 674 td = sc->sc_pipe[channel].desc; 675 dd = &sc->sc_desc[td]; 676 677 if (dd->callback != NULL) 678 softint_schedule(dd->softint); 679 break; 680 } 681 case DBRI_INTR_FXDT: /* fixed data change */ 682 DPRINTF("dbri_intr: Fixed data change (%d: %x)\n", channel, 683 val); 684 #if 0 685 printf("reg: %08x\n", sc->sc_mm.status); 686 #endif 687 if (sc->sc_pipe[channel].sdp & DBRI_SDP_MSB) 688 val = reverse_bytes(val, sc->sc_pipe[channel].length); 689 if (sc->sc_pipe[channel].prec) 690 *(sc->sc_pipe[channel].prec) = val; 691 #ifndef DBRI_SPIN 692 DPRINTF("%s: wakeup %p\n", device_xname(&sc->sc_dev), sc); 693 wakeup(sc); 694 #endif 695 break; 696 case DBRI_INTR_SBRI: 697 DPRINTF("dbri_intr: SBRI\n"); 698 break; 699 case DBRI_INTR_BRDY: 700 { 701 int td; 702 struct dbri_desc *dd; 703 704 td = sc->sc_pipe[channel].desc; 705 dd = &sc->sc_desc[td]; 706 707 if (dd->callback != NULL) 708 softint_schedule(dd->softint); 709 break; 710 } 711 case DBRI_INTR_UNDR: 712 { 713 volatile u_int32_t *cmd; 714 int td = sc->sc_pipe[channel].desc; 715 716 DPRINTF("%s: DBRI_INTR_UNDR\n", device_xname(&sc->sc_dev)); 717 718 sc->sc_dma->xmit[td].status = 0; 719 720 cmd = dbri_command_lock(sc); 721 *(cmd++) = DBRI_CMD(DBRI_COMMAND_SDP, 0, 722 sc->sc_pipe[channel].sdp | 723 DBRI_SDP_VALID_POINTER | 724 DBRI_SDP_CLEAR | 725 DBRI_SDP_2SAME); 726 *(cmd++) = sc->sc_dmabase + dbri_dma_off(xmit, td); 727 dbri_command_send(sc, cmd); 728 break; 729 } 730 case DBRI_INTR_CMDI: 731 DPRINTF("ok"); 732 break; 733 default: 734 735 aprint_error_dev(&sc->sc_dev, "unknown interrupt code %d\n", 736 code); 737 break; 738 } 739 740 return; 741 } 742 743 /* 744 * mmcodec stuff 745 */ 746 747 static int 748 mmcodec_init(struct dbri_softc *sc) 749 { 750 bus_space_handle_t ioh = sc->sc_ioh; 751 bus_space_tag_t iot = sc->sc_iot; 752 u_int32_t reg2; 753 int bail; 754 755 reg2 = bus_space_read_4(iot, ioh, DBRI_REG2); 756 DPRINTF("mmcodec_init: PIO reads %x\n", reg2); 757 758 if (reg2 & DBRI_PIO2) { 759 aprint_normal_dev(&sc->sc_dev, " onboard CS4215 detected\n"); 760 sc->sc_mm.onboard = 1; 761 } 762 763 if (reg2 & DBRI_PIO0) { 764 aprint_normal_dev(&sc->sc_dev, "speakerbox detected\n"); 765 bus_space_write_4(iot, ioh, DBRI_REG2, DBRI_PIO2_ENABLE); 766 sc->sc_mm.onboard = 0; 767 } 768 769 if ((reg2 & DBRI_PIO2) && (reg2 & DBRI_PIO0)) { 770 aprint_normal_dev(&sc->sc_dev, "using speakerbox\n"); 771 bus_space_write_4(iot, ioh, DBRI_REG2, DBRI_PIO2_ENABLE); 772 sc->sc_mm.onboard = 0; 773 } 774 775 if (!(reg2 & (DBRI_PIO0|DBRI_PIO2))) { 776 aprint_normal_dev(&sc->sc_dev, "no mmcodec found\n"); 777 return -1; 778 } 779 780 sc->sc_version = 0xff; 781 782 mmcodec_pipe_init(sc); 783 mmcodec_default(sc); 784 785 sc->sc_mm.offset = sc->sc_mm.onboard ? 0 : 8; 786 787 /* 788 * mmcodec_setcontrol() sometimes fails right after powerup 789 * so we just try again until we either get a useful response or run 790 * out of time 791 */ 792 bail = 0; 793 while (mmcodec_setcontrol(sc) == -1 || sc->sc_version == 0xff) { 794 795 bail++; 796 if (bail > 100) { 797 DPRINTF("%s: cs4215 probe failed at offset %d\n", 798 device_xname(&sc->sc_dev), sc->sc_mm.offset); 799 return (-1); 800 } 801 delay(10000); 802 } 803 804 aprint_normal_dev(&sc->sc_dev, "cs4215 rev %c found at offset %d\n", 805 0x43 + (sc->sc_version & 0xf), sc->sc_mm.offset); 806 807 /* set some sane defaults for mmcodec_init_data */ 808 sc->sc_params.channels = 2; 809 sc->sc_params.precision = 16; 810 811 mmcodec_init_data(sc); 812 813 return (0); 814 } 815 816 static void 817 mmcodec_init_data(struct dbri_softc *sc) 818 { 819 bus_space_tag_t iot = sc->sc_iot; 820 bus_space_handle_t ioh = sc->sc_ioh; 821 u_int32_t tmp; 822 int data_width; 823 824 tmp = bus_space_read_4(iot, ioh, DBRI_REG0); 825 tmp &= ~(DBRI_CHI_ACTIVATE); /* disable CHI */ 826 bus_space_write_4(iot, ioh, DBRI_REG0, tmp); 827 828 /* switch CS4215 to data mode - set PIO3 to 1 */ 829 tmp = DBRI_PIO_ENABLE_ALL | DBRI_PIO1 | DBRI_PIO3; 830 831 /* XXX */ 832 tmp |= (sc->sc_mm.onboard ? DBRI_PIO0 : DBRI_PIO2); 833 834 bus_space_write_4(iot, ioh, DBRI_REG2, tmp); 835 chi_reset(sc, CHIslave, 128); 836 837 data_width = sc->sc_params.channels * sc->sc_params.precision; 838 839 if ((data_width != 32) && (data_width != 8)) 840 aprint_error("%s: data_width is %d\n", __func__, data_width); 841 842 pipe_ts_link(sc, 20, PIPEoutput, 16, 32, sc->sc_mm.offset + 32); 843 pipe_ts_link(sc, 4, PIPEoutput, 16, data_width, sc->sc_mm.offset); 844 pipe_ts_link(sc, 6, PIPEinput, 16, data_width, sc->sc_mm.offset); 845 pipe_ts_link(sc, 21, PIPEinput, 16, 32, sc->sc_mm.offset + 32); 846 847 pipe_receive_fixed(sc, 21, &sc->sc_mm.status); 848 849 mmcodec_setgain(sc, 0); 850 851 tmp = bus_space_read_4(iot, ioh, DBRI_REG0); 852 tmp |= DBRI_CHI_ACTIVATE; 853 bus_space_write_4(iot, ioh, DBRI_REG0, tmp); 854 855 return; 856 } 857 858 static void 859 mmcodec_pipe_init(struct dbri_softc *sc) 860 { 861 862 pipe_setup(sc, 4, DBRI_SDP_MEM | DBRI_SDP_TO_SER | DBRI_SDP_MSB); 863 pipe_setup(sc, 20, DBRI_SDP_FIXED | DBRI_SDP_TO_SER | DBRI_SDP_MSB); 864 pipe_setup(sc, 6, DBRI_SDP_MEM | DBRI_SDP_FROM_SER | DBRI_SDP_MSB); 865 pipe_setup(sc, 21, DBRI_SDP_FIXED | DBRI_SDP_FROM_SER | DBRI_SDP_MSB); 866 867 pipe_setup(sc, 17, DBRI_SDP_FIXED | DBRI_SDP_TO_SER | DBRI_SDP_MSB); 868 pipe_setup(sc, 18, DBRI_SDP_FIXED | DBRI_SDP_FROM_SER | DBRI_SDP_MSB); 869 pipe_setup(sc, 19, DBRI_SDP_FIXED | DBRI_SDP_FROM_SER | DBRI_SDP_MSB); 870 871 sc->sc_mm.status = 0; 872 873 pipe_receive_fixed(sc, 18, &sc->sc_mm.status); 874 pipe_receive_fixed(sc, 19, &sc->sc_mm.version); 875 876 return; 877 } 878 879 static void 880 mmcodec_default(struct dbri_softc *sc) 881 { 882 struct cs4215_state *mm = &sc->sc_mm; 883 884 /* 885 * no action, memory resetting only 886 * 887 * data time slots 5-8 888 * speaker, line and headphone enable. set gain to half. 889 * input is line 890 */ 891 mm->d.bdata[0] = sc->sc_latt = 0x20 | CS4215_HE | CS4215_LE; 892 mm->d.bdata[1] = sc->sc_ratt = 0x20 | CS4215_SE; 893 sc->sc_linp = 128; 894 sc->sc_rinp = 128; 895 sc->sc_monitor = 0; 896 sc->sc_input = 1; /* line */ 897 mm->d.bdata[2] = (CS4215_LG((sc->sc_linp >> 4)) & 0x0f) | 898 ((sc->sc_input == 2) ? CS4215_IS : 0) | CS4215_PIO0 | CS4215_PIO1; 899 mm->d.bdata[3] = (CS4215_RG((sc->sc_rinp >> 4) & 0x0f)) | 900 CS4215_MA(15 - ((sc->sc_monitor >> 4) & 0x0f)); 901 902 903 /* 904 * control time slots 1-4 905 * 906 * 0: default I/O voltage scale 907 * 1: 8 bit ulaw, 8kHz, mono, high pass filter disabled 908 * 2: serial enable, CHI master, 128 bits per frame, clock 1 909 * 3: tests disabled 910 */ 911 mm->c.bcontrol[0] = CS4215_RSRVD_1 | CS4215_MLB; 912 mm->c.bcontrol[1] = CS4215_DFR_ULAW | CS4215_FREQ[0].csval; 913 mm->c.bcontrol[2] = CS4215_XCLK | CS4215_BSEL_128 | CS4215_FREQ[0].xtal; 914 mm->c.bcontrol[3] = 0; 915 916 return; 917 } 918 919 static void 920 mmcodec_setgain(struct dbri_softc *sc, int mute) 921 { 922 if (mute) { 923 /* disable all outputs, max. attenuation */ 924 sc->sc_mm.d.bdata[0] = sc->sc_latt | 63; 925 sc->sc_mm.d.bdata[1] = sc->sc_ratt | 63; 926 } else { 927 928 sc->sc_mm.d.bdata[0] = sc->sc_latt; 929 sc->sc_mm.d.bdata[1] = sc->sc_ratt; 930 } 931 932 /* input stuff */ 933 sc->sc_mm.d.bdata[2] = CS4215_LG((sc->sc_linp >> 4) & 0x0f) | 934 ((sc->sc_input == 2) ? CS4215_IS : 0) | CS4215_PIO0 | CS4215_PIO1; 935 sc->sc_mm.d.bdata[3] = (CS4215_RG((sc->sc_rinp >> 4)) & 0x0f) | 936 (CS4215_MA(15 - ((sc->sc_monitor >> 4) & 0x0f))); 937 938 if (sc->sc_powerstate == 0) 939 return; 940 pipe_transmit_fixed(sc, 20, sc->sc_mm.d.ldata); 941 942 DPRINTF("mmcodec_setgain: %08x\n", sc->sc_mm.d.ldata); 943 /* give the chip some time to execute the command */ 944 delay(250); 945 946 return; 947 } 948 949 static int 950 mmcodec_setcontrol(struct dbri_softc *sc) 951 { 952 bus_space_tag_t iot = sc->sc_iot; 953 bus_space_handle_t ioh = sc->sc_ioh; 954 u_int32_t val; 955 u_int32_t tmp; 956 int bail = 0; 957 #if DBRI_SPIN 958 int i; 959 #endif 960 961 /* 962 * Temporarily mute outputs and wait 125 us to make sure that it 963 * happens. This avoids clicking noises. 964 */ 965 mmcodec_setgain(sc, 1); 966 delay(125); 967 968 bus_space_write_4(iot, ioh, DBRI_REG2, 0); 969 delay(125); 970 971 /* enable control mode */ 972 val = DBRI_PIO_ENABLE_ALL | DBRI_PIO1; /* was PIO1 */ 973 974 /* XXX */ 975 val |= (sc->sc_mm.onboard ? DBRI_PIO0 : DBRI_PIO2); 976 977 bus_space_write_4(iot, ioh, DBRI_REG2, val); 978 979 delay(34); 980 981 /* 982 * in control mode, the cs4215 is the slave device, so the 983 * DBRI must act as the CHI master. 984 * 985 * in data mode, the cs4215 must be the CHI master to insure 986 * that the data stream is in sync with its codec 987 */ 988 tmp = bus_space_read_4(iot, ioh, DBRI_REG0); 989 tmp &= ~DBRI_COMMAND_CHI; 990 bus_space_write_4(iot, ioh, DBRI_REG0, tmp); 991 992 chi_reset(sc, CHImaster, 128); 993 994 /* control mode */ 995 pipe_ts_link(sc, 17, PIPEoutput, 16, 32, sc->sc_mm.offset); 996 pipe_ts_link(sc, 18, PIPEinput, 16, 8, sc->sc_mm.offset); 997 pipe_ts_link(sc, 19, PIPEinput, 16, 8, sc->sc_mm.offset + 48); 998 999 /* wait for the chip to echo back CLB as zero */ 1000 sc->sc_mm.c.bcontrol[0] &= ~CS4215_CLB; 1001 pipe_transmit_fixed(sc, 17, sc->sc_mm.c.lcontrol); 1002 1003 tmp = bus_space_read_4(iot, ioh, DBRI_REG0); 1004 tmp |= DBRI_CHI_ACTIVATE; 1005 bus_space_write_4(iot, ioh, DBRI_REG0, tmp); 1006 1007 #if DBRI_SPIN 1008 i = 1024; 1009 while (((sc->sc_mm.status & 0xe4) != 0x20) && --i) { 1010 delay(125); 1011 } 1012 1013 if (i == 0) { 1014 DPRINTF("%s: cs4215 didn't respond to CLB (0x%02x)\n", 1015 device_xname(&sc->sc_dev), sc->sc_mm.status); 1016 return (-1); 1017 } 1018 #else 1019 while (((sc->sc_mm.status & 0xe4) != 0x20) && (bail < 10)) { 1020 DPRINTF("%s: tsleep %p\n", device_xname(&sc->sc_dev), sc); 1021 tsleep(sc, PCATCH | PZERO, "dbrifxdt", hz); 1022 bail++; 1023 } 1024 #endif 1025 if (bail >= 10) { 1026 DPRINTF("%s: switching to control mode timed out (%x %x)\n", 1027 device_xname(&sc->sc_dev), sc->sc_mm.status, 1028 bus_space_read_4(iot, ioh, DBRI_REG2)); 1029 return -1; 1030 } 1031 1032 /* copy the version information before it becomes unreadable again */ 1033 sc->sc_version = sc->sc_mm.version; 1034 1035 /* terminate cs4215 control mode */ 1036 sc->sc_mm.c.bcontrol[0] |= CS4215_CLB; 1037 pipe_transmit_fixed(sc, 17, sc->sc_mm.c.lcontrol); 1038 1039 /* two frames of control info @ 8kHz frame rate = 250us delay */ 1040 delay(250); 1041 1042 mmcodec_setgain(sc, 0); 1043 1044 return (0); 1045 1046 } 1047 1048 /* 1049 * CHI combo 1050 */ 1051 static void 1052 chi_reset(struct dbri_softc *sc, enum ms ms, int bpf) 1053 { 1054 volatile u_int32_t *cmd; 1055 int val; 1056 int clockrate, divisor; 1057 1058 cmd = dbri_command_lock(sc); 1059 1060 /* set CHI anchor: pipe 16 */ 1061 val = DBRI_DTS_VI | DBRI_DTS_INS | DBRI_DTS_PRVIN(16) | DBRI_PIPE(16); 1062 *(cmd++) = DBRI_CMD(DBRI_COMMAND_DTS, 0, val); 1063 *(cmd++) = DBRI_TS_ANCHOR | DBRI_TS_NEXT(16); 1064 *(cmd++) = 0; 1065 1066 val = DBRI_DTS_VO | DBRI_DTS_INS | DBRI_DTS_PRVOUT(16) | DBRI_PIPE(16); 1067 *(cmd++) = DBRI_CMD(DBRI_COMMAND_DTS, 0, val); 1068 *(cmd++) = 0; 1069 *(cmd++) = DBRI_TS_ANCHOR | DBRI_TS_NEXT(16); 1070 1071 sc->sc_pipe[16].sdp = 1; 1072 sc->sc_pipe[16].next = 16; 1073 sc->sc_chi_pipe_in = 16; 1074 sc->sc_chi_pipe_out = 16; 1075 1076 switch (ms) { 1077 case CHIslave: 1078 *(cmd++) = DBRI_CMD(DBRI_COMMAND_CHI, 0, DBRI_CHI_CHICM(0)); 1079 break; 1080 case CHImaster: 1081 clockrate = bpf * 8; 1082 divisor = 12288 / clockrate; 1083 1084 if (divisor > 255 || divisor * clockrate != 12288) 1085 aprint_error_dev(&sc->sc_dev, "illegal bits-per-frame %d\n", 1086 bpf); 1087 1088 *(cmd++) = DBRI_CMD(DBRI_COMMAND_CHI, 0, 1089 DBRI_CHI_CHICM(divisor) | DBRI_CHI_FD | DBRI_CHI_BPF(bpf)); 1090 break; 1091 default: 1092 aprint_error_dev(&sc->sc_dev, "unknown value for ms!\n"); 1093 break; 1094 } 1095 1096 sc->sc_chi_bpf = bpf; 1097 1098 /* CHI data mode */ 1099 *(cmd++) = DBRI_CMD(DBRI_COMMAND_PAUSE, 0, 0); 1100 *(cmd++) = DBRI_CMD(DBRI_COMMAND_CDM, 0, 1101 DBRI_CDM_XCE | DBRI_CDM_XEN | DBRI_CDM_REN); 1102 1103 dbri_command_send(sc, cmd); 1104 1105 return; 1106 } 1107 1108 /* 1109 * pipe stuff 1110 */ 1111 static void 1112 pipe_setup(struct dbri_softc *sc, int pipe, int sdp) 1113 { 1114 DPRINTF("pipe setup: %d\n", pipe); 1115 if (pipe < 0 || pipe >= DBRI_PIPE_MAX) { 1116 aprint_error_dev(&sc->sc_dev, "illegal pipe number %d\n", 1117 pipe); 1118 return; 1119 } 1120 1121 if ((sdp & 0xf800) != sdp) 1122 aprint_error_dev(&sc->sc_dev, "strange SDP value %d\n", 1123 sdp); 1124 1125 if (DBRI_SDP_MODE(sdp) == DBRI_SDP_FIXED && 1126 !(sdp & DBRI_SDP_TO_SER)) 1127 sdp |= DBRI_SDP_CHANGE; 1128 1129 sdp |= DBRI_PIPE(pipe); 1130 1131 sc->sc_pipe[pipe].sdp = sdp; 1132 sc->sc_pipe[pipe].desc = -1; 1133 1134 pipe_reset(sc, pipe); 1135 1136 return; 1137 } 1138 1139 static void 1140 pipe_reset(struct dbri_softc *sc, int pipe) 1141 { 1142 struct dbri_desc *dd; 1143 int sdp; 1144 int desc; 1145 volatile u_int32_t *cmd; 1146 1147 if (pipe < 0 || pipe >= DBRI_PIPE_MAX) { 1148 aprint_error_dev(&sc->sc_dev, "illegal pipe number %d\n", 1149 pipe); 1150 return; 1151 } 1152 1153 sdp = sc->sc_pipe[pipe].sdp; 1154 if (sdp == 0) { 1155 aprint_error_dev(&sc->sc_dev, "can not reset uninitialized pipe %d\n", 1156 pipe); 1157 return; 1158 } 1159 1160 cmd = dbri_command_lock(sc); 1161 *(cmd++) = DBRI_CMD(DBRI_COMMAND_SDP, 0, 1162 sdp | DBRI_SDP_CLEAR | DBRI_SDP_VALID_POINTER); 1163 *(cmd++) = 0; 1164 dbri_command_send(sc, cmd); 1165 1166 desc = sc->sc_pipe[pipe].desc; 1167 1168 dd = &sc->sc_desc[desc]; 1169 1170 dd->busy = 0; 1171 1172 #if 0 1173 if (dd->callback) 1174 softint_schedule(dd->softint); 1175 #endif 1176 1177 sc->sc_pipe[pipe].desc = -1; 1178 1179 return; 1180 } 1181 1182 static void 1183 pipe_receive_fixed(struct dbri_softc *sc, int pipe, volatile u_int32_t *prec) 1184 { 1185 1186 if (pipe < DBRI_PIPE_MAX / 2 || pipe >= DBRI_PIPE_MAX) { 1187 aprint_error_dev(&sc->sc_dev, "illegal pipe number %d\n", 1188 pipe); 1189 return; 1190 } 1191 1192 if (DBRI_SDP_MODE(sc->sc_pipe[pipe].sdp) != DBRI_SDP_FIXED) { 1193 aprint_error_dev(&sc->sc_dev, "non-fixed pipe %d\n", 1194 pipe); 1195 return; 1196 } 1197 1198 if (sc->sc_pipe[pipe].sdp & DBRI_SDP_TO_SER) { 1199 aprint_error_dev(&sc->sc_dev, "can not receive on transmit pipe %d\b", 1200 pipe); 1201 return; 1202 } 1203 1204 sc->sc_pipe[pipe].prec = prec; 1205 1206 return; 1207 } 1208 1209 static void 1210 pipe_transmit_fixed(struct dbri_softc *sc, int pipe, u_int32_t data) 1211 { 1212 volatile u_int32_t *cmd; 1213 1214 if (pipe < DBRI_PIPE_MAX / 2 || pipe >= DBRI_PIPE_MAX) { 1215 aprint_error_dev(&sc->sc_dev, "illegal pipe number %d\n", 1216 pipe); 1217 return; 1218 } 1219 1220 if (DBRI_SDP_MODE(sc->sc_pipe[pipe].sdp) == 0) { 1221 aprint_error_dev(&sc->sc_dev, "uninitialized pipe %d\n", 1222 pipe); 1223 return; 1224 } 1225 1226 if (DBRI_SDP_MODE(sc->sc_pipe[pipe].sdp) != DBRI_SDP_FIXED) { 1227 aprint_error_dev(&sc->sc_dev, "non-fixed pipe %d\n", 1228 pipe); 1229 return; 1230 } 1231 1232 if (!(sc->sc_pipe[pipe].sdp & DBRI_SDP_TO_SER)) { 1233 aprint_error_dev(&sc->sc_dev, "called on receive pipe %d\n", 1234 pipe); 1235 return; 1236 } 1237 1238 if (sc->sc_pipe[pipe].sdp & DBRI_SDP_MSB) 1239 data = reverse_bytes(data, sc->sc_pipe[pipe].length); 1240 1241 cmd = dbri_command_lock(sc); 1242 *(cmd++) = DBRI_CMD(DBRI_COMMAND_SSP, 0, pipe); 1243 *(cmd++) = data; 1244 1245 dbri_command_send(sc, cmd); 1246 1247 return; 1248 } 1249 1250 static void 1251 setup_ring_xmit(struct dbri_softc *sc, int pipe, int which, int num, int blksz, 1252 void (*callback)(void *), void *callback_args) 1253 { 1254 volatile u_int32_t *cmd; 1255 int x, i; 1256 int td; 1257 int td_first, td_last; 1258 bus_addr_t dmabuf, dmabase; 1259 struct dbri_desc *dd = &sc->sc_desc[which]; 1260 1261 switch (pipe) { 1262 case 4: 1263 /* output, offset 0 */ 1264 break; 1265 default: 1266 aprint_error("%s: illegal pipe number (%d)\n", 1267 __func__, pipe); 1268 return; 1269 } 1270 1271 td = 0; 1272 td_first = td_last = -1; 1273 1274 if (sc->sc_pipe[pipe].sdp == 0) { 1275 aprint_error_dev(&sc->sc_dev, "uninitialized pipe %d\n", 1276 pipe); 1277 return; 1278 } 1279 1280 dmabuf = dd->dmabase; 1281 dmabase = sc->sc_dmabase; 1282 td = 0; 1283 1284 for (i = 0; i < (num - 1); i++) { 1285 1286 sc->sc_dma->xmit[i].flags = TX_BCNT(blksz) 1287 | TX_EOF | TX_BINT; 1288 sc->sc_dma->xmit[i].ba = dmabuf; 1289 sc->sc_dma->xmit[i].nda = dmabase + dbri_dma_off(xmit, i + 1); 1290 sc->sc_dma->xmit[i].status = 0; 1291 1292 td_last = td; 1293 dmabuf += blksz; 1294 } 1295 1296 sc->sc_dma->xmit[i].flags = TX_BCNT(blksz) | TX_EOF | TX_BINT; 1297 1298 sc->sc_dma->xmit[i].ba = dmabuf; 1299 sc->sc_dma->xmit[i].nda = dmabase + dbri_dma_off(xmit, 0); 1300 sc->sc_dma->xmit[i].status = 0; 1301 1302 dd->callback = callback; 1303 dd->callback_args = callback_args; 1304 1305 x = splsched(); 1306 1307 /* the pipe shouldn't be active */ 1308 if (pipe_active(sc, pipe)) { 1309 aprint_error("pipe active (CDP)\n"); 1310 /* pipe is already active */ 1311 #if 0 1312 td_last = sc->sc_pipe[pipe].desc; 1313 while (sc->sc_desc[td_last].next != -1) 1314 td_last = sc->sc_desc[td_last].next; 1315 1316 sc->sc_desc[td_last].next = td_first; 1317 sc->sc_dma->desc[td_last].nda = 1318 sc->sc_dmabase + dbri_dma_off(desc, td_first); 1319 1320 cmd = dbri_command_lock(sc); 1321 *(cmd++) = DBRI_CMD(DBRI_COMMAND_CDP, 0, pipe); 1322 dbri_command_send(sc, cmd); 1323 #endif 1324 } else { 1325 /* 1326 * pipe isn't active - issue an SDP command to start our 1327 * chain of TDs running 1328 */ 1329 sc->sc_pipe[pipe].desc = which; 1330 cmd = dbri_command_lock(sc); 1331 *(cmd++) = DBRI_CMD(DBRI_COMMAND_SDP, 0, 1332 sc->sc_pipe[pipe].sdp | 1333 DBRI_SDP_VALID_POINTER | 1334 DBRI_SDP_EVERY | 1335 DBRI_SDP_CLEAR); 1336 *(cmd++) = sc->sc_dmabase + dbri_dma_off(xmit, 0); 1337 dbri_command_send(sc, cmd); 1338 DPRINTF("%s: starting DMA\n", __func__); 1339 } 1340 1341 splx(x); 1342 1343 return; 1344 } 1345 1346 static void 1347 setup_ring_recv(struct dbri_softc *sc, int pipe, int which, int num, int blksz, 1348 void (*callback)(void *), void *callback_args) 1349 { 1350 volatile u_int32_t *cmd; 1351 int x, i; 1352 int td_first, td_last; 1353 bus_addr_t dmabuf, dmabase; 1354 struct dbri_desc *dd = &sc->sc_desc[which]; 1355 1356 switch (pipe) { 1357 case 6: 1358 break; 1359 default: 1360 aprint_error("%s: illegal pipe number (%d)\n", 1361 __func__, pipe); 1362 return; 1363 } 1364 1365 td_first = td_last = -1; 1366 1367 if (sc->sc_pipe[pipe].sdp == 0) { 1368 aprint_error_dev(&sc->sc_dev, "uninitialized pipe %d\n", 1369 pipe); 1370 return; 1371 } 1372 1373 dmabuf = dd->dmabase; 1374 dmabase = sc->sc_dmabase; 1375 1376 for (i = 0; i < (num - 1); i++) { 1377 1378 sc->sc_dma->recv[i].flags = RX_BSIZE(blksz) | RX_FINAL; 1379 sc->sc_dma->recv[i].ba = dmabuf; 1380 sc->sc_dma->recv[i].nda = dmabase + dbri_dma_off(recv, i + 1); 1381 sc->sc_dma->recv[i].status = RX_EOF; 1382 1383 td_last = i; 1384 dmabuf += blksz; 1385 } 1386 1387 sc->sc_dma->recv[i].flags = RX_BSIZE(blksz) | RX_FINAL; 1388 1389 sc->sc_dma->recv[i].ba = dmabuf; 1390 sc->sc_dma->recv[i].nda = dmabase + dbri_dma_off(recv, 0); 1391 sc->sc_dma->recv[i].status = RX_EOF; 1392 1393 dd->callback = callback; 1394 dd->callback_args = callback_args; 1395 1396 x = splsched(); 1397 1398 /* the pipe shouldn't be active */ 1399 if (pipe_active(sc, pipe)) { 1400 aprint_error("pipe active (CDP)\n"); 1401 /* pipe is already active */ 1402 #if 0 1403 td_last = sc->sc_pipe[pipe].desc; 1404 while (sc->sc_desc[td_last].next != -1) 1405 td_last = sc->sc_desc[td_last].next; 1406 1407 sc->sc_desc[td_last].next = td_first; 1408 sc->sc_dma->desc[td_last].nda = 1409 sc->sc_dmabase + dbri_dma_off(desc, td_first); 1410 1411 cmd = dbri_command_lock(sc); 1412 *(cmd++) = DBRI_CMD(DBRI_COMMAND_CDP, 0, pipe); 1413 dbri_command_send(sc, cmd); 1414 #endif 1415 } else { 1416 /* 1417 * pipe isn't active - issue an SDP command to start our 1418 * chain of TDs running 1419 */ 1420 sc->sc_pipe[pipe].desc = which; 1421 cmd = dbri_command_lock(sc); 1422 *(cmd++) = DBRI_CMD(DBRI_COMMAND_SDP, 0, 1423 sc->sc_pipe[pipe].sdp | 1424 DBRI_SDP_VALID_POINTER | 1425 DBRI_SDP_EVERY | 1426 DBRI_SDP_CLEAR); 1427 *(cmd++) = sc->sc_dmabase + dbri_dma_off(recv, 0); 1428 dbri_command_send(sc, cmd); 1429 DPRINTF("%s: starting DMA\n", __func__); 1430 } 1431 1432 splx(x); 1433 1434 return; 1435 } 1436 1437 static void 1438 pipe_ts_link(struct dbri_softc *sc, int pipe, enum io dir, int basepipe, 1439 int len, int cycle) 1440 { 1441 volatile u_int32_t *cmd; 1442 int prevpipe, nextpipe; 1443 int val; 1444 1445 DPRINTF("%s: %d\n", __func__, pipe); 1446 if (pipe < 0 || pipe >= DBRI_PIPE_MAX || 1447 basepipe < 0 || basepipe >= DBRI_PIPE_MAX) { 1448 aprint_error_dev(&sc->sc_dev, "illegal pipe numbers (%d, %d)\n", 1449 pipe, basepipe); 1450 return; 1451 } 1452 1453 if (sc->sc_pipe[pipe].sdp == 0 || sc->sc_pipe[basepipe].sdp == 0) { 1454 aprint_error_dev(&sc->sc_dev, "uninitialized pipe (%d, %d)\n", 1455 pipe, basepipe); 1456 return; 1457 } 1458 1459 if (basepipe == 16 && dir == PIPEoutput && cycle == 0) 1460 cycle = sc->sc_chi_bpf; 1461 1462 if (basepipe == pipe) 1463 prevpipe = nextpipe = pipe; 1464 else { 1465 if (basepipe == 16) { 1466 if (dir == PIPEinput) { 1467 prevpipe = sc->sc_chi_pipe_in; 1468 } else { 1469 prevpipe = sc->sc_chi_pipe_out; 1470 } 1471 } else 1472 prevpipe = basepipe; 1473 1474 nextpipe = sc->sc_pipe[prevpipe].next; 1475 1476 while (sc->sc_pipe[nextpipe].cycle < cycle && 1477 sc->sc_pipe[nextpipe].next != basepipe) { 1478 prevpipe = nextpipe; 1479 nextpipe = sc->sc_pipe[nextpipe].next; 1480 } 1481 } 1482 1483 if (prevpipe == 16) { 1484 if (dir == PIPEinput) { 1485 sc->sc_chi_pipe_in = pipe; 1486 } else { 1487 sc->sc_chi_pipe_out = pipe; 1488 } 1489 } else 1490 sc->sc_pipe[prevpipe].next = pipe; 1491 1492 sc->sc_pipe[pipe].next = nextpipe; 1493 sc->sc_pipe[pipe].cycle = cycle; 1494 sc->sc_pipe[pipe].length = len; 1495 1496 cmd = dbri_command_lock(sc); 1497 1498 switch (dir) { 1499 case PIPEinput: 1500 val = DBRI_DTS_VI | DBRI_DTS_INS | DBRI_DTS_PRVIN(prevpipe); 1501 val |= pipe; 1502 *(cmd++) = DBRI_CMD(DBRI_COMMAND_DTS, 0, val); 1503 *(cmd++) = DBRI_TS_LEN(len) | DBRI_TS_CYCLE(cycle) | 1504 DBRI_TS_NEXT(nextpipe); 1505 *(cmd++) = 0; 1506 break; 1507 case PIPEoutput: 1508 val = DBRI_DTS_VO | DBRI_DTS_INS | DBRI_DTS_PRVOUT(prevpipe); 1509 val |= pipe; 1510 *(cmd++) = DBRI_CMD(DBRI_COMMAND_DTS, 0, val); 1511 *(cmd++) = 0; 1512 *(cmd++) = DBRI_TS_LEN(len) | DBRI_TS_CYCLE(cycle) | 1513 DBRI_TS_NEXT(nextpipe); 1514 break; 1515 default: 1516 DPRINTF("%s: should not have happened!\n", 1517 device_xname(&sc->sc_dev)); 1518 break; 1519 } 1520 1521 dbri_command_send(sc, cmd); 1522 1523 return; 1524 } 1525 1526 static int 1527 pipe_active(struct dbri_softc *sc, int pipe) 1528 { 1529 1530 return (sc->sc_pipe[pipe].desc != -1); 1531 } 1532 1533 /* 1534 * subroutines required to interface with audio(9) 1535 */ 1536 1537 static int 1538 dbri_query_encoding(void *hdl, struct audio_encoding *ae) 1539 { 1540 1541 switch (ae->index) { 1542 case 0: 1543 strcpy(ae->name, AudioEulinear); 1544 ae->encoding = AUDIO_ENCODING_ULINEAR; 1545 ae->precision = 8; 1546 ae->flags = 0; 1547 break; 1548 case 1: 1549 strcpy(ae->name, AudioEmulaw); 1550 ae->encoding = AUDIO_ENCODING_ULAW; 1551 ae->precision = 8; 1552 ae->flags = 0; 1553 break; 1554 case 2: 1555 strcpy(ae->name, AudioEalaw); 1556 ae->encoding = AUDIO_ENCODING_ALAW; 1557 ae->precision = 8; 1558 ae->flags = 0; 1559 break; 1560 case 3: 1561 strcpy(ae->name, AudioEslinear); 1562 ae->encoding = AUDIO_ENCODING_SLINEAR; 1563 ae->precision = 8; 1564 ae->flags = AUDIO_ENCODINGFLAG_EMULATED; 1565 break; 1566 case 4: 1567 strcpy(ae->name, AudioEslinear_le); 1568 ae->encoding = AUDIO_ENCODING_SLINEAR_LE; 1569 ae->precision = 16; 1570 ae->flags = AUDIO_ENCODINGFLAG_EMULATED; 1571 break; 1572 case 5: 1573 strcpy(ae->name, AudioEulinear_le); 1574 ae->encoding = AUDIO_ENCODING_ULINEAR_LE; 1575 ae->precision = 16; 1576 ae->flags = AUDIO_ENCODINGFLAG_EMULATED; 1577 break; 1578 case 6: 1579 strcpy(ae->name, AudioEslinear_be); 1580 ae->encoding = AUDIO_ENCODING_SLINEAR_BE; 1581 ae->precision = 16; 1582 ae->flags = 0; 1583 break; 1584 case 7: 1585 strcpy(ae->name, AudioEulinear_be); 1586 ae->encoding = AUDIO_ENCODING_ULINEAR_BE; 1587 ae->precision = 16; 1588 ae->flags = AUDIO_ENCODINGFLAG_EMULATED; 1589 break; 1590 case 8: 1591 strcpy(ae->name, AudioEslinear); 1592 ae->encoding = AUDIO_ENCODING_SLINEAR; 1593 ae->precision = 16; 1594 ae->flags = 0; 1595 break; 1596 default: 1597 return (EINVAL); 1598 } 1599 1600 return (0); 1601 } 1602 1603 static int 1604 dbri_set_params(void *hdl, int setmode, int usemode, 1605 struct audio_params *play, struct audio_params *rec, 1606 stream_filter_list_t *pfil, stream_filter_list_t *rfil) 1607 { 1608 struct dbri_softc *sc = hdl; 1609 int rate; 1610 audio_params_t *p = NULL; 1611 stream_filter_list_t *fil; 1612 int mode; 1613 1614 /* 1615 * This device only has one clock, so make the sample rates match. 1616 */ 1617 if (play->sample_rate != rec->sample_rate && 1618 usemode == (AUMODE_PLAY | AUMODE_RECORD)) { 1619 if (setmode == AUMODE_PLAY) { 1620 rec->sample_rate = play->sample_rate; 1621 setmode |= AUMODE_RECORD; 1622 } else if (setmode == AUMODE_RECORD) { 1623 play->sample_rate = rec->sample_rate; 1624 setmode |= AUMODE_PLAY; 1625 } else 1626 return EINVAL; 1627 } 1628 1629 for (mode = AUMODE_RECORD; mode != -1; 1630 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) { 1631 if ((setmode & mode) == 0) 1632 continue; 1633 1634 p = mode == AUMODE_PLAY ? play : rec; 1635 if (p->sample_rate < 4000 || p->sample_rate > 50000) { 1636 DPRINTF("dbri_set_params: invalid rate %d\n", 1637 p->sample_rate); 1638 return EINVAL; 1639 } 1640 1641 fil = mode == AUMODE_PLAY ? pfil : rfil; 1642 DPRINTF("requested enc: %d rate: %d prec: %d chan: %d\n", p->encoding, 1643 p->sample_rate, p->precision, p->channels); 1644 if (auconv_set_converter(dbri_formats, DBRI_NFORMATS, 1645 mode, p, true, fil) < 0) { 1646 aprint_debug("dbri_set_params: auconv_set_converter failed\n"); 1647 return EINVAL; 1648 } 1649 if (fil->req_size > 0) 1650 p = &fil->filters[0].param; 1651 } 1652 1653 if (p == NULL) { 1654 DPRINTF("dbri_set_params: no parameters to set\n"); 1655 return 0; 1656 } 1657 1658 DPRINTF("native enc: %d rate: %d prec: %d chan: %d\n", p->encoding, 1659 p->sample_rate, p->precision, p->channels); 1660 1661 for (rate = 0; CS4215_FREQ[rate].freq; rate++) 1662 if (CS4215_FREQ[rate].freq == p->sample_rate) 1663 break; 1664 1665 if (CS4215_FREQ[rate].freq == 0) 1666 return (EINVAL); 1667 1668 /* set frequency */ 1669 sc->sc_mm.c.bcontrol[1] &= ~0x38; 1670 sc->sc_mm.c.bcontrol[1] |= CS4215_FREQ[rate].csval; 1671 sc->sc_mm.c.bcontrol[2] &= ~0x70; 1672 sc->sc_mm.c.bcontrol[2] |= CS4215_FREQ[rate].xtal; 1673 1674 switch (p->encoding) { 1675 case AUDIO_ENCODING_ULAW: 1676 sc->sc_mm.c.bcontrol[1] &= ~3; 1677 sc->sc_mm.c.bcontrol[1] |= CS4215_DFR_ULAW; 1678 break; 1679 case AUDIO_ENCODING_ALAW: 1680 sc->sc_mm.c.bcontrol[1] &= ~3; 1681 sc->sc_mm.c.bcontrol[1] |= CS4215_DFR_ALAW; 1682 break; 1683 case AUDIO_ENCODING_ULINEAR: 1684 sc->sc_mm.c.bcontrol[1] &= ~3; 1685 if (p->precision == 8) { 1686 sc->sc_mm.c.bcontrol[1] |= CS4215_DFR_LINEAR8; 1687 } else { 1688 sc->sc_mm.c.bcontrol[1] |= CS4215_DFR_LINEAR16; 1689 } 1690 break; 1691 case AUDIO_ENCODING_SLINEAR_BE: 1692 case AUDIO_ENCODING_SLINEAR: 1693 sc->sc_mm.c.bcontrol[1] &= ~3; 1694 sc->sc_mm.c.bcontrol[1] |= CS4215_DFR_LINEAR16; 1695 break; 1696 } 1697 1698 switch (p->channels) { 1699 case 1: 1700 sc->sc_mm.c.bcontrol[1] &= ~CS4215_DFR_STEREO; 1701 break; 1702 case 2: 1703 sc->sc_mm.c.bcontrol[1] |= CS4215_DFR_STEREO; 1704 break; 1705 } 1706 1707 return (0); 1708 } 1709 1710 static int 1711 dbri_round_blocksize(void *hdl, int bs, int mode, 1712 const audio_params_t *param) 1713 { 1714 1715 /* DBRI DMA segment size, rounded down to 32bit alignment */ 1716 return 0x1ffc; 1717 } 1718 1719 static int 1720 dbri_halt_output(void *hdl) 1721 { 1722 struct dbri_softc *sc = hdl; 1723 1724 if (!sc->sc_playing) 1725 return 0; 1726 1727 sc->sc_playing = 0; 1728 pipe_reset(sc, 4); 1729 return (0); 1730 } 1731 1732 static int 1733 dbri_getdev(void *hdl, struct audio_device *ret) 1734 { 1735 1736 *ret = dbri_device; 1737 return (0); 1738 } 1739 1740 static int 1741 dbri_set_port(void *hdl, mixer_ctrl_t *mc) 1742 { 1743 struct dbri_softc *sc = hdl; 1744 int latt = sc->sc_latt, ratt = sc->sc_ratt; 1745 1746 switch (mc->dev) { 1747 case DBRI_VOL_OUTPUT: /* master volume */ 1748 latt = (latt & 0xc0) | (63 - 1749 min(mc->un.value.level[AUDIO_MIXER_LEVEL_LEFT] >> 2, 63)); 1750 ratt = (ratt & 0xc0) | (63 - 1751 min(mc->un.value.level[AUDIO_MIXER_LEVEL_RIGHT] >> 2, 63)); 1752 break; 1753 case DBRI_ENABLE_MONO: /* built-in speaker */ 1754 if (mc->un.ord == 1) { 1755 ratt |= CS4215_SE; 1756 } else 1757 ratt &= ~CS4215_SE; 1758 break; 1759 case DBRI_ENABLE_HEADPHONE: /* headphones output */ 1760 if (mc->un.ord == 1) { 1761 latt |= CS4215_HE; 1762 } else 1763 latt &= ~CS4215_HE; 1764 break; 1765 case DBRI_ENABLE_LINE: /* line out */ 1766 if (mc->un.ord == 1) { 1767 latt |= CS4215_LE; 1768 } else 1769 latt &= ~CS4215_LE; 1770 break; 1771 case DBRI_VOL_MONITOR: 1772 if (mc->un.value.level[AUDIO_MIXER_LEVEL_LEFT] == 1773 sc->sc_monitor) 1774 return 0; 1775 sc->sc_monitor = mc->un.value.level[AUDIO_MIXER_LEVEL_LEFT]; 1776 break; 1777 case DBRI_INPUT_GAIN: 1778 sc->sc_linp = mc->un.value.level[AUDIO_MIXER_LEVEL_LEFT]; 1779 sc->sc_rinp = mc->un.value.level[AUDIO_MIXER_LEVEL_RIGHT]; 1780 break; 1781 case DBRI_INPUT_SELECT: 1782 if (mc->un.mask == sc->sc_input) 1783 return 0; 1784 sc->sc_input = mc->un.mask; 1785 break; 1786 } 1787 1788 sc->sc_latt = latt; 1789 sc->sc_ratt = ratt; 1790 1791 mmcodec_setgain(sc, 0); 1792 1793 return (0); 1794 } 1795 1796 static int 1797 dbri_get_port(void *hdl, mixer_ctrl_t *mc) 1798 { 1799 struct dbri_softc *sc = hdl; 1800 1801 switch (mc->dev) { 1802 case DBRI_VOL_OUTPUT: /* master volume */ 1803 mc->un.value.level[AUDIO_MIXER_LEVEL_LEFT] = 1804 (63 - (sc->sc_latt & 0x3f)) << 2; 1805 mc->un.value.level[AUDIO_MIXER_LEVEL_RIGHT] = 1806 (63 - (sc->sc_ratt & 0x3f)) << 2; 1807 return (0); 1808 case DBRI_ENABLE_MONO: /* built-in speaker */ 1809 mc->un.ord = (sc->sc_ratt & CS4215_SE) ? 1 : 0; 1810 return 0; 1811 case DBRI_ENABLE_HEADPHONE: /* headphones output */ 1812 mc->un.ord = (sc->sc_latt & CS4215_HE) ? 1 : 0; 1813 return 0; 1814 case DBRI_ENABLE_LINE: /* line out */ 1815 mc->un.ord = (sc->sc_latt & CS4215_LE) ? 1 : 0; 1816 return 0; 1817 case DBRI_VOL_MONITOR: 1818 mc->un.value.level[AUDIO_MIXER_LEVEL_LEFT] = sc->sc_monitor; 1819 return 0; 1820 case DBRI_INPUT_GAIN: 1821 mc->un.value.level[AUDIO_MIXER_LEVEL_LEFT] = sc->sc_linp; 1822 mc->un.value.level[AUDIO_MIXER_LEVEL_RIGHT] = sc->sc_rinp; 1823 return 0; 1824 case DBRI_INPUT_SELECT: 1825 mc->un.mask = sc->sc_input; 1826 return 0; 1827 } 1828 return (EINVAL); 1829 } 1830 1831 static int 1832 dbri_query_devinfo(void *hdl, mixer_devinfo_t *di) 1833 { 1834 1835 switch (di->index) { 1836 case DBRI_MONITOR_CLASS: 1837 di->mixer_class = DBRI_MONITOR_CLASS; 1838 strcpy(di->label.name, AudioCmonitor); 1839 di->type = AUDIO_MIXER_CLASS; 1840 di->next = di->prev = AUDIO_MIXER_LAST; 1841 return 0; 1842 case DBRI_OUTPUT_CLASS: 1843 di->mixer_class = DBRI_OUTPUT_CLASS; 1844 strcpy(di->label.name, AudioCoutputs); 1845 di->type = AUDIO_MIXER_CLASS; 1846 di->next = di->prev = AUDIO_MIXER_LAST; 1847 return 0; 1848 case DBRI_INPUT_CLASS: 1849 di->mixer_class = DBRI_INPUT_CLASS; 1850 strcpy(di->label.name, AudioCinputs); 1851 di->type = AUDIO_MIXER_CLASS; 1852 di->next = di->prev = AUDIO_MIXER_LAST; 1853 return 0; 1854 case DBRI_VOL_OUTPUT: /* master volume */ 1855 di->mixer_class = DBRI_OUTPUT_CLASS; 1856 di->next = di->prev = AUDIO_MIXER_LAST; 1857 strcpy(di->label.name, AudioNmaster); 1858 di->type = AUDIO_MIXER_VALUE; 1859 di->un.v.num_channels = 2; 1860 strcpy(di->un.v.units.name, AudioNvolume); 1861 return (0); 1862 case DBRI_INPUT_GAIN: /* input gain */ 1863 di->mixer_class = DBRI_INPUT_CLASS; 1864 di->next = di->prev = AUDIO_MIXER_LAST; 1865 strcpy(di->label.name, AudioNrecord); 1866 di->type = AUDIO_MIXER_VALUE; 1867 di->un.v.num_channels = 2; 1868 strcpy(di->un.v.units.name, AudioNvolume); 1869 return (0); 1870 case DBRI_VOL_MONITOR: /* monitor volume */ 1871 di->mixer_class = DBRI_MONITOR_CLASS; 1872 di->next = di->prev = AUDIO_MIXER_LAST; 1873 strcpy(di->label.name, AudioNmonitor); 1874 di->type = AUDIO_MIXER_VALUE; 1875 di->un.v.num_channels = 1; 1876 strcpy(di->un.v.units.name, AudioNvolume); 1877 return (0); 1878 case DBRI_ENABLE_MONO: /* built-in speaker */ 1879 di->mixer_class = DBRI_OUTPUT_CLASS; 1880 di->next = di->prev = AUDIO_MIXER_LAST; 1881 strcpy(di->label.name, AudioNmono); 1882 di->type = AUDIO_MIXER_ENUM; 1883 di->un.e.num_mem = 2; 1884 strcpy(di->un.e.member[0].label.name, AudioNoff); 1885 di->un.e.member[0].ord = 0; 1886 strcpy(di->un.e.member[1].label.name, AudioNon); 1887 di->un.e.member[1].ord = 1; 1888 return (0); 1889 case DBRI_ENABLE_HEADPHONE: /* headphones output */ 1890 di->mixer_class = DBRI_OUTPUT_CLASS; 1891 di->next = di->prev = AUDIO_MIXER_LAST; 1892 strcpy(di->label.name, AudioNheadphone); 1893 di->type = AUDIO_MIXER_ENUM; 1894 di->un.e.num_mem = 2; 1895 strcpy(di->un.e.member[0].label.name, AudioNoff); 1896 di->un.e.member[0].ord = 0; 1897 strcpy(di->un.e.member[1].label.name, AudioNon); 1898 di->un.e.member[1].ord = 1; 1899 return (0); 1900 case DBRI_ENABLE_LINE: /* line out */ 1901 di->mixer_class = DBRI_OUTPUT_CLASS; 1902 di->next = di->prev = AUDIO_MIXER_LAST; 1903 strcpy(di->label.name, AudioNline); 1904 di->type = AUDIO_MIXER_ENUM; 1905 di->un.e.num_mem = 2; 1906 strcpy(di->un.e.member[0].label.name, AudioNoff); 1907 di->un.e.member[0].ord = 0; 1908 strcpy(di->un.e.member[1].label.name, AudioNon); 1909 di->un.e.member[1].ord = 1; 1910 return (0); 1911 case DBRI_INPUT_SELECT: 1912 di->mixer_class = DBRI_INPUT_CLASS; 1913 strcpy(di->label.name, AudioNsource); 1914 di->type = AUDIO_MIXER_SET; 1915 di->prev = di->next = AUDIO_MIXER_LAST; 1916 di->un.s.num_mem = 2; 1917 strcpy(di->un.s.member[0].label.name, AudioNline); 1918 di->un.s.member[0].mask = 1 << 0; 1919 strcpy(di->un.s.member[1].label.name, AudioNmicrophone); 1920 di->un.s.member[1].mask = 1 << 1; 1921 return 0; 1922 } 1923 1924 return (ENXIO); 1925 } 1926 1927 static size_t 1928 dbri_round_buffersize(void *hdl, int dir, size_t bufsize) 1929 { 1930 #ifdef DBRI_BIG_BUFFER 1931 return 16*0x1ffc; /* use ~128KB buffer */ 1932 #else 1933 return bufsize; 1934 #endif 1935 } 1936 1937 static int 1938 dbri_get_props(void *hdl) 1939 { 1940 1941 return AUDIO_PROP_MMAP | AUDIO_PROP_FULLDUPLEX; 1942 } 1943 1944 static int 1945 dbri_trigger_output(void *hdl, void *start, void *end, int blksize, 1946 void (*intr)(void *), void *intrarg, 1947 const struct audio_params *param) 1948 { 1949 struct dbri_softc *sc = hdl; 1950 unsigned long count, num; 1951 1952 if (sc->sc_playing) 1953 return 0; 1954 1955 count = (unsigned long)(((char *)end - (char *)start)); 1956 num = count / blksize; 1957 1958 DPRINTF("trigger_output(%lx %lx) : %d %ld %ld\n", 1959 (unsigned long)intr, 1960 (unsigned long)intrarg, blksize, count, num); 1961 1962 sc->sc_params = *param; 1963 1964 if (sc->sc_recording == 0) { 1965 /* do not muck with the codec when it's already in use */ 1966 if (mmcodec_setcontrol(sc) != 0) 1967 return -1; 1968 mmcodec_init_data(sc); 1969 } 1970 1971 /* 1972 * always use DMA descriptor 0 for output 1973 * no need to allocate them dynamically since we only ever have 1974 * exactly one input stream and exactly one output stream 1975 */ 1976 setup_ring_xmit(sc, 4, 0, num, blksize, intr, intrarg); 1977 sc->sc_playing = 1; 1978 return 0; 1979 } 1980 1981 static int 1982 dbri_halt_input(void *cookie) 1983 { 1984 struct dbri_softc *sc = cookie; 1985 1986 if (!sc->sc_recording) 1987 return 0; 1988 1989 sc->sc_recording = 0; 1990 pipe_reset(sc, 6); 1991 return 0; 1992 } 1993 1994 static int 1995 dbri_trigger_input(void *hdl, void *start, void *end, int blksize, 1996 void (*intr)(void *), void *intrarg, 1997 const struct audio_params *param) 1998 { 1999 struct dbri_softc *sc = hdl; 2000 unsigned long count, num; 2001 2002 if (sc->sc_recording) 2003 return 0; 2004 2005 count = (unsigned long)(((char *)end - (char *)start)); 2006 num = count / blksize; 2007 2008 DPRINTF("trigger_input(%lx %lx) : %d %ld %ld\n", 2009 (unsigned long)intr, 2010 (unsigned long)intrarg, blksize, count, num); 2011 2012 sc->sc_params = *param; 2013 2014 if (sc->sc_playing == 0) { 2015 2016 /* 2017 * we don't support different parameters for playing and 2018 * recording anyway so don't bother whacking the codec if 2019 * it's already set up 2020 */ 2021 mmcodec_setcontrol(sc); 2022 mmcodec_init_data(sc); 2023 } 2024 2025 sc->sc_recording = 1; 2026 setup_ring_recv(sc, 6, 1, num, blksize, intr, intrarg); 2027 return 0; 2028 } 2029 2030 2031 static u_int32_t 2032 reverse_bytes(u_int32_t b, int len) 2033 { 2034 switch (len) { 2035 case 32: 2036 b = ((b & 0xffff0000) >> 16) | ((b & 0x0000ffff) << 16); 2037 case 16: 2038 b = ((b & 0xff00ff00) >> 8) | ((b & 0x00ff00ff) << 8); 2039 case 8: 2040 b = ((b & 0xf0f0f0f0) >> 4) | ((b & 0x0f0f0f0f) << 4); 2041 case 4: 2042 b = ((b & 0xcccccccc) >> 2) | ((b & 0x33333333) << 2); 2043 case 2: 2044 b = ((b & 0xaaaaaaaa) >> 1) | ((b & 0x55555555) << 1); 2045 case 1: 2046 case 0: 2047 break; 2048 default: 2049 DPRINTF("reverse_bytes: unsupported length\n"); 2050 }; 2051 2052 return (b); 2053 } 2054 2055 static void * 2056 dbri_malloc(void *v, int dir, size_t s, struct malloc_type *mt, int flags) 2057 { 2058 struct dbri_softc *sc = v; 2059 struct dbri_desc *dd = &sc->sc_desc[sc->sc_desc_used]; 2060 int rseg; 2061 2062 if (bus_dmamap_create(sc->sc_dmat, s, 1, s, 0, BUS_DMA_NOWAIT, 2063 &dd->dmamap) == 0) { 2064 if (bus_dmamem_alloc(sc->sc_dmat, s, 0, 0, &dd->dmaseg, 2065 1, &rseg, BUS_DMA_NOWAIT) == 0) { 2066 if (bus_dmamem_map(sc->sc_dmat, &dd->dmaseg, rseg, s, 2067 &dd->buf, BUS_DMA_NOWAIT|BUS_DMA_COHERENT) == 0) { 2068 if (dd->buf != NULL) { 2069 if (bus_dmamap_load(sc->sc_dmat, 2070 dd->dmamap, dd->buf, s, NULL, 2071 BUS_DMA_NOWAIT) == 0) { 2072 dd->len = s; 2073 dd->busy = 0; 2074 dd->callback = NULL; 2075 dd->dmabase = 2076 dd->dmamap->dm_segs[0].ds_addr; 2077 DPRINTF("dbri_malloc: using buffer %d %08x\n", 2078 sc->sc_desc_used, (uint32_t)dd->buf); 2079 sc->sc_desc_used++; 2080 return dd->buf; 2081 } else 2082 aprint_error("dbri_malloc: load failed\n"); 2083 } else 2084 aprint_error("dbri_malloc: map returned NULL\n"); 2085 } else 2086 aprint_error("dbri_malloc: map failed\n"); 2087 bus_dmamem_free(sc->sc_dmat, &dd->dmaseg, rseg); 2088 } else 2089 aprint_error("dbri_malloc: malloc() failed\n"); 2090 bus_dmamap_destroy(sc->sc_dmat, dd->dmamap); 2091 } else 2092 aprint_error("dbri_malloc: bus_dmamap_create() failed\n"); 2093 return NULL; 2094 } 2095 2096 static void 2097 dbri_free(void *v, void *p, struct malloc_type *mt) 2098 { 2099 free(p, mt); 2100 } 2101 2102 static paddr_t 2103 dbri_mappage(void *v, void *mem, off_t off, int prot) 2104 { 2105 struct dbri_softc *sc = v;; 2106 int current; 2107 2108 if (off < 0) 2109 return -1; 2110 2111 current = 0; 2112 while ((current < sc->sc_desc_used) && 2113 (sc->sc_desc[current].buf != mem)) 2114 current++; 2115 2116 if (current < sc->sc_desc_used) { 2117 return bus_dmamem_mmap(sc->sc_dmat, 2118 &sc->sc_desc[current].dmaseg, 1, off, prot, BUS_DMA_WAITOK); 2119 } 2120 2121 return -1; 2122 } 2123 2124 static int 2125 dbri_open(void *cookie, int flags) 2126 { 2127 struct dbri_softc *sc = cookie; 2128 2129 DPRINTF("%s: %d\n", __func__, sc->sc_refcount); 2130 2131 if (sc->sc_refcount == 0) 2132 dbri_bring_up(sc); 2133 2134 sc->sc_refcount++; 2135 2136 return 0; 2137 } 2138 2139 static void 2140 dbri_close(void *cookie) 2141 { 2142 struct dbri_softc *sc = cookie; 2143 2144 DPRINTF("%s: %d\n", __func__, sc->sc_refcount); 2145 2146 sc->sc_refcount--; 2147 KASSERT(sc->sc_refcount >= 0); 2148 if (sc->sc_refcount > 0) 2149 return; 2150 2151 dbri_set_power(sc, 0); 2152 sc->sc_playing = 0; 2153 sc->sc_recording = 0; 2154 } 2155 2156 static void 2157 dbri_powerhook(int why, void *cookie) 2158 { 2159 struct dbri_softc *sc = cookie; 2160 2161 if (why == sc->sc_pmgrstate) 2162 return; 2163 2164 switch(why) 2165 { 2166 case PWR_SUSPEND: 2167 dbri_set_power(sc, 0); 2168 break; 2169 case PWR_RESUME: 2170 if (sc->sc_powerstate != 0) 2171 break; 2172 aprint_verbose("resume: %d\n", sc->sc_refcount); 2173 sc->sc_pmgrstate = PWR_RESUME; 2174 if (sc->sc_playing) { 2175 volatile u_int32_t *cmd; 2176 int s; 2177 2178 dbri_bring_up(sc); 2179 s = splsched(); 2180 cmd = dbri_command_lock(sc); 2181 *(cmd++) = DBRI_CMD(DBRI_COMMAND_SDP, 2182 0, sc->sc_pipe[4].sdp | 2183 DBRI_SDP_VALID_POINTER | 2184 DBRI_SDP_EVERY | DBRI_SDP_CLEAR); 2185 *(cmd++) = sc->sc_dmabase + 2186 dbri_dma_off(xmit, 0); 2187 dbri_command_send(sc, cmd); 2188 splx(s); 2189 } 2190 break; 2191 default: 2192 return; 2193 } 2194 sc->sc_pmgrstate = why; 2195 } 2196 2197 #endif /* NAUDIO > 0 */ 2198
Indexes created Sat Sep 27 22:09:54 GMT 2025