dbri.c revision 1.23
1 /* $NetBSD: dbri.c,v 1.23 2009/05/16 18:24:44 martin Exp $ */ 2 3 /* 4 * Copyright (C) 1997 Rudolf Koenig (rfkoenig (at) immd4.informatik.uni-erlangen.de) 5 * Copyright (c) 1998, 1999 Brent Baccala (baccala (at) freesoft.org) 6 * Copyright (c) 2001, 2002 Jared D. McNeill <jmcneill (at) netbsd.org> 7 * Copyright (c) 2005 Michael Lorenz <macallan (at) netbsd.org> 8 * All rights reserved. 9 * 10 * This driver is losely based on a Linux driver written by Rudolf Koenig and 11 * Brent Baccala who kindly gave their permission to use their code in a 12 * BSD-licensed driver. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions 16 * are met: 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in the 21 * documentation and/or other materials provided with the distribution. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 28 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 29 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: dbri.c,v 1.23 2009/05/16 18:24:44 martin Exp $"); 38 39 #include "audio.h" 40 #if NAUDIO > 0 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/errno.h> 45 #include <sys/device.h> 46 #include <sys/malloc.h> 47 #include <sys/proc.h> 48 #include <sys/kernel.h> 49 #include <sys/bus.h> 50 #include <sys/intr.h> 51 52 #include <dev/sbus/sbusvar.h> 53 #include <sparc/sparc/auxreg.h> 54 #include <machine/autoconf.h> 55 56 #include <sys/audioio.h> 57 #include <dev/audio_if.h> 58 #include <dev/auconv.h> 59 60 #include <dev/ic/cs4215reg.h> 61 #include <dev/ic/cs4215var.h> 62 #include <dev/sbus/dbrireg.h> 63 #include <dev/sbus/dbrivar.h> 64 65 #include "opt_sbus_dbri.h" 66 67 #define DBRI_ROM_NAME_PREFIX "SUNW,DBRI" 68 69 #ifdef DBRI_DEBUG 70 # define DPRINTF aprint_normal 71 #else 72 # define DPRINTF while (0) printf 73 #endif 74 75 static const char *dbri_supported[] = { 76 "e", 77 "s3", 78 "" 79 }; 80 81 enum ms { 82 CHImaster, 83 CHIslave 84 }; 85 86 enum io { 87 PIPEinput, 88 PIPEoutput 89 }; 90 91 /* 92 * Function prototypes 93 */ 94 95 /* softc stuff */ 96 static void dbri_attach_sbus(device_t, device_t, void *); 97 static int dbri_match_sbus(device_t, cfdata_t, void *); 98 99 static void dbri_config_interrupts(device_t); 100 101 /* interrupt handler */ 102 static int dbri_intr(void *); 103 static void dbri_softint(void *); 104 105 /* supporting subroutines */ 106 static int dbri_init(struct dbri_softc *); 107 static int dbri_reset(struct dbri_softc *); 108 static volatile u_int32_t *dbri_command_lock(struct dbri_softc *); 109 static void dbri_command_send(struct dbri_softc *, volatile u_int32_t *); 110 static void dbri_process_interrupt_buffer(struct dbri_softc *); 111 static void dbri_process_interrupt(struct dbri_softc *, int32_t); 112 113 /* mmcodec subroutines */ 114 static int mmcodec_init(struct dbri_softc *); 115 static void mmcodec_init_data(struct dbri_softc *); 116 static void mmcodec_pipe_init(struct dbri_softc *); 117 static void mmcodec_default(struct dbri_softc *); 118 static void mmcodec_setgain(struct dbri_softc *, int); 119 static int mmcodec_setcontrol(struct dbri_softc *); 120 121 /* chi subroutines */ 122 static void chi_reset(struct dbri_softc *, enum ms, int); 123 124 /* pipe subroutines */ 125 static void pipe_setup(struct dbri_softc *, int, int); 126 static void pipe_reset(struct dbri_softc *, int); 127 static void pipe_receive_fixed(struct dbri_softc *, int, 128 volatile u_int32_t *); 129 static void pipe_transmit_fixed(struct dbri_softc *, int, u_int32_t); 130 131 static void pipe_ts_link(struct dbri_softc *, int, enum io, int, int, int); 132 static int pipe_active(struct dbri_softc *, int); 133 134 /* audio(9) stuff */ 135 static int dbri_query_encoding(void *, struct audio_encoding *); 136 static int dbri_set_params(void *, int, int, struct audio_params *, 137 struct audio_params *,stream_filter_list_t *, stream_filter_list_t *); 138 static int dbri_round_blocksize(void *, int, int, const audio_params_t *); 139 static int dbri_halt_output(void *); 140 static int dbri_halt_input(void *); 141 static int dbri_getdev(void *, struct audio_device *); 142 static int dbri_set_port(void *, mixer_ctrl_t *); 143 static int dbri_get_port(void *, mixer_ctrl_t *); 144 static int dbri_query_devinfo(void *, mixer_devinfo_t *); 145 static size_t dbri_round_buffersize(void *, int, size_t); 146 static int dbri_get_props(void *); 147 static int dbri_open(void *, int); 148 static void dbri_close(void *); 149 150 static void setup_ring_xmit(struct dbri_softc *, int, int, int, int, 151 void (*)(void *), void *); 152 static void setup_ring_recv(struct dbri_softc *, int, int, int, int, 153 void (*)(void *), void *); 154 155 static int dbri_trigger_output(void *, void *, void *, int, 156 void (*)(void *), void *, const struct audio_params *); 157 static int dbri_trigger_input(void *, void *, void *, int, 158 void (*)(void *), void *, const struct audio_params *); 159 160 static void *dbri_malloc(void *, int, size_t, struct malloc_type *, int); 161 static void dbri_free(void *, void *, struct malloc_type *); 162 static paddr_t dbri_mappage(void *, void *, off_t, int); 163 static void dbri_set_power(struct dbri_softc *, int); 164 static void dbri_bring_up(struct dbri_softc *); 165 static void dbri_powerhook(int, void *); 166 167 /* stupid support routines */ 168 static u_int32_t reverse_bytes(u_int32_t, int); 169 170 struct audio_device dbri_device = { 171 "CS4215", 172 "", 173 "dbri" 174 }; 175 176 struct audio_hw_if dbri_hw_if = { 177 dbri_open, 178 dbri_close, 179 NULL, /* drain */ 180 dbri_query_encoding, 181 dbri_set_params, 182 dbri_round_blocksize, 183 NULL, /* commit_settings */ 184 NULL, /* init_output */ 185 NULL, /* init_input */ 186 NULL, /* start_output */ 187 NULL, /* start_input */ 188 dbri_halt_output, 189 dbri_halt_input, 190 NULL, /* speaker_ctl */ 191 dbri_getdev, 192 NULL, /* setfd */ 193 dbri_set_port, 194 dbri_get_port, 195 dbri_query_devinfo, 196 dbri_malloc, 197 dbri_free, 198 dbri_round_buffersize, 199 dbri_mappage, 200 dbri_get_props, 201 dbri_trigger_output, 202 dbri_trigger_input 203 }; 204 205 CFATTACH_DECL_NEW(dbri, sizeof(struct dbri_softc), 206 dbri_match_sbus, dbri_attach_sbus, NULL, NULL); 207 208 #define DBRI_NFORMATS 4 209 static const struct audio_format dbri_formats[DBRI_NFORMATS] = { 210 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_SLINEAR_BE, 16, 16, 211 2, AUFMT_STEREO, 8, {8000, 9600, 11025, 16000, 22050, 32000, 44100, 212 48000}}, 213 /* {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_ULAW, 8, 8, 214 2, AUFMT_STEREO, 8, {8000, 9600, 11025, 16000, 22050, 32000, 44100, 215 48000}}, 216 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_ALAW, 8, 8, 217 2, AUFMT_STEREO, 8, {8000, 9600, 11025, 16000, 22050, 32000, 44100, 218 48000}}, 219 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_ULINEAR, 8, 8, 220 2, AUFMT_STEREO, 8, {8000, 9600, 11025, 16000, 22050, 32000, 44100, 221 48000}},*/ 222 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_ULAW, 8, 8, 223 1, AUFMT_MONAURAL, 8, {8000, 9600, 11025, 16000, 22050, 32000, 44100, 224 48000}}, 225 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_ALAW, 8, 8, 226 1, AUFMT_MONAURAL, 8, {8000, 9600, 11025, 16000, 22050, 32000, 44100, 227 48000}}, 228 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_ULINEAR, 8, 8, 229 1, AUFMT_MONAURAL, 8, {8000, 9600, 11025, 16000, 22050, 32000, 44100, 230 48000}}, 231 }; 232 233 enum { 234 DBRI_OUTPUT_CLASS, 235 DBRI_VOL_OUTPUT, 236 DBRI_ENABLE_MONO, 237 DBRI_ENABLE_HEADPHONE, 238 DBRI_ENABLE_LINE, 239 DBRI_MONITOR_CLASS, 240 DBRI_VOL_MONITOR, 241 DBRI_INPUT_CLASS, 242 DBRI_INPUT_GAIN, 243 DBRI_INPUT_SELECT, 244 DBRI_RECORD_CLASS, 245 DBRI_ENUM_LAST 246 }; 247 248 /* 249 * Autoconfig routines 250 */ 251 static int 252 dbri_match_sbus(device_t parent, cfdata_t match, void *aux) 253 { 254 struct sbus_attach_args *sa = aux; 255 char *ver; 256 int i; 257 258 if (strncmp(DBRI_ROM_NAME_PREFIX, sa->sa_name, 9)) 259 return (0); 260 261 ver = &sa->sa_name[9]; 262 263 for (i = 0; dbri_supported[i][0] != '\0'; i++) 264 if (strcmp(dbri_supported[i], ver) == 0) 265 return (1); 266 267 return (0); 268 } 269 270 static void 271 dbri_attach_sbus(device_t parent, device_t self, void *aux) 272 { 273 struct dbri_softc *sc = device_private(self); 274 struct sbus_attach_args *sa = aux; 275 bus_space_handle_t ioh; 276 bus_size_t size; 277 int error, rseg, pwr, i; 278 char *ver = &sa->sa_name[9]; 279 280 sc->sc_dev = self; 281 sc->sc_iot = sa->sa_bustag; 282 sc->sc_dmat = sa->sa_dmatag; 283 sc->sc_powerstate = 1; 284 285 pwr = prom_getpropint(sa->sa_node,"pwr-on-auxio",0); 286 aprint_normal(": rev %s\n", ver); 287 288 if (pwr) { 289 /* 290 * we can control DBRI power via auxio and we're initially 291 * powered down 292 */ 293 294 sc->sc_have_powerctl = 1; 295 sc->sc_powerstate = 0; 296 dbri_set_power(sc, 1); 297 powerhook_establish(device_xname(self), dbri_powerhook, sc); 298 } else { 299 /* we can't control power so we're always up */ 300 sc->sc_have_powerctl = 0; 301 sc->sc_powerstate = 1; 302 } 303 304 for (i = 0; i < DBRI_NUM_DESCRIPTORS; i++) { 305 sc->sc_desc[i].softint = softint_establish(SOFTINT_SERIAL, 306 dbri_softint, &sc->sc_desc[i]); 307 } 308 309 if (sa->sa_npromvaddrs) 310 ioh = (bus_space_handle_t)sa->sa_promvaddrs[0]; 311 else { 312 if (sbus_bus_map(sa->sa_bustag, sa->sa_slot, 313 sa->sa_offset, sa->sa_size, 314 BUS_SPACE_MAP_LINEAR, /*0,*/ &ioh) != 0) { 315 aprint_error("%s @ sbus: cannot map registers\n", 316 device_xname(self)); 317 return; 318 } 319 } 320 321 sc->sc_ioh = ioh; 322 323 size = sizeof(struct dbri_dma); 324 325 /* get a DMA handle */ 326 if ((error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, 327 BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) { 328 aprint_error_dev(self, "DMA map create error %d\n", 329 error); 330 return; 331 } 332 333 /* allocate DMA buffer */ 334 if ((error = bus_dmamem_alloc(sc->sc_dmat, size, 0, 0, &sc->sc_dmaseg, 335 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 336 aprint_error_dev(self, "DMA buffer alloc error %d\n", 337 error); 338 return; 339 } 340 341 /* map DMA buffer into CPU addressable space */ 342 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_dmaseg, rseg, size, 343 &sc->sc_membase, 344 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 345 aprint_error_dev(self, "DMA buffer map error %d\n", 346 error); 347 return; 348 } 349 350 /* load the buffer */ 351 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, 352 sc->sc_membase, size, NULL, 353 BUS_DMA_NOWAIT)) != 0) { 354 aprint_error_dev(self, "DMA buffer map load error %d\n", 355 error); 356 bus_dmamem_unmap(sc->sc_dmat, sc->sc_membase, size); 357 bus_dmamem_free(sc->sc_dmat, &sc->sc_dmaseg, rseg); 358 return; 359 } 360 361 /* map the registers into memory */ 362 363 /* kernel virtual address of DMA buffer */ 364 sc->sc_dma = (struct dbri_dma *)sc->sc_membase; 365 /* physical address of DMA buffer */ 366 sc->sc_dmabase = sc->sc_dmamap->dm_segs[0].ds_addr; 367 sc->sc_bufsiz = size; 368 369 sbus_establish(&sc->sc_sd, sc->sc_dev); 370 371 bus_intr_establish(sa->sa_bustag, sa->sa_pri, IPL_SCHED, dbri_intr, 372 sc); 373 374 sc->sc_locked = 0; 375 sc->sc_desc_used = 0; 376 sc->sc_refcount = 0; 377 sc->sc_playing = 0; 378 sc->sc_recording = 0; 379 sc->sc_pmgrstate = PWR_RESUME; 380 config_interrupts(self, &dbri_config_interrupts); 381 382 return; 383 } 384 385 /* 386 * lowlevel routine to switch power for the DBRI chip 387 */ 388 static void 389 dbri_set_power(struct dbri_softc *sc, int state) 390 { 391 int s; 392 393 if (sc->sc_have_powerctl == 0) 394 return; 395 if (sc->sc_powerstate == state) 396 return; 397 398 if (state) { 399 DPRINTF("%s: waiting to power up... ", 400 device_xname(sc->sc_dev)); 401 s = splhigh(); 402 *AUXIO4M_REG |= (AUXIO4M_MMX); 403 splx(s); 404 delay(10000); 405 DPRINTF("done (%02x)\n", *AUXIO4M_REG); 406 } else { 407 DPRINTF("%s: powering down\n", device_xname(sc->sc_dev)); 408 s = splhigh(); 409 *AUXIO4M_REG &= ~AUXIO4M_MMX; 410 splx(s); 411 DPRINTF("done (%02x})\n", *AUXIO4M_REG); 412 } 413 sc->sc_powerstate = state; 414 } 415 416 /* 417 * power up and re-initialize the chip 418 */ 419 static void 420 dbri_bring_up(struct dbri_softc *sc) 421 { 422 423 if (sc->sc_have_powerctl == 0) 424 return; 425 426 if (sc->sc_powerstate == 1) 427 return; 428 429 /* ok, we really need to do something */ 430 dbri_set_power(sc, 1); 431 432 /* 433 * re-initialize the chip but skip all the probing, don't overwrite 434 * any other settings either 435 */ 436 dbri_init(sc); 437 mmcodec_setgain(sc, 1); 438 mmcodec_pipe_init(sc); 439 mmcodec_init_data(sc); 440 mmcodec_setgain(sc, 0); 441 } 442 443 static void 444 dbri_config_interrupts(device_t dev) 445 { 446 struct dbri_softc *sc = device_private(dev); 447 448 dbri_init(sc); 449 mmcodec_init(sc); 450 451 /* Attach ourselves to the high level audio interface */ 452 audio_attach_mi(&dbri_hw_if, sc, sc->sc_dev); 453 454 /* power down until open() */ 455 dbri_set_power(sc, 0); 456 return; 457 } 458 459 static int 460 dbri_intr(void *hdl) 461 { 462 struct dbri_softc *sc = hdl; 463 bus_space_tag_t iot = sc->sc_iot; 464 bus_space_handle_t ioh = sc->sc_ioh; 465 int x; 466 467 /* clear interrupt */ 468 x = bus_space_read_4(iot, ioh, DBRI_REG1); 469 if (x & (DBRI_MRR | DBRI_MLE | DBRI_LBG | DBRI_MBE)) { 470 u_int32_t tmp; 471 472 if (x & DBRI_MRR) 473 aprint_debug_dev(sc->sc_dev, 474 "multiple ack error on sbus\n"); 475 if (x & DBRI_MLE) 476 aprint_debug_dev(sc->sc_dev, 477 "multiple late error on sbus\n"); 478 if (x & DBRI_LBG) 479 aprint_debug_dev(sc->sc_dev, 480 "lost bus grant on sbus\n"); 481 if (x & DBRI_MBE) 482 aprint_debug_dev(sc->sc_dev, "burst error on sbus\n"); 483 484 /* 485 * Some of these errors disable the chip's circuitry. 486 * Re-enable the circuitry and keep on going. 487 */ 488 489 tmp = bus_space_read_4(iot, ioh, DBRI_REG0); 490 tmp &= ~(DBRI_DISABLE_MASTER); 491 bus_space_write_4(iot, ioh, DBRI_REG0, tmp); 492 } 493 494 #if 0 495 if (!x & 1) /* XXX: DBRI_INTR_REQ */ 496 return (1); 497 #endif 498 499 dbri_process_interrupt_buffer(sc); 500 501 return (1); 502 } 503 504 static void 505 dbri_softint(void *cookie) 506 { 507 struct dbri_desc *dd = cookie; 508 509 if (dd->callback != NULL) 510 dd->callback(dd->callback_args); 511 } 512 513 static int 514 dbri_init(struct dbri_softc *sc) 515 { 516 bus_space_tag_t iot = sc->sc_iot; 517 bus_space_handle_t ioh = sc->sc_ioh; 518 u_int32_t reg; 519 volatile u_int32_t *cmd; 520 bus_addr_t dmaaddr; 521 int n; 522 523 dbri_reset(sc); 524 525 cmd = dbri_command_lock(sc); 526 527 /* XXX: Initialize interrupt ring buffer */ 528 sc->sc_dma->intr[0] = (u_int32_t)sc->sc_dmabase + dbri_dma_off(intr, 0); 529 sc->sc_irqp = 1; 530 531 /* Initialize pipes */ 532 for (n = 0; n < DBRI_PIPE_MAX; n++) 533 sc->sc_pipe[n].desc = sc->sc_pipe[n].next = -1; 534 535 for (n = 1; n < DBRI_INT_BLOCKS; n++) { 536 sc->sc_dma->intr[n] = 0; 537 } 538 539 /* Disable all SBus bursts */ 540 /* XXX 16 byte bursts cause errors, the rest works */ 541 reg = bus_space_read_4(iot, ioh, DBRI_REG0); 542 543 /*reg &= ~(DBRI_BURST_4 | DBRI_BURST_8 | DBRI_BURST_16);*/ 544 reg |= (DBRI_BURST_4 | DBRI_BURST_8); 545 bus_space_write_4(iot, ioh, DBRI_REG0, reg); 546 547 /* setup interrupt queue */ 548 dmaaddr = (u_int32_t)sc->sc_dmabase + dbri_dma_off(intr, 0); 549 *(cmd++) = DBRI_CMD(DBRI_COMMAND_IIQ, 0, 0); 550 *(cmd++) = dmaaddr; 551 552 dbri_command_send(sc, cmd); 553 return (0); 554 } 555 556 static int 557 dbri_reset(struct dbri_softc *sc) 558 { 559 int bail = 0; 560 561 bus_space_tag_t iot = sc->sc_iot; 562 bus_space_handle_t ioh = sc->sc_ioh; 563 564 bus_space_write_4(iot, ioh, DBRI_REG0, DBRI_SOFT_RESET); 565 while ((bus_space_read_4(iot, ioh, DBRI_REG0) & DBRI_SOFT_RESET) && 566 (bail < 100000)) { 567 bail++; 568 delay(10); 569 } 570 if (bail == 100000) 571 aprint_error_dev(sc->sc_dev, "reset timed out\n"); 572 return (0); 573 } 574 575 static volatile u_int32_t * 576 dbri_command_lock(struct dbri_softc *sc) 577 { 578 579 if (sc->sc_locked) 580 aprint_debug_dev(sc->sc_dev, "command buffer locked\n"); 581 582 sc->sc_locked++; 583 584 return (&sc->sc_dma->command[0]); 585 } 586 587 static void 588 dbri_command_send(struct dbri_softc *sc, volatile u_int32_t *cmd) 589 { 590 bus_space_handle_t ioh = sc->sc_ioh; 591 bus_space_tag_t iot = sc->sc_iot; 592 int maxloops = 1000000; 593 int x; 594 595 x = splsched(); 596 597 sc->sc_locked--; 598 599 if (sc->sc_locked != 0) { 600 aprint_error_dev(sc->sc_dev, 601 "command buffer improperly locked\n"); 602 } else if ((cmd - &sc->sc_dma->command[0]) >= DBRI_NUM_COMMANDS - 1) { 603 aprint_error_dev(sc->sc_dev, "command buffer overflow\n"); 604 } else { 605 *(cmd++) = DBRI_CMD(DBRI_COMMAND_PAUSE, 0, 0); 606 *(cmd++) = DBRI_CMD(DBRI_COMMAND_WAIT, 1, 0); 607 sc->sc_waitseen = 0; 608 bus_space_write_4(iot, ioh, DBRI_REG8, sc->sc_dmabase); 609 while ((--maxloops) > 0 && 610 (bus_space_read_4(iot, ioh, DBRI_REG0) 611 & DBRI_COMMAND_VALID)) { 612 bus_space_barrier(iot, ioh, DBRI_REG0, 4, 613 BUS_SPACE_BARRIER_READ); 614 delay(1000); 615 } 616 617 if (maxloops == 0) { 618 aprint_error_dev(sc->sc_dev, 619 "chip never completed command buffer\n"); 620 } else { 621 622 DPRINTF("%s: command completed\n", 623 device_xname(sc->sc_dev)); 624 625 while ((--maxloops) > 0 && (!sc->sc_waitseen)) 626 dbri_process_interrupt_buffer(sc); 627 if (maxloops == 0) { 628 aprint_error_dev(sc->sc_dev, "chip never acked WAIT\n"); 629 } 630 } 631 } 632 633 splx(x); 634 635 return; 636 } 637 638 static void 639 dbri_process_interrupt_buffer(struct dbri_softc *sc) 640 { 641 int32_t i; 642 643 while ((i = sc->sc_dma->intr[sc->sc_irqp]) != 0) { 644 sc->sc_dma->intr[sc->sc_irqp] = 0; 645 sc->sc_irqp++; 646 647 if (sc->sc_irqp == DBRI_INT_BLOCKS) 648 sc->sc_irqp = 1; 649 else if ((sc->sc_irqp & (DBRI_INT_BLOCKS - 1)) == 0) 650 sc->sc_irqp++; 651 652 dbri_process_interrupt(sc, i); 653 } 654 655 return; 656 } 657 658 static void 659 dbri_process_interrupt(struct dbri_softc *sc, int32_t i) 660 { 661 #if 0 662 const int liu_states[] = { 1, 0, 8, 3, 4, 5, 6, 7 }; 663 #endif 664 int val = DBRI_INTR_GETVAL(i); 665 int channel = DBRI_INTR_GETCHAN(i); 666 int command = DBRI_INTR_GETCMD(i); 667 int code = DBRI_INTR_GETCODE(i); 668 #if 0 669 int rval = DBRI_INTR_GETRVAL(i); 670 #endif 671 if (channel == DBRI_INTR_CMD && command == DBRI_COMMAND_WAIT) 672 sc->sc_waitseen++; 673 674 switch (code) { 675 case DBRI_INTR_XCMP: /* transmission complete */ 676 { 677 int td; 678 struct dbri_desc *dd; 679 680 td = sc->sc_pipe[channel].desc; 681 dd = &sc->sc_desc[td]; 682 683 if (dd->callback != NULL) 684 softint_schedule(dd->softint); 685 break; 686 } 687 case DBRI_INTR_FXDT: /* fixed data change */ 688 DPRINTF("dbri_intr: Fixed data change (%d: %x)\n", channel, 689 val); 690 #if 0 691 printf("reg: %08x\n", sc->sc_mm.status); 692 #endif 693 if (sc->sc_pipe[channel].sdp & DBRI_SDP_MSB) 694 val = reverse_bytes(val, sc->sc_pipe[channel].length); 695 if (sc->sc_pipe[channel].prec) 696 *(sc->sc_pipe[channel].prec) = val; 697 #ifndef DBRI_SPIN 698 DPRINTF("%s: wakeup %p\n", device_xname(sc->sc_dev), sc); 699 wakeup(sc); 700 #endif 701 break; 702 case DBRI_INTR_SBRI: 703 DPRINTF("dbri_intr: SBRI\n"); 704 break; 705 case DBRI_INTR_BRDY: 706 { 707 int td; 708 struct dbri_desc *dd; 709 710 td = sc->sc_pipe[channel].desc; 711 dd = &sc->sc_desc[td]; 712 713 if (dd->callback != NULL) 714 softint_schedule(dd->softint); 715 break; 716 } 717 case DBRI_INTR_UNDR: 718 { 719 volatile u_int32_t *cmd; 720 int td = sc->sc_pipe[channel].desc; 721 722 DPRINTF("%s: DBRI_INTR_UNDR\n", device_xname(sc->sc_dev)); 723 724 sc->sc_dma->xmit[td].status = 0; 725 726 cmd = dbri_command_lock(sc); 727 *(cmd++) = DBRI_CMD(DBRI_COMMAND_SDP, 0, 728 sc->sc_pipe[channel].sdp | 729 DBRI_SDP_VALID_POINTER | 730 DBRI_SDP_CLEAR | 731 DBRI_SDP_2SAME); 732 *(cmd++) = sc->sc_dmabase + dbri_dma_off(xmit, td); 733 dbri_command_send(sc, cmd); 734 break; 735 } 736 case DBRI_INTR_CMDI: 737 DPRINTF("ok"); 738 break; 739 default: 740 741 aprint_error_dev(sc->sc_dev, "unknown interrupt code %d\n", 742 code); 743 break; 744 } 745 746 return; 747 } 748 749 /* 750 * mmcodec stuff 751 */ 752 753 static int 754 mmcodec_init(struct dbri_softc *sc) 755 { 756 bus_space_handle_t ioh = sc->sc_ioh; 757 bus_space_tag_t iot = sc->sc_iot; 758 u_int32_t reg2; 759 int bail; 760 761 reg2 = bus_space_read_4(iot, ioh, DBRI_REG2); 762 DPRINTF("mmcodec_init: PIO reads %x\n", reg2); 763 764 if (reg2 & DBRI_PIO2) { 765 aprint_normal_dev(sc->sc_dev, " onboard CS4215 detected\n"); 766 sc->sc_mm.onboard = 1; 767 } 768 769 if (reg2 & DBRI_PIO0) { 770 aprint_normal_dev(sc->sc_dev, "speakerbox detected\n"); 771 bus_space_write_4(iot, ioh, DBRI_REG2, DBRI_PIO2_ENABLE); 772 sc->sc_mm.onboard = 0; 773 } 774 775 if ((reg2 & DBRI_PIO2) && (reg2 & DBRI_PIO0)) { 776 aprint_normal_dev(sc->sc_dev, "using speakerbox\n"); 777 bus_space_write_4(iot, ioh, DBRI_REG2, DBRI_PIO2_ENABLE); 778 sc->sc_mm.onboard = 0; 779 } 780 781 if (!(reg2 & (DBRI_PIO0|DBRI_PIO2))) { 782 aprint_normal_dev(sc->sc_dev, "no mmcodec found\n"); 783 return -1; 784 } 785 786 sc->sc_version = 0xff; 787 788 mmcodec_pipe_init(sc); 789 mmcodec_default(sc); 790 791 sc->sc_mm.offset = sc->sc_mm.onboard ? 0 : 8; 792 793 /* 794 * mmcodec_setcontrol() sometimes fails right after powerup 795 * so we just try again until we either get a useful response or run 796 * out of time 797 */ 798 bail = 0; 799 while (mmcodec_setcontrol(sc) == -1 || sc->sc_version == 0xff) { 800 801 bail++; 802 if (bail > 100) { 803 DPRINTF("%s: cs4215 probe failed at offset %d\n", 804 device_xname(sc->sc_dev), sc->sc_mm.offset); 805 return (-1); 806 } 807 delay(10000); 808 } 809 810 aprint_normal_dev(sc->sc_dev, "cs4215 rev %c found at offset %d\n", 811 0x43 + (sc->sc_version & 0xf), sc->sc_mm.offset); 812 813 /* set some sane defaults for mmcodec_init_data */ 814 sc->sc_params.channels = 2; 815 sc->sc_params.precision = 16; 816 817 mmcodec_init_data(sc); 818 819 return (0); 820 } 821 822 static void 823 mmcodec_init_data(struct dbri_softc *sc) 824 { 825 bus_space_tag_t iot = sc->sc_iot; 826 bus_space_handle_t ioh = sc->sc_ioh; 827 u_int32_t tmp; 828 int data_width; 829 830 tmp = bus_space_read_4(iot, ioh, DBRI_REG0); 831 tmp &= ~(DBRI_CHI_ACTIVATE); /* disable CHI */ 832 bus_space_write_4(iot, ioh, DBRI_REG0, tmp); 833 834 /* switch CS4215 to data mode - set PIO3 to 1 */ 835 tmp = DBRI_PIO_ENABLE_ALL | DBRI_PIO1 | DBRI_PIO3; 836 837 /* XXX */ 838 tmp |= (sc->sc_mm.onboard ? DBRI_PIO0 : DBRI_PIO2); 839 840 bus_space_write_4(iot, ioh, DBRI_REG2, tmp); 841 chi_reset(sc, CHIslave, 128); 842 843 data_width = sc->sc_params.channels * sc->sc_params.precision; 844 845 if ((data_width != 32) && (data_width != 8)) 846 aprint_error("%s: data_width is %d\n", __func__, data_width); 847 848 pipe_ts_link(sc, 20, PIPEoutput, 16, 32, sc->sc_mm.offset + 32); 849 pipe_ts_link(sc, 4, PIPEoutput, 16, data_width, sc->sc_mm.offset); 850 pipe_ts_link(sc, 6, PIPEinput, 16, data_width, sc->sc_mm.offset); 851 pipe_ts_link(sc, 21, PIPEinput, 16, 32, sc->sc_mm.offset + 32); 852 853 pipe_receive_fixed(sc, 21, &sc->sc_mm.status); 854 855 mmcodec_setgain(sc, 0); 856 857 tmp = bus_space_read_4(iot, ioh, DBRI_REG0); 858 tmp |= DBRI_CHI_ACTIVATE; 859 bus_space_write_4(iot, ioh, DBRI_REG0, tmp); 860 861 return; 862 } 863 864 static void 865 mmcodec_pipe_init(struct dbri_softc *sc) 866 { 867 868 pipe_setup(sc, 4, DBRI_SDP_MEM | DBRI_SDP_TO_SER | DBRI_SDP_MSB); 869 pipe_setup(sc, 20, DBRI_SDP_FIXED | DBRI_SDP_TO_SER | DBRI_SDP_MSB); 870 pipe_setup(sc, 6, DBRI_SDP_MEM | DBRI_SDP_FROM_SER | DBRI_SDP_MSB); 871 pipe_setup(sc, 21, DBRI_SDP_FIXED | DBRI_SDP_FROM_SER | DBRI_SDP_MSB); 872 873 pipe_setup(sc, 17, DBRI_SDP_FIXED | DBRI_SDP_TO_SER | DBRI_SDP_MSB); 874 pipe_setup(sc, 18, DBRI_SDP_FIXED | DBRI_SDP_FROM_SER | DBRI_SDP_MSB); 875 pipe_setup(sc, 19, DBRI_SDP_FIXED | DBRI_SDP_FROM_SER | DBRI_SDP_MSB); 876 877 sc->sc_mm.status = 0; 878 879 pipe_receive_fixed(sc, 18, &sc->sc_mm.status); 880 pipe_receive_fixed(sc, 19, &sc->sc_mm.version); 881 882 return; 883 } 884 885 static void 886 mmcodec_default(struct dbri_softc *sc) 887 { 888 struct cs4215_state *mm = &sc->sc_mm; 889 890 /* 891 * no action, memory resetting only 892 * 893 * data time slots 5-8 894 * speaker, line and headphone enable. set gain to half. 895 * input is line 896 */ 897 mm->d.bdata[0] = sc->sc_latt = 0x20 | CS4215_HE | CS4215_LE; 898 mm->d.bdata[1] = sc->sc_ratt = 0x20 | CS4215_SE; 899 sc->sc_linp = 128; 900 sc->sc_rinp = 128; 901 sc->sc_monitor = 0; 902 sc->sc_input = 1; /* line */ 903 mm->d.bdata[2] = (CS4215_LG((sc->sc_linp >> 4)) & 0x0f) | 904 ((sc->sc_input == 2) ? CS4215_IS : 0) | CS4215_PIO0 | CS4215_PIO1; 905 mm->d.bdata[3] = (CS4215_RG((sc->sc_rinp >> 4) & 0x0f)) | 906 CS4215_MA(15 - ((sc->sc_monitor >> 4) & 0x0f)); 907 908 909 /* 910 * control time slots 1-4 911 * 912 * 0: default I/O voltage scale 913 * 1: 8 bit ulaw, 8kHz, mono, high pass filter disabled 914 * 2: serial enable, CHI master, 128 bits per frame, clock 1 915 * 3: tests disabled 916 */ 917 mm->c.bcontrol[0] = CS4215_RSRVD_1 | CS4215_MLB; 918 mm->c.bcontrol[1] = CS4215_DFR_ULAW | CS4215_FREQ[0].csval; 919 mm->c.bcontrol[2] = CS4215_XCLK | CS4215_BSEL_128 | CS4215_FREQ[0].xtal; 920 mm->c.bcontrol[3] = 0; 921 922 return; 923 } 924 925 static void 926 mmcodec_setgain(struct dbri_softc *sc, int mute) 927 { 928 if (mute) { 929 /* disable all outputs, max. attenuation */ 930 sc->sc_mm.d.bdata[0] = sc->sc_latt | 63; 931 sc->sc_mm.d.bdata[1] = sc->sc_ratt | 63; 932 } else { 933 934 sc->sc_mm.d.bdata[0] = sc->sc_latt; 935 sc->sc_mm.d.bdata[1] = sc->sc_ratt; 936 } 937 938 /* input stuff */ 939 sc->sc_mm.d.bdata[2] = CS4215_LG((sc->sc_linp >> 4) & 0x0f) | 940 ((sc->sc_input == 2) ? CS4215_IS : 0) | CS4215_PIO0 | CS4215_PIO1; 941 sc->sc_mm.d.bdata[3] = (CS4215_RG((sc->sc_rinp >> 4)) & 0x0f) | 942 (CS4215_MA(15 - ((sc->sc_monitor >> 4) & 0x0f))); 943 944 if (sc->sc_powerstate == 0) 945 return; 946 pipe_transmit_fixed(sc, 20, sc->sc_mm.d.ldata); 947 948 DPRINTF("mmcodec_setgain: %08x\n", sc->sc_mm.d.ldata); 949 /* give the chip some time to execute the command */ 950 delay(250); 951 952 return; 953 } 954 955 static int 956 mmcodec_setcontrol(struct dbri_softc *sc) 957 { 958 bus_space_tag_t iot = sc->sc_iot; 959 bus_space_handle_t ioh = sc->sc_ioh; 960 u_int32_t val; 961 u_int32_t tmp; 962 int bail = 0; 963 #if DBRI_SPIN 964 int i; 965 #endif 966 967 /* 968 * Temporarily mute outputs and wait 125 us to make sure that it 969 * happens. This avoids clicking noises. 970 */ 971 mmcodec_setgain(sc, 1); 972 delay(125); 973 974 bus_space_write_4(iot, ioh, DBRI_REG2, 0); 975 delay(125); 976 977 /* enable control mode */ 978 val = DBRI_PIO_ENABLE_ALL | DBRI_PIO1; /* was PIO1 */ 979 980 /* XXX */ 981 val |= (sc->sc_mm.onboard ? DBRI_PIO0 : DBRI_PIO2); 982 983 bus_space_write_4(iot, ioh, DBRI_REG2, val); 984 985 delay(34); 986 987 /* 988 * in control mode, the cs4215 is the slave device, so the 989 * DBRI must act as the CHI master. 990 * 991 * in data mode, the cs4215 must be the CHI master to insure 992 * that the data stream is in sync with its codec 993 */ 994 tmp = bus_space_read_4(iot, ioh, DBRI_REG0); 995 tmp &= ~DBRI_COMMAND_CHI; 996 bus_space_write_4(iot, ioh, DBRI_REG0, tmp); 997 998 chi_reset(sc, CHImaster, 128); 999 1000 /* control mode */ 1001 pipe_ts_link(sc, 17, PIPEoutput, 16, 32, sc->sc_mm.offset); 1002 pipe_ts_link(sc, 18, PIPEinput, 16, 8, sc->sc_mm.offset); 1003 pipe_ts_link(sc, 19, PIPEinput, 16, 8, sc->sc_mm.offset + 48); 1004 1005 /* wait for the chip to echo back CLB as zero */ 1006 sc->sc_mm.c.bcontrol[0] &= ~CS4215_CLB; 1007 pipe_transmit_fixed(sc, 17, sc->sc_mm.c.lcontrol); 1008 1009 tmp = bus_space_read_4(iot, ioh, DBRI_REG0); 1010 tmp |= DBRI_CHI_ACTIVATE; 1011 bus_space_write_4(iot, ioh, DBRI_REG0, tmp); 1012 1013 #if DBRI_SPIN 1014 i = 1024; 1015 while (((sc->sc_mm.status & 0xe4) != 0x20) && --i) { 1016 delay(125); 1017 } 1018 1019 if (i == 0) { 1020 DPRINTF("%s: cs4215 didn't respond to CLB (0x%02x)\n", 1021 device_xname(sc->sc_dev), sc->sc_mm.status); 1022 return (-1); 1023 } 1024 #else 1025 while (((sc->sc_mm.status & 0xe4) != 0x20) && (bail < 10)) { 1026 DPRINTF("%s: tsleep %p\n", device_xname(sc->sc_dev), sc); 1027 tsleep(sc, PCATCH | PZERO, "dbrifxdt", hz); 1028 bail++; 1029 } 1030 #endif 1031 if (bail >= 10) { 1032 DPRINTF("%s: switching to control mode timed out (%x %x)\n", 1033 device_xname(sc->sc_dev), sc->sc_mm.status, 1034 bus_space_read_4(iot, ioh, DBRI_REG2)); 1035 return -1; 1036 } 1037 1038 /* copy the version information before it becomes unreadable again */ 1039 sc->sc_version = sc->sc_mm.version; 1040 1041 /* terminate cs4215 control mode */ 1042 sc->sc_mm.c.bcontrol[0] |= CS4215_CLB; 1043 pipe_transmit_fixed(sc, 17, sc->sc_mm.c.lcontrol); 1044 1045 /* two frames of control info @ 8kHz frame rate = 250us delay */ 1046 delay(250); 1047 1048 mmcodec_setgain(sc, 0); 1049 1050 return (0); 1051 1052 } 1053 1054 /* 1055 * CHI combo 1056 */ 1057 static void 1058 chi_reset(struct dbri_softc *sc, enum ms ms, int bpf) 1059 { 1060 volatile u_int32_t *cmd; 1061 int val; 1062 int clockrate, divisor; 1063 1064 cmd = dbri_command_lock(sc); 1065 1066 /* set CHI anchor: pipe 16 */ 1067 val = DBRI_DTS_VI | DBRI_DTS_INS | DBRI_DTS_PRVIN(16) | DBRI_PIPE(16); 1068 *(cmd++) = DBRI_CMD(DBRI_COMMAND_DTS, 0, val); 1069 *(cmd++) = DBRI_TS_ANCHOR | DBRI_TS_NEXT(16); 1070 *(cmd++) = 0; 1071 1072 val = DBRI_DTS_VO | DBRI_DTS_INS | DBRI_DTS_PRVOUT(16) | DBRI_PIPE(16); 1073 *(cmd++) = DBRI_CMD(DBRI_COMMAND_DTS, 0, val); 1074 *(cmd++) = 0; 1075 *(cmd++) = DBRI_TS_ANCHOR | DBRI_TS_NEXT(16); 1076 1077 sc->sc_pipe[16].sdp = 1; 1078 sc->sc_pipe[16].next = 16; 1079 sc->sc_chi_pipe_in = 16; 1080 sc->sc_chi_pipe_out = 16; 1081 1082 switch (ms) { 1083 case CHIslave: 1084 *(cmd++) = DBRI_CMD(DBRI_COMMAND_CHI, 0, DBRI_CHI_CHICM(0)); 1085 break; 1086 case CHImaster: 1087 clockrate = bpf * 8; 1088 divisor = 12288 / clockrate; 1089 1090 if (divisor > 255 || divisor * clockrate != 12288) 1091 aprint_error_dev(sc->sc_dev, 1092 "illegal bits-per-frame %d\n", bpf); 1093 1094 *(cmd++) = DBRI_CMD(DBRI_COMMAND_CHI, 0, 1095 DBRI_CHI_CHICM(divisor) | DBRI_CHI_FD | DBRI_CHI_BPF(bpf)); 1096 break; 1097 default: 1098 aprint_error_dev(sc->sc_dev, "unknown value for ms!\n"); 1099 break; 1100 } 1101 1102 sc->sc_chi_bpf = bpf; 1103 1104 /* CHI data mode */ 1105 *(cmd++) = DBRI_CMD(DBRI_COMMAND_PAUSE, 0, 0); 1106 *(cmd++) = DBRI_CMD(DBRI_COMMAND_CDM, 0, 1107 DBRI_CDM_XCE | DBRI_CDM_XEN | DBRI_CDM_REN); 1108 1109 dbri_command_send(sc, cmd); 1110 1111 return; 1112 } 1113 1114 /* 1115 * pipe stuff 1116 */ 1117 static void 1118 pipe_setup(struct dbri_softc *sc, int pipe, int sdp) 1119 { 1120 DPRINTF("pipe setup: %d\n", pipe); 1121 if (pipe < 0 || pipe >= DBRI_PIPE_MAX) { 1122 aprint_error_dev(sc->sc_dev, "illegal pipe number %d\n", 1123 pipe); 1124 return; 1125 } 1126 1127 if ((sdp & 0xf800) != sdp) 1128 aprint_error_dev(sc->sc_dev, "strange SDP value %d\n", 1129 sdp); 1130 1131 if (DBRI_SDP_MODE(sdp) == DBRI_SDP_FIXED && 1132 !(sdp & DBRI_SDP_TO_SER)) 1133 sdp |= DBRI_SDP_CHANGE; 1134 1135 sdp |= DBRI_PIPE(pipe); 1136 1137 sc->sc_pipe[pipe].sdp = sdp; 1138 sc->sc_pipe[pipe].desc = -1; 1139 1140 pipe_reset(sc, pipe); 1141 1142 return; 1143 } 1144 1145 static void 1146 pipe_reset(struct dbri_softc *sc, int pipe) 1147 { 1148 struct dbri_desc *dd; 1149 int sdp; 1150 int desc; 1151 volatile u_int32_t *cmd; 1152 1153 if (pipe < 0 || pipe >= DBRI_PIPE_MAX) { 1154 aprint_error_dev(sc->sc_dev, "illegal pipe number %d\n", 1155 pipe); 1156 return; 1157 } 1158 1159 sdp = sc->sc_pipe[pipe].sdp; 1160 if (sdp == 0) { 1161 aprint_error_dev(sc->sc_dev, "can not reset uninitialized pipe %d\n", 1162 pipe); 1163 return; 1164 } 1165 1166 cmd = dbri_command_lock(sc); 1167 *(cmd++) = DBRI_CMD(DBRI_COMMAND_SDP, 0, 1168 sdp | DBRI_SDP_CLEAR | DBRI_SDP_VALID_POINTER); 1169 *(cmd++) = 0; 1170 dbri_command_send(sc, cmd); 1171 1172 desc = sc->sc_pipe[pipe].desc; 1173 1174 dd = &sc->sc_desc[desc]; 1175 1176 dd->busy = 0; 1177 1178 #if 0 1179 if (dd->callback) 1180 softint_schedule(dd->softint); 1181 #endif 1182 1183 sc->sc_pipe[pipe].desc = -1; 1184 1185 return; 1186 } 1187 1188 static void 1189 pipe_receive_fixed(struct dbri_softc *sc, int pipe, volatile u_int32_t *prec) 1190 { 1191 1192 if (pipe < DBRI_PIPE_MAX / 2 || pipe >= DBRI_PIPE_MAX) { 1193 aprint_error_dev(sc->sc_dev, "illegal pipe number %d\n", 1194 pipe); 1195 return; 1196 } 1197 1198 if (DBRI_SDP_MODE(sc->sc_pipe[pipe].sdp) != DBRI_SDP_FIXED) { 1199 aprint_error_dev(sc->sc_dev, "non-fixed pipe %d\n", 1200 pipe); 1201 return; 1202 } 1203 1204 if (sc->sc_pipe[pipe].sdp & DBRI_SDP_TO_SER) { 1205 aprint_error_dev(sc->sc_dev, "can not receive on transmit pipe %d\b", 1206 pipe); 1207 return; 1208 } 1209 1210 sc->sc_pipe[pipe].prec = prec; 1211 1212 return; 1213 } 1214 1215 static void 1216 pipe_transmit_fixed(struct dbri_softc *sc, int pipe, u_int32_t data) 1217 { 1218 volatile u_int32_t *cmd; 1219 1220 if (pipe < DBRI_PIPE_MAX / 2 || pipe >= DBRI_PIPE_MAX) { 1221 aprint_error_dev(sc->sc_dev, "illegal pipe number %d\n", 1222 pipe); 1223 return; 1224 } 1225 1226 if (DBRI_SDP_MODE(sc->sc_pipe[pipe].sdp) == 0) { 1227 aprint_error_dev(sc->sc_dev, "uninitialized pipe %d\n", 1228 pipe); 1229 return; 1230 } 1231 1232 if (DBRI_SDP_MODE(sc->sc_pipe[pipe].sdp) != DBRI_SDP_FIXED) { 1233 aprint_error_dev(sc->sc_dev, "non-fixed pipe %d\n", 1234 pipe); 1235 return; 1236 } 1237 1238 if (!(sc->sc_pipe[pipe].sdp & DBRI_SDP_TO_SER)) { 1239 aprint_error_dev(sc->sc_dev, "called on receive pipe %d\n", 1240 pipe); 1241 return; 1242 } 1243 1244 if (sc->sc_pipe[pipe].sdp & DBRI_SDP_MSB) 1245 data = reverse_bytes(data, sc->sc_pipe[pipe].length); 1246 1247 cmd = dbri_command_lock(sc); 1248 *(cmd++) = DBRI_CMD(DBRI_COMMAND_SSP, 0, pipe); 1249 *(cmd++) = data; 1250 1251 dbri_command_send(sc, cmd); 1252 1253 return; 1254 } 1255 1256 static void 1257 setup_ring_xmit(struct dbri_softc *sc, int pipe, int which, int num, int blksz, 1258 void (*callback)(void *), void *callback_args) 1259 { 1260 volatile u_int32_t *cmd; 1261 int x, i; 1262 int td; 1263 int td_first, td_last; 1264 bus_addr_t dmabuf, dmabase; 1265 struct dbri_desc *dd = &sc->sc_desc[which]; 1266 1267 switch (pipe) { 1268 case 4: 1269 /* output, offset 0 */ 1270 break; 1271 default: 1272 aprint_error("%s: illegal pipe number (%d)\n", 1273 __func__, pipe); 1274 return; 1275 } 1276 1277 td = 0; 1278 td_first = td_last = -1; 1279 1280 if (sc->sc_pipe[pipe].sdp == 0) { 1281 aprint_error_dev(sc->sc_dev, "uninitialized pipe %d\n", 1282 pipe); 1283 return; 1284 } 1285 1286 dmabuf = dd->dmabase; 1287 dmabase = sc->sc_dmabase; 1288 td = 0; 1289 1290 for (i = 0; i < (num - 1); i++) { 1291 1292 sc->sc_dma->xmit[i].flags = TX_BCNT(blksz) 1293 | TX_EOF | TX_BINT; 1294 sc->sc_dma->xmit[i].ba = dmabuf; 1295 sc->sc_dma->xmit[i].nda = dmabase + dbri_dma_off(xmit, i + 1); 1296 sc->sc_dma->xmit[i].status = 0; 1297 1298 td_last = td; 1299 dmabuf += blksz; 1300 } 1301 1302 sc->sc_dma->xmit[i].flags = TX_BCNT(blksz) | TX_EOF | TX_BINT; 1303 1304 sc->sc_dma->xmit[i].ba = dmabuf; 1305 sc->sc_dma->xmit[i].nda = dmabase + dbri_dma_off(xmit, 0); 1306 sc->sc_dma->xmit[i].status = 0; 1307 1308 dd->callback = callback; 1309 dd->callback_args = callback_args; 1310 1311 x = splsched(); 1312 1313 /* the pipe shouldn't be active */ 1314 if (pipe_active(sc, pipe)) { 1315 aprint_error("pipe active (CDP)\n"); 1316 /* pipe is already active */ 1317 #if 0 1318 td_last = sc->sc_pipe[pipe].desc; 1319 while (sc->sc_desc[td_last].next != -1) 1320 td_last = sc->sc_desc[td_last].next; 1321 1322 sc->sc_desc[td_last].next = td_first; 1323 sc->sc_dma->desc[td_last].nda = 1324 sc->sc_dmabase + dbri_dma_off(desc, td_first); 1325 1326 cmd = dbri_command_lock(sc); 1327 *(cmd++) = DBRI_CMD(DBRI_COMMAND_CDP, 0, pipe); 1328 dbri_command_send(sc, cmd); 1329 #endif 1330 } else { 1331 /* 1332 * pipe isn't active - issue an SDP command to start our 1333 * chain of TDs running 1334 */ 1335 sc->sc_pipe[pipe].desc = which; 1336 cmd = dbri_command_lock(sc); 1337 *(cmd++) = DBRI_CMD(DBRI_COMMAND_SDP, 0, 1338 sc->sc_pipe[pipe].sdp | 1339 DBRI_SDP_VALID_POINTER | 1340 DBRI_SDP_EVERY | 1341 DBRI_SDP_CLEAR); 1342 *(cmd++) = sc->sc_dmabase + dbri_dma_off(xmit, 0); 1343 dbri_command_send(sc, cmd); 1344 DPRINTF("%s: starting DMA\n", __func__); 1345 } 1346 1347 splx(x); 1348 1349 return; 1350 } 1351 1352 static void 1353 setup_ring_recv(struct dbri_softc *sc, int pipe, int which, int num, int blksz, 1354 void (*callback)(void *), void *callback_args) 1355 { 1356 volatile u_int32_t *cmd; 1357 int x, i; 1358 int td_first, td_last; 1359 bus_addr_t dmabuf, dmabase; 1360 struct dbri_desc *dd = &sc->sc_desc[which]; 1361 1362 switch (pipe) { 1363 case 6: 1364 break; 1365 default: 1366 aprint_error("%s: illegal pipe number (%d)\n", 1367 __func__, pipe); 1368 return; 1369 } 1370 1371 td_first = td_last = -1; 1372 1373 if (sc->sc_pipe[pipe].sdp == 0) { 1374 aprint_error_dev(sc->sc_dev, "uninitialized pipe %d\n", 1375 pipe); 1376 return; 1377 } 1378 1379 dmabuf = dd->dmabase; 1380 dmabase = sc->sc_dmabase; 1381 1382 for (i = 0; i < (num - 1); i++) { 1383 1384 sc->sc_dma->recv[i].flags = RX_BSIZE(blksz) | RX_FINAL; 1385 sc->sc_dma->recv[i].ba = dmabuf; 1386 sc->sc_dma->recv[i].nda = dmabase + dbri_dma_off(recv, i + 1); 1387 sc->sc_dma->recv[i].status = RX_EOF; 1388 1389 td_last = i; 1390 dmabuf += blksz; 1391 } 1392 1393 sc->sc_dma->recv[i].flags = RX_BSIZE(blksz) | RX_FINAL; 1394 1395 sc->sc_dma->recv[i].ba = dmabuf; 1396 sc->sc_dma->recv[i].nda = dmabase + dbri_dma_off(recv, 0); 1397 sc->sc_dma->recv[i].status = RX_EOF; 1398 1399 dd->callback = callback; 1400 dd->callback_args = callback_args; 1401 1402 x = splsched(); 1403 1404 /* the pipe shouldn't be active */ 1405 if (pipe_active(sc, pipe)) { 1406 aprint_error("pipe active (CDP)\n"); 1407 /* pipe is already active */ 1408 #if 0 1409 td_last = sc->sc_pipe[pipe].desc; 1410 while (sc->sc_desc[td_last].next != -1) 1411 td_last = sc->sc_desc[td_last].next; 1412 1413 sc->sc_desc[td_last].next = td_first; 1414 sc->sc_dma->desc[td_last].nda = 1415 sc->sc_dmabase + dbri_dma_off(desc, td_first); 1416 1417 cmd = dbri_command_lock(sc); 1418 *(cmd++) = DBRI_CMD(DBRI_COMMAND_CDP, 0, pipe); 1419 dbri_command_send(sc, cmd); 1420 #endif 1421 } else { 1422 /* 1423 * pipe isn't active - issue an SDP command to start our 1424 * chain of TDs running 1425 */ 1426 sc->sc_pipe[pipe].desc = which; 1427 cmd = dbri_command_lock(sc); 1428 *(cmd++) = DBRI_CMD(DBRI_COMMAND_SDP, 0, 1429 sc->sc_pipe[pipe].sdp | 1430 DBRI_SDP_VALID_POINTER | 1431 DBRI_SDP_EVERY | 1432 DBRI_SDP_CLEAR); 1433 *(cmd++) = sc->sc_dmabase + dbri_dma_off(recv, 0); 1434 dbri_command_send(sc, cmd); 1435 DPRINTF("%s: starting DMA\n", __func__); 1436 } 1437 1438 splx(x); 1439 1440 return; 1441 } 1442 1443 static void 1444 pipe_ts_link(struct dbri_softc *sc, int pipe, enum io dir, int basepipe, 1445 int len, int cycle) 1446 { 1447 volatile u_int32_t *cmd; 1448 int prevpipe, nextpipe; 1449 int val; 1450 1451 DPRINTF("%s: %d\n", __func__, pipe); 1452 if (pipe < 0 || pipe >= DBRI_PIPE_MAX || 1453 basepipe < 0 || basepipe >= DBRI_PIPE_MAX) { 1454 aprint_error_dev(sc->sc_dev, "illegal pipe numbers (%d, %d)\n", 1455 pipe, basepipe); 1456 return; 1457 } 1458 1459 if (sc->sc_pipe[pipe].sdp == 0 || sc->sc_pipe[basepipe].sdp == 0) { 1460 aprint_error_dev(sc->sc_dev, "uninitialized pipe (%d, %d)\n", 1461 pipe, basepipe); 1462 return; 1463 } 1464 1465 if (basepipe == 16 && dir == PIPEoutput && cycle == 0) 1466 cycle = sc->sc_chi_bpf; 1467 1468 if (basepipe == pipe) 1469 prevpipe = nextpipe = pipe; 1470 else { 1471 if (basepipe == 16) { 1472 if (dir == PIPEinput) { 1473 prevpipe = sc->sc_chi_pipe_in; 1474 } else { 1475 prevpipe = sc->sc_chi_pipe_out; 1476 } 1477 } else 1478 prevpipe = basepipe; 1479 1480 nextpipe = sc->sc_pipe[prevpipe].next; 1481 1482 while (sc->sc_pipe[nextpipe].cycle < cycle && 1483 sc->sc_pipe[nextpipe].next != basepipe) { 1484 prevpipe = nextpipe; 1485 nextpipe = sc->sc_pipe[nextpipe].next; 1486 } 1487 } 1488 1489 if (prevpipe == 16) { 1490 if (dir == PIPEinput) { 1491 sc->sc_chi_pipe_in = pipe; 1492 } else { 1493 sc->sc_chi_pipe_out = pipe; 1494 } 1495 } else 1496 sc->sc_pipe[prevpipe].next = pipe; 1497 1498 sc->sc_pipe[pipe].next = nextpipe; 1499 sc->sc_pipe[pipe].cycle = cycle; 1500 sc->sc_pipe[pipe].length = len; 1501 1502 cmd = dbri_command_lock(sc); 1503 1504 switch (dir) { 1505 case PIPEinput: 1506 val = DBRI_DTS_VI | DBRI_DTS_INS | DBRI_DTS_PRVIN(prevpipe); 1507 val |= pipe; 1508 *(cmd++) = DBRI_CMD(DBRI_COMMAND_DTS, 0, val); 1509 *(cmd++) = DBRI_TS_LEN(len) | DBRI_TS_CYCLE(cycle) | 1510 DBRI_TS_NEXT(nextpipe); 1511 *(cmd++) = 0; 1512 break; 1513 case PIPEoutput: 1514 val = DBRI_DTS_VO | DBRI_DTS_INS | DBRI_DTS_PRVOUT(prevpipe); 1515 val |= pipe; 1516 *(cmd++) = DBRI_CMD(DBRI_COMMAND_DTS, 0, val); 1517 *(cmd++) = 0; 1518 *(cmd++) = DBRI_TS_LEN(len) | DBRI_TS_CYCLE(cycle) | 1519 DBRI_TS_NEXT(nextpipe); 1520 break; 1521 default: 1522 DPRINTF("%s: should not have happened!\n", 1523 device_xname(sc->sc_dev)); 1524 break; 1525 } 1526 1527 dbri_command_send(sc, cmd); 1528 1529 return; 1530 } 1531 1532 static int 1533 pipe_active(struct dbri_softc *sc, int pipe) 1534 { 1535 1536 return (sc->sc_pipe[pipe].desc != -1); 1537 } 1538 1539 /* 1540 * subroutines required to interface with audio(9) 1541 */ 1542 1543 static int 1544 dbri_query_encoding(void *hdl, struct audio_encoding *ae) 1545 { 1546 1547 switch (ae->index) { 1548 case 0: 1549 strcpy(ae->name, AudioEulinear); 1550 ae->encoding = AUDIO_ENCODING_ULINEAR; 1551 ae->precision = 8; 1552 ae->flags = 0; 1553 break; 1554 case 1: 1555 strcpy(ae->name, AudioEmulaw); 1556 ae->encoding = AUDIO_ENCODING_ULAW; 1557 ae->precision = 8; 1558 ae->flags = 0; 1559 break; 1560 case 2: 1561 strcpy(ae->name, AudioEalaw); 1562 ae->encoding = AUDIO_ENCODING_ALAW; 1563 ae->precision = 8; 1564 ae->flags = 0; 1565 break; 1566 case 3: 1567 strcpy(ae->name, AudioEslinear); 1568 ae->encoding = AUDIO_ENCODING_SLINEAR; 1569 ae->precision = 8; 1570 ae->flags = AUDIO_ENCODINGFLAG_EMULATED; 1571 break; 1572 case 4: 1573 strcpy(ae->name, AudioEslinear_le); 1574 ae->encoding = AUDIO_ENCODING_SLINEAR_LE; 1575 ae->precision = 16; 1576 ae->flags = AUDIO_ENCODINGFLAG_EMULATED; 1577 break; 1578 case 5: 1579 strcpy(ae->name, AudioEulinear_le); 1580 ae->encoding = AUDIO_ENCODING_ULINEAR_LE; 1581 ae->precision = 16; 1582 ae->flags = AUDIO_ENCODINGFLAG_EMULATED; 1583 break; 1584 case 6: 1585 strcpy(ae->name, AudioEslinear_be); 1586 ae->encoding = AUDIO_ENCODING_SLINEAR_BE; 1587 ae->precision = 16; 1588 ae->flags = 0; 1589 break; 1590 case 7: 1591 strcpy(ae->name, AudioEulinear_be); 1592 ae->encoding = AUDIO_ENCODING_ULINEAR_BE; 1593 ae->precision = 16; 1594 ae->flags = AUDIO_ENCODINGFLAG_EMULATED; 1595 break; 1596 case 8: 1597 strcpy(ae->name, AudioEslinear); 1598 ae->encoding = AUDIO_ENCODING_SLINEAR; 1599 ae->precision = 16; 1600 ae->flags = 0; 1601 break; 1602 default: 1603 return (EINVAL); 1604 } 1605 1606 return (0); 1607 } 1608 1609 static int 1610 dbri_set_params(void *hdl, int setmode, int usemode, 1611 struct audio_params *play, struct audio_params *rec, 1612 stream_filter_list_t *pfil, stream_filter_list_t *rfil) 1613 { 1614 struct dbri_softc *sc = hdl; 1615 int rate; 1616 audio_params_t *p = NULL; 1617 stream_filter_list_t *fil; 1618 int mode; 1619 1620 /* 1621 * This device only has one clock, so make the sample rates match. 1622 */ 1623 if (play->sample_rate != rec->sample_rate && 1624 usemode == (AUMODE_PLAY | AUMODE_RECORD)) { 1625 if (setmode == AUMODE_PLAY) { 1626 rec->sample_rate = play->sample_rate; 1627 setmode |= AUMODE_RECORD; 1628 } else if (setmode == AUMODE_RECORD) { 1629 play->sample_rate = rec->sample_rate; 1630 setmode |= AUMODE_PLAY; 1631 } else 1632 return EINVAL; 1633 } 1634 1635 for (mode = AUMODE_RECORD; mode != -1; 1636 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) { 1637 if ((setmode & mode) == 0) 1638 continue; 1639 1640 p = mode == AUMODE_PLAY ? play : rec; 1641 if (p->sample_rate < 4000 || p->sample_rate > 50000) { 1642 DPRINTF("dbri_set_params: invalid rate %d\n", 1643 p->sample_rate); 1644 return EINVAL; 1645 } 1646 1647 fil = mode == AUMODE_PLAY ? pfil : rfil; 1648 DPRINTF("requested enc: %d rate: %d prec: %d chan: %d\n", p->encoding, 1649 p->sample_rate, p->precision, p->channels); 1650 if (auconv_set_converter(dbri_formats, DBRI_NFORMATS, 1651 mode, p, true, fil) < 0) { 1652 aprint_debug("dbri_set_params: auconv_set_converter failed\n"); 1653 return EINVAL; 1654 } 1655 if (fil->req_size > 0) 1656 p = &fil->filters[0].param; 1657 } 1658 1659 if (p == NULL) { 1660 DPRINTF("dbri_set_params: no parameters to set\n"); 1661 return 0; 1662 } 1663 1664 DPRINTF("native enc: %d rate: %d prec: %d chan: %d\n", p->encoding, 1665 p->sample_rate, p->precision, p->channels); 1666 1667 for (rate = 0; CS4215_FREQ[rate].freq; rate++) 1668 if (CS4215_FREQ[rate].freq == p->sample_rate) 1669 break; 1670 1671 if (CS4215_FREQ[rate].freq == 0) 1672 return (EINVAL); 1673 1674 /* set frequency */ 1675 sc->sc_mm.c.bcontrol[1] &= ~0x38; 1676 sc->sc_mm.c.bcontrol[1] |= CS4215_FREQ[rate].csval; 1677 sc->sc_mm.c.bcontrol[2] &= ~0x70; 1678 sc->sc_mm.c.bcontrol[2] |= CS4215_FREQ[rate].xtal; 1679 1680 switch (p->encoding) { 1681 case AUDIO_ENCODING_ULAW: 1682 sc->sc_mm.c.bcontrol[1] &= ~3; 1683 sc->sc_mm.c.bcontrol[1] |= CS4215_DFR_ULAW; 1684 break; 1685 case AUDIO_ENCODING_ALAW: 1686 sc->sc_mm.c.bcontrol[1] &= ~3; 1687 sc->sc_mm.c.bcontrol[1] |= CS4215_DFR_ALAW; 1688 break; 1689 case AUDIO_ENCODING_ULINEAR: 1690 sc->sc_mm.c.bcontrol[1] &= ~3; 1691 if (p->precision == 8) { 1692 sc->sc_mm.c.bcontrol[1] |= CS4215_DFR_LINEAR8; 1693 } else { 1694 sc->sc_mm.c.bcontrol[1] |= CS4215_DFR_LINEAR16; 1695 } 1696 break; 1697 case AUDIO_ENCODING_SLINEAR_BE: 1698 case AUDIO_ENCODING_SLINEAR: 1699 sc->sc_mm.c.bcontrol[1] &= ~3; 1700 sc->sc_mm.c.bcontrol[1] |= CS4215_DFR_LINEAR16; 1701 break; 1702 } 1703 1704 switch (p->channels) { 1705 case 1: 1706 sc->sc_mm.c.bcontrol[1] &= ~CS4215_DFR_STEREO; 1707 break; 1708 case 2: 1709 sc->sc_mm.c.bcontrol[1] |= CS4215_DFR_STEREO; 1710 break; 1711 } 1712 1713 return (0); 1714 } 1715 1716 static int 1717 dbri_round_blocksize(void *hdl, int bs, int mode, 1718 const audio_params_t *param) 1719 { 1720 1721 /* DBRI DMA segment size, rounded down to 32bit alignment */ 1722 return 0x1ffc; 1723 } 1724 1725 static int 1726 dbri_halt_output(void *hdl) 1727 { 1728 struct dbri_softc *sc = hdl; 1729 1730 if (!sc->sc_playing) 1731 return 0; 1732 1733 sc->sc_playing = 0; 1734 pipe_reset(sc, 4); 1735 return (0); 1736 } 1737 1738 static int 1739 dbri_getdev(void *hdl, struct audio_device *ret) 1740 { 1741 1742 *ret = dbri_device; 1743 return (0); 1744 } 1745 1746 static int 1747 dbri_set_port(void *hdl, mixer_ctrl_t *mc) 1748 { 1749 struct dbri_softc *sc = hdl; 1750 int latt = sc->sc_latt, ratt = sc->sc_ratt; 1751 1752 switch (mc->dev) { 1753 case DBRI_VOL_OUTPUT: /* master volume */ 1754 latt = (latt & 0xc0) | (63 - 1755 min(mc->un.value.level[AUDIO_MIXER_LEVEL_LEFT] >> 2, 63)); 1756 ratt = (ratt & 0xc0) | (63 - 1757 min(mc->un.value.level[AUDIO_MIXER_LEVEL_RIGHT] >> 2, 63)); 1758 break; 1759 case DBRI_ENABLE_MONO: /* built-in speaker */ 1760 if (mc->un.ord == 1) { 1761 ratt |= CS4215_SE; 1762 } else 1763 ratt &= ~CS4215_SE; 1764 break; 1765 case DBRI_ENABLE_HEADPHONE: /* headphones output */ 1766 if (mc->un.ord == 1) { 1767 latt |= CS4215_HE; 1768 } else 1769 latt &= ~CS4215_HE; 1770 break; 1771 case DBRI_ENABLE_LINE: /* line out */ 1772 if (mc->un.ord == 1) { 1773 latt |= CS4215_LE; 1774 } else 1775 latt &= ~CS4215_LE; 1776 break; 1777 case DBRI_VOL_MONITOR: 1778 if (mc->un.value.level[AUDIO_MIXER_LEVEL_LEFT] == 1779 sc->sc_monitor) 1780 return 0; 1781 sc->sc_monitor = mc->un.value.level[AUDIO_MIXER_LEVEL_LEFT]; 1782 break; 1783 case DBRI_INPUT_GAIN: 1784 sc->sc_linp = mc->un.value.level[AUDIO_MIXER_LEVEL_LEFT]; 1785 sc->sc_rinp = mc->un.value.level[AUDIO_MIXER_LEVEL_RIGHT]; 1786 break; 1787 case DBRI_INPUT_SELECT: 1788 if (mc->un.mask == sc->sc_input) 1789 return 0; 1790 sc->sc_input = mc->un.mask; 1791 break; 1792 } 1793 1794 sc->sc_latt = latt; 1795 sc->sc_ratt = ratt; 1796 1797 mmcodec_setgain(sc, 0); 1798 1799 return (0); 1800 } 1801 1802 static int 1803 dbri_get_port(void *hdl, mixer_ctrl_t *mc) 1804 { 1805 struct dbri_softc *sc = hdl; 1806 1807 switch (mc->dev) { 1808 case DBRI_VOL_OUTPUT: /* master volume */ 1809 mc->un.value.level[AUDIO_MIXER_LEVEL_LEFT] = 1810 (63 - (sc->sc_latt & 0x3f)) << 2; 1811 mc->un.value.level[AUDIO_MIXER_LEVEL_RIGHT] = 1812 (63 - (sc->sc_ratt & 0x3f)) << 2; 1813 return (0); 1814 case DBRI_ENABLE_MONO: /* built-in speaker */ 1815 mc->un.ord = (sc->sc_ratt & CS4215_SE) ? 1 : 0; 1816 return 0; 1817 case DBRI_ENABLE_HEADPHONE: /* headphones output */ 1818 mc->un.ord = (sc->sc_latt & CS4215_HE) ? 1 : 0; 1819 return 0; 1820 case DBRI_ENABLE_LINE: /* line out */ 1821 mc->un.ord = (sc->sc_latt & CS4215_LE) ? 1 : 0; 1822 return 0; 1823 case DBRI_VOL_MONITOR: 1824 mc->un.value.level[AUDIO_MIXER_LEVEL_LEFT] = sc->sc_monitor; 1825 return 0; 1826 case DBRI_INPUT_GAIN: 1827 mc->un.value.level[AUDIO_MIXER_LEVEL_LEFT] = sc->sc_linp; 1828 mc->un.value.level[AUDIO_MIXER_LEVEL_RIGHT] = sc->sc_rinp; 1829 return 0; 1830 case DBRI_INPUT_SELECT: 1831 mc->un.mask = sc->sc_input; 1832 return 0; 1833 } 1834 return (EINVAL); 1835 } 1836 1837 static int 1838 dbri_query_devinfo(void *hdl, mixer_devinfo_t *di) 1839 { 1840 1841 switch (di->index) { 1842 case DBRI_MONITOR_CLASS: 1843 di->mixer_class = DBRI_MONITOR_CLASS; 1844 strcpy(di->label.name, AudioCmonitor); 1845 di->type = AUDIO_MIXER_CLASS; 1846 di->next = di->prev = AUDIO_MIXER_LAST; 1847 return 0; 1848 case DBRI_OUTPUT_CLASS: 1849 di->mixer_class = DBRI_OUTPUT_CLASS; 1850 strcpy(di->label.name, AudioCoutputs); 1851 di->type = AUDIO_MIXER_CLASS; 1852 di->next = di->prev = AUDIO_MIXER_LAST; 1853 return 0; 1854 case DBRI_INPUT_CLASS: 1855 di->mixer_class = DBRI_INPUT_CLASS; 1856 strcpy(di->label.name, AudioCinputs); 1857 di->type = AUDIO_MIXER_CLASS; 1858 di->next = di->prev = AUDIO_MIXER_LAST; 1859 return 0; 1860 case DBRI_VOL_OUTPUT: /* master volume */ 1861 di->mixer_class = DBRI_OUTPUT_CLASS; 1862 di->next = di->prev = AUDIO_MIXER_LAST; 1863 strcpy(di->label.name, AudioNmaster); 1864 di->type = AUDIO_MIXER_VALUE; 1865 di->un.v.num_channels = 2; 1866 strcpy(di->un.v.units.name, AudioNvolume); 1867 return (0); 1868 case DBRI_INPUT_GAIN: /* input gain */ 1869 di->mixer_class = DBRI_INPUT_CLASS; 1870 di->next = di->prev = AUDIO_MIXER_LAST; 1871 strcpy(di->label.name, AudioNrecord); 1872 di->type = AUDIO_MIXER_VALUE; 1873 di->un.v.num_channels = 2; 1874 strcpy(di->un.v.units.name, AudioNvolume); 1875 return (0); 1876 case DBRI_VOL_MONITOR: /* monitor volume */ 1877 di->mixer_class = DBRI_MONITOR_CLASS; 1878 di->next = di->prev = AUDIO_MIXER_LAST; 1879 strcpy(di->label.name, AudioNmonitor); 1880 di->type = AUDIO_MIXER_VALUE; 1881 di->un.v.num_channels = 1; 1882 strcpy(di->un.v.units.name, AudioNvolume); 1883 return (0); 1884 case DBRI_ENABLE_MONO: /* built-in speaker */ 1885 di->mixer_class = DBRI_OUTPUT_CLASS; 1886 di->next = di->prev = AUDIO_MIXER_LAST; 1887 strcpy(di->label.name, AudioNmono); 1888 di->type = AUDIO_MIXER_ENUM; 1889 di->un.e.num_mem = 2; 1890 strcpy(di->un.e.member[0].label.name, AudioNoff); 1891 di->un.e.member[0].ord = 0; 1892 strcpy(di->un.e.member[1].label.name, AudioNon); 1893 di->un.e.member[1].ord = 1; 1894 return (0); 1895 case DBRI_ENABLE_HEADPHONE: /* headphones output */ 1896 di->mixer_class = DBRI_OUTPUT_CLASS; 1897 di->next = di->prev = AUDIO_MIXER_LAST; 1898 strcpy(di->label.name, AudioNheadphone); 1899 di->type = AUDIO_MIXER_ENUM; 1900 di->un.e.num_mem = 2; 1901 strcpy(di->un.e.member[0].label.name, AudioNoff); 1902 di->un.e.member[0].ord = 0; 1903 strcpy(di->un.e.member[1].label.name, AudioNon); 1904 di->un.e.member[1].ord = 1; 1905 return (0); 1906 case DBRI_ENABLE_LINE: /* line out */ 1907 di->mixer_class = DBRI_OUTPUT_CLASS; 1908 di->next = di->prev = AUDIO_MIXER_LAST; 1909 strcpy(di->label.name, AudioNline); 1910 di->type = AUDIO_MIXER_ENUM; 1911 di->un.e.num_mem = 2; 1912 strcpy(di->un.e.member[0].label.name, AudioNoff); 1913 di->un.e.member[0].ord = 0; 1914 strcpy(di->un.e.member[1].label.name, AudioNon); 1915 di->un.e.member[1].ord = 1; 1916 return (0); 1917 case DBRI_INPUT_SELECT: 1918 di->mixer_class = DBRI_INPUT_CLASS; 1919 strcpy(di->label.name, AudioNsource); 1920 di->type = AUDIO_MIXER_SET; 1921 di->prev = di->next = AUDIO_MIXER_LAST; 1922 di->un.s.num_mem = 2; 1923 strcpy(di->un.s.member[0].label.name, AudioNline); 1924 di->un.s.member[0].mask = 1 << 0; 1925 strcpy(di->un.s.member[1].label.name, AudioNmicrophone); 1926 di->un.s.member[1].mask = 1 << 1; 1927 return 0; 1928 } 1929 1930 return (ENXIO); 1931 } 1932 1933 static size_t 1934 dbri_round_buffersize(void *hdl, int dir, size_t bufsize) 1935 { 1936 #ifdef DBRI_BIG_BUFFER 1937 return 16*0x1ffc; /* use ~128KB buffer */ 1938 #else 1939 return bufsize; 1940 #endif 1941 } 1942 1943 static int 1944 dbri_get_props(void *hdl) 1945 { 1946 1947 return AUDIO_PROP_MMAP | AUDIO_PROP_FULLDUPLEX; 1948 } 1949 1950 static int 1951 dbri_trigger_output(void *hdl, void *start, void *end, int blksize, 1952 void (*intr)(void *), void *intrarg, 1953 const struct audio_params *param) 1954 { 1955 struct dbri_softc *sc = hdl; 1956 unsigned long count, num; 1957 1958 if (sc->sc_playing) 1959 return 0; 1960 1961 count = (unsigned long)(((char *)end - (char *)start)); 1962 num = count / blksize; 1963 1964 DPRINTF("trigger_output(%lx %lx) : %d %ld %ld\n", 1965 (unsigned long)intr, 1966 (unsigned long)intrarg, blksize, count, num); 1967 1968 sc->sc_params = *param; 1969 1970 if (sc->sc_recording == 0) { 1971 /* do not muck with the codec when it's already in use */ 1972 if (mmcodec_setcontrol(sc) != 0) 1973 return -1; 1974 mmcodec_init_data(sc); 1975 } 1976 1977 /* 1978 * always use DMA descriptor 0 for output 1979 * no need to allocate them dynamically since we only ever have 1980 * exactly one input stream and exactly one output stream 1981 */ 1982 setup_ring_xmit(sc, 4, 0, num, blksize, intr, intrarg); 1983 sc->sc_playing = 1; 1984 return 0; 1985 } 1986 1987 static int 1988 dbri_halt_input(void *cookie) 1989 { 1990 struct dbri_softc *sc = cookie; 1991 1992 if (!sc->sc_recording) 1993 return 0; 1994 1995 sc->sc_recording = 0; 1996 pipe_reset(sc, 6); 1997 return 0; 1998 } 1999 2000 static int 2001 dbri_trigger_input(void *hdl, void *start, void *end, int blksize, 2002 void (*intr)(void *), void *intrarg, 2003 const struct audio_params *param) 2004 { 2005 struct dbri_softc *sc = hdl; 2006 unsigned long count, num; 2007 2008 if (sc->sc_recording) 2009 return 0; 2010 2011 count = (unsigned long)(((char *)end - (char *)start)); 2012 num = count / blksize; 2013 2014 DPRINTF("trigger_input(%lx %lx) : %d %ld %ld\n", 2015 (unsigned long)intr, 2016 (unsigned long)intrarg, blksize, count, num); 2017 2018 sc->sc_params = *param; 2019 2020 if (sc->sc_playing == 0) { 2021 2022 /* 2023 * we don't support different parameters for playing and 2024 * recording anyway so don't bother whacking the codec if 2025 * it's already set up 2026 */ 2027 mmcodec_setcontrol(sc); 2028 mmcodec_init_data(sc); 2029 } 2030 2031 sc->sc_recording = 1; 2032 setup_ring_recv(sc, 6, 1, num, blksize, intr, intrarg); 2033 return 0; 2034 } 2035 2036 2037 static u_int32_t 2038 reverse_bytes(u_int32_t b, int len) 2039 { 2040 switch (len) { 2041 case 32: 2042 b = ((b & 0xffff0000) >> 16) | ((b & 0x0000ffff) << 16); 2043 case 16: 2044 b = ((b & 0xff00ff00) >> 8) | ((b & 0x00ff00ff) << 8); 2045 case 8: 2046 b = ((b & 0xf0f0f0f0) >> 4) | ((b & 0x0f0f0f0f) << 4); 2047 case 4: 2048 b = ((b & 0xcccccccc) >> 2) | ((b & 0x33333333) << 2); 2049 case 2: 2050 b = ((b & 0xaaaaaaaa) >> 1) | ((b & 0x55555555) << 1); 2051 case 1: 2052 case 0: 2053 break; 2054 default: 2055 DPRINTF("reverse_bytes: unsupported length\n"); 2056 }; 2057 2058 return (b); 2059 } 2060 2061 static void * 2062 dbri_malloc(void *v, int dir, size_t s, struct malloc_type *mt, int flags) 2063 { 2064 struct dbri_softc *sc = v; 2065 struct dbri_desc *dd = &sc->sc_desc[sc->sc_desc_used]; 2066 int rseg; 2067 2068 if (bus_dmamap_create(sc->sc_dmat, s, 1, s, 0, BUS_DMA_NOWAIT, 2069 &dd->dmamap) == 0) { 2070 if (bus_dmamem_alloc(sc->sc_dmat, s, 0, 0, &dd->dmaseg, 2071 1, &rseg, BUS_DMA_NOWAIT) == 0) { 2072 if (bus_dmamem_map(sc->sc_dmat, &dd->dmaseg, rseg, s, 2073 &dd->buf, BUS_DMA_NOWAIT|BUS_DMA_COHERENT) == 0) { 2074 if (dd->buf != NULL) { 2075 if (bus_dmamap_load(sc->sc_dmat, 2076 dd->dmamap, dd->buf, s, NULL, 2077 BUS_DMA_NOWAIT) == 0) { 2078 dd->len = s; 2079 dd->busy = 0; 2080 dd->callback = NULL; 2081 dd->dmabase = 2082 dd->dmamap->dm_segs[0].ds_addr; 2083 DPRINTF("dbri_malloc: using buffer %d %08x\n", 2084 sc->sc_desc_used, (uint32_t)dd->buf); 2085 sc->sc_desc_used++; 2086 return dd->buf; 2087 } else 2088 aprint_error("dbri_malloc: load failed\n"); 2089 } else 2090 aprint_error("dbri_malloc: map returned NULL\n"); 2091 } else 2092 aprint_error("dbri_malloc: map failed\n"); 2093 bus_dmamem_free(sc->sc_dmat, &dd->dmaseg, rseg); 2094 } else 2095 aprint_error("dbri_malloc: malloc() failed\n"); 2096 bus_dmamap_destroy(sc->sc_dmat, dd->dmamap); 2097 } else 2098 aprint_error("dbri_malloc: bus_dmamap_create() failed\n"); 2099 return NULL; 2100 } 2101 2102 static void 2103 dbri_free(void *v, void *p, struct malloc_type *mt) 2104 { 2105 struct dbri_softc *sc = v; 2106 struct dbri_desc *dd; 2107 int i; 2108 2109 for (i = 0; i < sc->sc_desc_used; i++) { 2110 dd = &sc->sc_desc[i]; 2111 if (dd->buf == p) 2112 break; 2113 } 2114 if (i >= sc->sc_desc_used) 2115 return; 2116 bus_dmamap_unload(sc->sc_dmat, dd->dmamap); 2117 bus_dmamap_destroy(sc->sc_dmat, dd->dmamap); 2118 } 2119 2120 static paddr_t 2121 dbri_mappage(void *v, void *mem, off_t off, int prot) 2122 { 2123 struct dbri_softc *sc = v; 2124 int current; 2125 2126 if (off < 0) 2127 return -1; 2128 2129 current = 0; 2130 while ((current < sc->sc_desc_used) && 2131 (sc->sc_desc[current].buf != mem)) 2132 current++; 2133 2134 if (current < sc->sc_desc_used) { 2135 return bus_dmamem_mmap(sc->sc_dmat, 2136 &sc->sc_desc[current].dmaseg, 1, off, prot, BUS_DMA_WAITOK); 2137 } 2138 2139 return -1; 2140 } 2141 2142 static int 2143 dbri_open(void *cookie, int flags) 2144 { 2145 struct dbri_softc *sc = cookie; 2146 2147 DPRINTF("%s: %d\n", __func__, sc->sc_refcount); 2148 2149 if (sc->sc_refcount == 0) 2150 dbri_bring_up(sc); 2151 2152 sc->sc_refcount++; 2153 2154 return 0; 2155 } 2156 2157 static void 2158 dbri_close(void *cookie) 2159 { 2160 struct dbri_softc *sc = cookie; 2161 2162 DPRINTF("%s: %d\n", __func__, sc->sc_refcount); 2163 2164 sc->sc_refcount--; 2165 KASSERT(sc->sc_refcount >= 0); 2166 if (sc->sc_refcount > 0) 2167 return; 2168 2169 dbri_set_power(sc, 0); 2170 sc->sc_playing = 0; 2171 sc->sc_recording = 0; 2172 } 2173 2174 static void 2175 dbri_powerhook(int why, void *cookie) 2176 { 2177 struct dbri_softc *sc = cookie; 2178 2179 if (why == sc->sc_pmgrstate) 2180 return; 2181 2182 switch(why) 2183 { 2184 case PWR_SUSPEND: 2185 dbri_set_power(sc, 0); 2186 break; 2187 case PWR_RESUME: 2188 if (sc->sc_powerstate != 0) 2189 break; 2190 aprint_verbose("resume: %d\n", sc->sc_refcount); 2191 sc->sc_pmgrstate = PWR_RESUME; 2192 if (sc->sc_playing) { 2193 volatile u_int32_t *cmd; 2194 int s; 2195 2196 dbri_bring_up(sc); 2197 s = splsched(); 2198 cmd = dbri_command_lock(sc); 2199 *(cmd++) = DBRI_CMD(DBRI_COMMAND_SDP, 2200 0, sc->sc_pipe[4].sdp | 2201 DBRI_SDP_VALID_POINTER | 2202 DBRI_SDP_EVERY | DBRI_SDP_CLEAR); 2203 *(cmd++) = sc->sc_dmabase + 2204 dbri_dma_off(xmit, 0); 2205 dbri_command_send(sc, cmd); 2206 splx(s); 2207 } 2208 break; 2209 default: 2210 return; 2211 } 2212 sc->sc_pmgrstate = why; 2213 } 2214 2215 #endif /* NAUDIO > 0 */ 2216
Indexes created Thu Sep 25 16:09:42 GMT 2025