dbri.c revision 1.37
1 /* $NetBSD: dbri.c,v 1.37 2017/12/21 21:56:29 macallan Exp $ */ 2 3 /* 4 * Copyright (C) 1997 Rudolf Koenig (rfkoenig (at) immd4.informatik.uni-erlangen.de) 5 * Copyright (c) 1998, 1999 Brent Baccala (baccala (at) freesoft.org) 6 * Copyright (c) 2001, 2002 Jared D. McNeill <jmcneill (at) netbsd.org> 7 * Copyright (c) 2005 Michael Lorenz <macallan (at) netbsd.org> 8 * All rights reserved. 9 * 10 * This driver is losely based on a Linux driver written by Rudolf Koenig and 11 * Brent Baccala who kindly gave their permission to use their code in a 12 * BSD-licensed driver. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions 16 * are met: 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in the 21 * documentation and/or other materials provided with the distribution. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 28 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 29 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: dbri.c,v 1.37 2017/12/21 21:56:29 macallan Exp $"); 38 39 #include "audio.h" 40 #if NAUDIO > 0 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/errno.h> 45 #include <sys/device.h> 46 #include <sys/proc.h> 47 #include <sys/kernel.h> 48 #include <sys/bus.h> 49 #include <sys/intr.h> 50 #include <sys/kmem.h> 51 52 #include <dev/sbus/sbusvar.h> 53 #include <sparc/sparc/auxreg.h> 54 #include <machine/autoconf.h> 55 56 #include <sys/audioio.h> 57 #include <dev/audio_if.h> 58 #include <dev/auconv.h> 59 60 #include <dev/ic/cs4215reg.h> 61 #include <dev/ic/cs4215var.h> 62 #include <dev/sbus/dbrireg.h> 63 #include <dev/sbus/dbrivar.h> 64 65 #include "opt_sbus_dbri.h" 66 67 #define DBRI_ROM_NAME_PREFIX "SUNW,DBRI" 68 69 #ifdef DBRI_DEBUG 70 # define DPRINTF aprint_normal 71 #else 72 # define DPRINTF while (0) printf 73 #endif 74 75 static const char *dbri_supported[] = { 76 "e", 77 "s3", 78 "" 79 }; 80 81 enum ms { 82 CHImaster, 83 CHIslave 84 }; 85 86 enum io { 87 PIPEinput, 88 PIPEoutput 89 }; 90 91 /* 92 * Function prototypes 93 */ 94 95 /* softc stuff */ 96 static void dbri_attach_sbus(device_t, device_t, void *); 97 static int dbri_match_sbus(device_t, cfdata_t, void *); 98 99 static int dbri_config_interrupts(device_t); 100 101 /* interrupt handler */ 102 static int dbri_intr(void *); 103 static void dbri_softint(void *); 104 105 /* supporting subroutines */ 106 static int dbri_init(struct dbri_softc *); 107 static int dbri_reset(struct dbri_softc *); 108 static volatile uint32_t *dbri_command_lock(struct dbri_softc *); 109 static void dbri_command_send(struct dbri_softc *, volatile uint32_t *); 110 static void dbri_process_interrupt_buffer(struct dbri_softc *); 111 static void dbri_process_interrupt(struct dbri_softc *, int32_t); 112 113 /* mmcodec subroutines */ 114 static int mmcodec_init(struct dbri_softc *); 115 static void mmcodec_init_data(struct dbri_softc *); 116 static void mmcodec_pipe_init(struct dbri_softc *); 117 static void mmcodec_default(struct dbri_softc *); 118 static void mmcodec_setgain(struct dbri_softc *, int); 119 static int mmcodec_setcontrol(struct dbri_softc *); 120 121 /* chi subroutines */ 122 static void chi_reset(struct dbri_softc *, enum ms, int); 123 124 /* pipe subroutines */ 125 static void pipe_setup(struct dbri_softc *, int, int); 126 static void pipe_reset(struct dbri_softc *, int); 127 static void pipe_receive_fixed(struct dbri_softc *, int, 128 volatile uint32_t *); 129 static void pipe_transmit_fixed(struct dbri_softc *, int, uint32_t); 130 131 static void pipe_ts_link(struct dbri_softc *, int, enum io, int, int, int); 132 static int pipe_active(struct dbri_softc *, int); 133 134 /* audio(9) stuff */ 135 static int dbri_query_encoding(void *, struct audio_encoding *); 136 static int dbri_set_params(void *, int, int, struct audio_params *, 137 struct audio_params *,stream_filter_list_t *, stream_filter_list_t *); 138 static int dbri_round_blocksize(void *, int, int, const audio_params_t *); 139 static int dbri_halt_output(void *); 140 static int dbri_halt_input(void *); 141 static int dbri_getdev(void *, struct audio_device *); 142 static int dbri_set_port(void *, mixer_ctrl_t *); 143 static int dbri_get_port(void *, mixer_ctrl_t *); 144 static int dbri_query_devinfo(void *, mixer_devinfo_t *); 145 static size_t dbri_round_buffersize(void *, int, size_t); 146 static int dbri_get_props(void *); 147 static int dbri_open(void *, int); 148 static void dbri_close(void *); 149 150 static void setup_ring_xmit(struct dbri_softc *, int, int, int, int, 151 void (*)(void *), void *); 152 static void setup_ring_recv(struct dbri_softc *, int, int, int, int, 153 void (*)(void *), void *); 154 155 static int dbri_trigger_output(void *, void *, void *, int, 156 void (*)(void *), void *, const struct audio_params *); 157 static int dbri_trigger_input(void *, void *, void *, int, 158 void (*)(void *), void *, const struct audio_params *); 159 static void dbri_get_locks(void *, kmutex_t **, kmutex_t **); 160 161 static void *dbri_malloc(void *, int, size_t); 162 static void dbri_free(void *, void *, size_t); 163 static paddr_t dbri_mappage(void *, void *, off_t, int); 164 static void dbri_set_power(struct dbri_softc *, int); 165 static void dbri_bring_up(struct dbri_softc *); 166 static bool dbri_suspend(device_t, const pmf_qual_t *); 167 static bool dbri_resume(device_t, const pmf_qual_t *); 168 static int dbri_commit(void *); 169 170 /* stupid support routines */ 171 static uint32_t reverse_bytes(uint32_t, int); 172 173 struct audio_device dbri_device = { 174 "CS4215", 175 "", 176 "dbri" 177 }; 178 179 struct audio_hw_if dbri_hw_if = { 180 .open = dbri_open, 181 .close = dbri_close, 182 .query_encoding = dbri_query_encoding, 183 .set_params = dbri_set_params, 184 .round_blocksize = dbri_round_blocksize, 185 .halt_output = dbri_halt_output, 186 .halt_input = dbri_halt_input, 187 .getdev = dbri_getdev, 188 .set_port = dbri_set_port, 189 .get_port = dbri_get_port, 190 .query_devinfo = dbri_query_devinfo, 191 .allocm = dbri_malloc, 192 .freem = dbri_free, 193 .round_buffersize = dbri_round_buffersize, 194 .mappage = dbri_mappage, 195 .get_props = dbri_get_props, 196 .trigger_output = dbri_trigger_output, 197 .trigger_input = dbri_trigger_input, 198 .get_locks = dbri_get_locks, 199 .commit_settings = dbri_commit, 200 }; 201 202 CFATTACH_DECL_NEW(dbri, sizeof(struct dbri_softc), 203 dbri_match_sbus, dbri_attach_sbus, NULL, NULL); 204 205 #define DBRI_NFORMATS 4 206 static const struct audio_format dbri_formats[DBRI_NFORMATS] = { 207 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_SLINEAR_BE, 16, 16, 208 2, AUFMT_STEREO, 8, {8000, 9600, 11025, 16000, 22050, 32000, 44100, 209 48000}}, 210 /* {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_ULAW, 8, 8, 211 2, AUFMT_STEREO, 8, {8000, 9600, 11025, 16000, 22050, 32000, 44100, 212 48000}}, 213 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_ALAW, 8, 8, 214 2, AUFMT_STEREO, 8, {8000, 9600, 11025, 16000, 22050, 32000, 44100, 215 48000}}, 216 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_ULINEAR, 8, 8, 217 2, AUFMT_STEREO, 8, {8000, 9600, 11025, 16000, 22050, 32000, 44100, 218 48000}},*/ 219 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_ULAW, 8, 8, 220 1, AUFMT_MONAURAL, 8, {8000, 9600, 11025, 16000, 22050, 32000, 44100, 221 48000}}, 222 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_ALAW, 8, 8, 223 1, AUFMT_MONAURAL, 8, {8000, 9600, 11025, 16000, 22050, 32000, 44100, 224 48000}}, 225 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_ULINEAR, 8, 8, 226 1, AUFMT_MONAURAL, 8, {8000, 9600, 11025, 16000, 22050, 32000, 44100, 227 48000}}, 228 }; 229 230 enum { 231 DBRI_OUTPUT_CLASS, 232 DBRI_VOL_OUTPUT, 233 DBRI_ENABLE_MONO, 234 DBRI_ENABLE_HEADPHONE, 235 DBRI_ENABLE_LINE, 236 DBRI_MONITOR_CLASS, 237 DBRI_VOL_MONITOR, 238 DBRI_INPUT_CLASS, 239 DBRI_INPUT_GAIN, 240 DBRI_INPUT_SELECT, 241 DBRI_RECORD_CLASS, 242 DBRI_ENUM_LAST 243 }; 244 245 /* 246 * Autoconfig routines 247 */ 248 static int 249 dbri_match_sbus(device_t parent, cfdata_t match, void *aux) 250 { 251 struct sbus_attach_args *sa = aux; 252 char *ver; 253 int i; 254 255 if (strncmp(DBRI_ROM_NAME_PREFIX, sa->sa_name, 9)) 256 return (0); 257 258 ver = &sa->sa_name[9]; 259 260 for (i = 0; dbri_supported[i][0] != '\0'; i++) 261 if (strcmp(dbri_supported[i], ver) == 0) 262 return (1); 263 264 return (0); 265 } 266 267 static void 268 dbri_attach_sbus(device_t parent, device_t self, void *aux) 269 { 270 struct dbri_softc *sc = device_private(self); 271 struct sbus_attach_args *sa = aux; 272 bus_space_handle_t ioh; 273 bus_size_t size; 274 int error, rseg, pwr, i; 275 char *ver = &sa->sa_name[9]; 276 277 sc->sc_dev = self; 278 sc->sc_iot = sa->sa_bustag; 279 sc->sc_dmat = sa->sa_dmatag; 280 sc->sc_powerstate = 1; 281 282 sc->sc_whack_codec = 0; 283 284 pwr = prom_getpropint(sa->sa_node,"pwr-on-auxio",0); 285 aprint_normal(": rev %s\n", ver); 286 287 if (pwr) { 288 /* 289 * we can control DBRI power via auxio and we're initially 290 * powered down 291 */ 292 293 sc->sc_have_powerctl = 1; 294 sc->sc_powerstate = 0; 295 dbri_set_power(sc, 1); 296 if (!pmf_device_register(self, dbri_suspend, dbri_resume)) { 297 aprint_error_dev(self, 298 "cannot set power mgmt handler\n"); 299 } 300 } else { 301 /* we can't control power so we're always up */ 302 sc->sc_have_powerctl = 0; 303 sc->sc_powerstate = 1; 304 } 305 306 for (i = 0; i < DBRI_NUM_DESCRIPTORS; i++) { 307 sc->sc_desc[i].softint = softint_establish(SOFTINT_SERIAL, 308 dbri_softint, &sc->sc_desc[i]); 309 } 310 311 if (sa->sa_npromvaddrs) 312 ioh = (bus_space_handle_t)sa->sa_promvaddrs[0]; 313 else { 314 if (sbus_bus_map(sa->sa_bustag, sa->sa_slot, 315 sa->sa_offset, sa->sa_size, 316 BUS_SPACE_MAP_LINEAR, /*0,*/ &ioh) != 0) { 317 aprint_error("%s @ sbus: cannot map registers\n", 318 device_xname(self)); 319 return; 320 } 321 } 322 323 sc->sc_ioh = ioh; 324 325 size = sizeof(struct dbri_dma); 326 327 /* get a DMA handle */ 328 if ((error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, 329 BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) { 330 aprint_error_dev(self, "DMA map create error %d\n", 331 error); 332 return; 333 } 334 335 /* allocate DMA buffer */ 336 if ((error = bus_dmamem_alloc(sc->sc_dmat, size, 0, 0, &sc->sc_dmaseg, 337 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 338 aprint_error_dev(self, "DMA buffer alloc error %d\n", 339 error); 340 return; 341 } 342 343 /* map DMA buffer into CPU addressable space */ 344 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_dmaseg, rseg, size, 345 &sc->sc_membase, 346 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 347 aprint_error_dev(self, "DMA buffer map error %d\n", 348 error); 349 return; 350 } 351 352 /* load the buffer */ 353 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, 354 sc->sc_membase, size, NULL, 355 BUS_DMA_NOWAIT)) != 0) { 356 aprint_error_dev(self, "DMA buffer map load error %d\n", 357 error); 358 bus_dmamem_unmap(sc->sc_dmat, sc->sc_membase, size); 359 bus_dmamem_free(sc->sc_dmat, &sc->sc_dmaseg, rseg); 360 return; 361 } 362 363 /* map the registers into memory */ 364 365 /* kernel virtual address of DMA buffer */ 366 sc->sc_dma = (struct dbri_dma *)sc->sc_membase; 367 /* physical address of DMA buffer */ 368 sc->sc_dmabase = sc->sc_dmamap->dm_segs[0].ds_addr; 369 sc->sc_bufsiz = size; 370 371 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_NONE); 372 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_AUDIO); 373 374 #ifndef DBRI_SPIN 375 cv_init(&sc->sc_cv, "dbricv"); 376 #endif 377 378 bus_intr_establish(sa->sa_bustag, sa->sa_pri, IPL_AUDIO, dbri_intr, 379 sc); 380 381 sc->sc_locked = 0; 382 sc->sc_desc_used = 0; 383 sc->sc_refcount = 0; 384 sc->sc_playing = 0; 385 sc->sc_recording = 0; 386 sc->sc_init_done = 0; 387 config_finalize_register(self, &dbri_config_interrupts); 388 389 return; 390 } 391 392 /* 393 * lowlevel routine to switch power for the DBRI chip 394 */ 395 static void 396 dbri_set_power(struct dbri_softc *sc, int state) 397 { 398 int s; 399 400 if (sc->sc_have_powerctl == 0) 401 return; 402 if (sc->sc_powerstate == state) 403 return; 404 405 if (state) { 406 DPRINTF("%s: waiting to power up... ", 407 device_xname(sc->sc_dev)); 408 s = splhigh(); 409 *AUXIO4M_REG |= (AUXIO4M_MMX); 410 splx(s); 411 delay(10000); 412 DPRINTF("done (%02x)\n", *AUXIO4M_REG); 413 } else { 414 DPRINTF("%s: powering down\n", device_xname(sc->sc_dev)); 415 s = splhigh(); 416 *AUXIO4M_REG &= ~AUXIO4M_MMX; 417 splx(s); 418 DPRINTF("done (%02x})\n", *AUXIO4M_REG); 419 } 420 sc->sc_powerstate = state; 421 } 422 423 /* 424 * power up and re-initialize the chip 425 */ 426 static void 427 dbri_bring_up(struct dbri_softc *sc) 428 { 429 430 if (sc->sc_have_powerctl == 0) 431 return; 432 433 if (sc->sc_powerstate == 1) 434 return; 435 436 /* ok, we really need to do something */ 437 dbri_set_power(sc, 1); 438 439 /* 440 * re-initialize the chip but skip all the probing, don't overwrite 441 * any other settings either 442 */ 443 dbri_init(sc); 444 mmcodec_setgain(sc, 1); 445 mmcodec_pipe_init(sc); 446 mmcodec_init_data(sc); 447 mmcodec_setgain(sc, 0); 448 } 449 450 static int 451 dbri_config_interrupts(device_t dev) 452 { 453 struct dbri_softc *sc = device_private(dev); 454 455 mutex_spin_enter(&sc->sc_intr_lock); 456 if (sc->sc_init_done != 0) { 457 mutex_spin_exit(&sc->sc_intr_lock); 458 return 0; 459 } 460 sc->sc_init_done = 1; 461 462 dbri_init(sc); 463 464 mutex_spin_exit(&sc->sc_intr_lock); 465 466 467 /* talking to the codec needs working interrupts */ 468 if (mmcodec_init(sc) == -1) { 469 printf("%s: no codec detected, aborting\n", 470 device_xname(dev)); 471 return 0; 472 } 473 474 /* Attach ourselves to the high level audio interface */ 475 audio_attach_mi(&dbri_hw_if, sc, sc->sc_dev); 476 477 /* power down until open() */ 478 mutex_spin_enter(&sc->sc_intr_lock); 479 dbri_set_power(sc, 0); 480 mutex_spin_exit(&sc->sc_intr_lock); 481 482 return 0; 483 } 484 485 static int 486 dbri_intr(void *hdl) 487 { 488 struct dbri_softc *sc = hdl; 489 bus_space_tag_t iot = sc->sc_iot; 490 bus_space_handle_t ioh = sc->sc_ioh; 491 int x; 492 493 mutex_spin_enter(&sc->sc_intr_lock); 494 495 /* clear interrupt */ 496 x = bus_space_read_4(iot, ioh, DBRI_REG1); 497 if (x & (DBRI_MRR | DBRI_MLE | DBRI_LBG | DBRI_MBE)) { 498 uint32_t tmp; 499 500 if (x & DBRI_MRR) 501 aprint_debug_dev(sc->sc_dev, 502 "multiple ack error on sbus\n"); 503 if (x & DBRI_MLE) 504 aprint_debug_dev(sc->sc_dev, 505 "multiple late error on sbus\n"); 506 if (x & DBRI_LBG) 507 aprint_debug_dev(sc->sc_dev, 508 "lost bus grant on sbus\n"); 509 if (x & DBRI_MBE) 510 aprint_debug_dev(sc->sc_dev, "burst error on sbus\n"); 511 512 /* 513 * Some of these errors disable the chip's circuitry. 514 * Re-enable the circuitry and keep on going. 515 */ 516 517 tmp = bus_space_read_4(iot, ioh, DBRI_REG0); 518 tmp &= ~(DBRI_DISABLE_MASTER); 519 bus_space_write_4(iot, ioh, DBRI_REG0, tmp); 520 } 521 522 #if 0 523 if (!x & 1) /* XXX: DBRI_INTR_REQ */ 524 return (1); 525 #endif 526 527 dbri_process_interrupt_buffer(sc); 528 529 mutex_spin_exit(&sc->sc_intr_lock); 530 531 return (1); 532 } 533 534 static void 535 dbri_softint(void *cookie) 536 { 537 struct dbri_desc *dd = cookie; 538 539 if (dd->callback != NULL) 540 dd->callback(dd->callback_args); 541 } 542 543 static int 544 dbri_init(struct dbri_softc *sc) 545 { 546 bus_space_tag_t iot = sc->sc_iot; 547 bus_space_handle_t ioh = sc->sc_ioh; 548 uint32_t reg; 549 volatile uint32_t *cmd; 550 bus_addr_t dmaaddr; 551 int n; 552 553 KASSERT(mutex_owned(sc->sc_intr_lock)); 554 555 dbri_reset(sc); 556 sc->sc_mm.status = 0; 557 558 cmd = dbri_command_lock(sc); 559 560 /* XXX: Initialize interrupt ring buffer */ 561 sc->sc_dma->intr[0] = (uint32_t)sc->sc_dmabase + dbri_dma_off(intr, 0); 562 sc->sc_irqp = 1; 563 564 /* Initialize pipes */ 565 for (n = 0; n < DBRI_PIPE_MAX; n++) 566 sc->sc_pipe[n].desc = sc->sc_pipe[n].next = -1; 567 568 for (n = 1; n < DBRI_INT_BLOCKS; n++) { 569 sc->sc_dma->intr[n] = 0; 570 } 571 572 /* XXX 16 byte bursts cause errors, the rest works */ 573 reg = bus_space_read_4(iot, ioh, DBRI_REG0); 574 575 /*reg &= ~(DBRI_BURST_4 | DBRI_BURST_8 | DBRI_BURST_16);*/ 576 reg |= (DBRI_BURST_4 | DBRI_BURST_8); 577 bus_space_write_4(iot, ioh, DBRI_REG0, reg); 578 579 /* setup interrupt queue */ 580 dmaaddr = (uint32_t)sc->sc_dmabase + dbri_dma_off(intr, 0); 581 *(cmd++) = DBRI_CMD(DBRI_COMMAND_IIQ, 0, 0); 582 *(cmd++) = dmaaddr; 583 584 dbri_command_send(sc, cmd); 585 586 return (0); 587 } 588 589 static int 590 dbri_reset(struct dbri_softc *sc) 591 { 592 int bail = 0; 593 594 bus_space_tag_t iot = sc->sc_iot; 595 bus_space_handle_t ioh = sc->sc_ioh; 596 597 bus_space_write_4(iot, ioh, DBRI_REG0, DBRI_SOFT_RESET); 598 while ((bus_space_read_4(iot, ioh, DBRI_REG0) & DBRI_SOFT_RESET) && 599 (bail < 100000)) { 600 bail++; 601 delay(10); 602 } 603 if (bail == 100000) 604 aprint_error_dev(sc->sc_dev, "reset timed out\n"); 605 return (0); 606 } 607 608 static volatile uint32_t * 609 dbri_command_lock(struct dbri_softc *sc) 610 { 611 612 if (sc->sc_locked) 613 aprint_debug_dev(sc->sc_dev, "command buffer locked\n"); 614 615 sc->sc_locked++; 616 617 return (&sc->sc_dma->command[0]); 618 } 619 620 static void 621 dbri_command_send(struct dbri_softc *sc, volatile uint32_t *cmd) 622 { 623 bus_space_handle_t ioh = sc->sc_ioh; 624 bus_space_tag_t iot = sc->sc_iot; 625 int maxloops = 1000000; 626 627 KASSERT(mutex_owned(sc->sc_intr_lock)); 628 629 sc->sc_locked--; 630 631 if (sc->sc_locked != 0) { 632 aprint_error_dev(sc->sc_dev, 633 "command buffer improperly locked\n"); 634 } else if ((cmd - &sc->sc_dma->command[0]) >= DBRI_NUM_COMMANDS - 1) { 635 aprint_error_dev(sc->sc_dev, "command buffer overflow\n"); 636 } else { 637 *(cmd++) = DBRI_CMD(DBRI_COMMAND_PAUSE, 0, 0); 638 *(cmd++) = DBRI_CMD(DBRI_COMMAND_WAIT, 1, 0); 639 sc->sc_waitseen = 0; 640 bus_space_write_4(iot, ioh, DBRI_REG8, sc->sc_dmabase); 641 while ((--maxloops) > 0 && 642 (bus_space_read_4(iot, ioh, DBRI_REG0) 643 & DBRI_COMMAND_VALID)) { 644 bus_space_barrier(iot, ioh, DBRI_REG0, 4, 645 BUS_SPACE_BARRIER_READ); 646 delay(1000); 647 } 648 649 if (maxloops == 0) { 650 aprint_error_dev(sc->sc_dev, 651 "chip never completed command buffer\n"); 652 } else { 653 654 DPRINTF("%s: command completed\n", 655 device_xname(sc->sc_dev)); 656 657 while ((--maxloops) > 0 && (!sc->sc_waitseen)) 658 dbri_process_interrupt_buffer(sc); 659 if (maxloops == 0) { 660 aprint_error_dev(sc->sc_dev, "chip never acked WAIT\n"); 661 } 662 } 663 } 664 665 return; 666 } 667 668 static void 669 dbri_process_interrupt_buffer(struct dbri_softc *sc) 670 { 671 int32_t i; 672 int orig_irqp = sc->sc_irqp; 673 674 KASSERT(mutex_owned(sc->sc_intr_lock)); 675 676 while ((i = sc->sc_dma->intr[sc->sc_irqp]) != 0) { 677 sc->sc_dma->intr[sc->sc_irqp] = 0; 678 sc->sc_irqp++; 679 680 if (sc->sc_irqp == DBRI_INT_BLOCKS) 681 sc->sc_irqp = 1; 682 else if ((sc->sc_irqp & (DBRI_INT_BLOCKS - 1)) == 0) 683 sc->sc_irqp++; 684 685 dbri_process_interrupt(sc, i); 686 687 /* don't loop more than once. */ 688 if (orig_irqp == sc->sc_irqp) 689 break; 690 } 691 692 return; 693 } 694 695 static void 696 dbri_process_interrupt(struct dbri_softc *sc, int32_t i) 697 { 698 #if 0 699 const int liu_states[] = { 1, 0, 8, 3, 4, 5, 6, 7 }; 700 #endif 701 int val = DBRI_INTR_GETVAL(i); 702 int channel = DBRI_INTR_GETCHAN(i); 703 int command = DBRI_INTR_GETCMD(i); 704 int code = DBRI_INTR_GETCODE(i); 705 #if 0 706 int rval = DBRI_INTR_GETRVAL(i); 707 #endif 708 if (channel == DBRI_INTR_CMD && command == DBRI_COMMAND_WAIT) 709 sc->sc_waitseen++; 710 711 switch (code) { 712 case DBRI_INTR_XCMP: /* transmission complete */ 713 { 714 int td; 715 struct dbri_desc *dd; 716 717 DPRINTF("%s:%d tx complete\n", __func__, channel); 718 td = sc->sc_pipe[channel].desc; 719 dd = &sc->sc_desc[td]; 720 721 if (dd->callback != NULL) 722 softint_schedule(dd->softint); 723 break; 724 } 725 case DBRI_INTR_FXDT: /* fixed data change */ 726 DPRINTF("%s:%d: Fixed data change: %x\n", __func__, channel, 727 val); 728 if (sc->sc_pipe[channel].sdp & DBRI_SDP_MSB) 729 val = reverse_bytes(val, sc->sc_pipe[channel].length); 730 if (sc->sc_pipe[channel].prec) 731 *(sc->sc_pipe[channel].prec) = val; 732 #ifndef DBRI_SPIN 733 DPRINTF("%s: cv_broadcast %p\n", device_xname(sc->sc_dev), sc); 734 cv_broadcast(&sc->sc_cv); 735 #endif 736 break; 737 case DBRI_INTR_SBRI: 738 DPRINTF("dbri_intr: SBRI\n"); 739 break; 740 case DBRI_INTR_BRDY: 741 { 742 int td; 743 struct dbri_desc *dd; 744 745 DPRINTF("dbri_intr: buffer ready (%d)\n", channel); 746 td = sc->sc_pipe[channel].desc; 747 dd = &sc->sc_desc[td]; 748 749 if (dd->callback != NULL) 750 softint_schedule(dd->softint); 751 break; 752 } 753 case DBRI_INTR_UNDR: 754 { 755 volatile uint32_t *cmd; 756 int td = sc->sc_pipe[channel].desc; 757 758 DPRINTF("%s: DBRI_INTR_UNDR\n", device_xname(sc->sc_dev)); 759 760 sc->sc_dma->xmit[td].status = 0; 761 762 cmd = dbri_command_lock(sc); 763 *(cmd++) = DBRI_CMD(DBRI_COMMAND_SDP, 0, 764 sc->sc_pipe[channel].sdp | 765 DBRI_SDP_VALID_POINTER | 766 DBRI_SDP_CLEAR | 767 DBRI_SDP_2SAME); 768 *(cmd++) = sc->sc_dmabase + dbri_dma_off(xmit, td); 769 dbri_command_send(sc, cmd); 770 break; 771 } 772 case DBRI_INTR_CMDI: 773 DPRINTF("ok"); 774 break; 775 default: 776 777 aprint_error_dev(sc->sc_dev, "unknown interrupt code %d\n", 778 code); 779 break; 780 } 781 782 return; 783 } 784 785 /* 786 * mmcodec stuff 787 */ 788 789 static int 790 mmcodec_init(struct dbri_softc *sc) 791 { 792 bus_space_handle_t ioh = sc->sc_ioh; 793 bus_space_tag_t iot = sc->sc_iot; 794 uint32_t reg2; 795 int bail; 796 797 reg2 = bus_space_read_4(iot, ioh, DBRI_REG2); 798 DPRINTF("mmcodec_init: PIO reads %x\n", reg2); 799 800 if (reg2 & DBRI_PIO2) { 801 aprint_normal_dev(sc->sc_dev, " onboard CS4215 detected\n"); 802 sc->sc_mm.onboard = 1; 803 } 804 805 if (reg2 & DBRI_PIO0) { 806 aprint_normal_dev(sc->sc_dev, "speakerbox detected\n"); 807 bus_space_write_4(iot, ioh, DBRI_REG2, DBRI_PIO2_ENABLE); 808 sc->sc_mm.onboard = 0; 809 } 810 811 if ((reg2 & DBRI_PIO2) && (reg2 & DBRI_PIO0)) { 812 aprint_normal_dev(sc->sc_dev, "using speakerbox\n"); 813 bus_space_write_4(iot, ioh, DBRI_REG2, DBRI_PIO2_ENABLE); 814 sc->sc_mm.onboard = 0; 815 } 816 817 if (!(reg2 & (DBRI_PIO0|DBRI_PIO2))) { 818 aprint_normal_dev(sc->sc_dev, "no mmcodec found\n"); 819 return -1; 820 } 821 822 sc->sc_version = 0xff; 823 824 mmcodec_pipe_init(sc); 825 mmcodec_default(sc); 826 827 sc->sc_mm.offset = sc->sc_mm.onboard ? 0 : 8; 828 829 /* 830 * mmcodec_setcontrol() sometimes fails right after powerup 831 * so we just try again until we either get a useful response or run 832 * out of time 833 */ 834 bail = 0; 835 while (mmcodec_setcontrol(sc) == -1 || sc->sc_version == 0xff) { 836 837 bail++; 838 if (bail > 100) { 839 DPRINTF("%s: cs4215 probe failed at offset %d\n", 840 device_xname(sc->sc_dev), sc->sc_mm.offset); 841 return (-1); 842 } 843 delay(10000); 844 } 845 846 aprint_normal_dev(sc->sc_dev, "cs4215 rev %c found at offset %d\n", 847 0x43 + (sc->sc_version & 0xf), sc->sc_mm.offset); 848 849 /* set some sane defaults for mmcodec_init_data */ 850 sc->sc_params.channels = 2; 851 sc->sc_params.precision = 16; 852 853 mmcodec_init_data(sc); 854 855 return (0); 856 } 857 858 static void 859 mmcodec_init_data(struct dbri_softc *sc) 860 { 861 bus_space_tag_t iot = sc->sc_iot; 862 bus_space_handle_t ioh = sc->sc_ioh; 863 uint32_t tmp; 864 int data_width; 865 866 tmp = bus_space_read_4(iot, ioh, DBRI_REG0); 867 tmp &= ~(DBRI_CHI_ACTIVATE); /* disable CHI */ 868 bus_space_write_4(iot, ioh, DBRI_REG0, tmp); 869 870 /* switch CS4215 to data mode - set PIO3 to 1 */ 871 tmp = DBRI_PIO_ENABLE_ALL | DBRI_PIO1 | DBRI_PIO3; 872 873 /* XXX */ 874 tmp |= (sc->sc_mm.onboard ? DBRI_PIO0 : DBRI_PIO2); 875 876 bus_space_write_4(iot, ioh, DBRI_REG2, tmp); 877 chi_reset(sc, CHIslave, 128); 878 879 data_width = sc->sc_params.channels * sc->sc_params.precision; 880 881 if ((data_width != 32) && (data_width != 8)) 882 aprint_error("%s: data_width is %d\n", __func__, data_width); 883 884 pipe_ts_link(sc, 20, PIPEoutput, 16, 32, sc->sc_mm.offset + 32); 885 pipe_ts_link(sc, 4, PIPEoutput, 16, data_width, sc->sc_mm.offset); 886 pipe_ts_link(sc, 6, PIPEinput, 16, data_width, sc->sc_mm.offset); 887 #if 0 888 /* readback for the mixer registers - we don't use that */ 889 pipe_ts_link(sc, 21, PIPEinput, 16, 32, sc->sc_mm.offset + 32); 890 891 pipe_receive_fixed(sc, 21, &sc->sc_mm.d.ldata); 892 #endif 893 mmcodec_setgain(sc, 0); 894 895 tmp = bus_space_read_4(iot, ioh, DBRI_REG0); 896 tmp |= DBRI_CHI_ACTIVATE; 897 bus_space_write_4(iot, ioh, DBRI_REG0, tmp); 898 899 return; 900 } 901 902 static void 903 mmcodec_pipe_init(struct dbri_softc *sc) 904 { 905 906 pipe_setup(sc, 4, DBRI_SDP_MEM | DBRI_SDP_TO_SER | DBRI_SDP_MSB); 907 pipe_setup(sc, 20, DBRI_SDP_FIXED | DBRI_SDP_TO_SER | DBRI_SDP_MSB); 908 pipe_setup(sc, 6, DBRI_SDP_MEM | DBRI_SDP_FROM_SER | DBRI_SDP_MSB); 909 #if 0 910 pipe_setup(sc, 21, DBRI_SDP_FIXED | DBRI_SDP_FROM_SER | DBRI_SDP_MSB); 911 #endif 912 pipe_setup(sc, 17, DBRI_SDP_FIXED | DBRI_SDP_TO_SER | DBRI_SDP_MSB); 913 pipe_setup(sc, 18, DBRI_SDP_FIXED | DBRI_SDP_FROM_SER | DBRI_SDP_MSB); 914 pipe_setup(sc, 19, DBRI_SDP_FIXED | DBRI_SDP_FROM_SER | DBRI_SDP_MSB); 915 916 pipe_receive_fixed(sc, 18, &sc->sc_mm.status); 917 pipe_receive_fixed(sc, 19, &sc->sc_mm.version); 918 919 return; 920 } 921 922 static void 923 mmcodec_default(struct dbri_softc *sc) 924 { 925 struct cs4215_state *mm = &sc->sc_mm; 926 927 /* 928 * no action, memory resetting only 929 * 930 * data time slots 5-8 931 * speaker, line and headphone enable. set gain to half. 932 * input is line 933 */ 934 mm->d.bdata[0] = sc->sc_latt = 0x20 | CS4215_HE | CS4215_LE; 935 mm->d.bdata[1] = sc->sc_ratt = 0x20 | CS4215_SE; 936 sc->sc_linp = 128; 937 sc->sc_rinp = 128; 938 sc->sc_monitor = 0; 939 sc->sc_input = 1; /* line */ 940 mm->d.bdata[2] = (CS4215_LG((sc->sc_linp >> 4)) & 0x0f) | 941 ((sc->sc_input == 2) ? CS4215_IS : 0) | CS4215_PIO0 | CS4215_PIO1; 942 mm->d.bdata[3] = (CS4215_RG((sc->sc_rinp >> 4) & 0x0f)) | 943 CS4215_MA(15 - ((sc->sc_monitor >> 4) & 0x0f)); 944 945 946 /* 947 * control time slots 1-4 948 * 949 * 0: default I/O voltage scale 950 * 1: 8 bit ulaw, 8kHz, mono, high pass filter disabled 951 * 2: serial enable, CHI master, 128 bits per frame, clock 1 952 * 3: tests disabled 953 */ 954 mm->c.bcontrol[0] = CS4215_ONE | CS4215_MLB; 955 mm->c.bcontrol[1] = CS4215_DFR_ULAW | CS4215_FREQ[0].csval; 956 mm->c.bcontrol[2] = CS4215_XCLK | CS4215_BSEL_128 | CS4215_FREQ[0].xtal; 957 mm->c.bcontrol[3] = 0; 958 959 return; 960 } 961 962 static void 963 mmcodec_setgain(struct dbri_softc *sc, int mute) 964 { 965 if (mute) { 966 /* disable all outputs, max. attenuation */ 967 sc->sc_mm.d.bdata[0] = sc->sc_latt | 63; 968 sc->sc_mm.d.bdata[1] = sc->sc_ratt | 63; 969 } else { 970 971 sc->sc_mm.d.bdata[0] = sc->sc_latt; 972 sc->sc_mm.d.bdata[1] = sc->sc_ratt; 973 } 974 975 /* input stuff */ 976 sc->sc_mm.d.bdata[2] = CS4215_LG((sc->sc_linp >> 4) & 0x0f) | 977 ((sc->sc_input == 2) ? CS4215_IS : 0) | CS4215_PIO0 | CS4215_PIO1; 978 sc->sc_mm.d.bdata[3] = (CS4215_RG((sc->sc_rinp >> 4)) & 0x0f) | 979 (CS4215_MA(15 - ((sc->sc_monitor >> 4) & 0x0f))); 980 981 if (sc->sc_powerstate == 0) 982 return; 983 pipe_transmit_fixed(sc, 20, sc->sc_mm.d.ldata); 984 985 DPRINTF("mmcodec_setgain: %08x\n", sc->sc_mm.d.ldata); 986 /* give the chip some time to execute the command */ 987 delay(250); 988 989 return; 990 } 991 992 static int 993 mmcodec_setcontrol(struct dbri_softc *sc) 994 { 995 bus_space_tag_t iot = sc->sc_iot; 996 bus_space_handle_t ioh = sc->sc_ioh; 997 uint32_t val; 998 uint32_t tmp; 999 int ret = 0; 1000 #ifdef DBRI_SPIN 1001 int i; 1002 #else 1003 int error, bail = 0; 1004 #endif 1005 1006 /* 1007 * Temporarily mute outputs and wait 125 us to make sure that it 1008 * happens. This avoids clicking noises. 1009 */ 1010 mmcodec_setgain(sc, 1); 1011 delay(125); 1012 1013 tmp = bus_space_read_4(iot, ioh, DBRI_REG0); 1014 tmp &= ~(DBRI_CHI_ACTIVATE); /* disable CHI */ 1015 bus_space_write_4(iot, ioh, DBRI_REG0, tmp); 1016 1017 bus_space_write_4(iot, ioh, DBRI_REG2, 0); 1018 delay(125); 1019 1020 /* enable control mode */ 1021 val = DBRI_PIO_ENABLE_ALL | DBRI_PIO1; /* was PIO1 */ 1022 1023 /* XXX */ 1024 val |= (sc->sc_mm.onboard ? DBRI_PIO0 : DBRI_PIO2); 1025 1026 bus_space_write_4(iot, ioh, DBRI_REG2, val); 1027 delay(34); 1028 1029 /* 1030 * in control mode, the cs4215 is the slave device, so the 1031 * DBRI must act as the CHI master. 1032 * 1033 * in data mode, the cs4215 must be the CHI master to insure 1034 * that the data stream is in sync with its codec 1035 */ 1036 tmp = bus_space_read_4(iot, ioh, DBRI_REG0); 1037 tmp &= ~DBRI_COMMAND_CHI; 1038 bus_space_write_4(iot, ioh, DBRI_REG0, tmp); 1039 1040 chi_reset(sc, CHImaster, 128); 1041 1042 /* control mode */ 1043 pipe_ts_link(sc, 17, PIPEoutput, 16, 32, sc->sc_mm.offset); 1044 pipe_ts_link(sc, 18, PIPEinput, 16, 8, sc->sc_mm.offset); 1045 pipe_ts_link(sc, 19, PIPEinput, 16, 8, sc->sc_mm.offset + 48); 1046 1047 pipe_receive_fixed(sc, 18, &sc->sc_mm.status); 1048 1049 /* wait for the chip to echo back CLB as zero */ 1050 sc->sc_mm.c.bcontrol[0] &= ~CS4215_CLB; 1051 pipe_transmit_fixed(sc, 17, sc->sc_mm.c.lcontrol); 1052 1053 tmp = bus_space_read_4(iot, ioh, DBRI_REG0); 1054 tmp |= DBRI_CHI_ACTIVATE; 1055 bus_space_write_4(iot, ioh, DBRI_REG0, tmp); 1056 1057 #ifdef DBRI_SPIN 1058 i = 1024; 1059 while (((sc->sc_mm.status & 0xe4) != CS4215_ONE) && (i > 0)) { 1060 i--; 1061 delay(125); 1062 } 1063 1064 if (i == 0) { 1065 DPRINTF("%s: cs4215 didn't respond to CLB (0x%02x)\n", 1066 device_xname(sc->sc_dev), sc->sc_mm.status); 1067 ret = -1; 1068 goto fail; 1069 } 1070 #else 1071 mutex_spin_enter(&sc->sc_intr_lock); 1072 while (((sc->sc_mm.status & 0xe4) != CS4215_ONE) && (bail < 10)) { 1073 DPRINTF("%s: cv_wait_sig %p\n", device_xname(sc->sc_dev), sc); 1074 error = cv_timedwait_sig(&sc->sc_cv, &sc->sc_intr_lock, hz); 1075 if (error == EINTR) { 1076 DPRINTF("%s: interrupted\n", device_xname(sc->sc_dev)); 1077 ret = -1; 1078 mutex_spin_exit(&sc->sc_intr_lock); 1079 goto fail; 1080 } 1081 bail++; 1082 } 1083 mutex_spin_exit(&sc->sc_intr_lock); 1084 if (bail >= 10) { 1085 aprint_error("%s: switching to control mode timed out (%x %x)\n", 1086 device_xname(sc->sc_dev), sc->sc_mm.status, 1087 bus_space_read_4(iot, ioh, DBRI_REG2)); 1088 ret = -1; 1089 goto fail; 1090 } 1091 #endif 1092 1093 /* copy the version information before it becomes unreadable again */ 1094 sc->sc_version = sc->sc_mm.version; 1095 sc->sc_whack_codec = 0; 1096 1097 fail: 1098 /* terminate cs4215 control mode */ 1099 sc->sc_mm.c.bcontrol[0] |= CS4215_CLB; 1100 pipe_transmit_fixed(sc, 17, sc->sc_mm.c.lcontrol); 1101 1102 /* two frames of control info @ 8kHz frame rate = 250us delay */ 1103 delay(250); 1104 1105 mmcodec_setgain(sc, 0); 1106 1107 return ret; 1108 1109 } 1110 1111 /* 1112 * CHI combo 1113 */ 1114 static void 1115 chi_reset(struct dbri_softc *sc, enum ms ms, int bpf) 1116 { 1117 volatile uint32_t *cmd; 1118 int val; 1119 int clockrate, divisor; 1120 1121 cmd = dbri_command_lock(sc); 1122 1123 /* set CHI anchor: pipe 16 */ 1124 val = DBRI_DTS_VI | DBRI_DTS_INS | DBRI_DTS_PRVIN(16) | DBRI_PIPE(16); 1125 *(cmd++) = DBRI_CMD(DBRI_COMMAND_DTS, 0, val); 1126 *(cmd++) = DBRI_TS_ANCHOR | DBRI_TS_NEXT(16); 1127 *(cmd++) = 0; 1128 1129 val = DBRI_DTS_VO | DBRI_DTS_INS | DBRI_DTS_PRVOUT(16) | DBRI_PIPE(16); 1130 *(cmd++) = DBRI_CMD(DBRI_COMMAND_DTS, 0, val); 1131 *(cmd++) = 0; 1132 *(cmd++) = DBRI_TS_ANCHOR | DBRI_TS_NEXT(16); 1133 1134 sc->sc_pipe[16].sdp = 1; 1135 sc->sc_pipe[16].next = 16; 1136 sc->sc_chi_pipe_in = 16; 1137 sc->sc_chi_pipe_out = 16; 1138 1139 switch (ms) { 1140 case CHIslave: 1141 *(cmd++) = DBRI_CMD(DBRI_COMMAND_CHI, 0, DBRI_CHI_CHICM(0)); 1142 break; 1143 case CHImaster: 1144 clockrate = bpf * 8; 1145 divisor = 12288 / clockrate; 1146 1147 if (divisor > 255 || divisor * clockrate != 12288) 1148 aprint_error_dev(sc->sc_dev, 1149 "illegal bits-per-frame %d\n", bpf); 1150 1151 *(cmd++) = DBRI_CMD(DBRI_COMMAND_CHI, 0, 1152 DBRI_CHI_CHICM(divisor) | DBRI_CHI_FD | DBRI_CHI_BPF(bpf)); 1153 break; 1154 default: 1155 aprint_error_dev(sc->sc_dev, "unknown value for ms!\n"); 1156 break; 1157 } 1158 1159 sc->sc_chi_bpf = bpf; 1160 1161 /* CHI data mode */ 1162 *(cmd++) = DBRI_CMD(DBRI_COMMAND_PAUSE, 0, 0); 1163 *(cmd++) = DBRI_CMD(DBRI_COMMAND_CDM, 0, 1164 DBRI_CDM_XCE | DBRI_CDM_XEN | DBRI_CDM_REN); 1165 1166 dbri_command_send(sc, cmd); 1167 1168 return; 1169 } 1170 1171 /* 1172 * pipe stuff 1173 */ 1174 static void 1175 pipe_setup(struct dbri_softc *sc, int pipe, int sdp) 1176 { 1177 DPRINTF("pipe setup: %d\n", pipe); 1178 if (pipe < 0 || pipe >= DBRI_PIPE_MAX) { 1179 aprint_error_dev(sc->sc_dev, "illegal pipe number %d\n", 1180 pipe); 1181 return; 1182 } 1183 1184 if ((sdp & 0xf800) != sdp) 1185 aprint_error_dev(sc->sc_dev, "strange SDP value %d\n", 1186 sdp); 1187 1188 if (DBRI_SDP_MODE(sdp) == DBRI_SDP_FIXED && 1189 !(sdp & DBRI_SDP_TO_SER)) 1190 sdp |= DBRI_SDP_CHANGE; 1191 1192 sdp |= DBRI_PIPE(pipe); 1193 1194 sc->sc_pipe[pipe].sdp = sdp; 1195 sc->sc_pipe[pipe].desc = -1; 1196 1197 pipe_reset(sc, pipe); 1198 1199 return; 1200 } 1201 1202 static void 1203 pipe_reset(struct dbri_softc *sc, int pipe) 1204 { 1205 struct dbri_desc *dd; 1206 int sdp; 1207 int desc; 1208 volatile uint32_t *cmd; 1209 1210 if (pipe < 0 || pipe >= DBRI_PIPE_MAX) { 1211 aprint_error_dev(sc->sc_dev, "illegal pipe number %d\n", 1212 pipe); 1213 return; 1214 } 1215 1216 sdp = sc->sc_pipe[pipe].sdp; 1217 if (sdp == 0) { 1218 aprint_error_dev(sc->sc_dev, "can not reset uninitialized pipe %d\n", 1219 pipe); 1220 return; 1221 } 1222 1223 cmd = dbri_command_lock(sc); 1224 *(cmd++) = DBRI_CMD(DBRI_COMMAND_SDP, 0, 1225 sdp | DBRI_SDP_CLEAR | DBRI_SDP_VALID_POINTER); 1226 *(cmd++) = 0; 1227 dbri_command_send(sc, cmd); 1228 1229 desc = sc->sc_pipe[pipe].desc; 1230 1231 dd = &sc->sc_desc[desc]; 1232 1233 dd->busy = 0; 1234 1235 #if 0 1236 if (dd->callback) 1237 softint_schedule(dd->softint); 1238 #endif 1239 1240 sc->sc_pipe[pipe].desc = -1; 1241 1242 return; 1243 } 1244 1245 static void 1246 pipe_receive_fixed(struct dbri_softc *sc, int pipe, volatile uint32_t *prec) 1247 { 1248 1249 if (pipe < DBRI_PIPE_MAX / 2 || pipe >= DBRI_PIPE_MAX) { 1250 aprint_error_dev(sc->sc_dev, "illegal pipe number %d\n", 1251 pipe); 1252 return; 1253 } 1254 1255 if (DBRI_SDP_MODE(sc->sc_pipe[pipe].sdp) != DBRI_SDP_FIXED) { 1256 aprint_error_dev(sc->sc_dev, "non-fixed pipe %d\n", 1257 pipe); 1258 return; 1259 } 1260 1261 if (sc->sc_pipe[pipe].sdp & DBRI_SDP_TO_SER) { 1262 aprint_error_dev(sc->sc_dev, "can not receive on transmit pipe %d\b", 1263 pipe); 1264 return; 1265 } 1266 1267 sc->sc_pipe[pipe].prec = prec; 1268 1269 return; 1270 } 1271 1272 static void 1273 pipe_transmit_fixed(struct dbri_softc *sc, int pipe, uint32_t data) 1274 { 1275 volatile uint32_t *cmd; 1276 1277 if (pipe < DBRI_PIPE_MAX / 2 || pipe >= DBRI_PIPE_MAX) { 1278 aprint_error_dev(sc->sc_dev, "illegal pipe number %d\n", 1279 pipe); 1280 return; 1281 } 1282 1283 if (DBRI_SDP_MODE(sc->sc_pipe[pipe].sdp) == 0) { 1284 aprint_error_dev(sc->sc_dev, "uninitialized pipe %d\n", 1285 pipe); 1286 return; 1287 } 1288 1289 if (DBRI_SDP_MODE(sc->sc_pipe[pipe].sdp) != DBRI_SDP_FIXED) { 1290 aprint_error_dev(sc->sc_dev, "non-fixed pipe %d\n", 1291 pipe); 1292 return; 1293 } 1294 1295 if (!(sc->sc_pipe[pipe].sdp & DBRI_SDP_TO_SER)) { 1296 aprint_error_dev(sc->sc_dev, "called on receive pipe %d\n", 1297 pipe); 1298 return; 1299 } 1300 1301 if (sc->sc_pipe[pipe].sdp & DBRI_SDP_MSB) 1302 data = reverse_bytes(data, sc->sc_pipe[pipe].length); 1303 1304 cmd = dbri_command_lock(sc); 1305 *(cmd++) = DBRI_CMD(DBRI_COMMAND_SSP, 0, pipe); 1306 *(cmd++) = data; 1307 1308 dbri_command_send(sc, cmd); 1309 1310 return; 1311 } 1312 1313 static void 1314 setup_ring_xmit(struct dbri_softc *sc, int pipe, int which, int num, int blksz, 1315 void (*callback)(void *), void *callback_args) 1316 { 1317 volatile uint32_t *cmd; 1318 int i; 1319 #if 0 1320 int td; 1321 int td_first, td_last; 1322 #endif 1323 bus_addr_t dmabuf, dmabase; 1324 struct dbri_desc *dd = &sc->sc_desc[which]; 1325 1326 switch (pipe) { 1327 case 4: 1328 /* output, offset 0 */ 1329 break; 1330 default: 1331 aprint_error("%s: illegal pipe number (%d)\n", 1332 __func__, pipe); 1333 return; 1334 } 1335 1336 #if 0 1337 td = 0; 1338 td_first = td_last = -1; 1339 #endif 1340 1341 if (sc->sc_pipe[pipe].sdp == 0) { 1342 aprint_error_dev(sc->sc_dev, "uninitialized pipe %d\n", 1343 pipe); 1344 return; 1345 } 1346 1347 dmabuf = dd->dmabase; 1348 dmabase = sc->sc_dmabase; 1349 1350 for (i = 0; i < (num - 1); i++) { 1351 1352 sc->sc_dma->xmit[i].flags = TX_BCNT(blksz) 1353 | TX_EOF | TX_BINT; 1354 sc->sc_dma->xmit[i].ba = dmabuf; 1355 sc->sc_dma->xmit[i].nda = dmabase + dbri_dma_off(xmit, i + 1); 1356 sc->sc_dma->xmit[i].status = 0; 1357 1358 #if 0 1359 td_last = td; 1360 #endif 1361 dmabuf += blksz; 1362 } 1363 1364 sc->sc_dma->xmit[i].flags = TX_BCNT(blksz) | TX_EOF | TX_BINT; 1365 1366 sc->sc_dma->xmit[i].ba = dmabuf; 1367 sc->sc_dma->xmit[i].nda = dmabase + dbri_dma_off(xmit, 0); 1368 sc->sc_dma->xmit[i].status = 0; 1369 1370 dd->callback = callback; 1371 dd->callback_args = callback_args; 1372 1373 /* the pipe shouldn't be active */ 1374 if (pipe_active(sc, pipe)) { 1375 aprint_error("pipe active (CDP)\n"); 1376 /* pipe is already active */ 1377 #if 0 1378 td_last = sc->sc_pipe[pipe].desc; 1379 while (sc->sc_desc[td_last].next != -1) 1380 td_last = sc->sc_desc[td_last].next; 1381 1382 sc->sc_desc[td_last].next = td_first; 1383 sc->sc_dma->desc[td_last].nda = 1384 sc->sc_dmabase + dbri_dma_off(desc, td_first); 1385 1386 cmd = dbri_command_lock(sc); 1387 *(cmd++) = DBRI_CMD(DBRI_COMMAND_CDP, 0, pipe); 1388 dbri_command_send(sc, cmd); 1389 #endif 1390 } else { 1391 /* 1392 * pipe isn't active - issue an SDP command to start our 1393 * chain of TDs running 1394 */ 1395 sc->sc_pipe[pipe].desc = which; 1396 cmd = dbri_command_lock(sc); 1397 *(cmd++) = DBRI_CMD(DBRI_COMMAND_SDP, 0, 1398 sc->sc_pipe[pipe].sdp | 1399 DBRI_SDP_VALID_POINTER | 1400 DBRI_SDP_EVERY | 1401 DBRI_SDP_CLEAR); 1402 *(cmd++) = sc->sc_dmabase + dbri_dma_off(xmit, 0); 1403 dbri_command_send(sc, cmd); 1404 DPRINTF("%s: starting DMA\n", __func__); 1405 } 1406 1407 return; 1408 } 1409 1410 static void 1411 setup_ring_recv(struct dbri_softc *sc, int pipe, int which, int num, int blksz, 1412 void (*callback)(void *), void *callback_args) 1413 { 1414 volatile uint32_t *cmd; 1415 int i; 1416 #if 0 1417 int td_first, td_last; 1418 #endif 1419 bus_addr_t dmabuf, dmabase; 1420 struct dbri_desc *dd = &sc->sc_desc[which]; 1421 1422 switch (pipe) { 1423 case 6: 1424 break; 1425 default: 1426 aprint_error("%s: illegal pipe number (%d)\n", 1427 __func__, pipe); 1428 return; 1429 } 1430 1431 #if 0 1432 td_first = td_last = -1; 1433 #endif 1434 1435 if (sc->sc_pipe[pipe].sdp == 0) { 1436 aprint_error_dev(sc->sc_dev, "uninitialized pipe %d\n", 1437 pipe); 1438 return; 1439 } 1440 1441 dmabuf = dd->dmabase; 1442 dmabase = sc->sc_dmabase; 1443 1444 for (i = 0; i < (num - 1); i++) { 1445 1446 sc->sc_dma->recv[i].flags = RX_BSIZE(blksz) | RX_FINAL; 1447 sc->sc_dma->recv[i].ba = dmabuf; 1448 sc->sc_dma->recv[i].nda = dmabase + dbri_dma_off(recv, i + 1); 1449 sc->sc_dma->recv[i].status = RX_EOF; 1450 1451 #if 0 1452 td_last = i; 1453 #endif 1454 dmabuf += blksz; 1455 } 1456 1457 sc->sc_dma->recv[i].flags = RX_BSIZE(blksz) | RX_FINAL; 1458 1459 sc->sc_dma->recv[i].ba = dmabuf; 1460 sc->sc_dma->recv[i].nda = dmabase + dbri_dma_off(recv, 0); 1461 sc->sc_dma->recv[i].status = RX_EOF; 1462 1463 dd->callback = callback; 1464 dd->callback_args = callback_args; 1465 1466 /* the pipe shouldn't be active */ 1467 if (pipe_active(sc, pipe)) { 1468 aprint_error("pipe active (CDP)\n"); 1469 /* pipe is already active */ 1470 #if 0 1471 td_last = sc->sc_pipe[pipe].desc; 1472 while (sc->sc_desc[td_last].next != -1) 1473 td_last = sc->sc_desc[td_last].next; 1474 1475 sc->sc_desc[td_last].next = td_first; 1476 sc->sc_dma->desc[td_last].nda = 1477 sc->sc_dmabase + dbri_dma_off(desc, td_first); 1478 1479 cmd = dbri_command_lock(sc); 1480 *(cmd++) = DBRI_CMD(DBRI_COMMAND_CDP, 0, pipe); 1481 dbri_command_send(sc, cmd); 1482 #endif 1483 } else { 1484 /* 1485 * pipe isn't active - issue an SDP command to start our 1486 * chain of TDs running 1487 */ 1488 sc->sc_pipe[pipe].desc = which; 1489 cmd = dbri_command_lock(sc); 1490 *(cmd++) = DBRI_CMD(DBRI_COMMAND_SDP, 0, 1491 sc->sc_pipe[pipe].sdp | 1492 DBRI_SDP_VALID_POINTER | 1493 DBRI_SDP_EVERY | 1494 DBRI_SDP_CLEAR); 1495 *(cmd++) = sc->sc_dmabase + dbri_dma_off(recv, 0); 1496 dbri_command_send(sc, cmd); 1497 DPRINTF("%s: starting DMA\n", __func__); 1498 } 1499 1500 return; 1501 } 1502 1503 static void 1504 pipe_ts_link(struct dbri_softc *sc, int pipe, enum io dir, int basepipe, 1505 int len, int cycle) 1506 { 1507 volatile uint32_t *cmd; 1508 int prevpipe, nextpipe; 1509 int val; 1510 1511 DPRINTF("%s: %d\n", __func__, pipe); 1512 if (pipe < 0 || pipe >= DBRI_PIPE_MAX || 1513 basepipe < 0 || basepipe >= DBRI_PIPE_MAX) { 1514 aprint_error_dev(sc->sc_dev, "illegal pipe numbers (%d, %d)\n", 1515 pipe, basepipe); 1516 return; 1517 } 1518 1519 if (sc->sc_pipe[pipe].sdp == 0 || sc->sc_pipe[basepipe].sdp == 0) { 1520 aprint_error_dev(sc->sc_dev, "uninitialized pipe (%d, %d)\n", 1521 pipe, basepipe); 1522 return; 1523 } 1524 1525 if (basepipe == 16 && dir == PIPEoutput && cycle == 0) 1526 cycle = sc->sc_chi_bpf; 1527 1528 if (basepipe == pipe) 1529 prevpipe = nextpipe = pipe; 1530 else { 1531 if (basepipe == 16) { 1532 if (dir == PIPEinput) { 1533 prevpipe = sc->sc_chi_pipe_in; 1534 } else { 1535 prevpipe = sc->sc_chi_pipe_out; 1536 } 1537 } else 1538 prevpipe = basepipe; 1539 1540 nextpipe = sc->sc_pipe[prevpipe].next; 1541 1542 while (sc->sc_pipe[nextpipe].cycle < cycle && 1543 sc->sc_pipe[nextpipe].next != basepipe) { 1544 prevpipe = nextpipe; 1545 nextpipe = sc->sc_pipe[nextpipe].next; 1546 } 1547 } 1548 1549 if (prevpipe == 16) { 1550 if (dir == PIPEinput) { 1551 sc->sc_chi_pipe_in = pipe; 1552 } else { 1553 sc->sc_chi_pipe_out = pipe; 1554 } 1555 } else 1556 sc->sc_pipe[prevpipe].next = pipe; 1557 1558 sc->sc_pipe[pipe].next = nextpipe; 1559 sc->sc_pipe[pipe].cycle = cycle; 1560 sc->sc_pipe[pipe].length = len; 1561 1562 cmd = dbri_command_lock(sc); 1563 1564 switch (dir) { 1565 case PIPEinput: 1566 val = DBRI_DTS_VI | DBRI_DTS_INS | DBRI_DTS_PRVIN(prevpipe); 1567 val |= pipe; 1568 *(cmd++) = DBRI_CMD(DBRI_COMMAND_DTS, 0, val); 1569 *(cmd++) = DBRI_TS_LEN(len) | DBRI_TS_CYCLE(cycle) | 1570 DBRI_TS_NEXT(nextpipe); 1571 *(cmd++) = 0; 1572 break; 1573 case PIPEoutput: 1574 val = DBRI_DTS_VO | DBRI_DTS_INS | DBRI_DTS_PRVOUT(prevpipe); 1575 val |= pipe; 1576 *(cmd++) = DBRI_CMD(DBRI_COMMAND_DTS, 0, val); 1577 *(cmd++) = 0; 1578 *(cmd++) = DBRI_TS_LEN(len) | DBRI_TS_CYCLE(cycle) | 1579 DBRI_TS_NEXT(nextpipe); 1580 break; 1581 default: 1582 DPRINTF("%s: should not have happened!\n", 1583 device_xname(sc->sc_dev)); 1584 break; 1585 } 1586 1587 dbri_command_send(sc, cmd); 1588 1589 return; 1590 } 1591 1592 static int 1593 pipe_active(struct dbri_softc *sc, int pipe) 1594 { 1595 1596 return (sc->sc_pipe[pipe].desc != -1); 1597 } 1598 1599 /* 1600 * subroutines required to interface with audio(9) 1601 */ 1602 1603 static int 1604 dbri_query_encoding(void *hdl, struct audio_encoding *ae) 1605 { 1606 1607 switch (ae->index) { 1608 case 0: 1609 strcpy(ae->name, AudioEulinear); 1610 ae->encoding = AUDIO_ENCODING_ULINEAR; 1611 ae->precision = 8; 1612 ae->flags = 0; 1613 break; 1614 case 1: 1615 strcpy(ae->name, AudioEmulaw); 1616 ae->encoding = AUDIO_ENCODING_ULAW; 1617 ae->precision = 8; 1618 ae->flags = 0; 1619 break; 1620 case 2: 1621 strcpy(ae->name, AudioEalaw); 1622 ae->encoding = AUDIO_ENCODING_ALAW; 1623 ae->precision = 8; 1624 ae->flags = 0; 1625 break; 1626 case 3: 1627 strcpy(ae->name, AudioEslinear); 1628 ae->encoding = AUDIO_ENCODING_SLINEAR; 1629 ae->precision = 8; 1630 ae->flags = AUDIO_ENCODINGFLAG_EMULATED; 1631 break; 1632 case 4: 1633 strcpy(ae->name, AudioEslinear_le); 1634 ae->encoding = AUDIO_ENCODING_SLINEAR_LE; 1635 ae->precision = 16; 1636 ae->flags = AUDIO_ENCODINGFLAG_EMULATED; 1637 break; 1638 case 5: 1639 strcpy(ae->name, AudioEulinear_le); 1640 ae->encoding = AUDIO_ENCODING_ULINEAR_LE; 1641 ae->precision = 16; 1642 ae->flags = AUDIO_ENCODINGFLAG_EMULATED; 1643 break; 1644 case 6: 1645 strcpy(ae->name, AudioEslinear_be); 1646 ae->encoding = AUDIO_ENCODING_SLINEAR_BE; 1647 ae->precision = 16; 1648 ae->flags = 0; 1649 break; 1650 case 7: 1651 strcpy(ae->name, AudioEulinear_be); 1652 ae->encoding = AUDIO_ENCODING_ULINEAR_BE; 1653 ae->precision = 16; 1654 ae->flags = AUDIO_ENCODINGFLAG_EMULATED; 1655 break; 1656 case 8: 1657 strcpy(ae->name, AudioEslinear); 1658 ae->encoding = AUDIO_ENCODING_SLINEAR; 1659 ae->precision = 16; 1660 ae->flags = 0; 1661 break; 1662 default: 1663 return (EINVAL); 1664 } 1665 1666 return (0); 1667 } 1668 1669 static int 1670 dbri_set_params(void *hdl, int setmode, int usemode, 1671 struct audio_params *play, struct audio_params *rec, 1672 stream_filter_list_t *pfil, stream_filter_list_t *rfil) 1673 { 1674 struct dbri_softc *sc = hdl; 1675 int rate; 1676 audio_params_t *p = NULL; 1677 stream_filter_list_t *fil; 1678 int mode; 1679 1680 /* 1681 * This device only has one clock, so make the sample rates match. 1682 */ 1683 if (play->sample_rate != rec->sample_rate && 1684 usemode == (AUMODE_PLAY | AUMODE_RECORD)) { 1685 if (setmode == AUMODE_PLAY) { 1686 rec->sample_rate = play->sample_rate; 1687 setmode |= AUMODE_RECORD; 1688 } else if (setmode == AUMODE_RECORD) { 1689 play->sample_rate = rec->sample_rate; 1690 setmode |= AUMODE_PLAY; 1691 } else 1692 return EINVAL; 1693 } 1694 1695 for (mode = AUMODE_RECORD; mode != -1; 1696 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) { 1697 if ((setmode & mode) == 0) 1698 continue; 1699 1700 p = mode == AUMODE_PLAY ? play : rec; 1701 if (p->sample_rate < 4000 || p->sample_rate > 50000) { 1702 DPRINTF("dbri_set_params: invalid rate %d\n", 1703 p->sample_rate); 1704 return EINVAL; 1705 } 1706 1707 fil = mode == AUMODE_PLAY ? pfil : rfil; 1708 DPRINTF("requested enc: %d rate: %d prec: %d chan: %d\n", p->encoding, 1709 p->sample_rate, p->precision, p->channels); 1710 if (auconv_set_converter(dbri_formats, DBRI_NFORMATS, 1711 mode, p, true, fil) < 0) { 1712 aprint_debug("dbri_set_params: auconv_set_converter failed\n"); 1713 return EINVAL; 1714 } 1715 if (fil->req_size > 0) 1716 p = &fil->filters[0].param; 1717 } 1718 1719 if (p == NULL) { 1720 DPRINTF("dbri_set_params: no parameters to set\n"); 1721 return 0; 1722 } 1723 1724 DPRINTF("native enc: %d rate: %d prec: %d chan: %d\n", p->encoding, 1725 p->sample_rate, p->precision, p->channels); 1726 1727 for (rate = 0; CS4215_FREQ[rate].freq; rate++) 1728 if (CS4215_FREQ[rate].freq == p->sample_rate) 1729 break; 1730 1731 if (CS4215_FREQ[rate].freq == 0) 1732 return (EINVAL); 1733 1734 /* set frequency */ 1735 sc->sc_mm.c.bcontrol[1] &= ~0x38; 1736 sc->sc_mm.c.bcontrol[1] |= CS4215_FREQ[rate].csval; 1737 sc->sc_mm.c.bcontrol[2] &= ~0x70; 1738 sc->sc_mm.c.bcontrol[2] |= CS4215_FREQ[rate].xtal; 1739 1740 switch (p->encoding) { 1741 case AUDIO_ENCODING_ULAW: 1742 sc->sc_mm.c.bcontrol[1] &= ~3; 1743 sc->sc_mm.c.bcontrol[1] |= CS4215_DFR_ULAW; 1744 break; 1745 case AUDIO_ENCODING_ALAW: 1746 sc->sc_mm.c.bcontrol[1] &= ~3; 1747 sc->sc_mm.c.bcontrol[1] |= CS4215_DFR_ALAW; 1748 break; 1749 case AUDIO_ENCODING_ULINEAR: 1750 sc->sc_mm.c.bcontrol[1] &= ~3; 1751 if (p->precision == 8) { 1752 sc->sc_mm.c.bcontrol[1] |= CS4215_DFR_LINEAR8; 1753 } else { 1754 sc->sc_mm.c.bcontrol[1] |= CS4215_DFR_LINEAR16; 1755 } 1756 break; 1757 case AUDIO_ENCODING_SLINEAR_BE: 1758 case AUDIO_ENCODING_SLINEAR: 1759 sc->sc_mm.c.bcontrol[1] &= ~3; 1760 sc->sc_mm.c.bcontrol[1] |= CS4215_DFR_LINEAR16; 1761 break; 1762 } 1763 1764 switch (p->channels) { 1765 case 1: 1766 sc->sc_mm.c.bcontrol[1] &= ~CS4215_DFR_STEREO; 1767 break; 1768 case 2: 1769 sc->sc_mm.c.bcontrol[1] |= CS4215_DFR_STEREO; 1770 break; 1771 } 1772 sc->sc_whack_codec = 1; 1773 return (0); 1774 } 1775 1776 static int 1777 dbri_round_blocksize(void *hdl, int bs, int mode, 1778 const audio_params_t *param) 1779 { 1780 1781 /* 1782 * DBRI DMA segment size can be up to 0x1fff, sixes that are not powers 1783 * of two seem to confuse the upper audio layer so we're going with 1784 * 0x1000 here 1785 */ 1786 return 0x1000; 1787 } 1788 1789 static int 1790 dbri_halt_output(void *hdl) 1791 { 1792 struct dbri_softc *sc = hdl; 1793 1794 if (!sc->sc_playing) 1795 return 0; 1796 1797 sc->sc_playing = 0; 1798 pipe_reset(sc, 4); 1799 return (0); 1800 } 1801 1802 static int 1803 dbri_getdev(void *hdl, struct audio_device *ret) 1804 { 1805 1806 *ret = dbri_device; 1807 return (0); 1808 } 1809 1810 static int 1811 dbri_set_port(void *hdl, mixer_ctrl_t *mc) 1812 { 1813 struct dbri_softc *sc = hdl; 1814 int latt = sc->sc_latt, ratt = sc->sc_ratt; 1815 1816 switch (mc->dev) { 1817 case DBRI_VOL_OUTPUT: /* master volume */ 1818 latt = (latt & 0xc0) | (63 - 1819 min(mc->un.value.level[AUDIO_MIXER_LEVEL_LEFT] >> 2, 63)); 1820 ratt = (ratt & 0xc0) | (63 - 1821 min(mc->un.value.level[AUDIO_MIXER_LEVEL_RIGHT] >> 2, 63)); 1822 break; 1823 case DBRI_ENABLE_MONO: /* built-in speaker */ 1824 if (mc->un.ord == 1) { 1825 ratt |= CS4215_SE; 1826 } else 1827 ratt &= ~CS4215_SE; 1828 break; 1829 case DBRI_ENABLE_HEADPHONE: /* headphones output */ 1830 if (mc->un.ord == 1) { 1831 latt |= CS4215_HE; 1832 } else 1833 latt &= ~CS4215_HE; 1834 break; 1835 case DBRI_ENABLE_LINE: /* line out */ 1836 if (mc->un.ord == 1) { 1837 latt |= CS4215_LE; 1838 } else 1839 latt &= ~CS4215_LE; 1840 break; 1841 case DBRI_VOL_MONITOR: 1842 if (mc->un.value.level[AUDIO_MIXER_LEVEL_LEFT] == 1843 sc->sc_monitor) 1844 return 0; 1845 sc->sc_monitor = mc->un.value.level[AUDIO_MIXER_LEVEL_LEFT]; 1846 break; 1847 case DBRI_INPUT_GAIN: 1848 sc->sc_linp = mc->un.value.level[AUDIO_MIXER_LEVEL_LEFT]; 1849 sc->sc_rinp = mc->un.value.level[AUDIO_MIXER_LEVEL_RIGHT]; 1850 break; 1851 case DBRI_INPUT_SELECT: 1852 if (mc->un.mask == sc->sc_input) 1853 return 0; 1854 sc->sc_input = mc->un.mask; 1855 break; 1856 } 1857 1858 sc->sc_latt = latt; 1859 sc->sc_ratt = ratt; 1860 1861 mmcodec_setgain(sc, 0); 1862 1863 return (0); 1864 } 1865 1866 static int 1867 dbri_get_port(void *hdl, mixer_ctrl_t *mc) 1868 { 1869 struct dbri_softc *sc = hdl; 1870 1871 switch (mc->dev) { 1872 case DBRI_VOL_OUTPUT: /* master volume */ 1873 mc->un.value.level[AUDIO_MIXER_LEVEL_LEFT] = 1874 (63 - (sc->sc_latt & 0x3f)) << 2; 1875 mc->un.value.level[AUDIO_MIXER_LEVEL_RIGHT] = 1876 (63 - (sc->sc_ratt & 0x3f)) << 2; 1877 return (0); 1878 case DBRI_ENABLE_MONO: /* built-in speaker */ 1879 mc->un.ord = (sc->sc_ratt & CS4215_SE) ? 1 : 0; 1880 return 0; 1881 case DBRI_ENABLE_HEADPHONE: /* headphones output */ 1882 mc->un.ord = (sc->sc_latt & CS4215_HE) ? 1 : 0; 1883 return 0; 1884 case DBRI_ENABLE_LINE: /* line out */ 1885 mc->un.ord = (sc->sc_latt & CS4215_LE) ? 1 : 0; 1886 return 0; 1887 case DBRI_VOL_MONITOR: 1888 mc->un.value.level[AUDIO_MIXER_LEVEL_LEFT] = sc->sc_monitor; 1889 return 0; 1890 case DBRI_INPUT_GAIN: 1891 mc->un.value.level[AUDIO_MIXER_LEVEL_LEFT] = sc->sc_linp; 1892 mc->un.value.level[AUDIO_MIXER_LEVEL_RIGHT] = sc->sc_rinp; 1893 return 0; 1894 case DBRI_INPUT_SELECT: 1895 mc->un.mask = sc->sc_input; 1896 return 0; 1897 } 1898 return (EINVAL); 1899 } 1900 1901 static int 1902 dbri_query_devinfo(void *hdl, mixer_devinfo_t *di) 1903 { 1904 1905 switch (di->index) { 1906 case DBRI_MONITOR_CLASS: 1907 di->mixer_class = DBRI_MONITOR_CLASS; 1908 strcpy(di->label.name, AudioCmonitor); 1909 di->type = AUDIO_MIXER_CLASS; 1910 di->next = di->prev = AUDIO_MIXER_LAST; 1911 return 0; 1912 case DBRI_OUTPUT_CLASS: 1913 di->mixer_class = DBRI_OUTPUT_CLASS; 1914 strcpy(di->label.name, AudioCoutputs); 1915 di->type = AUDIO_MIXER_CLASS; 1916 di->next = di->prev = AUDIO_MIXER_LAST; 1917 return 0; 1918 case DBRI_INPUT_CLASS: 1919 di->mixer_class = DBRI_INPUT_CLASS; 1920 strcpy(di->label.name, AudioCinputs); 1921 di->type = AUDIO_MIXER_CLASS; 1922 di->next = di->prev = AUDIO_MIXER_LAST; 1923 return 0; 1924 case DBRI_VOL_OUTPUT: /* master volume */ 1925 di->mixer_class = DBRI_OUTPUT_CLASS; 1926 di->next = di->prev = AUDIO_MIXER_LAST; 1927 strcpy(di->label.name, AudioNmaster); 1928 di->type = AUDIO_MIXER_VALUE; 1929 di->un.v.num_channels = 2; 1930 di->un.v.delta = 16; 1931 strcpy(di->un.v.units.name, AudioNvolume); 1932 return (0); 1933 case DBRI_INPUT_GAIN: /* input gain */ 1934 di->mixer_class = DBRI_INPUT_CLASS; 1935 di->next = di->prev = AUDIO_MIXER_LAST; 1936 strcpy(di->label.name, AudioNrecord); 1937 di->type = AUDIO_MIXER_VALUE; 1938 di->un.v.num_channels = 2; 1939 strcpy(di->un.v.units.name, AudioNvolume); 1940 return (0); 1941 case DBRI_VOL_MONITOR: /* monitor volume */ 1942 di->mixer_class = DBRI_MONITOR_CLASS; 1943 di->next = di->prev = AUDIO_MIXER_LAST; 1944 strcpy(di->label.name, AudioNmonitor); 1945 di->type = AUDIO_MIXER_VALUE; 1946 di->un.v.num_channels = 1; 1947 strcpy(di->un.v.units.name, AudioNvolume); 1948 return (0); 1949 case DBRI_ENABLE_MONO: /* built-in speaker */ 1950 di->mixer_class = DBRI_OUTPUT_CLASS; 1951 di->next = di->prev = AUDIO_MIXER_LAST; 1952 strcpy(di->label.name, AudioNmono); 1953 di->type = AUDIO_MIXER_ENUM; 1954 di->un.e.num_mem = 2; 1955 strcpy(di->un.e.member[0].label.name, AudioNoff); 1956 di->un.e.member[0].ord = 0; 1957 strcpy(di->un.e.member[1].label.name, AudioNon); 1958 di->un.e.member[1].ord = 1; 1959 return (0); 1960 case DBRI_ENABLE_HEADPHONE: /* headphones output */ 1961 di->mixer_class = DBRI_OUTPUT_CLASS; 1962 di->next = di->prev = AUDIO_MIXER_LAST; 1963 strcpy(di->label.name, AudioNheadphone); 1964 di->type = AUDIO_MIXER_ENUM; 1965 di->un.e.num_mem = 2; 1966 strcpy(di->un.e.member[0].label.name, AudioNoff); 1967 di->un.e.member[0].ord = 0; 1968 strcpy(di->un.e.member[1].label.name, AudioNon); 1969 di->un.e.member[1].ord = 1; 1970 return (0); 1971 case DBRI_ENABLE_LINE: /* line out */ 1972 di->mixer_class = DBRI_OUTPUT_CLASS; 1973 di->next = di->prev = AUDIO_MIXER_LAST; 1974 strcpy(di->label.name, AudioNline); 1975 di->type = AUDIO_MIXER_ENUM; 1976 di->un.e.num_mem = 2; 1977 strcpy(di->un.e.member[0].label.name, AudioNoff); 1978 di->un.e.member[0].ord = 0; 1979 strcpy(di->un.e.member[1].label.name, AudioNon); 1980 di->un.e.member[1].ord = 1; 1981 return (0); 1982 case DBRI_INPUT_SELECT: 1983 di->mixer_class = DBRI_INPUT_CLASS; 1984 strcpy(di->label.name, AudioNsource); 1985 di->type = AUDIO_MIXER_SET; 1986 di->prev = di->next = AUDIO_MIXER_LAST; 1987 di->un.s.num_mem = 2; 1988 strcpy(di->un.s.member[0].label.name, AudioNline); 1989 di->un.s.member[0].mask = 1 << 0; 1990 strcpy(di->un.s.member[1].label.name, AudioNmicrophone); 1991 di->un.s.member[1].mask = 1 << 1; 1992 return 0; 1993 } 1994 1995 return (ENXIO); 1996 } 1997 1998 static size_t 1999 dbri_round_buffersize(void *hdl, int dir, size_t bufsize) 2000 { 2001 #ifdef DBRI_BIG_BUFFER 2002 return 0x20000; /* use 128KB buffer */ 2003 #else 2004 return bufsize; 2005 #endif 2006 } 2007 2008 static int 2009 dbri_get_props(void *hdl) 2010 { 2011 2012 return AUDIO_PROP_MMAP | AUDIO_PROP_FULLDUPLEX; 2013 } 2014 2015 static int 2016 dbri_commit(void *hdl) 2017 { 2018 struct dbri_softc *sc = hdl; 2019 int ret = 0; 2020 2021 /* 2022 * we only need to whack the codec if things like sample format or 2023 * frequency changed, not for mixer stuff 2024 */ 2025 if (sc->sc_whack_codec == 0) 2026 return 0; 2027 2028 ret = mmcodec_setcontrol(sc); 2029 if (ret) { 2030 DPRINTF("%s: control mode failed. Mutex %s PIL %x\n", __func__, 2031 mutex_owned(&sc->sc_intr_lock) ? "held" : "free", 2032 (getpsr() & PSR_PIL) >> 8); 2033 } else 2034 DPRINTF("%s: control mode ok\n", __func__); 2035 mmcodec_init_data(sc); 2036 return 0; 2037 } 2038 2039 static int 2040 dbri_trigger_output(void *hdl, void *start, void *end, int blksize, 2041 void (*intr)(void *), void *intrarg, 2042 const struct audio_params *param) 2043 { 2044 struct dbri_softc *sc = hdl; 2045 unsigned long count, num; 2046 2047 if (sc->sc_playing) 2048 return 0; 2049 2050 count = (unsigned long)(((char *)end - (char *)start)); 2051 num = count / blksize; 2052 2053 DPRINTF("trigger_output(%lx %lx) : %d %ld %ld\n", 2054 (unsigned long)intr, 2055 (unsigned long)intrarg, blksize, count, num); 2056 2057 sc->sc_params = *param; 2058 2059 /* 2060 * always use DMA descriptor 0 for output 2061 * no need to allocate them dynamically since we only ever have 2062 * exactly one input stream and exactly one output stream 2063 */ 2064 setup_ring_xmit(sc, 4, 0, num, blksize, intr, intrarg); 2065 sc->sc_playing = 1; 2066 return 0; 2067 } 2068 2069 static int 2070 dbri_halt_input(void *cookie) 2071 { 2072 struct dbri_softc *sc = cookie; 2073 2074 if (!sc->sc_recording) 2075 return 0; 2076 2077 sc->sc_recording = 0; 2078 pipe_reset(sc, 6); 2079 return 0; 2080 } 2081 2082 static int 2083 dbri_trigger_input(void *hdl, void *start, void *end, int blksize, 2084 void (*intr)(void *), void *intrarg, 2085 const struct audio_params *param) 2086 { 2087 struct dbri_softc *sc = hdl; 2088 unsigned long count, num; 2089 2090 if (sc->sc_recording) 2091 return 0; 2092 2093 count = (unsigned long)(((char *)end - (char *)start)); 2094 num = count / blksize; 2095 2096 DPRINTF("trigger_input(%lx %lx) : %d %ld %ld\n", 2097 (unsigned long)intr, 2098 (unsigned long)intrarg, blksize, count, num); 2099 2100 sc->sc_params = *param; 2101 2102 sc->sc_recording = 1; 2103 setup_ring_recv(sc, 6, 1, num, blksize, intr, intrarg); 2104 return 0; 2105 } 2106 2107 static void 2108 dbri_get_locks(void *opaque, kmutex_t **intr, kmutex_t **thread) 2109 { 2110 struct dbri_softc *sc = opaque; 2111 2112 *intr = &sc->sc_intr_lock; 2113 *thread = &sc->sc_lock; 2114 } 2115 2116 static uint32_t 2117 reverse_bytes(uint32_t b, int len) 2118 { 2119 switch (len) { 2120 case 32: 2121 b = ((b & 0xffff0000) >> 16) | ((b & 0x0000ffff) << 16); 2122 case 16: 2123 b = ((b & 0xff00ff00) >> 8) | ((b & 0x00ff00ff) << 8); 2124 case 8: 2125 b = ((b & 0xf0f0f0f0) >> 4) | ((b & 0x0f0f0f0f) << 4); 2126 case 4: 2127 b = ((b & 0xcccccccc) >> 2) | ((b & 0x33333333) << 2); 2128 case 2: 2129 b = ((b & 0xaaaaaaaa) >> 1) | ((b & 0x55555555) << 1); 2130 case 1: 2131 case 0: 2132 break; 2133 default: 2134 DPRINTF("reverse_bytes: unsupported length\n"); 2135 }; 2136 2137 return (b); 2138 } 2139 2140 static void * 2141 dbri_malloc(void *v, int dir, size_t s) 2142 { 2143 struct dbri_softc *sc = v; 2144 struct dbri_desc *dd = &sc->sc_desc[sc->sc_desc_used]; 2145 int rseg; 2146 2147 if (bus_dmamap_create(sc->sc_dmat, s, 1, s, 0, BUS_DMA_NOWAIT, 2148 &dd->dmamap) == 0) { 2149 if (bus_dmamem_alloc(sc->sc_dmat, s, 0, 0, &dd->dmaseg, 2150 1, &rseg, BUS_DMA_NOWAIT) == 0) { 2151 if (bus_dmamem_map(sc->sc_dmat, &dd->dmaseg, rseg, s, 2152 &dd->buf, BUS_DMA_NOWAIT|BUS_DMA_COHERENT) == 0) { 2153 if (dd->buf != NULL) { 2154 if (bus_dmamap_load(sc->sc_dmat, 2155 dd->dmamap, dd->buf, s, NULL, 2156 BUS_DMA_NOWAIT) == 0) { 2157 dd->len = s; 2158 dd->busy = 0; 2159 dd->callback = NULL; 2160 dd->dmabase = 2161 dd->dmamap->dm_segs[0].ds_addr; 2162 DPRINTF("dbri_malloc: using buffer %d %08x\n", 2163 sc->sc_desc_used, (uint32_t)dd->buf); 2164 sc->sc_desc_used++; 2165 return dd->buf; 2166 } else 2167 aprint_error("dbri_malloc: load failed\n"); 2168 } else 2169 aprint_error("dbri_malloc: map returned NULL\n"); 2170 } else 2171 aprint_error("dbri_malloc: map failed\n"); 2172 bus_dmamem_free(sc->sc_dmat, &dd->dmaseg, rseg); 2173 } else 2174 aprint_error("dbri_malloc: malloc() failed\n"); 2175 bus_dmamap_destroy(sc->sc_dmat, dd->dmamap); 2176 } else 2177 aprint_error("dbri_malloc: bus_dmamap_create() failed\n"); 2178 return NULL; 2179 } 2180 2181 static void 2182 dbri_free(void *v, void *p, size_t size) 2183 { 2184 struct dbri_softc *sc = v; 2185 struct dbri_desc *dd; 2186 int i; 2187 2188 for (i = 0; i < sc->sc_desc_used; i++) { 2189 dd = &sc->sc_desc[i]; 2190 if (dd->buf == p) 2191 break; 2192 } 2193 if (i >= sc->sc_desc_used) 2194 return; 2195 bus_dmamap_unload(sc->sc_dmat, dd->dmamap); 2196 bus_dmamap_destroy(sc->sc_dmat, dd->dmamap); 2197 } 2198 2199 static paddr_t 2200 dbri_mappage(void *v, void *mem, off_t off, int prot) 2201 { 2202 struct dbri_softc *sc = v; 2203 int current; 2204 2205 if (off < 0) 2206 return -1; 2207 2208 current = 0; 2209 while ((current < sc->sc_desc_used) && 2210 (sc->sc_desc[current].buf != mem)) 2211 current++; 2212 2213 if (current < sc->sc_desc_used) { 2214 return bus_dmamem_mmap(sc->sc_dmat, 2215 &sc->sc_desc[current].dmaseg, 1, off, prot, BUS_DMA_WAITOK); 2216 } 2217 2218 return -1; 2219 } 2220 2221 static int 2222 dbri_open(void *cookie, int flags) 2223 { 2224 struct dbri_softc *sc = cookie; 2225 2226 DPRINTF("%s: %d\n", __func__, sc->sc_refcount); 2227 2228 if (sc->sc_refcount == 0) 2229 dbri_bring_up(sc); 2230 2231 sc->sc_refcount++; 2232 2233 return 0; 2234 } 2235 2236 static void 2237 dbri_close(void *cookie) 2238 { 2239 struct dbri_softc *sc = cookie; 2240 2241 DPRINTF("%s: %d\n", __func__, sc->sc_refcount); 2242 2243 sc->sc_refcount--; 2244 KASSERT(sc->sc_refcount >= 0); 2245 if (sc->sc_refcount > 0) 2246 return; 2247 2248 dbri_set_power(sc, 0); 2249 sc->sc_playing = 0; 2250 sc->sc_recording = 0; 2251 } 2252 2253 static bool 2254 dbri_suspend(device_t self, const pmf_qual_t *qual) 2255 { 2256 struct dbri_softc *sc = device_private(self); 2257 2258 mutex_spin_enter(&sc->sc_intr_lock); 2259 dbri_set_power(sc, 0); 2260 mutex_spin_exit(&sc->sc_intr_lock); 2261 return true; 2262 } 2263 2264 static bool 2265 dbri_resume(device_t self, const pmf_qual_t *qual) 2266 { 2267 struct dbri_softc *sc = device_private(self); 2268 2269 if (sc->sc_powerstate != 0) 2270 return true; 2271 aprint_verbose("resume: %d\n", sc->sc_refcount); 2272 if (sc->sc_playing) { 2273 volatile uint32_t *cmd; 2274 2275 mutex_spin_enter(&sc->sc_intr_lock); 2276 dbri_bring_up(sc); 2277 cmd = dbri_command_lock(sc); 2278 *(cmd++) = DBRI_CMD(DBRI_COMMAND_SDP, 2279 0, sc->sc_pipe[4].sdp | 2280 DBRI_SDP_VALID_POINTER | 2281 DBRI_SDP_EVERY | DBRI_SDP_CLEAR); 2282 *(cmd++) = sc->sc_dmabase + 2283 dbri_dma_off(xmit, 0); 2284 dbri_command_send(sc, cmd); 2285 mutex_spin_exit(&sc->sc_intr_lock); 2286 } 2287 return true; 2288 } 2289 2290 #endif /* NAUDIO > 0 */ 2291
Indexes created Thu Sep 25 16:09:42 GMT 2025