dbri.c revision 1.38
1 /* $NetBSD: dbri.c,v 1.38 2018/01/12 05:59:20 mrg Exp $ */ 2 3 /* 4 * Copyright (C) 1997 Rudolf Koenig (rfkoenig (at) immd4.informatik.uni-erlangen.de) 5 * Copyright (c) 1998, 1999 Brent Baccala (baccala (at) freesoft.org) 6 * Copyright (c) 2001, 2002 Jared D. McNeill <jmcneill (at) netbsd.org> 7 * Copyright (c) 2005 Michael Lorenz <macallan (at) netbsd.org> 8 * All rights reserved. 9 * 10 * This driver is losely based on a Linux driver written by Rudolf Koenig and 11 * Brent Baccala who kindly gave their permission to use their code in a 12 * BSD-licensed driver. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions 16 * are met: 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in the 21 * documentation and/or other materials provided with the distribution. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 28 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 29 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: dbri.c,v 1.38 2018/01/12 05:59:20 mrg Exp $"); 38 39 #include "audio.h" 40 #if NAUDIO > 0 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/errno.h> 45 #include <sys/device.h> 46 #include <sys/proc.h> 47 #include <sys/kernel.h> 48 #include <sys/bus.h> 49 #include <sys/intr.h> 50 #include <sys/kmem.h> 51 52 #include <dev/sbus/sbusvar.h> 53 #include <sparc/sparc/auxreg.h> 54 #include <machine/autoconf.h> 55 56 #include <sys/audioio.h> 57 #include <dev/audio_if.h> 58 #include <dev/auconv.h> 59 60 #include <dev/ic/cs4215reg.h> 61 #include <dev/ic/cs4215var.h> 62 #include <dev/sbus/dbrireg.h> 63 #include <dev/sbus/dbrivar.h> 64 65 #include "opt_sbus_dbri.h" 66 67 #define DBRI_ROM_NAME_PREFIX "SUNW,DBRI" 68 69 #ifdef DBRI_DEBUG 70 # define DPRINTF aprint_normal 71 #else 72 # define DPRINTF while (0) printf 73 #endif 74 75 static const char *dbri_supported[] = { 76 "e", 77 "s3", 78 "" 79 }; 80 81 enum ms { 82 CHImaster, 83 CHIslave 84 }; 85 86 enum io { 87 PIPEinput, 88 PIPEoutput 89 }; 90 91 /* 92 * Function prototypes 93 */ 94 95 /* softc stuff */ 96 static void dbri_attach_sbus(device_t, device_t, void *); 97 static int dbri_match_sbus(device_t, cfdata_t, void *); 98 99 static int dbri_config_interrupts(device_t); 100 101 /* interrupt handler */ 102 static int dbri_intr(void *); 103 static void dbri_softint(void *); 104 105 /* supporting subroutines */ 106 static int dbri_init(struct dbri_softc *); 107 static int dbri_reset(struct dbri_softc *); 108 static volatile uint32_t *dbri_command_lock(struct dbri_softc *); 109 static void dbri_command_send(struct dbri_softc *, volatile uint32_t *); 110 static void dbri_process_interrupt_buffer(struct dbri_softc *); 111 static void dbri_process_interrupt(struct dbri_softc *, int32_t); 112 113 /* mmcodec subroutines */ 114 static int mmcodec_init(struct dbri_softc *); 115 static void mmcodec_init_data(struct dbri_softc *); 116 static void mmcodec_pipe_init(struct dbri_softc *); 117 static void mmcodec_default(struct dbri_softc *); 118 static void mmcodec_setgain(struct dbri_softc *, int); 119 static int mmcodec_setcontrol(struct dbri_softc *); 120 121 /* chi subroutines */ 122 static void chi_reset(struct dbri_softc *, enum ms, int); 123 124 /* pipe subroutines */ 125 static void pipe_setup(struct dbri_softc *, int, int); 126 static void pipe_reset(struct dbri_softc *, int); 127 static void pipe_receive_fixed(struct dbri_softc *, int, 128 volatile uint32_t *); 129 static void pipe_transmit_fixed(struct dbri_softc *, int, uint32_t); 130 131 static void pipe_ts_link(struct dbri_softc *, int, enum io, int, int, int); 132 static int pipe_active(struct dbri_softc *, int); 133 134 /* audio(9) stuff */ 135 static int dbri_query_encoding(void *, struct audio_encoding *); 136 static int dbri_set_params(void *, int, int, struct audio_params *, 137 struct audio_params *,stream_filter_list_t *, stream_filter_list_t *); 138 static int dbri_round_blocksize(void *, int, int, const audio_params_t *); 139 static int dbri_halt_output(void *); 140 static int dbri_halt_input(void *); 141 static int dbri_getdev(void *, struct audio_device *); 142 static int dbri_set_port(void *, mixer_ctrl_t *); 143 static int dbri_get_port(void *, mixer_ctrl_t *); 144 static int dbri_query_devinfo(void *, mixer_devinfo_t *); 145 static size_t dbri_round_buffersize(void *, int, size_t); 146 static int dbri_get_props(void *); 147 static int dbri_open(void *, int); 148 static void dbri_close(void *); 149 150 static void setup_ring_xmit(struct dbri_softc *, int, int, int, int, 151 void (*)(void *), void *); 152 static void setup_ring_recv(struct dbri_softc *, int, int, int, int, 153 void (*)(void *), void *); 154 155 static int dbri_trigger_output(void *, void *, void *, int, 156 void (*)(void *), void *, const struct audio_params *); 157 static int dbri_trigger_input(void *, void *, void *, int, 158 void (*)(void *), void *, const struct audio_params *); 159 static void dbri_get_locks(void *, kmutex_t **, kmutex_t **); 160 161 static void *dbri_malloc(void *, int, size_t); 162 static void dbri_free(void *, void *, size_t); 163 static paddr_t dbri_mappage(void *, void *, off_t, int); 164 static void dbri_set_power(struct dbri_softc *, int); 165 static void dbri_bring_up(struct dbri_softc *); 166 static bool dbri_suspend(device_t, const pmf_qual_t *); 167 static bool dbri_resume(device_t, const pmf_qual_t *); 168 static int dbri_commit(void *); 169 170 /* stupid support routines */ 171 static uint32_t reverse_bytes(uint32_t, int); 172 173 struct audio_device dbri_device = { 174 "CS4215", 175 "", 176 "dbri" 177 }; 178 179 struct audio_hw_if dbri_hw_if = { 180 .open = dbri_open, 181 .close = dbri_close, 182 .query_encoding = dbri_query_encoding, 183 .set_params = dbri_set_params, 184 .round_blocksize = dbri_round_blocksize, 185 .halt_output = dbri_halt_output, 186 .halt_input = dbri_halt_input, 187 .getdev = dbri_getdev, 188 .set_port = dbri_set_port, 189 .get_port = dbri_get_port, 190 .query_devinfo = dbri_query_devinfo, 191 .allocm = dbri_malloc, 192 .freem = dbri_free, 193 .round_buffersize = dbri_round_buffersize, 194 .mappage = dbri_mappage, 195 .get_props = dbri_get_props, 196 .trigger_output = dbri_trigger_output, 197 .trigger_input = dbri_trigger_input, 198 .get_locks = dbri_get_locks, 199 .commit_settings = dbri_commit, 200 }; 201 202 CFATTACH_DECL_NEW(dbri, sizeof(struct dbri_softc), 203 dbri_match_sbus, dbri_attach_sbus, NULL, NULL); 204 205 #define DBRI_NFORMATS 4 206 static const struct audio_format dbri_formats[DBRI_NFORMATS] = { 207 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_SLINEAR_BE, 16, 16, 208 2, AUFMT_STEREO, 8, {8000, 9600, 11025, 16000, 22050, 32000, 44100, 209 48000}}, 210 /* {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_ULAW, 8, 8, 211 2, AUFMT_STEREO, 8, {8000, 9600, 11025, 16000, 22050, 32000, 44100, 212 48000}}, 213 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_ALAW, 8, 8, 214 2, AUFMT_STEREO, 8, {8000, 9600, 11025, 16000, 22050, 32000, 44100, 215 48000}}, 216 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_ULINEAR, 8, 8, 217 2, AUFMT_STEREO, 8, {8000, 9600, 11025, 16000, 22050, 32000, 44100, 218 48000}},*/ 219 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_ULAW, 8, 8, 220 1, AUFMT_MONAURAL, 8, {8000, 9600, 11025, 16000, 22050, 32000, 44100, 221 48000}}, 222 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_ALAW, 8, 8, 223 1, AUFMT_MONAURAL, 8, {8000, 9600, 11025, 16000, 22050, 32000, 44100, 224 48000}}, 225 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_ULINEAR, 8, 8, 226 1, AUFMT_MONAURAL, 8, {8000, 9600, 11025, 16000, 22050, 32000, 44100, 227 48000}}, 228 }; 229 230 enum { 231 DBRI_OUTPUT_CLASS, 232 DBRI_VOL_OUTPUT, 233 DBRI_ENABLE_MONO, 234 DBRI_ENABLE_HEADPHONE, 235 DBRI_ENABLE_LINE, 236 DBRI_MONITOR_CLASS, 237 DBRI_VOL_MONITOR, 238 DBRI_INPUT_CLASS, 239 DBRI_INPUT_GAIN, 240 DBRI_INPUT_SELECT, 241 DBRI_RECORD_CLASS, 242 DBRI_ENUM_LAST 243 }; 244 245 /* 246 * Autoconfig routines 247 */ 248 static int 249 dbri_match_sbus(device_t parent, cfdata_t match, void *aux) 250 { 251 struct sbus_attach_args *sa = aux; 252 char *ver; 253 int i; 254 255 if (strncmp(DBRI_ROM_NAME_PREFIX, sa->sa_name, 9)) 256 return (0); 257 258 ver = &sa->sa_name[9]; 259 260 for (i = 0; dbri_supported[i][0] != '\0'; i++) 261 if (strcmp(dbri_supported[i], ver) == 0) 262 return (1); 263 264 return (0); 265 } 266 267 static void 268 dbri_attach_sbus(device_t parent, device_t self, void *aux) 269 { 270 struct dbri_softc *sc = device_private(self); 271 struct sbus_attach_args *sa = aux; 272 bus_space_handle_t ioh; 273 bus_size_t size; 274 int error, rseg, pwr, i; 275 char *ver = &sa->sa_name[9]; 276 277 sc->sc_dev = self; 278 sc->sc_iot = sa->sa_bustag; 279 sc->sc_dmat = sa->sa_dmatag; 280 sc->sc_powerstate = 1; 281 282 sc->sc_whack_codec = 0; 283 284 pwr = prom_getpropint(sa->sa_node,"pwr-on-auxio",0); 285 aprint_normal(": rev %s\n", ver); 286 287 if (pwr) { 288 /* 289 * we can control DBRI power via auxio and we're initially 290 * powered down 291 */ 292 293 sc->sc_have_powerctl = 1; 294 sc->sc_powerstate = 0; 295 dbri_set_power(sc, 1); 296 if (!pmf_device_register(self, dbri_suspend, dbri_resume)) { 297 aprint_error_dev(self, 298 "cannot set power mgmt handler\n"); 299 } 300 } else { 301 /* we can't control power so we're always up */ 302 sc->sc_have_powerctl = 0; 303 sc->sc_powerstate = 1; 304 } 305 306 for (i = 0; i < DBRI_NUM_DESCRIPTORS; i++) { 307 sc->sc_desc[i].softint = softint_establish(SOFTINT_SERIAL, 308 dbri_softint, &sc->sc_desc[i]); 309 } 310 311 if (sa->sa_npromvaddrs) 312 ioh = (bus_space_handle_t)sa->sa_promvaddrs[0]; 313 else { 314 if (sbus_bus_map(sa->sa_bustag, sa->sa_slot, 315 sa->sa_offset, sa->sa_size, 316 BUS_SPACE_MAP_LINEAR, /*0,*/ &ioh) != 0) { 317 aprint_error("%s @ sbus: cannot map registers\n", 318 device_xname(self)); 319 return; 320 } 321 } 322 323 sc->sc_ioh = ioh; 324 325 size = sizeof(struct dbri_dma); 326 327 /* get a DMA handle */ 328 if ((error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, 329 BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) { 330 aprint_error_dev(self, "DMA map create error %d\n", 331 error); 332 return; 333 } 334 335 /* allocate DMA buffer */ 336 if ((error = bus_dmamem_alloc(sc->sc_dmat, size, 0, 0, &sc->sc_dmaseg, 337 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 338 aprint_error_dev(self, "DMA buffer alloc error %d\n", 339 error); 340 return; 341 } 342 343 /* map DMA buffer into CPU addressable space */ 344 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_dmaseg, rseg, size, 345 &sc->sc_membase, 346 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 347 aprint_error_dev(self, "DMA buffer map error %d\n", 348 error); 349 return; 350 } 351 352 /* load the buffer */ 353 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, 354 sc->sc_membase, size, NULL, 355 BUS_DMA_NOWAIT)) != 0) { 356 aprint_error_dev(self, "DMA buffer map load error %d\n", 357 error); 358 bus_dmamem_unmap(sc->sc_dmat, sc->sc_membase, size); 359 bus_dmamem_free(sc->sc_dmat, &sc->sc_dmaseg, rseg); 360 return; 361 } 362 363 /* map the registers into memory */ 364 365 /* kernel virtual address of DMA buffer */ 366 sc->sc_dma = (struct dbri_dma *)sc->sc_membase; 367 /* physical address of DMA buffer */ 368 sc->sc_dmabase = sc->sc_dmamap->dm_segs[0].ds_addr; 369 sc->sc_bufsiz = size; 370 371 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_NONE); 372 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_AUDIO); 373 374 #ifndef DBRI_SPIN 375 cv_init(&sc->sc_cv, "dbricv"); 376 #endif 377 378 bus_intr_establish(sa->sa_bustag, sa->sa_pri, IPL_AUDIO, dbri_intr, 379 sc); 380 381 sc->sc_locked = 0; 382 sc->sc_desc_used = 0; 383 sc->sc_refcount = 0; 384 sc->sc_playing = 0; 385 sc->sc_recording = 0; 386 sc->sc_init_done = 0; 387 config_finalize_register(self, &dbri_config_interrupts); 388 389 return; 390 } 391 392 /* 393 * lowlevel routine to switch power for the DBRI chip 394 */ 395 static void 396 dbri_set_power(struct dbri_softc *sc, int state) 397 { 398 int s; 399 400 if (sc->sc_have_powerctl == 0) 401 return; 402 if (sc->sc_powerstate == state) 403 return; 404 405 if (state) { 406 DPRINTF("%s: waiting to power up... ", 407 device_xname(sc->sc_dev)); 408 s = splhigh(); 409 *AUXIO4M_REG |= (AUXIO4M_MMX); 410 splx(s); 411 delay(10000); 412 DPRINTF("done (%02x)\n", *AUXIO4M_REG); 413 } else { 414 DPRINTF("%s: powering down\n", device_xname(sc->sc_dev)); 415 s = splhigh(); 416 *AUXIO4M_REG &= ~AUXIO4M_MMX; 417 splx(s); 418 DPRINTF("done (%02x})\n", *AUXIO4M_REG); 419 } 420 sc->sc_powerstate = state; 421 } 422 423 /* 424 * power up and re-initialize the chip 425 */ 426 static void 427 dbri_bring_up(struct dbri_softc *sc) 428 { 429 430 if (sc->sc_have_powerctl == 0) 431 return; 432 433 if (sc->sc_powerstate == 1) 434 return; 435 436 /* ok, we really need to do something */ 437 dbri_set_power(sc, 1); 438 439 /* 440 * re-initialize the chip but skip all the probing, don't overwrite 441 * any other settings either 442 */ 443 dbri_init(sc); 444 mmcodec_setgain(sc, 1); 445 mmcodec_pipe_init(sc); 446 mmcodec_init_data(sc); 447 mmcodec_setgain(sc, 0); 448 } 449 450 static int 451 dbri_config_interrupts(device_t dev) 452 { 453 struct dbri_softc *sc = device_private(dev); 454 455 mutex_spin_enter(&sc->sc_intr_lock); 456 if (sc->sc_init_done != 0) { 457 mutex_spin_exit(&sc->sc_intr_lock); 458 return 0; 459 } 460 sc->sc_init_done = 1; 461 462 dbri_init(sc); 463 464 /* talking to the codec needs working interrupts */ 465 if (mmcodec_init(sc) == -1) { 466 mutex_spin_exit(&sc->sc_intr_lock); 467 printf("%s: no codec detected, aborting\n", 468 device_xname(dev)); 469 return 0; 470 } 471 mutex_spin_exit(&sc->sc_intr_lock); 472 473 /* Attach ourselves to the high level audio interface */ 474 audio_attach_mi(&dbri_hw_if, sc, sc->sc_dev); 475 476 /* power down until open() */ 477 mutex_spin_enter(&sc->sc_intr_lock); 478 dbri_set_power(sc, 0); 479 mutex_spin_exit(&sc->sc_intr_lock); 480 481 return 0; 482 } 483 484 static int 485 dbri_intr(void *hdl) 486 { 487 struct dbri_softc *sc = hdl; 488 bus_space_tag_t iot = sc->sc_iot; 489 bus_space_handle_t ioh = sc->sc_ioh; 490 int x; 491 492 mutex_spin_enter(&sc->sc_intr_lock); 493 494 /* clear interrupt */ 495 x = bus_space_read_4(iot, ioh, DBRI_REG1); 496 if (x & (DBRI_MRR | DBRI_MLE | DBRI_LBG | DBRI_MBE)) { 497 uint32_t tmp; 498 499 if (x & DBRI_MRR) 500 aprint_debug_dev(sc->sc_dev, 501 "multiple ack error on sbus\n"); 502 if (x & DBRI_MLE) 503 aprint_debug_dev(sc->sc_dev, 504 "multiple late error on sbus\n"); 505 if (x & DBRI_LBG) 506 aprint_debug_dev(sc->sc_dev, 507 "lost bus grant on sbus\n"); 508 if (x & DBRI_MBE) 509 aprint_debug_dev(sc->sc_dev, "burst error on sbus\n"); 510 511 /* 512 * Some of these errors disable the chip's circuitry. 513 * Re-enable the circuitry and keep on going. 514 */ 515 516 tmp = bus_space_read_4(iot, ioh, DBRI_REG0); 517 tmp &= ~(DBRI_DISABLE_MASTER); 518 bus_space_write_4(iot, ioh, DBRI_REG0, tmp); 519 } 520 521 #if 0 522 if (!x & 1) /* XXX: DBRI_INTR_REQ */ 523 return (1); 524 #endif 525 526 dbri_process_interrupt_buffer(sc); 527 528 mutex_spin_exit(&sc->sc_intr_lock); 529 530 return (1); 531 } 532 533 static void 534 dbri_softint(void *cookie) 535 { 536 struct dbri_desc *dd = cookie; 537 538 if (dd->callback != NULL) 539 dd->callback(dd->callback_args); 540 } 541 542 static int 543 dbri_init(struct dbri_softc *sc) 544 { 545 bus_space_tag_t iot = sc->sc_iot; 546 bus_space_handle_t ioh = sc->sc_ioh; 547 uint32_t reg; 548 volatile uint32_t *cmd; 549 bus_addr_t dmaaddr; 550 int n; 551 552 KASSERT(mutex_owned(&sc->sc_intr_lock)); 553 554 dbri_reset(sc); 555 sc->sc_mm.status = 0; 556 557 cmd = dbri_command_lock(sc); 558 559 /* XXX: Initialize interrupt ring buffer */ 560 sc->sc_dma->intr[0] = (uint32_t)sc->sc_dmabase + dbri_dma_off(intr, 0); 561 sc->sc_irqp = 1; 562 563 /* Initialize pipes */ 564 for (n = 0; n < DBRI_PIPE_MAX; n++) 565 sc->sc_pipe[n].desc = sc->sc_pipe[n].next = -1; 566 567 for (n = 1; n < DBRI_INT_BLOCKS; n++) { 568 sc->sc_dma->intr[n] = 0; 569 } 570 571 /* XXX 16 byte bursts cause errors, the rest works */ 572 reg = bus_space_read_4(iot, ioh, DBRI_REG0); 573 574 /*reg &= ~(DBRI_BURST_4 | DBRI_BURST_8 | DBRI_BURST_16);*/ 575 reg |= (DBRI_BURST_4 | DBRI_BURST_8); 576 bus_space_write_4(iot, ioh, DBRI_REG0, reg); 577 578 /* setup interrupt queue */ 579 dmaaddr = (uint32_t)sc->sc_dmabase + dbri_dma_off(intr, 0); 580 *(cmd++) = DBRI_CMD(DBRI_COMMAND_IIQ, 0, 0); 581 *(cmd++) = dmaaddr; 582 583 dbri_command_send(sc, cmd); 584 585 return (0); 586 } 587 588 static int 589 dbri_reset(struct dbri_softc *sc) 590 { 591 int bail = 0; 592 593 bus_space_tag_t iot = sc->sc_iot; 594 bus_space_handle_t ioh = sc->sc_ioh; 595 596 bus_space_write_4(iot, ioh, DBRI_REG0, DBRI_SOFT_RESET); 597 while ((bus_space_read_4(iot, ioh, DBRI_REG0) & DBRI_SOFT_RESET) && 598 (bail < 100000)) { 599 bail++; 600 delay(10); 601 } 602 if (bail == 100000) 603 aprint_error_dev(sc->sc_dev, "reset timed out\n"); 604 return (0); 605 } 606 607 static volatile uint32_t * 608 dbri_command_lock(struct dbri_softc *sc) 609 { 610 611 if (sc->sc_locked) 612 aprint_debug_dev(sc->sc_dev, "command buffer locked\n"); 613 614 sc->sc_locked++; 615 616 return (&sc->sc_dma->command[0]); 617 } 618 619 static void 620 dbri_command_send(struct dbri_softc *sc, volatile uint32_t *cmd) 621 { 622 bus_space_handle_t ioh = sc->sc_ioh; 623 bus_space_tag_t iot = sc->sc_iot; 624 int maxloops = 1000000; 625 626 KASSERT(mutex_owned(&sc->sc_intr_lock)); 627 628 sc->sc_locked--; 629 630 if (sc->sc_locked != 0) { 631 aprint_error_dev(sc->sc_dev, 632 "command buffer improperly locked\n"); 633 } else if ((cmd - &sc->sc_dma->command[0]) >= DBRI_NUM_COMMANDS - 1) { 634 aprint_error_dev(sc->sc_dev, "command buffer overflow\n"); 635 } else { 636 *(cmd++) = DBRI_CMD(DBRI_COMMAND_PAUSE, 0, 0); 637 *(cmd++) = DBRI_CMD(DBRI_COMMAND_WAIT, 1, 0); 638 sc->sc_waitseen = 0; 639 bus_space_write_4(iot, ioh, DBRI_REG8, sc->sc_dmabase); 640 while ((--maxloops) > 0 && 641 (bus_space_read_4(iot, ioh, DBRI_REG0) 642 & DBRI_COMMAND_VALID)) { 643 bus_space_barrier(iot, ioh, DBRI_REG0, 4, 644 BUS_SPACE_BARRIER_READ); 645 delay(1000); 646 } 647 648 if (maxloops == 0) { 649 aprint_error_dev(sc->sc_dev, 650 "chip never completed command buffer\n"); 651 } else { 652 653 DPRINTF("%s: command completed\n", 654 device_xname(sc->sc_dev)); 655 656 while ((--maxloops) > 0 && (!sc->sc_waitseen)) 657 dbri_process_interrupt_buffer(sc); 658 if (maxloops == 0) { 659 aprint_error_dev(sc->sc_dev, "chip never acked WAIT\n"); 660 } 661 } 662 } 663 664 return; 665 } 666 667 static void 668 dbri_process_interrupt_buffer(struct dbri_softc *sc) 669 { 670 int32_t i; 671 int orig_irqp = sc->sc_irqp; 672 673 KASSERT(mutex_owned(&sc->sc_intr_lock)); 674 675 while ((i = sc->sc_dma->intr[sc->sc_irqp]) != 0) { 676 sc->sc_dma->intr[sc->sc_irqp] = 0; 677 sc->sc_irqp++; 678 679 if (sc->sc_irqp == DBRI_INT_BLOCKS) 680 sc->sc_irqp = 1; 681 else if ((sc->sc_irqp & (DBRI_INT_BLOCKS - 1)) == 0) 682 sc->sc_irqp++; 683 684 dbri_process_interrupt(sc, i); 685 686 /* don't loop more than once. */ 687 if (orig_irqp == sc->sc_irqp) 688 break; 689 } 690 691 return; 692 } 693 694 static void 695 dbri_process_interrupt(struct dbri_softc *sc, int32_t i) 696 { 697 #if 0 698 const int liu_states[] = { 1, 0, 8, 3, 4, 5, 6, 7 }; 699 #endif 700 int val = DBRI_INTR_GETVAL(i); 701 int channel = DBRI_INTR_GETCHAN(i); 702 int command = DBRI_INTR_GETCMD(i); 703 int code = DBRI_INTR_GETCODE(i); 704 #if 0 705 int rval = DBRI_INTR_GETRVAL(i); 706 #endif 707 if (channel == DBRI_INTR_CMD && command == DBRI_COMMAND_WAIT) 708 sc->sc_waitseen++; 709 710 switch (code) { 711 case DBRI_INTR_XCMP: /* transmission complete */ 712 { 713 int td; 714 struct dbri_desc *dd; 715 716 DPRINTF("%s:%d tx complete\n", __func__, channel); 717 td = sc->sc_pipe[channel].desc; 718 dd = &sc->sc_desc[td]; 719 720 if (dd->callback != NULL) 721 softint_schedule(dd->softint); 722 break; 723 } 724 case DBRI_INTR_FXDT: /* fixed data change */ 725 DPRINTF("%s:%d: Fixed data change: %x\n", __func__, channel, 726 val); 727 if (sc->sc_pipe[channel].sdp & DBRI_SDP_MSB) 728 val = reverse_bytes(val, sc->sc_pipe[channel].length); 729 if (sc->sc_pipe[channel].prec) 730 *(sc->sc_pipe[channel].prec) = val; 731 #ifndef DBRI_SPIN 732 DPRINTF("%s: cv_broadcast %p\n", device_xname(sc->sc_dev), sc); 733 cv_broadcast(&sc->sc_cv); 734 #endif 735 break; 736 case DBRI_INTR_SBRI: 737 DPRINTF("dbri_intr: SBRI\n"); 738 break; 739 case DBRI_INTR_BRDY: 740 { 741 int td; 742 struct dbri_desc *dd; 743 744 DPRINTF("dbri_intr: buffer ready (%d)\n", channel); 745 td = sc->sc_pipe[channel].desc; 746 dd = &sc->sc_desc[td]; 747 748 if (dd->callback != NULL) 749 softint_schedule(dd->softint); 750 break; 751 } 752 case DBRI_INTR_UNDR: 753 { 754 volatile uint32_t *cmd; 755 int td = sc->sc_pipe[channel].desc; 756 757 DPRINTF("%s: DBRI_INTR_UNDR\n", device_xname(sc->sc_dev)); 758 759 sc->sc_dma->xmit[td].status = 0; 760 761 cmd = dbri_command_lock(sc); 762 *(cmd++) = DBRI_CMD(DBRI_COMMAND_SDP, 0, 763 sc->sc_pipe[channel].sdp | 764 DBRI_SDP_VALID_POINTER | 765 DBRI_SDP_CLEAR | 766 DBRI_SDP_2SAME); 767 *(cmd++) = sc->sc_dmabase + dbri_dma_off(xmit, td); 768 dbri_command_send(sc, cmd); 769 break; 770 } 771 case DBRI_INTR_CMDI: 772 DPRINTF("ok"); 773 break; 774 default: 775 776 aprint_error_dev(sc->sc_dev, "unknown interrupt code %d\n", 777 code); 778 break; 779 } 780 781 return; 782 } 783 784 /* 785 * mmcodec stuff 786 */ 787 788 static int 789 mmcodec_init(struct dbri_softc *sc) 790 { 791 bus_space_handle_t ioh = sc->sc_ioh; 792 bus_space_tag_t iot = sc->sc_iot; 793 uint32_t reg2; 794 int bail; 795 796 reg2 = bus_space_read_4(iot, ioh, DBRI_REG2); 797 DPRINTF("mmcodec_init: PIO reads %x\n", reg2); 798 799 if (reg2 & DBRI_PIO2) { 800 aprint_normal_dev(sc->sc_dev, " onboard CS4215 detected\n"); 801 sc->sc_mm.onboard = 1; 802 } 803 804 if (reg2 & DBRI_PIO0) { 805 aprint_normal_dev(sc->sc_dev, "speakerbox detected\n"); 806 bus_space_write_4(iot, ioh, DBRI_REG2, DBRI_PIO2_ENABLE); 807 sc->sc_mm.onboard = 0; 808 } 809 810 if ((reg2 & DBRI_PIO2) && (reg2 & DBRI_PIO0)) { 811 aprint_normal_dev(sc->sc_dev, "using speakerbox\n"); 812 bus_space_write_4(iot, ioh, DBRI_REG2, DBRI_PIO2_ENABLE); 813 sc->sc_mm.onboard = 0; 814 } 815 816 if (!(reg2 & (DBRI_PIO0|DBRI_PIO2))) { 817 aprint_normal_dev(sc->sc_dev, "no mmcodec found\n"); 818 return -1; 819 } 820 821 sc->sc_version = 0xff; 822 823 mmcodec_pipe_init(sc); 824 mmcodec_default(sc); 825 826 sc->sc_mm.offset = sc->sc_mm.onboard ? 0 : 8; 827 828 /* 829 * mmcodec_setcontrol() sometimes fails right after powerup 830 * so we just try again until we either get a useful response or run 831 * out of time 832 */ 833 bail = 0; 834 while (mmcodec_setcontrol(sc) == -1 || sc->sc_version == 0xff) { 835 836 bail++; 837 if (bail > 100) { 838 DPRINTF("%s: cs4215 probe failed at offset %d\n", 839 device_xname(sc->sc_dev), sc->sc_mm.offset); 840 return (-1); 841 } 842 delay(10000); 843 } 844 845 aprint_normal_dev(sc->sc_dev, "cs4215 rev %c found at offset %d\n", 846 0x43 + (sc->sc_version & 0xf), sc->sc_mm.offset); 847 848 /* set some sane defaults for mmcodec_init_data */ 849 sc->sc_params.channels = 2; 850 sc->sc_params.precision = 16; 851 852 mmcodec_init_data(sc); 853 854 return (0); 855 } 856 857 static void 858 mmcodec_init_data(struct dbri_softc *sc) 859 { 860 bus_space_tag_t iot = sc->sc_iot; 861 bus_space_handle_t ioh = sc->sc_ioh; 862 uint32_t tmp; 863 int data_width; 864 865 tmp = bus_space_read_4(iot, ioh, DBRI_REG0); 866 tmp &= ~(DBRI_CHI_ACTIVATE); /* disable CHI */ 867 bus_space_write_4(iot, ioh, DBRI_REG0, tmp); 868 869 /* switch CS4215 to data mode - set PIO3 to 1 */ 870 tmp = DBRI_PIO_ENABLE_ALL | DBRI_PIO1 | DBRI_PIO3; 871 872 /* XXX */ 873 tmp |= (sc->sc_mm.onboard ? DBRI_PIO0 : DBRI_PIO2); 874 875 bus_space_write_4(iot, ioh, DBRI_REG2, tmp); 876 chi_reset(sc, CHIslave, 128); 877 878 data_width = sc->sc_params.channels * sc->sc_params.precision; 879 880 if ((data_width != 32) && (data_width != 8)) 881 aprint_error("%s: data_width is %d\n", __func__, data_width); 882 883 pipe_ts_link(sc, 20, PIPEoutput, 16, 32, sc->sc_mm.offset + 32); 884 pipe_ts_link(sc, 4, PIPEoutput, 16, data_width, sc->sc_mm.offset); 885 pipe_ts_link(sc, 6, PIPEinput, 16, data_width, sc->sc_mm.offset); 886 #if 0 887 /* readback for the mixer registers - we don't use that */ 888 pipe_ts_link(sc, 21, PIPEinput, 16, 32, sc->sc_mm.offset + 32); 889 890 pipe_receive_fixed(sc, 21, &sc->sc_mm.d.ldata); 891 #endif 892 mmcodec_setgain(sc, 0); 893 894 tmp = bus_space_read_4(iot, ioh, DBRI_REG0); 895 tmp |= DBRI_CHI_ACTIVATE; 896 bus_space_write_4(iot, ioh, DBRI_REG0, tmp); 897 898 return; 899 } 900 901 static void 902 mmcodec_pipe_init(struct dbri_softc *sc) 903 { 904 905 pipe_setup(sc, 4, DBRI_SDP_MEM | DBRI_SDP_TO_SER | DBRI_SDP_MSB); 906 pipe_setup(sc, 20, DBRI_SDP_FIXED | DBRI_SDP_TO_SER | DBRI_SDP_MSB); 907 pipe_setup(sc, 6, DBRI_SDP_MEM | DBRI_SDP_FROM_SER | DBRI_SDP_MSB); 908 #if 0 909 pipe_setup(sc, 21, DBRI_SDP_FIXED | DBRI_SDP_FROM_SER | DBRI_SDP_MSB); 910 #endif 911 pipe_setup(sc, 17, DBRI_SDP_FIXED | DBRI_SDP_TO_SER | DBRI_SDP_MSB); 912 pipe_setup(sc, 18, DBRI_SDP_FIXED | DBRI_SDP_FROM_SER | DBRI_SDP_MSB); 913 pipe_setup(sc, 19, DBRI_SDP_FIXED | DBRI_SDP_FROM_SER | DBRI_SDP_MSB); 914 915 pipe_receive_fixed(sc, 18, &sc->sc_mm.status); 916 pipe_receive_fixed(sc, 19, &sc->sc_mm.version); 917 918 return; 919 } 920 921 static void 922 mmcodec_default(struct dbri_softc *sc) 923 { 924 struct cs4215_state *mm = &sc->sc_mm; 925 926 /* 927 * no action, memory resetting only 928 * 929 * data time slots 5-8 930 * speaker, line and headphone enable. set gain to half. 931 * input is line 932 */ 933 mm->d.bdata[0] = sc->sc_latt = 0x20 | CS4215_HE | CS4215_LE; 934 mm->d.bdata[1] = sc->sc_ratt = 0x20 | CS4215_SE; 935 sc->sc_linp = 128; 936 sc->sc_rinp = 128; 937 sc->sc_monitor = 0; 938 sc->sc_input = 1; /* line */ 939 mm->d.bdata[2] = (CS4215_LG((sc->sc_linp >> 4)) & 0x0f) | 940 ((sc->sc_input == 2) ? CS4215_IS : 0) | CS4215_PIO0 | CS4215_PIO1; 941 mm->d.bdata[3] = (CS4215_RG((sc->sc_rinp >> 4) & 0x0f)) | 942 CS4215_MA(15 - ((sc->sc_monitor >> 4) & 0x0f)); 943 944 945 /* 946 * control time slots 1-4 947 * 948 * 0: default I/O voltage scale 949 * 1: 8 bit ulaw, 8kHz, mono, high pass filter disabled 950 * 2: serial enable, CHI master, 128 bits per frame, clock 1 951 * 3: tests disabled 952 */ 953 mm->c.bcontrol[0] = CS4215_ONE | CS4215_MLB; 954 mm->c.bcontrol[1] = CS4215_DFR_ULAW | CS4215_FREQ[0].csval; 955 mm->c.bcontrol[2] = CS4215_XCLK | CS4215_BSEL_128 | CS4215_FREQ[0].xtal; 956 mm->c.bcontrol[3] = 0; 957 958 return; 959 } 960 961 static void 962 mmcodec_setgain(struct dbri_softc *sc, int mute) 963 { 964 if (mute) { 965 /* disable all outputs, max. attenuation */ 966 sc->sc_mm.d.bdata[0] = sc->sc_latt | 63; 967 sc->sc_mm.d.bdata[1] = sc->sc_ratt | 63; 968 } else { 969 970 sc->sc_mm.d.bdata[0] = sc->sc_latt; 971 sc->sc_mm.d.bdata[1] = sc->sc_ratt; 972 } 973 974 /* input stuff */ 975 sc->sc_mm.d.bdata[2] = CS4215_LG((sc->sc_linp >> 4) & 0x0f) | 976 ((sc->sc_input == 2) ? CS4215_IS : 0) | CS4215_PIO0 | CS4215_PIO1; 977 sc->sc_mm.d.bdata[3] = (CS4215_RG((sc->sc_rinp >> 4)) & 0x0f) | 978 (CS4215_MA(15 - ((sc->sc_monitor >> 4) & 0x0f))); 979 980 if (sc->sc_powerstate == 0) 981 return; 982 pipe_transmit_fixed(sc, 20, sc->sc_mm.d.ldata); 983 984 DPRINTF("mmcodec_setgain: %08x\n", sc->sc_mm.d.ldata); 985 /* give the chip some time to execute the command */ 986 delay(250); 987 988 return; 989 } 990 991 static int 992 mmcodec_setcontrol(struct dbri_softc *sc) 993 { 994 bus_space_tag_t iot = sc->sc_iot; 995 bus_space_handle_t ioh = sc->sc_ioh; 996 uint32_t val; 997 uint32_t tmp; 998 int ret = 0; 999 #ifdef DBRI_SPIN 1000 int i; 1001 #else 1002 int error, bail = 0; 1003 #endif 1004 1005 KASSERT(mutex_owned(&sc->sc_intr_lock)); 1006 1007 /* 1008 * Temporarily mute outputs and wait 125 us to make sure that it 1009 * happens. This avoids clicking noises. 1010 */ 1011 mmcodec_setgain(sc, 1); 1012 delay(125); 1013 1014 tmp = bus_space_read_4(iot, ioh, DBRI_REG0); 1015 tmp &= ~(DBRI_CHI_ACTIVATE); /* disable CHI */ 1016 bus_space_write_4(iot, ioh, DBRI_REG0, tmp); 1017 1018 bus_space_write_4(iot, ioh, DBRI_REG2, 0); 1019 delay(125); 1020 1021 /* enable control mode */ 1022 val = DBRI_PIO_ENABLE_ALL | DBRI_PIO1; /* was PIO1 */ 1023 1024 /* XXX */ 1025 val |= (sc->sc_mm.onboard ? DBRI_PIO0 : DBRI_PIO2); 1026 1027 bus_space_write_4(iot, ioh, DBRI_REG2, val); 1028 delay(34); 1029 1030 /* 1031 * in control mode, the cs4215 is the slave device, so the 1032 * DBRI must act as the CHI master. 1033 * 1034 * in data mode, the cs4215 must be the CHI master to insure 1035 * that the data stream is in sync with its codec 1036 */ 1037 tmp = bus_space_read_4(iot, ioh, DBRI_REG0); 1038 tmp &= ~DBRI_COMMAND_CHI; 1039 bus_space_write_4(iot, ioh, DBRI_REG0, tmp); 1040 1041 chi_reset(sc, CHImaster, 128); 1042 1043 /* control mode */ 1044 pipe_ts_link(sc, 17, PIPEoutput, 16, 32, sc->sc_mm.offset); 1045 pipe_ts_link(sc, 18, PIPEinput, 16, 8, sc->sc_mm.offset); 1046 pipe_ts_link(sc, 19, PIPEinput, 16, 8, sc->sc_mm.offset + 48); 1047 1048 pipe_receive_fixed(sc, 18, &sc->sc_mm.status); 1049 1050 /* wait for the chip to echo back CLB as zero */ 1051 sc->sc_mm.c.bcontrol[0] &= ~CS4215_CLB; 1052 pipe_transmit_fixed(sc, 17, sc->sc_mm.c.lcontrol); 1053 1054 tmp = bus_space_read_4(iot, ioh, DBRI_REG0); 1055 tmp |= DBRI_CHI_ACTIVATE; 1056 bus_space_write_4(iot, ioh, DBRI_REG0, tmp); 1057 1058 #ifdef DBRI_SPIN 1059 i = 1024; 1060 while (((sc->sc_mm.status & 0xe4) != CS4215_ONE) && (i > 0)) { 1061 i--; 1062 delay(125); 1063 } 1064 1065 if (i == 0) { 1066 DPRINTF("%s: cs4215 didn't respond to CLB (0x%02x)\n", 1067 device_xname(sc->sc_dev), sc->sc_mm.status); 1068 ret = -1; 1069 goto fail; 1070 } 1071 #else 1072 while (((sc->sc_mm.status & 0xe4) != CS4215_ONE) && (bail < 10)) { 1073 DPRINTF("%s: cv_wait_sig %p\n", device_xname(sc->sc_dev), sc); 1074 error = cv_timedwait_sig(&sc->sc_cv, &sc->sc_intr_lock, hz); 1075 if (error == EINTR) { 1076 DPRINTF("%s: interrupted\n", device_xname(sc->sc_dev)); 1077 ret = -1; 1078 mutex_spin_exit(&sc->sc_intr_lock); 1079 goto fail; 1080 } 1081 bail++; 1082 } 1083 if (bail >= 10) { 1084 aprint_error("%s: switching to control mode timed out (%x %x)\n", 1085 device_xname(sc->sc_dev), sc->sc_mm.status, 1086 bus_space_read_4(iot, ioh, DBRI_REG2)); 1087 ret = -1; 1088 goto fail; 1089 } 1090 #endif 1091 1092 /* copy the version information before it becomes unreadable again */ 1093 sc->sc_version = sc->sc_mm.version; 1094 sc->sc_whack_codec = 0; 1095 1096 fail: 1097 /* terminate cs4215 control mode */ 1098 sc->sc_mm.c.bcontrol[0] |= CS4215_CLB; 1099 pipe_transmit_fixed(sc, 17, sc->sc_mm.c.lcontrol); 1100 1101 /* two frames of control info @ 8kHz frame rate = 250us delay */ 1102 delay(250); 1103 1104 mmcodec_setgain(sc, 0); 1105 1106 return ret; 1107 1108 } 1109 1110 /* 1111 * CHI combo 1112 */ 1113 static void 1114 chi_reset(struct dbri_softc *sc, enum ms ms, int bpf) 1115 { 1116 volatile uint32_t *cmd; 1117 int val; 1118 int clockrate, divisor; 1119 1120 cmd = dbri_command_lock(sc); 1121 1122 /* set CHI anchor: pipe 16 */ 1123 val = DBRI_DTS_VI | DBRI_DTS_INS | DBRI_DTS_PRVIN(16) | DBRI_PIPE(16); 1124 *(cmd++) = DBRI_CMD(DBRI_COMMAND_DTS, 0, val); 1125 *(cmd++) = DBRI_TS_ANCHOR | DBRI_TS_NEXT(16); 1126 *(cmd++) = 0; 1127 1128 val = DBRI_DTS_VO | DBRI_DTS_INS | DBRI_DTS_PRVOUT(16) | DBRI_PIPE(16); 1129 *(cmd++) = DBRI_CMD(DBRI_COMMAND_DTS, 0, val); 1130 *(cmd++) = 0; 1131 *(cmd++) = DBRI_TS_ANCHOR | DBRI_TS_NEXT(16); 1132 1133 sc->sc_pipe[16].sdp = 1; 1134 sc->sc_pipe[16].next = 16; 1135 sc->sc_chi_pipe_in = 16; 1136 sc->sc_chi_pipe_out = 16; 1137 1138 switch (ms) { 1139 case CHIslave: 1140 *(cmd++) = DBRI_CMD(DBRI_COMMAND_CHI, 0, DBRI_CHI_CHICM(0)); 1141 break; 1142 case CHImaster: 1143 clockrate = bpf * 8; 1144 divisor = 12288 / clockrate; 1145 1146 if (divisor > 255 || divisor * clockrate != 12288) 1147 aprint_error_dev(sc->sc_dev, 1148 "illegal bits-per-frame %d\n", bpf); 1149 1150 *(cmd++) = DBRI_CMD(DBRI_COMMAND_CHI, 0, 1151 DBRI_CHI_CHICM(divisor) | DBRI_CHI_FD | DBRI_CHI_BPF(bpf)); 1152 break; 1153 default: 1154 aprint_error_dev(sc->sc_dev, "unknown value for ms!\n"); 1155 break; 1156 } 1157 1158 sc->sc_chi_bpf = bpf; 1159 1160 /* CHI data mode */ 1161 *(cmd++) = DBRI_CMD(DBRI_COMMAND_PAUSE, 0, 0); 1162 *(cmd++) = DBRI_CMD(DBRI_COMMAND_CDM, 0, 1163 DBRI_CDM_XCE | DBRI_CDM_XEN | DBRI_CDM_REN); 1164 1165 dbri_command_send(sc, cmd); 1166 1167 return; 1168 } 1169 1170 /* 1171 * pipe stuff 1172 */ 1173 static void 1174 pipe_setup(struct dbri_softc *sc, int pipe, int sdp) 1175 { 1176 DPRINTF("pipe setup: %d\n", pipe); 1177 if (pipe < 0 || pipe >= DBRI_PIPE_MAX) { 1178 aprint_error_dev(sc->sc_dev, "illegal pipe number %d\n", 1179 pipe); 1180 return; 1181 } 1182 1183 if ((sdp & 0xf800) != sdp) 1184 aprint_error_dev(sc->sc_dev, "strange SDP value %d\n", 1185 sdp); 1186 1187 if (DBRI_SDP_MODE(sdp) == DBRI_SDP_FIXED && 1188 !(sdp & DBRI_SDP_TO_SER)) 1189 sdp |= DBRI_SDP_CHANGE; 1190 1191 sdp |= DBRI_PIPE(pipe); 1192 1193 sc->sc_pipe[pipe].sdp = sdp; 1194 sc->sc_pipe[pipe].desc = -1; 1195 1196 pipe_reset(sc, pipe); 1197 1198 return; 1199 } 1200 1201 static void 1202 pipe_reset(struct dbri_softc *sc, int pipe) 1203 { 1204 struct dbri_desc *dd; 1205 int sdp; 1206 int desc; 1207 volatile uint32_t *cmd; 1208 1209 if (pipe < 0 || pipe >= DBRI_PIPE_MAX) { 1210 aprint_error_dev(sc->sc_dev, "illegal pipe number %d\n", 1211 pipe); 1212 return; 1213 } 1214 1215 sdp = sc->sc_pipe[pipe].sdp; 1216 if (sdp == 0) { 1217 aprint_error_dev(sc->sc_dev, "can not reset uninitialized pipe %d\n", 1218 pipe); 1219 return; 1220 } 1221 1222 cmd = dbri_command_lock(sc); 1223 *(cmd++) = DBRI_CMD(DBRI_COMMAND_SDP, 0, 1224 sdp | DBRI_SDP_CLEAR | DBRI_SDP_VALID_POINTER); 1225 *(cmd++) = 0; 1226 dbri_command_send(sc, cmd); 1227 1228 desc = sc->sc_pipe[pipe].desc; 1229 1230 dd = &sc->sc_desc[desc]; 1231 1232 dd->busy = 0; 1233 1234 #if 0 1235 if (dd->callback) 1236 softint_schedule(dd->softint); 1237 #endif 1238 1239 sc->sc_pipe[pipe].desc = -1; 1240 1241 return; 1242 } 1243 1244 static void 1245 pipe_receive_fixed(struct dbri_softc *sc, int pipe, volatile uint32_t *prec) 1246 { 1247 1248 if (pipe < DBRI_PIPE_MAX / 2 || pipe >= DBRI_PIPE_MAX) { 1249 aprint_error_dev(sc->sc_dev, "illegal pipe number %d\n", 1250 pipe); 1251 return; 1252 } 1253 1254 if (DBRI_SDP_MODE(sc->sc_pipe[pipe].sdp) != DBRI_SDP_FIXED) { 1255 aprint_error_dev(sc->sc_dev, "non-fixed pipe %d\n", 1256 pipe); 1257 return; 1258 } 1259 1260 if (sc->sc_pipe[pipe].sdp & DBRI_SDP_TO_SER) { 1261 aprint_error_dev(sc->sc_dev, "can not receive on transmit pipe %d\b", 1262 pipe); 1263 return; 1264 } 1265 1266 sc->sc_pipe[pipe].prec = prec; 1267 1268 return; 1269 } 1270 1271 static void 1272 pipe_transmit_fixed(struct dbri_softc *sc, int pipe, uint32_t data) 1273 { 1274 volatile uint32_t *cmd; 1275 1276 if (pipe < DBRI_PIPE_MAX / 2 || pipe >= DBRI_PIPE_MAX) { 1277 aprint_error_dev(sc->sc_dev, "illegal pipe number %d\n", 1278 pipe); 1279 return; 1280 } 1281 1282 if (DBRI_SDP_MODE(sc->sc_pipe[pipe].sdp) == 0) { 1283 aprint_error_dev(sc->sc_dev, "uninitialized pipe %d\n", 1284 pipe); 1285 return; 1286 } 1287 1288 if (DBRI_SDP_MODE(sc->sc_pipe[pipe].sdp) != DBRI_SDP_FIXED) { 1289 aprint_error_dev(sc->sc_dev, "non-fixed pipe %d\n", 1290 pipe); 1291 return; 1292 } 1293 1294 if (!(sc->sc_pipe[pipe].sdp & DBRI_SDP_TO_SER)) { 1295 aprint_error_dev(sc->sc_dev, "called on receive pipe %d\n", 1296 pipe); 1297 return; 1298 } 1299 1300 if (sc->sc_pipe[pipe].sdp & DBRI_SDP_MSB) 1301 data = reverse_bytes(data, sc->sc_pipe[pipe].length); 1302 1303 cmd = dbri_command_lock(sc); 1304 *(cmd++) = DBRI_CMD(DBRI_COMMAND_SSP, 0, pipe); 1305 *(cmd++) = data; 1306 1307 dbri_command_send(sc, cmd); 1308 1309 return; 1310 } 1311 1312 static void 1313 setup_ring_xmit(struct dbri_softc *sc, int pipe, int which, int num, int blksz, 1314 void (*callback)(void *), void *callback_args) 1315 { 1316 volatile uint32_t *cmd; 1317 int i; 1318 #if 0 1319 int td; 1320 int td_first, td_last; 1321 #endif 1322 bus_addr_t dmabuf, dmabase; 1323 struct dbri_desc *dd = &sc->sc_desc[which]; 1324 1325 switch (pipe) { 1326 case 4: 1327 /* output, offset 0 */ 1328 break; 1329 default: 1330 aprint_error("%s: illegal pipe number (%d)\n", 1331 __func__, pipe); 1332 return; 1333 } 1334 1335 #if 0 1336 td = 0; 1337 td_first = td_last = -1; 1338 #endif 1339 1340 if (sc->sc_pipe[pipe].sdp == 0) { 1341 aprint_error_dev(sc->sc_dev, "uninitialized pipe %d\n", 1342 pipe); 1343 return; 1344 } 1345 1346 dmabuf = dd->dmabase; 1347 dmabase = sc->sc_dmabase; 1348 1349 for (i = 0; i < (num - 1); i++) { 1350 1351 sc->sc_dma->xmit[i].flags = TX_BCNT(blksz) 1352 | TX_EOF | TX_BINT; 1353 sc->sc_dma->xmit[i].ba = dmabuf; 1354 sc->sc_dma->xmit[i].nda = dmabase + dbri_dma_off(xmit, i + 1); 1355 sc->sc_dma->xmit[i].status = 0; 1356 1357 #if 0 1358 td_last = td; 1359 #endif 1360 dmabuf += blksz; 1361 } 1362 1363 sc->sc_dma->xmit[i].flags = TX_BCNT(blksz) | TX_EOF | TX_BINT; 1364 1365 sc->sc_dma->xmit[i].ba = dmabuf; 1366 sc->sc_dma->xmit[i].nda = dmabase + dbri_dma_off(xmit, 0); 1367 sc->sc_dma->xmit[i].status = 0; 1368 1369 dd->callback = callback; 1370 dd->callback_args = callback_args; 1371 1372 /* the pipe shouldn't be active */ 1373 if (pipe_active(sc, pipe)) { 1374 aprint_error("pipe active (CDP)\n"); 1375 /* pipe is already active */ 1376 #if 0 1377 td_last = sc->sc_pipe[pipe].desc; 1378 while (sc->sc_desc[td_last].next != -1) 1379 td_last = sc->sc_desc[td_last].next; 1380 1381 sc->sc_desc[td_last].next = td_first; 1382 sc->sc_dma->desc[td_last].nda = 1383 sc->sc_dmabase + dbri_dma_off(desc, td_first); 1384 1385 cmd = dbri_command_lock(sc); 1386 *(cmd++) = DBRI_CMD(DBRI_COMMAND_CDP, 0, pipe); 1387 dbri_command_send(sc, cmd); 1388 #endif 1389 } else { 1390 /* 1391 * pipe isn't active - issue an SDP command to start our 1392 * chain of TDs running 1393 */ 1394 sc->sc_pipe[pipe].desc = which; 1395 cmd = dbri_command_lock(sc); 1396 *(cmd++) = DBRI_CMD(DBRI_COMMAND_SDP, 0, 1397 sc->sc_pipe[pipe].sdp | 1398 DBRI_SDP_VALID_POINTER | 1399 DBRI_SDP_EVERY | 1400 DBRI_SDP_CLEAR); 1401 *(cmd++) = sc->sc_dmabase + dbri_dma_off(xmit, 0); 1402 dbri_command_send(sc, cmd); 1403 DPRINTF("%s: starting DMA\n", __func__); 1404 } 1405 1406 return; 1407 } 1408 1409 static void 1410 setup_ring_recv(struct dbri_softc *sc, int pipe, int which, int num, int blksz, 1411 void (*callback)(void *), void *callback_args) 1412 { 1413 volatile uint32_t *cmd; 1414 int i; 1415 #if 0 1416 int td_first, td_last; 1417 #endif 1418 bus_addr_t dmabuf, dmabase; 1419 struct dbri_desc *dd = &sc->sc_desc[which]; 1420 1421 switch (pipe) { 1422 case 6: 1423 break; 1424 default: 1425 aprint_error("%s: illegal pipe number (%d)\n", 1426 __func__, pipe); 1427 return; 1428 } 1429 1430 #if 0 1431 td_first = td_last = -1; 1432 #endif 1433 1434 if (sc->sc_pipe[pipe].sdp == 0) { 1435 aprint_error_dev(sc->sc_dev, "uninitialized pipe %d\n", 1436 pipe); 1437 return; 1438 } 1439 1440 dmabuf = dd->dmabase; 1441 dmabase = sc->sc_dmabase; 1442 1443 for (i = 0; i < (num - 1); i++) { 1444 1445 sc->sc_dma->recv[i].flags = RX_BSIZE(blksz) | RX_FINAL; 1446 sc->sc_dma->recv[i].ba = dmabuf; 1447 sc->sc_dma->recv[i].nda = dmabase + dbri_dma_off(recv, i + 1); 1448 sc->sc_dma->recv[i].status = RX_EOF; 1449 1450 #if 0 1451 td_last = i; 1452 #endif 1453 dmabuf += blksz; 1454 } 1455 1456 sc->sc_dma->recv[i].flags = RX_BSIZE(blksz) | RX_FINAL; 1457 1458 sc->sc_dma->recv[i].ba = dmabuf; 1459 sc->sc_dma->recv[i].nda = dmabase + dbri_dma_off(recv, 0); 1460 sc->sc_dma->recv[i].status = RX_EOF; 1461 1462 dd->callback = callback; 1463 dd->callback_args = callback_args; 1464 1465 /* the pipe shouldn't be active */ 1466 if (pipe_active(sc, pipe)) { 1467 aprint_error("pipe active (CDP)\n"); 1468 /* pipe is already active */ 1469 #if 0 1470 td_last = sc->sc_pipe[pipe].desc; 1471 while (sc->sc_desc[td_last].next != -1) 1472 td_last = sc->sc_desc[td_last].next; 1473 1474 sc->sc_desc[td_last].next = td_first; 1475 sc->sc_dma->desc[td_last].nda = 1476 sc->sc_dmabase + dbri_dma_off(desc, td_first); 1477 1478 cmd = dbri_command_lock(sc); 1479 *(cmd++) = DBRI_CMD(DBRI_COMMAND_CDP, 0, pipe); 1480 dbri_command_send(sc, cmd); 1481 #endif 1482 } else { 1483 /* 1484 * pipe isn't active - issue an SDP command to start our 1485 * chain of TDs running 1486 */ 1487 sc->sc_pipe[pipe].desc = which; 1488 cmd = dbri_command_lock(sc); 1489 *(cmd++) = DBRI_CMD(DBRI_COMMAND_SDP, 0, 1490 sc->sc_pipe[pipe].sdp | 1491 DBRI_SDP_VALID_POINTER | 1492 DBRI_SDP_EVERY | 1493 DBRI_SDP_CLEAR); 1494 *(cmd++) = sc->sc_dmabase + dbri_dma_off(recv, 0); 1495 dbri_command_send(sc, cmd); 1496 DPRINTF("%s: starting DMA\n", __func__); 1497 } 1498 1499 return; 1500 } 1501 1502 static void 1503 pipe_ts_link(struct dbri_softc *sc, int pipe, enum io dir, int basepipe, 1504 int len, int cycle) 1505 { 1506 volatile uint32_t *cmd; 1507 int prevpipe, nextpipe; 1508 int val; 1509 1510 DPRINTF("%s: %d\n", __func__, pipe); 1511 if (pipe < 0 || pipe >= DBRI_PIPE_MAX || 1512 basepipe < 0 || basepipe >= DBRI_PIPE_MAX) { 1513 aprint_error_dev(sc->sc_dev, "illegal pipe numbers (%d, %d)\n", 1514 pipe, basepipe); 1515 return; 1516 } 1517 1518 if (sc->sc_pipe[pipe].sdp == 0 || sc->sc_pipe[basepipe].sdp == 0) { 1519 aprint_error_dev(sc->sc_dev, "uninitialized pipe (%d, %d)\n", 1520 pipe, basepipe); 1521 return; 1522 } 1523 1524 if (basepipe == 16 && dir == PIPEoutput && cycle == 0) 1525 cycle = sc->sc_chi_bpf; 1526 1527 if (basepipe == pipe) 1528 prevpipe = nextpipe = pipe; 1529 else { 1530 if (basepipe == 16) { 1531 if (dir == PIPEinput) { 1532 prevpipe = sc->sc_chi_pipe_in; 1533 } else { 1534 prevpipe = sc->sc_chi_pipe_out; 1535 } 1536 } else 1537 prevpipe = basepipe; 1538 1539 nextpipe = sc->sc_pipe[prevpipe].next; 1540 1541 while (sc->sc_pipe[nextpipe].cycle < cycle && 1542 sc->sc_pipe[nextpipe].next != basepipe) { 1543 prevpipe = nextpipe; 1544 nextpipe = sc->sc_pipe[nextpipe].next; 1545 } 1546 } 1547 1548 if (prevpipe == 16) { 1549 if (dir == PIPEinput) { 1550 sc->sc_chi_pipe_in = pipe; 1551 } else { 1552 sc->sc_chi_pipe_out = pipe; 1553 } 1554 } else 1555 sc->sc_pipe[prevpipe].next = pipe; 1556 1557 sc->sc_pipe[pipe].next = nextpipe; 1558 sc->sc_pipe[pipe].cycle = cycle; 1559 sc->sc_pipe[pipe].length = len; 1560 1561 cmd = dbri_command_lock(sc); 1562 1563 switch (dir) { 1564 case PIPEinput: 1565 val = DBRI_DTS_VI | DBRI_DTS_INS | DBRI_DTS_PRVIN(prevpipe); 1566 val |= pipe; 1567 *(cmd++) = DBRI_CMD(DBRI_COMMAND_DTS, 0, val); 1568 *(cmd++) = DBRI_TS_LEN(len) | DBRI_TS_CYCLE(cycle) | 1569 DBRI_TS_NEXT(nextpipe); 1570 *(cmd++) = 0; 1571 break; 1572 case PIPEoutput: 1573 val = DBRI_DTS_VO | DBRI_DTS_INS | DBRI_DTS_PRVOUT(prevpipe); 1574 val |= pipe; 1575 *(cmd++) = DBRI_CMD(DBRI_COMMAND_DTS, 0, val); 1576 *(cmd++) = 0; 1577 *(cmd++) = DBRI_TS_LEN(len) | DBRI_TS_CYCLE(cycle) | 1578 DBRI_TS_NEXT(nextpipe); 1579 break; 1580 default: 1581 DPRINTF("%s: should not have happened!\n", 1582 device_xname(sc->sc_dev)); 1583 break; 1584 } 1585 1586 dbri_command_send(sc, cmd); 1587 1588 return; 1589 } 1590 1591 static int 1592 pipe_active(struct dbri_softc *sc, int pipe) 1593 { 1594 1595 return (sc->sc_pipe[pipe].desc != -1); 1596 } 1597 1598 /* 1599 * subroutines required to interface with audio(9) 1600 */ 1601 1602 static int 1603 dbri_query_encoding(void *hdl, struct audio_encoding *ae) 1604 { 1605 1606 switch (ae->index) { 1607 case 0: 1608 strcpy(ae->name, AudioEulinear); 1609 ae->encoding = AUDIO_ENCODING_ULINEAR; 1610 ae->precision = 8; 1611 ae->flags = 0; 1612 break; 1613 case 1: 1614 strcpy(ae->name, AudioEmulaw); 1615 ae->encoding = AUDIO_ENCODING_ULAW; 1616 ae->precision = 8; 1617 ae->flags = 0; 1618 break; 1619 case 2: 1620 strcpy(ae->name, AudioEalaw); 1621 ae->encoding = AUDIO_ENCODING_ALAW; 1622 ae->precision = 8; 1623 ae->flags = 0; 1624 break; 1625 case 3: 1626 strcpy(ae->name, AudioEslinear); 1627 ae->encoding = AUDIO_ENCODING_SLINEAR; 1628 ae->precision = 8; 1629 ae->flags = AUDIO_ENCODINGFLAG_EMULATED; 1630 break; 1631 case 4: 1632 strcpy(ae->name, AudioEslinear_le); 1633 ae->encoding = AUDIO_ENCODING_SLINEAR_LE; 1634 ae->precision = 16; 1635 ae->flags = AUDIO_ENCODINGFLAG_EMULATED; 1636 break; 1637 case 5: 1638 strcpy(ae->name, AudioEulinear_le); 1639 ae->encoding = AUDIO_ENCODING_ULINEAR_LE; 1640 ae->precision = 16; 1641 ae->flags = AUDIO_ENCODINGFLAG_EMULATED; 1642 break; 1643 case 6: 1644 strcpy(ae->name, AudioEslinear_be); 1645 ae->encoding = AUDIO_ENCODING_SLINEAR_BE; 1646 ae->precision = 16; 1647 ae->flags = 0; 1648 break; 1649 case 7: 1650 strcpy(ae->name, AudioEulinear_be); 1651 ae->encoding = AUDIO_ENCODING_ULINEAR_BE; 1652 ae->precision = 16; 1653 ae->flags = AUDIO_ENCODINGFLAG_EMULATED; 1654 break; 1655 case 8: 1656 strcpy(ae->name, AudioEslinear); 1657 ae->encoding = AUDIO_ENCODING_SLINEAR; 1658 ae->precision = 16; 1659 ae->flags = 0; 1660 break; 1661 default: 1662 return (EINVAL); 1663 } 1664 1665 return (0); 1666 } 1667 1668 static int 1669 dbri_set_params(void *hdl, int setmode, int usemode, 1670 struct audio_params *play, struct audio_params *rec, 1671 stream_filter_list_t *pfil, stream_filter_list_t *rfil) 1672 { 1673 struct dbri_softc *sc = hdl; 1674 int rate; 1675 audio_params_t *p = NULL; 1676 stream_filter_list_t *fil; 1677 int mode; 1678 1679 /* 1680 * This device only has one clock, so make the sample rates match. 1681 */ 1682 if (play->sample_rate != rec->sample_rate && 1683 usemode == (AUMODE_PLAY | AUMODE_RECORD)) { 1684 if (setmode == AUMODE_PLAY) { 1685 rec->sample_rate = play->sample_rate; 1686 setmode |= AUMODE_RECORD; 1687 } else if (setmode == AUMODE_RECORD) { 1688 play->sample_rate = rec->sample_rate; 1689 setmode |= AUMODE_PLAY; 1690 } else 1691 return EINVAL; 1692 } 1693 1694 for (mode = AUMODE_RECORD; mode != -1; 1695 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) { 1696 if ((setmode & mode) == 0) 1697 continue; 1698 1699 p = mode == AUMODE_PLAY ? play : rec; 1700 if (p->sample_rate < 4000 || p->sample_rate > 50000) { 1701 DPRINTF("dbri_set_params: invalid rate %d\n", 1702 p->sample_rate); 1703 return EINVAL; 1704 } 1705 1706 fil = mode == AUMODE_PLAY ? pfil : rfil; 1707 DPRINTF("requested enc: %d rate: %d prec: %d chan: %d\n", p->encoding, 1708 p->sample_rate, p->precision, p->channels); 1709 if (auconv_set_converter(dbri_formats, DBRI_NFORMATS, 1710 mode, p, true, fil) < 0) { 1711 aprint_debug("dbri_set_params: auconv_set_converter failed\n"); 1712 return EINVAL; 1713 } 1714 if (fil->req_size > 0) 1715 p = &fil->filters[0].param; 1716 } 1717 1718 if (p == NULL) { 1719 DPRINTF("dbri_set_params: no parameters to set\n"); 1720 return 0; 1721 } 1722 1723 DPRINTF("native enc: %d rate: %d prec: %d chan: %d\n", p->encoding, 1724 p->sample_rate, p->precision, p->channels); 1725 1726 for (rate = 0; CS4215_FREQ[rate].freq; rate++) 1727 if (CS4215_FREQ[rate].freq == p->sample_rate) 1728 break; 1729 1730 if (CS4215_FREQ[rate].freq == 0) 1731 return (EINVAL); 1732 1733 /* set frequency */ 1734 sc->sc_mm.c.bcontrol[1] &= ~0x38; 1735 sc->sc_mm.c.bcontrol[1] |= CS4215_FREQ[rate].csval; 1736 sc->sc_mm.c.bcontrol[2] &= ~0x70; 1737 sc->sc_mm.c.bcontrol[2] |= CS4215_FREQ[rate].xtal; 1738 1739 switch (p->encoding) { 1740 case AUDIO_ENCODING_ULAW: 1741 sc->sc_mm.c.bcontrol[1] &= ~3; 1742 sc->sc_mm.c.bcontrol[1] |= CS4215_DFR_ULAW; 1743 break; 1744 case AUDIO_ENCODING_ALAW: 1745 sc->sc_mm.c.bcontrol[1] &= ~3; 1746 sc->sc_mm.c.bcontrol[1] |= CS4215_DFR_ALAW; 1747 break; 1748 case AUDIO_ENCODING_ULINEAR: 1749 sc->sc_mm.c.bcontrol[1] &= ~3; 1750 if (p->precision == 8) { 1751 sc->sc_mm.c.bcontrol[1] |= CS4215_DFR_LINEAR8; 1752 } else { 1753 sc->sc_mm.c.bcontrol[1] |= CS4215_DFR_LINEAR16; 1754 } 1755 break; 1756 case AUDIO_ENCODING_SLINEAR_BE: 1757 case AUDIO_ENCODING_SLINEAR: 1758 sc->sc_mm.c.bcontrol[1] &= ~3; 1759 sc->sc_mm.c.bcontrol[1] |= CS4215_DFR_LINEAR16; 1760 break; 1761 } 1762 1763 switch (p->channels) { 1764 case 1: 1765 sc->sc_mm.c.bcontrol[1] &= ~CS4215_DFR_STEREO; 1766 break; 1767 case 2: 1768 sc->sc_mm.c.bcontrol[1] |= CS4215_DFR_STEREO; 1769 break; 1770 } 1771 sc->sc_whack_codec = 1; 1772 return (0); 1773 } 1774 1775 static int 1776 dbri_round_blocksize(void *hdl, int bs, int mode, 1777 const audio_params_t *param) 1778 { 1779 1780 /* 1781 * DBRI DMA segment size can be up to 0x1fff, sixes that are not powers 1782 * of two seem to confuse the upper audio layer so we're going with 1783 * 0x1000 here 1784 */ 1785 return 0x1000; 1786 } 1787 1788 static int 1789 dbri_halt_output(void *hdl) 1790 { 1791 struct dbri_softc *sc = hdl; 1792 1793 if (!sc->sc_playing) 1794 return 0; 1795 1796 sc->sc_playing = 0; 1797 pipe_reset(sc, 4); 1798 return (0); 1799 } 1800 1801 static int 1802 dbri_getdev(void *hdl, struct audio_device *ret) 1803 { 1804 1805 *ret = dbri_device; 1806 return (0); 1807 } 1808 1809 static int 1810 dbri_set_port(void *hdl, mixer_ctrl_t *mc) 1811 { 1812 struct dbri_softc *sc = hdl; 1813 int latt = sc->sc_latt, ratt = sc->sc_ratt; 1814 1815 switch (mc->dev) { 1816 case DBRI_VOL_OUTPUT: /* master volume */ 1817 latt = (latt & 0xc0) | (63 - 1818 min(mc->un.value.level[AUDIO_MIXER_LEVEL_LEFT] >> 2, 63)); 1819 ratt = (ratt & 0xc0) | (63 - 1820 min(mc->un.value.level[AUDIO_MIXER_LEVEL_RIGHT] >> 2, 63)); 1821 break; 1822 case DBRI_ENABLE_MONO: /* built-in speaker */ 1823 if (mc->un.ord == 1) { 1824 ratt |= CS4215_SE; 1825 } else 1826 ratt &= ~CS4215_SE; 1827 break; 1828 case DBRI_ENABLE_HEADPHONE: /* headphones output */ 1829 if (mc->un.ord == 1) { 1830 latt |= CS4215_HE; 1831 } else 1832 latt &= ~CS4215_HE; 1833 break; 1834 case DBRI_ENABLE_LINE: /* line out */ 1835 if (mc->un.ord == 1) { 1836 latt |= CS4215_LE; 1837 } else 1838 latt &= ~CS4215_LE; 1839 break; 1840 case DBRI_VOL_MONITOR: 1841 if (mc->un.value.level[AUDIO_MIXER_LEVEL_LEFT] == 1842 sc->sc_monitor) 1843 return 0; 1844 sc->sc_monitor = mc->un.value.level[AUDIO_MIXER_LEVEL_LEFT]; 1845 break; 1846 case DBRI_INPUT_GAIN: 1847 sc->sc_linp = mc->un.value.level[AUDIO_MIXER_LEVEL_LEFT]; 1848 sc->sc_rinp = mc->un.value.level[AUDIO_MIXER_LEVEL_RIGHT]; 1849 break; 1850 case DBRI_INPUT_SELECT: 1851 if (mc->un.mask == sc->sc_input) 1852 return 0; 1853 sc->sc_input = mc->un.mask; 1854 break; 1855 } 1856 1857 sc->sc_latt = latt; 1858 sc->sc_ratt = ratt; 1859 1860 mmcodec_setgain(sc, 0); 1861 1862 return (0); 1863 } 1864 1865 static int 1866 dbri_get_port(void *hdl, mixer_ctrl_t *mc) 1867 { 1868 struct dbri_softc *sc = hdl; 1869 1870 switch (mc->dev) { 1871 case DBRI_VOL_OUTPUT: /* master volume */ 1872 mc->un.value.level[AUDIO_MIXER_LEVEL_LEFT] = 1873 (63 - (sc->sc_latt & 0x3f)) << 2; 1874 mc->un.value.level[AUDIO_MIXER_LEVEL_RIGHT] = 1875 (63 - (sc->sc_ratt & 0x3f)) << 2; 1876 return (0); 1877 case DBRI_ENABLE_MONO: /* built-in speaker */ 1878 mc->un.ord = (sc->sc_ratt & CS4215_SE) ? 1 : 0; 1879 return 0; 1880 case DBRI_ENABLE_HEADPHONE: /* headphones output */ 1881 mc->un.ord = (sc->sc_latt & CS4215_HE) ? 1 : 0; 1882 return 0; 1883 case DBRI_ENABLE_LINE: /* line out */ 1884 mc->un.ord = (sc->sc_latt & CS4215_LE) ? 1 : 0; 1885 return 0; 1886 case DBRI_VOL_MONITOR: 1887 mc->un.value.level[AUDIO_MIXER_LEVEL_LEFT] = sc->sc_monitor; 1888 return 0; 1889 case DBRI_INPUT_GAIN: 1890 mc->un.value.level[AUDIO_MIXER_LEVEL_LEFT] = sc->sc_linp; 1891 mc->un.value.level[AUDIO_MIXER_LEVEL_RIGHT] = sc->sc_rinp; 1892 return 0; 1893 case DBRI_INPUT_SELECT: 1894 mc->un.mask = sc->sc_input; 1895 return 0; 1896 } 1897 return (EINVAL); 1898 } 1899 1900 static int 1901 dbri_query_devinfo(void *hdl, mixer_devinfo_t *di) 1902 { 1903 1904 switch (di->index) { 1905 case DBRI_MONITOR_CLASS: 1906 di->mixer_class = DBRI_MONITOR_CLASS; 1907 strcpy(di->label.name, AudioCmonitor); 1908 di->type = AUDIO_MIXER_CLASS; 1909 di->next = di->prev = AUDIO_MIXER_LAST; 1910 return 0; 1911 case DBRI_OUTPUT_CLASS: 1912 di->mixer_class = DBRI_OUTPUT_CLASS; 1913 strcpy(di->label.name, AudioCoutputs); 1914 di->type = AUDIO_MIXER_CLASS; 1915 di->next = di->prev = AUDIO_MIXER_LAST; 1916 return 0; 1917 case DBRI_INPUT_CLASS: 1918 di->mixer_class = DBRI_INPUT_CLASS; 1919 strcpy(di->label.name, AudioCinputs); 1920 di->type = AUDIO_MIXER_CLASS; 1921 di->next = di->prev = AUDIO_MIXER_LAST; 1922 return 0; 1923 case DBRI_VOL_OUTPUT: /* master volume */ 1924 di->mixer_class = DBRI_OUTPUT_CLASS; 1925 di->next = di->prev = AUDIO_MIXER_LAST; 1926 strcpy(di->label.name, AudioNmaster); 1927 di->type = AUDIO_MIXER_VALUE; 1928 di->un.v.num_channels = 2; 1929 di->un.v.delta = 16; 1930 strcpy(di->un.v.units.name, AudioNvolume); 1931 return (0); 1932 case DBRI_INPUT_GAIN: /* input gain */ 1933 di->mixer_class = DBRI_INPUT_CLASS; 1934 di->next = di->prev = AUDIO_MIXER_LAST; 1935 strcpy(di->label.name, AudioNrecord); 1936 di->type = AUDIO_MIXER_VALUE; 1937 di->un.v.num_channels = 2; 1938 strcpy(di->un.v.units.name, AudioNvolume); 1939 return (0); 1940 case DBRI_VOL_MONITOR: /* monitor volume */ 1941 di->mixer_class = DBRI_MONITOR_CLASS; 1942 di->next = di->prev = AUDIO_MIXER_LAST; 1943 strcpy(di->label.name, AudioNmonitor); 1944 di->type = AUDIO_MIXER_VALUE; 1945 di->un.v.num_channels = 1; 1946 strcpy(di->un.v.units.name, AudioNvolume); 1947 return (0); 1948 case DBRI_ENABLE_MONO: /* built-in speaker */ 1949 di->mixer_class = DBRI_OUTPUT_CLASS; 1950 di->next = di->prev = AUDIO_MIXER_LAST; 1951 strcpy(di->label.name, AudioNmono); 1952 di->type = AUDIO_MIXER_ENUM; 1953 di->un.e.num_mem = 2; 1954 strcpy(di->un.e.member[0].label.name, AudioNoff); 1955 di->un.e.member[0].ord = 0; 1956 strcpy(di->un.e.member[1].label.name, AudioNon); 1957 di->un.e.member[1].ord = 1; 1958 return (0); 1959 case DBRI_ENABLE_HEADPHONE: /* headphones output */ 1960 di->mixer_class = DBRI_OUTPUT_CLASS; 1961 di->next = di->prev = AUDIO_MIXER_LAST; 1962 strcpy(di->label.name, AudioNheadphone); 1963 di->type = AUDIO_MIXER_ENUM; 1964 di->un.e.num_mem = 2; 1965 strcpy(di->un.e.member[0].label.name, AudioNoff); 1966 di->un.e.member[0].ord = 0; 1967 strcpy(di->un.e.member[1].label.name, AudioNon); 1968 di->un.e.member[1].ord = 1; 1969 return (0); 1970 case DBRI_ENABLE_LINE: /* line out */ 1971 di->mixer_class = DBRI_OUTPUT_CLASS; 1972 di->next = di->prev = AUDIO_MIXER_LAST; 1973 strcpy(di->label.name, AudioNline); 1974 di->type = AUDIO_MIXER_ENUM; 1975 di->un.e.num_mem = 2; 1976 strcpy(di->un.e.member[0].label.name, AudioNoff); 1977 di->un.e.member[0].ord = 0; 1978 strcpy(di->un.e.member[1].label.name, AudioNon); 1979 di->un.e.member[1].ord = 1; 1980 return (0); 1981 case DBRI_INPUT_SELECT: 1982 di->mixer_class = DBRI_INPUT_CLASS; 1983 strcpy(di->label.name, AudioNsource); 1984 di->type = AUDIO_MIXER_SET; 1985 di->prev = di->next = AUDIO_MIXER_LAST; 1986 di->un.s.num_mem = 2; 1987 strcpy(di->un.s.member[0].label.name, AudioNline); 1988 di->un.s.member[0].mask = 1 << 0; 1989 strcpy(di->un.s.member[1].label.name, AudioNmicrophone); 1990 di->un.s.member[1].mask = 1 << 1; 1991 return 0; 1992 } 1993 1994 return (ENXIO); 1995 } 1996 1997 static size_t 1998 dbri_round_buffersize(void *hdl, int dir, size_t bufsize) 1999 { 2000 #ifdef DBRI_BIG_BUFFER 2001 return 0x20000; /* use 128KB buffer */ 2002 #else 2003 return bufsize; 2004 #endif 2005 } 2006 2007 static int 2008 dbri_get_props(void *hdl) 2009 { 2010 2011 return AUDIO_PROP_MMAP | AUDIO_PROP_FULLDUPLEX; 2012 } 2013 2014 static int 2015 dbri_commit(void *hdl) 2016 { 2017 struct dbri_softc *sc = hdl; 2018 int ret = 0; 2019 2020 /* 2021 * we only need to whack the codec if things like sample format or 2022 * frequency changed, not for mixer stuff 2023 */ 2024 if (sc->sc_whack_codec == 0) 2025 return 0; 2026 2027 mutex_spin_enter(&sc->sc_intr_lock); 2028 ret = mmcodec_setcontrol(sc); 2029 if (ret) { 2030 DPRINTF("%s: control mode failed. Mutex %s PIL %x\n", __func__, 2031 mutex_owned(&sc->sc_intr_lock) ? "held" : "free", 2032 (getpsr() & PSR_PIL) >> 8); 2033 } else 2034 DPRINTF("%s: control mode ok\n", __func__); 2035 mmcodec_init_data(sc); 2036 mutex_spin_exit(&sc->sc_intr_lock); 2037 return 0; 2038 } 2039 2040 static int 2041 dbri_trigger_output(void *hdl, void *start, void *end, int blksize, 2042 void (*intr)(void *), void *intrarg, 2043 const struct audio_params *param) 2044 { 2045 struct dbri_softc *sc = hdl; 2046 unsigned long count, num; 2047 2048 if (sc->sc_playing) 2049 return 0; 2050 2051 count = (unsigned long)(((char *)end - (char *)start)); 2052 num = count / blksize; 2053 2054 DPRINTF("trigger_output(%lx %lx) : %d %ld %ld\n", 2055 (unsigned long)intr, 2056 (unsigned long)intrarg, blksize, count, num); 2057 2058 sc->sc_params = *param; 2059 2060 /* 2061 * always use DMA descriptor 0 for output 2062 * no need to allocate them dynamically since we only ever have 2063 * exactly one input stream and exactly one output stream 2064 */ 2065 setup_ring_xmit(sc, 4, 0, num, blksize, intr, intrarg); 2066 sc->sc_playing = 1; 2067 return 0; 2068 } 2069 2070 static int 2071 dbri_halt_input(void *cookie) 2072 { 2073 struct dbri_softc *sc = cookie; 2074 2075 if (!sc->sc_recording) 2076 return 0; 2077 2078 sc->sc_recording = 0; 2079 pipe_reset(sc, 6); 2080 return 0; 2081 } 2082 2083 static int 2084 dbri_trigger_input(void *hdl, void *start, void *end, int blksize, 2085 void (*intr)(void *), void *intrarg, 2086 const struct audio_params *param) 2087 { 2088 struct dbri_softc *sc = hdl; 2089 unsigned long count, num; 2090 2091 if (sc->sc_recording) 2092 return 0; 2093 2094 count = (unsigned long)(((char *)end - (char *)start)); 2095 num = count / blksize; 2096 2097 DPRINTF("trigger_input(%lx %lx) : %d %ld %ld\n", 2098 (unsigned long)intr, 2099 (unsigned long)intrarg, blksize, count, num); 2100 2101 sc->sc_params = *param; 2102 2103 sc->sc_recording = 1; 2104 setup_ring_recv(sc, 6, 1, num, blksize, intr, intrarg); 2105 return 0; 2106 } 2107 2108 static void 2109 dbri_get_locks(void *opaque, kmutex_t **intr, kmutex_t **thread) 2110 { 2111 struct dbri_softc *sc = opaque; 2112 2113 *intr = &sc->sc_intr_lock; 2114 *thread = &sc->sc_lock; 2115 } 2116 2117 static uint32_t 2118 reverse_bytes(uint32_t b, int len) 2119 { 2120 switch (len) { 2121 case 32: 2122 b = ((b & 0xffff0000) >> 16) | ((b & 0x0000ffff) << 16); 2123 case 16: 2124 b = ((b & 0xff00ff00) >> 8) | ((b & 0x00ff00ff) << 8); 2125 case 8: 2126 b = ((b & 0xf0f0f0f0) >> 4) | ((b & 0x0f0f0f0f) << 4); 2127 case 4: 2128 b = ((b & 0xcccccccc) >> 2) | ((b & 0x33333333) << 2); 2129 case 2: 2130 b = ((b & 0xaaaaaaaa) >> 1) | ((b & 0x55555555) << 1); 2131 case 1: 2132 case 0: 2133 break; 2134 default: 2135 DPRINTF("reverse_bytes: unsupported length\n"); 2136 }; 2137 2138 return (b); 2139 } 2140 2141 static void * 2142 dbri_malloc(void *v, int dir, size_t s) 2143 { 2144 struct dbri_softc *sc = v; 2145 struct dbri_desc *dd = &sc->sc_desc[sc->sc_desc_used]; 2146 int rseg; 2147 2148 if (bus_dmamap_create(sc->sc_dmat, s, 1, s, 0, BUS_DMA_NOWAIT, 2149 &dd->dmamap) == 0) { 2150 if (bus_dmamem_alloc(sc->sc_dmat, s, 0, 0, &dd->dmaseg, 2151 1, &rseg, BUS_DMA_NOWAIT) == 0) { 2152 if (bus_dmamem_map(sc->sc_dmat, &dd->dmaseg, rseg, s, 2153 &dd->buf, BUS_DMA_NOWAIT|BUS_DMA_COHERENT) == 0) { 2154 if (dd->buf != NULL) { 2155 if (bus_dmamap_load(sc->sc_dmat, 2156 dd->dmamap, dd->buf, s, NULL, 2157 BUS_DMA_NOWAIT) == 0) { 2158 dd->len = s; 2159 dd->busy = 0; 2160 dd->callback = NULL; 2161 dd->dmabase = 2162 dd->dmamap->dm_segs[0].ds_addr; 2163 DPRINTF("dbri_malloc: using buffer %d %08x\n", 2164 sc->sc_desc_used, (uint32_t)dd->buf); 2165 sc->sc_desc_used++; 2166 return dd->buf; 2167 } else 2168 aprint_error("dbri_malloc: load failed\n"); 2169 } else 2170 aprint_error("dbri_malloc: map returned NULL\n"); 2171 } else 2172 aprint_error("dbri_malloc: map failed\n"); 2173 bus_dmamem_free(sc->sc_dmat, &dd->dmaseg, rseg); 2174 } else 2175 aprint_error("dbri_malloc: malloc() failed\n"); 2176 bus_dmamap_destroy(sc->sc_dmat, dd->dmamap); 2177 } else 2178 aprint_error("dbri_malloc: bus_dmamap_create() failed\n"); 2179 return NULL; 2180 } 2181 2182 static void 2183 dbri_free(void *v, void *p, size_t size) 2184 { 2185 struct dbri_softc *sc = v; 2186 struct dbri_desc *dd; 2187 int i; 2188 2189 for (i = 0; i < sc->sc_desc_used; i++) { 2190 dd = &sc->sc_desc[i]; 2191 if (dd->buf == p) 2192 break; 2193 } 2194 if (i >= sc->sc_desc_used) 2195 return; 2196 bus_dmamap_unload(sc->sc_dmat, dd->dmamap); 2197 bus_dmamap_destroy(sc->sc_dmat, dd->dmamap); 2198 } 2199 2200 static paddr_t 2201 dbri_mappage(void *v, void *mem, off_t off, int prot) 2202 { 2203 struct dbri_softc *sc = v; 2204 int current; 2205 2206 if (off < 0) 2207 return -1; 2208 2209 current = 0; 2210 while ((current < sc->sc_desc_used) && 2211 (sc->sc_desc[current].buf != mem)) 2212 current++; 2213 2214 if (current < sc->sc_desc_used) { 2215 return bus_dmamem_mmap(sc->sc_dmat, 2216 &sc->sc_desc[current].dmaseg, 1, off, prot, BUS_DMA_WAITOK); 2217 } 2218 2219 return -1; 2220 } 2221 2222 static int 2223 dbri_open(void *cookie, int flags) 2224 { 2225 struct dbri_softc *sc = cookie; 2226 2227 DPRINTF("%s: %d\n", __func__, sc->sc_refcount); 2228 2229 if (sc->sc_refcount == 0) { 2230 dbri_bring_up(sc); 2231 } 2232 2233 sc->sc_refcount++; 2234 2235 return 0; 2236 } 2237 2238 static void 2239 dbri_close(void *cookie) 2240 { 2241 struct dbri_softc *sc = cookie; 2242 2243 DPRINTF("%s: %d\n", __func__, sc->sc_refcount); 2244 2245 sc->sc_refcount--; 2246 KASSERT(sc->sc_refcount >= 0); 2247 if (sc->sc_refcount > 0) 2248 return; 2249 2250 dbri_set_power(sc, 0); 2251 sc->sc_playing = 0; 2252 sc->sc_recording = 0; 2253 } 2254 2255 static bool 2256 dbri_suspend(device_t self, const pmf_qual_t *qual) 2257 { 2258 struct dbri_softc *sc = device_private(self); 2259 2260 mutex_spin_enter(&sc->sc_intr_lock); 2261 dbri_set_power(sc, 0); 2262 mutex_spin_exit(&sc->sc_intr_lock); 2263 return true; 2264 } 2265 2266 static bool 2267 dbri_resume(device_t self, const pmf_qual_t *qual) 2268 { 2269 struct dbri_softc *sc = device_private(self); 2270 2271 if (sc->sc_powerstate != 0) 2272 return true; 2273 aprint_verbose("resume: %d\n", sc->sc_refcount); 2274 if (sc->sc_playing) { 2275 volatile uint32_t *cmd; 2276 2277 mutex_spin_enter(&sc->sc_intr_lock); 2278 dbri_bring_up(sc); 2279 cmd = dbri_command_lock(sc); 2280 *(cmd++) = DBRI_CMD(DBRI_COMMAND_SDP, 2281 0, sc->sc_pipe[4].sdp | 2282 DBRI_SDP_VALID_POINTER | 2283 DBRI_SDP_EVERY | DBRI_SDP_CLEAR); 2284 *(cmd++) = sc->sc_dmabase + 2285 dbri_dma_off(xmit, 0); 2286 dbri_command_send(sc, cmd); 2287 mutex_spin_exit(&sc->sc_intr_lock); 2288 } 2289 return true; 2290 } 2291 2292 #endif /* NAUDIO > 0 */ 2293
Indexes created Fri Sep 26 08:10:20 GMT 2025