dbri.c revision 1.41
1 /* $NetBSD: dbri.c,v 1.41 2019/06/08 08:02:38 isaki Exp $ */ 2 3 /* 4 * Copyright (C) 1997 Rudolf Koenig (rfkoenig (at) immd4.informatik.uni-erlangen.de) 5 * Copyright (c) 1998, 1999 Brent Baccala (baccala (at) freesoft.org) 6 * Copyright (c) 2001, 2002 Jared D. McNeill <jmcneill (at) netbsd.org> 7 * Copyright (c) 2005 Michael Lorenz <macallan (at) netbsd.org> 8 * All rights reserved. 9 * 10 * This driver is losely based on a Linux driver written by Rudolf Koenig and 11 * Brent Baccala who kindly gave their permission to use their code in a 12 * BSD-licensed driver. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions 16 * are met: 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in the 21 * documentation and/or other materials provided with the distribution. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 28 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 29 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: dbri.c,v 1.41 2019/06/08 08:02:38 isaki Exp $"); 38 39 #include "audio.h" 40 #if NAUDIO > 0 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/errno.h> 45 #include <sys/device.h> 46 #include <sys/proc.h> 47 #include <sys/kernel.h> 48 #include <sys/bus.h> 49 #include <sys/intr.h> 50 #include <sys/kmem.h> 51 52 #include <dev/sbus/sbusvar.h> 53 #include <sparc/sparc/auxreg.h> 54 #include <machine/autoconf.h> 55 56 #include <sys/audioio.h> 57 #include <dev/audio/audio_if.h> 58 59 #include <dev/ic/cs4215reg.h> 60 #include <dev/ic/cs4215var.h> 61 #include <dev/sbus/dbrireg.h> 62 #include <dev/sbus/dbrivar.h> 63 64 #include "opt_sbus_dbri.h" 65 66 #define DBRI_ROM_NAME_PREFIX "SUNW,DBRI" 67 68 #ifdef DBRI_DEBUG 69 # define DPRINTF aprint_normal 70 #else 71 # define DPRINTF while (0) printf 72 #endif 73 74 static const char *dbri_supported[] = { 75 "e", 76 "s3", 77 "" 78 }; 79 80 enum ms { 81 CHImaster, 82 CHIslave 83 }; 84 85 enum io { 86 PIPEinput, 87 PIPEoutput 88 }; 89 90 /* 91 * Function prototypes 92 */ 93 94 /* softc stuff */ 95 static void dbri_attach_sbus(device_t, device_t, void *); 96 static int dbri_match_sbus(device_t, cfdata_t, void *); 97 98 static int dbri_config_interrupts(device_t); 99 100 /* interrupt handler */ 101 static int dbri_intr(void *); 102 static void dbri_softint(void *); 103 104 /* supporting subroutines */ 105 static int dbri_init(struct dbri_softc *); 106 static int dbri_reset(struct dbri_softc *); 107 static volatile uint32_t *dbri_command_lock(struct dbri_softc *); 108 static void dbri_command_send(struct dbri_softc *, volatile uint32_t *); 109 static void dbri_process_interrupt_buffer(struct dbri_softc *); 110 static void dbri_process_interrupt(struct dbri_softc *, int32_t); 111 112 /* mmcodec subroutines */ 113 static int mmcodec_init(struct dbri_softc *); 114 static void mmcodec_init_data(struct dbri_softc *); 115 static void mmcodec_pipe_init(struct dbri_softc *); 116 static void mmcodec_default(struct dbri_softc *); 117 static void mmcodec_setgain(struct dbri_softc *, int); 118 static int mmcodec_setcontrol(struct dbri_softc *); 119 120 /* chi subroutines */ 121 static void chi_reset(struct dbri_softc *, enum ms, int); 122 123 /* pipe subroutines */ 124 static void pipe_setup(struct dbri_softc *, int, int); 125 static void pipe_reset(struct dbri_softc *, int); 126 static void pipe_receive_fixed(struct dbri_softc *, int, 127 volatile uint32_t *); 128 static void pipe_transmit_fixed(struct dbri_softc *, int, uint32_t); 129 130 static void pipe_ts_link(struct dbri_softc *, int, enum io, int, int, int); 131 static int pipe_active(struct dbri_softc *, int); 132 133 /* audio(9) stuff */ 134 static int dbri_query_format(void *, audio_format_query_t *); 135 static int dbri_set_format(void *, int, 136 const audio_params_t *, const audio_params_t *, 137 audio_filter_reg_t *, audio_filter_reg_t *); 138 static int dbri_round_blocksize(void *, int, int, const audio_params_t *); 139 static int dbri_halt_output(void *); 140 static int dbri_halt_input(void *); 141 static int dbri_getdev(void *, struct audio_device *); 142 static int dbri_set_port(void *, mixer_ctrl_t *); 143 static int dbri_get_port(void *, mixer_ctrl_t *); 144 static int dbri_query_devinfo(void *, mixer_devinfo_t *); 145 static int dbri_get_props(void *); 146 static int dbri_open(void *, int); 147 static void dbri_close(void *); 148 149 static void setup_ring_xmit(struct dbri_softc *, int, int, int, int, 150 void (*)(void *), void *); 151 static void setup_ring_recv(struct dbri_softc *, int, int, int, int, 152 void (*)(void *), void *); 153 154 static int dbri_trigger_output(void *, void *, void *, int, 155 void (*)(void *), void *, const struct audio_params *); 156 static int dbri_trigger_input(void *, void *, void *, int, 157 void (*)(void *), void *, const struct audio_params *); 158 static void dbri_get_locks(void *, kmutex_t **, kmutex_t **); 159 160 static void *dbri_malloc(void *, int, size_t); 161 static void dbri_free(void *, void *, size_t); 162 static void dbri_set_power(struct dbri_softc *, int); 163 static void dbri_bring_up(struct dbri_softc *); 164 static bool dbri_suspend(device_t, const pmf_qual_t *); 165 static bool dbri_resume(device_t, const pmf_qual_t *); 166 static int dbri_commit(void *); 167 168 /* stupid support routines */ 169 static uint32_t reverse_bytes(uint32_t, int); 170 171 struct audio_device dbri_device = { 172 "CS4215", 173 "", 174 "dbri" 175 }; 176 177 struct audio_hw_if dbri_hw_if = { 178 .open = dbri_open, 179 .close = dbri_close, 180 .query_format = dbri_query_format, 181 .set_format = dbri_set_format, 182 .round_blocksize = dbri_round_blocksize, 183 .halt_output = dbri_halt_output, 184 .halt_input = dbri_halt_input, 185 .getdev = dbri_getdev, 186 .set_port = dbri_set_port, 187 .get_port = dbri_get_port, 188 .query_devinfo = dbri_query_devinfo, 189 .allocm = dbri_malloc, 190 .freem = dbri_free, 191 .get_props = dbri_get_props, 192 .trigger_output = dbri_trigger_output, 193 .trigger_input = dbri_trigger_input, 194 .get_locks = dbri_get_locks, 195 .commit_settings = dbri_commit, 196 }; 197 198 CFATTACH_DECL_NEW(dbri, sizeof(struct dbri_softc), 199 dbri_match_sbus, dbri_attach_sbus, NULL, NULL); 200 201 /* The HW actually supports more encodings/frequencies, but it's enough. */ 202 static const struct audio_format dbri_formats[] = { 203 { 204 .mode = AUMODE_PLAY | AUMODE_RECORD, 205 .encoding = AUDIO_ENCODING_SLINEAR_BE, 206 .validbits = 16, 207 .precision = 16, 208 .channels = 2, 209 .channel_mask = AUFMT_STEREO, 210 .frequency_type = 8, 211 .frequency = 212 { 8000, 9600, 11025, 16000, 22050, 32000, 44100, 48000 }, 213 }, 214 }; 215 #define DBRI_NFORMATS __arraycount(dbri_formats) 216 217 enum { 218 DBRI_OUTPUT_CLASS, 219 DBRI_VOL_OUTPUT, 220 DBRI_ENABLE_MONO, 221 DBRI_ENABLE_HEADPHONE, 222 DBRI_ENABLE_LINE, 223 DBRI_MONITOR_CLASS, 224 DBRI_VOL_MONITOR, 225 DBRI_INPUT_CLASS, 226 DBRI_INPUT_GAIN, 227 DBRI_INPUT_SELECT, 228 DBRI_RECORD_CLASS, 229 DBRI_ENUM_LAST 230 }; 231 232 /* 233 * Autoconfig routines 234 */ 235 static int 236 dbri_match_sbus(device_t parent, cfdata_t match, void *aux) 237 { 238 struct sbus_attach_args *sa = aux; 239 char *ver; 240 int i; 241 242 if (strncmp(DBRI_ROM_NAME_PREFIX, sa->sa_name, 9)) 243 return (0); 244 245 ver = &sa->sa_name[9]; 246 247 for (i = 0; dbri_supported[i][0] != '\0'; i++) 248 if (strcmp(dbri_supported[i], ver) == 0) 249 return (1); 250 251 return (0); 252 } 253 254 static void 255 dbri_attach_sbus(device_t parent, device_t self, void *aux) 256 { 257 struct dbri_softc *sc = device_private(self); 258 struct sbus_attach_args *sa = aux; 259 bus_space_handle_t ioh; 260 bus_size_t size; 261 int error, rseg, pwr, i; 262 char *ver = &sa->sa_name[9]; 263 264 sc->sc_dev = self; 265 sc->sc_iot = sa->sa_bustag; 266 sc->sc_dmat = sa->sa_dmatag; 267 sc->sc_powerstate = 1; 268 269 sc->sc_whack_codec = 0; 270 271 pwr = prom_getpropint(sa->sa_node,"pwr-on-auxio",0); 272 aprint_normal(": rev %s\n", ver); 273 274 if (pwr) { 275 /* 276 * we can control DBRI power via auxio and we're initially 277 * powered down 278 */ 279 280 sc->sc_have_powerctl = 1; 281 sc->sc_powerstate = 0; 282 dbri_set_power(sc, 1); 283 if (!pmf_device_register(self, dbri_suspend, dbri_resume)) { 284 aprint_error_dev(self, 285 "cannot set power mgmt handler\n"); 286 } 287 } else { 288 /* we can't control power so we're always up */ 289 sc->sc_have_powerctl = 0; 290 sc->sc_powerstate = 1; 291 } 292 293 for (i = 0; i < DBRI_NUM_DESCRIPTORS; i++) { 294 sc->sc_desc[i].softint = softint_establish(SOFTINT_SERIAL, 295 dbri_softint, &sc->sc_desc[i]); 296 sc->sc_desc[i].sc = sc; 297 } 298 299 if (sa->sa_npromvaddrs) 300 ioh = (bus_space_handle_t)sa->sa_promvaddrs[0]; 301 else { 302 if (sbus_bus_map(sa->sa_bustag, sa->sa_slot, 303 sa->sa_offset, sa->sa_size, 304 BUS_SPACE_MAP_LINEAR, /*0,*/ &ioh) != 0) { 305 aprint_error("%s @ sbus: cannot map registers\n", 306 device_xname(self)); 307 return; 308 } 309 } 310 311 sc->sc_ioh = ioh; 312 313 size = sizeof(struct dbri_dma); 314 315 /* get a DMA handle */ 316 if ((error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, 317 BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) { 318 aprint_error_dev(self, "DMA map create error %d\n", 319 error); 320 return; 321 } 322 323 /* allocate DMA buffer */ 324 if ((error = bus_dmamem_alloc(sc->sc_dmat, size, 0, 0, &sc->sc_dmaseg, 325 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 326 aprint_error_dev(self, "DMA buffer alloc error %d\n", 327 error); 328 return; 329 } 330 331 /* map DMA buffer into CPU addressable space */ 332 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_dmaseg, rseg, size, 333 &sc->sc_membase, 334 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 335 aprint_error_dev(self, "DMA buffer map error %d\n", 336 error); 337 return; 338 } 339 340 /* load the buffer */ 341 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, 342 sc->sc_membase, size, NULL, 343 BUS_DMA_NOWAIT)) != 0) { 344 aprint_error_dev(self, "DMA buffer map load error %d\n", 345 error); 346 bus_dmamem_unmap(sc->sc_dmat, sc->sc_membase, size); 347 bus_dmamem_free(sc->sc_dmat, &sc->sc_dmaseg, rseg); 348 return; 349 } 350 351 /* map the registers into memory */ 352 353 /* kernel virtual address of DMA buffer */ 354 sc->sc_dma = (struct dbri_dma *)sc->sc_membase; 355 /* physical address of DMA buffer */ 356 sc->sc_dmabase = sc->sc_dmamap->dm_segs[0].ds_addr; 357 sc->sc_bufsiz = size; 358 359 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_NONE); 360 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_AUDIO); 361 362 #ifndef DBRI_SPIN 363 cv_init(&sc->sc_cv, "dbricv"); 364 #endif 365 366 bus_intr_establish(sa->sa_bustag, sa->sa_pri, IPL_AUDIO, dbri_intr, 367 sc); 368 369 sc->sc_locked = 0; 370 sc->sc_desc_used = 0; 371 sc->sc_refcount = 0; 372 sc->sc_playing = 0; 373 sc->sc_recording = 0; 374 sc->sc_init_done = 0; 375 config_finalize_register(self, &dbri_config_interrupts); 376 377 return; 378 } 379 380 /* 381 * lowlevel routine to switch power for the DBRI chip 382 */ 383 static void 384 dbri_set_power(struct dbri_softc *sc, int state) 385 { 386 int s; 387 388 if (sc->sc_have_powerctl == 0) 389 return; 390 if (sc->sc_powerstate == state) 391 return; 392 393 if (state) { 394 DPRINTF("%s: waiting to power up... ", 395 device_xname(sc->sc_dev)); 396 s = splhigh(); 397 *AUXIO4M_REG |= (AUXIO4M_MMX); 398 splx(s); 399 delay(10000); 400 DPRINTF("done (%02x)\n", *AUXIO4M_REG); 401 } else { 402 DPRINTF("%s: powering down\n", device_xname(sc->sc_dev)); 403 s = splhigh(); 404 *AUXIO4M_REG &= ~AUXIO4M_MMX; 405 splx(s); 406 DPRINTF("done (%02x})\n", *AUXIO4M_REG); 407 } 408 sc->sc_powerstate = state; 409 } 410 411 /* 412 * power up and re-initialize the chip 413 */ 414 static void 415 dbri_bring_up(struct dbri_softc *sc) 416 { 417 418 if (sc->sc_have_powerctl == 0) 419 return; 420 421 if (sc->sc_powerstate == 1) 422 return; 423 424 /* ok, we really need to do something */ 425 dbri_set_power(sc, 1); 426 427 /* 428 * re-initialize the chip but skip all the probing, don't overwrite 429 * any other settings either 430 */ 431 dbri_init(sc); 432 mmcodec_setgain(sc, 1); 433 mmcodec_pipe_init(sc); 434 mmcodec_init_data(sc); 435 mmcodec_setgain(sc, 0); 436 } 437 438 static int 439 dbri_config_interrupts(device_t dev) 440 { 441 struct dbri_softc *sc = device_private(dev); 442 443 mutex_spin_enter(&sc->sc_intr_lock); 444 if (sc->sc_init_done != 0) { 445 mutex_spin_exit(&sc->sc_intr_lock); 446 return 0; 447 } 448 sc->sc_init_done = 1; 449 450 dbri_init(sc); 451 452 /* talking to the codec needs working interrupts */ 453 if (mmcodec_init(sc) == -1) { 454 mutex_spin_exit(&sc->sc_intr_lock); 455 printf("%s: no codec detected, aborting\n", 456 device_xname(dev)); 457 return 0; 458 } 459 mutex_spin_exit(&sc->sc_intr_lock); 460 461 /* Attach ourselves to the high level audio interface */ 462 audio_attach_mi(&dbri_hw_if, sc, sc->sc_dev); 463 464 /* power down until open() */ 465 mutex_spin_enter(&sc->sc_intr_lock); 466 dbri_set_power(sc, 0); 467 mutex_spin_exit(&sc->sc_intr_lock); 468 469 return 0; 470 } 471 472 static int 473 dbri_intr(void *hdl) 474 { 475 struct dbri_softc *sc = hdl; 476 bus_space_tag_t iot = sc->sc_iot; 477 bus_space_handle_t ioh = sc->sc_ioh; 478 int x; 479 480 mutex_spin_enter(&sc->sc_intr_lock); 481 482 /* clear interrupt */ 483 x = bus_space_read_4(iot, ioh, DBRI_REG1); 484 if (x & (DBRI_MRR | DBRI_MLE | DBRI_LBG | DBRI_MBE)) { 485 uint32_t tmp; 486 487 if (x & DBRI_MRR) 488 aprint_debug_dev(sc->sc_dev, 489 "multiple ack error on sbus\n"); 490 if (x & DBRI_MLE) 491 aprint_debug_dev(sc->sc_dev, 492 "multiple late error on sbus\n"); 493 if (x & DBRI_LBG) 494 aprint_debug_dev(sc->sc_dev, 495 "lost bus grant on sbus\n"); 496 if (x & DBRI_MBE) 497 aprint_debug_dev(sc->sc_dev, "burst error on sbus\n"); 498 499 /* 500 * Some of these errors disable the chip's circuitry. 501 * Re-enable the circuitry and keep on going. 502 */ 503 504 tmp = bus_space_read_4(iot, ioh, DBRI_REG0); 505 tmp &= ~(DBRI_DISABLE_MASTER); 506 bus_space_write_4(iot, ioh, DBRI_REG0, tmp); 507 } 508 509 #if 0 510 if (!x & 1) /* XXX: DBRI_INTR_REQ */ 511 return (1); 512 #endif 513 514 dbri_process_interrupt_buffer(sc); 515 516 mutex_spin_exit(&sc->sc_intr_lock); 517 518 return (1); 519 } 520 521 static void 522 dbri_softint(void *cookie) 523 { 524 struct dbri_desc *dd = cookie; 525 struct dbri_softc *sc = dd->sc; 526 527 mutex_spin_enter(&sc->sc_intr_lock); 528 if (dd->callback != NULL) 529 dd->callback(dd->callback_args); 530 mutex_spin_exit(&sc->sc_intr_lock); 531 } 532 533 static int 534 dbri_init(struct dbri_softc *sc) 535 { 536 bus_space_tag_t iot = sc->sc_iot; 537 bus_space_handle_t ioh = sc->sc_ioh; 538 uint32_t reg; 539 volatile uint32_t *cmd; 540 bus_addr_t dmaaddr; 541 int n; 542 543 KASSERT(mutex_owned(&sc->sc_intr_lock)); 544 545 dbri_reset(sc); 546 sc->sc_mm.status = 0; 547 548 cmd = dbri_command_lock(sc); 549 550 /* XXX: Initialize interrupt ring buffer */ 551 sc->sc_dma->intr[0] = (uint32_t)sc->sc_dmabase + dbri_dma_off(intr, 0); 552 sc->sc_irqp = 1; 553 554 /* Initialize pipes */ 555 for (n = 0; n < DBRI_PIPE_MAX; n++) 556 sc->sc_pipe[n].desc = sc->sc_pipe[n].next = -1; 557 558 for (n = 1; n < DBRI_INT_BLOCKS; n++) { 559 sc->sc_dma->intr[n] = 0; 560 } 561 562 /* XXX 16 byte bursts cause errors, the rest works */ 563 reg = bus_space_read_4(iot, ioh, DBRI_REG0); 564 565 /*reg &= ~(DBRI_BURST_4 | DBRI_BURST_8 | DBRI_BURST_16);*/ 566 reg |= (DBRI_BURST_4 | DBRI_BURST_8); 567 bus_space_write_4(iot, ioh, DBRI_REG0, reg); 568 569 /* setup interrupt queue */ 570 dmaaddr = (uint32_t)sc->sc_dmabase + dbri_dma_off(intr, 0); 571 *(cmd++) = DBRI_CMD(DBRI_COMMAND_IIQ, 0, 0); 572 *(cmd++) = dmaaddr; 573 574 dbri_command_send(sc, cmd); 575 576 return (0); 577 } 578 579 static int 580 dbri_reset(struct dbri_softc *sc) 581 { 582 int bail = 0; 583 584 bus_space_tag_t iot = sc->sc_iot; 585 bus_space_handle_t ioh = sc->sc_ioh; 586 587 bus_space_write_4(iot, ioh, DBRI_REG0, DBRI_SOFT_RESET); 588 while ((bus_space_read_4(iot, ioh, DBRI_REG0) & DBRI_SOFT_RESET) && 589 (bail < 100000)) { 590 bail++; 591 delay(10); 592 } 593 if (bail == 100000) 594 aprint_error_dev(sc->sc_dev, "reset timed out\n"); 595 return (0); 596 } 597 598 static volatile uint32_t * 599 dbri_command_lock(struct dbri_softc *sc) 600 { 601 602 if (sc->sc_locked) 603 aprint_debug_dev(sc->sc_dev, "command buffer locked\n"); 604 605 sc->sc_locked++; 606 607 return (&sc->sc_dma->command[0]); 608 } 609 610 static void 611 dbri_command_send(struct dbri_softc *sc, volatile uint32_t *cmd) 612 { 613 bus_space_handle_t ioh = sc->sc_ioh; 614 bus_space_tag_t iot = sc->sc_iot; 615 int maxloops = 1000000; 616 617 KASSERT(mutex_owned(&sc->sc_intr_lock)); 618 619 sc->sc_locked--; 620 621 if (sc->sc_locked != 0) { 622 aprint_error_dev(sc->sc_dev, 623 "command buffer improperly locked\n"); 624 } else if ((cmd - &sc->sc_dma->command[0]) >= DBRI_NUM_COMMANDS - 1) { 625 aprint_error_dev(sc->sc_dev, "command buffer overflow\n"); 626 } else { 627 *(cmd++) = DBRI_CMD(DBRI_COMMAND_PAUSE, 0, 0); 628 *(cmd++) = DBRI_CMD(DBRI_COMMAND_WAIT, 1, 0); 629 sc->sc_waitseen = 0; 630 bus_space_write_4(iot, ioh, DBRI_REG8, sc->sc_dmabase); 631 while ((--maxloops) > 0 && 632 (bus_space_read_4(iot, ioh, DBRI_REG0) 633 & DBRI_COMMAND_VALID)) { 634 bus_space_barrier(iot, ioh, DBRI_REG0, 4, 635 BUS_SPACE_BARRIER_READ); 636 delay(1000); 637 } 638 639 if (maxloops == 0) { 640 aprint_error_dev(sc->sc_dev, 641 "chip never completed command buffer\n"); 642 } else { 643 644 DPRINTF("%s: command completed\n", 645 device_xname(sc->sc_dev)); 646 647 while ((--maxloops) > 0 && (!sc->sc_waitseen)) 648 dbri_process_interrupt_buffer(sc); 649 if (maxloops == 0) { 650 aprint_error_dev(sc->sc_dev, "chip never acked WAIT\n"); 651 } 652 } 653 } 654 655 return; 656 } 657 658 static void 659 dbri_process_interrupt_buffer(struct dbri_softc *sc) 660 { 661 int32_t i; 662 int orig_irqp = sc->sc_irqp; 663 664 KASSERT(mutex_owned(&sc->sc_intr_lock)); 665 666 while ((i = sc->sc_dma->intr[sc->sc_irqp]) != 0) { 667 sc->sc_dma->intr[sc->sc_irqp] = 0; 668 sc->sc_irqp++; 669 670 if (sc->sc_irqp == DBRI_INT_BLOCKS) 671 sc->sc_irqp = 1; 672 else if ((sc->sc_irqp & (DBRI_INT_BLOCKS - 1)) == 0) 673 sc->sc_irqp++; 674 675 dbri_process_interrupt(sc, i); 676 677 /* don't loop more than once. */ 678 if (orig_irqp == sc->sc_irqp) 679 break; 680 } 681 682 return; 683 } 684 685 static void 686 dbri_process_interrupt(struct dbri_softc *sc, int32_t i) 687 { 688 #if 0 689 const int liu_states[] = { 1, 0, 8, 3, 4, 5, 6, 7 }; 690 #endif 691 int val = DBRI_INTR_GETVAL(i); 692 int channel = DBRI_INTR_GETCHAN(i); 693 int command = DBRI_INTR_GETCMD(i); 694 int code = DBRI_INTR_GETCODE(i); 695 #if 0 696 int rval = DBRI_INTR_GETRVAL(i); 697 #endif 698 if (channel == DBRI_INTR_CMD && command == DBRI_COMMAND_WAIT) 699 sc->sc_waitseen++; 700 701 switch (code) { 702 case DBRI_INTR_XCMP: /* transmission complete */ 703 { 704 int td; 705 struct dbri_desc *dd; 706 707 DPRINTF("%s:%d tx complete\n", __func__, channel); 708 td = sc->sc_pipe[channel].desc; 709 dd = &sc->sc_desc[td]; 710 711 if (dd->callback != NULL) 712 softint_schedule(dd->softint); 713 break; 714 } 715 case DBRI_INTR_FXDT: /* fixed data change */ 716 DPRINTF("%s:%d: Fixed data change: %x\n", __func__, channel, 717 val); 718 if (sc->sc_pipe[channel].sdp & DBRI_SDP_MSB) 719 val = reverse_bytes(val, sc->sc_pipe[channel].length); 720 if (sc->sc_pipe[channel].prec) 721 *(sc->sc_pipe[channel].prec) = val; 722 #ifndef DBRI_SPIN 723 DPRINTF("%s: cv_broadcast %p\n", device_xname(sc->sc_dev), sc); 724 cv_broadcast(&sc->sc_cv); 725 #endif 726 break; 727 case DBRI_INTR_SBRI: 728 DPRINTF("dbri_intr: SBRI\n"); 729 break; 730 case DBRI_INTR_BRDY: 731 { 732 int td; 733 struct dbri_desc *dd; 734 735 DPRINTF("dbri_intr: buffer ready (%d)\n", channel); 736 td = sc->sc_pipe[channel].desc; 737 dd = &sc->sc_desc[td]; 738 739 if (dd->callback != NULL) 740 softint_schedule(dd->softint); 741 break; 742 } 743 case DBRI_INTR_UNDR: 744 { 745 volatile uint32_t *cmd; 746 int td = sc->sc_pipe[channel].desc; 747 748 DPRINTF("%s: DBRI_INTR_UNDR\n", device_xname(sc->sc_dev)); 749 750 sc->sc_dma->xmit[td].status = 0; 751 752 cmd = dbri_command_lock(sc); 753 *(cmd++) = DBRI_CMD(DBRI_COMMAND_SDP, 0, 754 sc->sc_pipe[channel].sdp | 755 DBRI_SDP_VALID_POINTER | 756 DBRI_SDP_CLEAR | 757 DBRI_SDP_2SAME); 758 *(cmd++) = sc->sc_dmabase + dbri_dma_off(xmit, td); 759 dbri_command_send(sc, cmd); 760 break; 761 } 762 case DBRI_INTR_CMDI: 763 DPRINTF("ok"); 764 break; 765 default: 766 767 aprint_error_dev(sc->sc_dev, "unknown interrupt code %d\n", 768 code); 769 break; 770 } 771 772 return; 773 } 774 775 /* 776 * mmcodec stuff 777 */ 778 779 static int 780 mmcodec_init(struct dbri_softc *sc) 781 { 782 bus_space_handle_t ioh = sc->sc_ioh; 783 bus_space_tag_t iot = sc->sc_iot; 784 uint32_t reg2; 785 int bail; 786 787 reg2 = bus_space_read_4(iot, ioh, DBRI_REG2); 788 DPRINTF("mmcodec_init: PIO reads %x\n", reg2); 789 790 if (reg2 & DBRI_PIO2) { 791 aprint_normal_dev(sc->sc_dev, " onboard CS4215 detected\n"); 792 sc->sc_mm.onboard = 1; 793 } 794 795 if (reg2 & DBRI_PIO0) { 796 aprint_normal_dev(sc->sc_dev, "speakerbox detected\n"); 797 bus_space_write_4(iot, ioh, DBRI_REG2, DBRI_PIO2_ENABLE); 798 sc->sc_mm.onboard = 0; 799 } 800 801 if ((reg2 & DBRI_PIO2) && (reg2 & DBRI_PIO0)) { 802 aprint_normal_dev(sc->sc_dev, "using speakerbox\n"); 803 bus_space_write_4(iot, ioh, DBRI_REG2, DBRI_PIO2_ENABLE); 804 sc->sc_mm.onboard = 0; 805 } 806 807 if (!(reg2 & (DBRI_PIO0|DBRI_PIO2))) { 808 aprint_normal_dev(sc->sc_dev, "no mmcodec found\n"); 809 return -1; 810 } 811 812 sc->sc_version = 0xff; 813 814 mmcodec_pipe_init(sc); 815 mmcodec_default(sc); 816 817 sc->sc_mm.offset = sc->sc_mm.onboard ? 0 : 8; 818 819 /* 820 * mmcodec_setcontrol() sometimes fails right after powerup 821 * so we just try again until we either get a useful response or run 822 * out of time 823 */ 824 bail = 0; 825 while (mmcodec_setcontrol(sc) == -1 || sc->sc_version == 0xff) { 826 827 bail++; 828 if (bail > 100) { 829 DPRINTF("%s: cs4215 probe failed at offset %d\n", 830 device_xname(sc->sc_dev), sc->sc_mm.offset); 831 return (-1); 832 } 833 delay(10000); 834 } 835 836 aprint_normal_dev(sc->sc_dev, "cs4215 rev %c found at offset %d\n", 837 0x43 + (sc->sc_version & 0xf), sc->sc_mm.offset); 838 839 /* set some sane defaults for mmcodec_init_data */ 840 sc->sc_params.channels = 2; 841 sc->sc_params.precision = 16; 842 843 mmcodec_init_data(sc); 844 845 return (0); 846 } 847 848 static void 849 mmcodec_init_data(struct dbri_softc *sc) 850 { 851 bus_space_tag_t iot = sc->sc_iot; 852 bus_space_handle_t ioh = sc->sc_ioh; 853 uint32_t tmp; 854 int data_width; 855 856 tmp = bus_space_read_4(iot, ioh, DBRI_REG0); 857 tmp &= ~(DBRI_CHI_ACTIVATE); /* disable CHI */ 858 bus_space_write_4(iot, ioh, DBRI_REG0, tmp); 859 860 /* switch CS4215 to data mode - set PIO3 to 1 */ 861 tmp = DBRI_PIO_ENABLE_ALL | DBRI_PIO1 | DBRI_PIO3; 862 863 /* XXX */ 864 tmp |= (sc->sc_mm.onboard ? DBRI_PIO0 : DBRI_PIO2); 865 866 bus_space_write_4(iot, ioh, DBRI_REG2, tmp); 867 chi_reset(sc, CHIslave, 128); 868 869 data_width = sc->sc_params.channels * sc->sc_params.precision; 870 871 if ((data_width != 32) && (data_width != 8)) 872 aprint_error("%s: data_width is %d\n", __func__, data_width); 873 874 pipe_ts_link(sc, 20, PIPEoutput, 16, 32, sc->sc_mm.offset + 32); 875 pipe_ts_link(sc, 4, PIPEoutput, 16, data_width, sc->sc_mm.offset); 876 pipe_ts_link(sc, 6, PIPEinput, 16, data_width, sc->sc_mm.offset); 877 #if 0 878 /* readback for the mixer registers - we don't use that */ 879 pipe_ts_link(sc, 21, PIPEinput, 16, 32, sc->sc_mm.offset + 32); 880 881 pipe_receive_fixed(sc, 21, &sc->sc_mm.d.ldata); 882 #endif 883 mmcodec_setgain(sc, 0); 884 885 tmp = bus_space_read_4(iot, ioh, DBRI_REG0); 886 tmp |= DBRI_CHI_ACTIVATE; 887 bus_space_write_4(iot, ioh, DBRI_REG0, tmp); 888 889 return; 890 } 891 892 static void 893 mmcodec_pipe_init(struct dbri_softc *sc) 894 { 895 896 pipe_setup(sc, 4, DBRI_SDP_MEM | DBRI_SDP_TO_SER | DBRI_SDP_MSB); 897 pipe_setup(sc, 20, DBRI_SDP_FIXED | DBRI_SDP_TO_SER | DBRI_SDP_MSB); 898 pipe_setup(sc, 6, DBRI_SDP_MEM | DBRI_SDP_FROM_SER | DBRI_SDP_MSB); 899 #if 0 900 pipe_setup(sc, 21, DBRI_SDP_FIXED | DBRI_SDP_FROM_SER | DBRI_SDP_MSB); 901 #endif 902 pipe_setup(sc, 17, DBRI_SDP_FIXED | DBRI_SDP_TO_SER | DBRI_SDP_MSB); 903 pipe_setup(sc, 18, DBRI_SDP_FIXED | DBRI_SDP_FROM_SER | DBRI_SDP_MSB); 904 pipe_setup(sc, 19, DBRI_SDP_FIXED | DBRI_SDP_FROM_SER | DBRI_SDP_MSB); 905 906 pipe_receive_fixed(sc, 18, &sc->sc_mm.status); 907 pipe_receive_fixed(sc, 19, &sc->sc_mm.version); 908 909 return; 910 } 911 912 static void 913 mmcodec_default(struct dbri_softc *sc) 914 { 915 struct cs4215_state *mm = &sc->sc_mm; 916 917 /* 918 * no action, memory resetting only 919 * 920 * data time slots 5-8 921 * speaker, line and headphone enable. set gain to half. 922 * input is line 923 */ 924 mm->d.bdata[0] = sc->sc_latt = 0x20 | CS4215_HE | CS4215_LE; 925 mm->d.bdata[1] = sc->sc_ratt = 0x20 | CS4215_SE; 926 sc->sc_linp = 128; 927 sc->sc_rinp = 128; 928 sc->sc_monitor = 0; 929 sc->sc_input = 1; /* line */ 930 mm->d.bdata[2] = (CS4215_LG((sc->sc_linp >> 4)) & 0x0f) | 931 ((sc->sc_input == 2) ? CS4215_IS : 0) | CS4215_PIO0 | CS4215_PIO1; 932 mm->d.bdata[3] = (CS4215_RG((sc->sc_rinp >> 4) & 0x0f)) | 933 CS4215_MA(15 - ((sc->sc_monitor >> 4) & 0x0f)); 934 935 936 /* 937 * control time slots 1-4 938 * 939 * 0: default I/O voltage scale 940 * 1: 8 bit ulaw, 8kHz, mono, high pass filter disabled 941 * 2: serial enable, CHI master, 128 bits per frame, clock 1 942 * 3: tests disabled 943 */ 944 mm->c.bcontrol[0] = CS4215_ONE | CS4215_MLB; 945 mm->c.bcontrol[1] = CS4215_DFR_ULAW | CS4215_FREQ[0].csval; 946 mm->c.bcontrol[2] = CS4215_XCLK | CS4215_BSEL_128 | CS4215_FREQ[0].xtal; 947 mm->c.bcontrol[3] = 0; 948 949 return; 950 } 951 952 static void 953 mmcodec_setgain(struct dbri_softc *sc, int mute) 954 { 955 if (mute) { 956 /* disable all outputs, max. attenuation */ 957 sc->sc_mm.d.bdata[0] = sc->sc_latt | 63; 958 sc->sc_mm.d.bdata[1] = sc->sc_ratt | 63; 959 } else { 960 961 sc->sc_mm.d.bdata[0] = sc->sc_latt; 962 sc->sc_mm.d.bdata[1] = sc->sc_ratt; 963 } 964 965 /* input stuff */ 966 sc->sc_mm.d.bdata[2] = CS4215_LG((sc->sc_linp >> 4) & 0x0f) | 967 ((sc->sc_input == 2) ? CS4215_IS : 0) | CS4215_PIO0 | CS4215_PIO1; 968 sc->sc_mm.d.bdata[3] = (CS4215_RG((sc->sc_rinp >> 4)) & 0x0f) | 969 (CS4215_MA(15 - ((sc->sc_monitor >> 4) & 0x0f))); 970 971 if (sc->sc_powerstate == 0) 972 return; 973 pipe_transmit_fixed(sc, 20, sc->sc_mm.d.ldata); 974 975 DPRINTF("mmcodec_setgain: %08x\n", sc->sc_mm.d.ldata); 976 /* give the chip some time to execute the command */ 977 delay(250); 978 979 return; 980 } 981 982 static int 983 mmcodec_setcontrol(struct dbri_softc *sc) 984 { 985 bus_space_tag_t iot = sc->sc_iot; 986 bus_space_handle_t ioh = sc->sc_ioh; 987 uint32_t val; 988 uint32_t tmp; 989 int ret = 0; 990 #ifdef DBRI_SPIN 991 int i; 992 #else 993 int error, bail = 0; 994 #endif 995 996 KASSERT(mutex_owned(&sc->sc_intr_lock)); 997 998 /* 999 * Temporarily mute outputs and wait 125 us to make sure that it 1000 * happens. This avoids clicking noises. 1001 */ 1002 mmcodec_setgain(sc, 1); 1003 delay(125); 1004 1005 tmp = bus_space_read_4(iot, ioh, DBRI_REG0); 1006 tmp &= ~(DBRI_CHI_ACTIVATE); /* disable CHI */ 1007 bus_space_write_4(iot, ioh, DBRI_REG0, tmp); 1008 1009 bus_space_write_4(iot, ioh, DBRI_REG2, 0); 1010 delay(125); 1011 1012 /* enable control mode */ 1013 val = DBRI_PIO_ENABLE_ALL | DBRI_PIO1; /* was PIO1 */ 1014 1015 /* XXX */ 1016 val |= (sc->sc_mm.onboard ? DBRI_PIO0 : DBRI_PIO2); 1017 1018 bus_space_write_4(iot, ioh, DBRI_REG2, val); 1019 delay(34); 1020 1021 /* 1022 * in control mode, the cs4215 is the slave device, so the 1023 * DBRI must act as the CHI master. 1024 * 1025 * in data mode, the cs4215 must be the CHI master to insure 1026 * that the data stream is in sync with its codec 1027 */ 1028 tmp = bus_space_read_4(iot, ioh, DBRI_REG0); 1029 tmp &= ~DBRI_COMMAND_CHI; 1030 bus_space_write_4(iot, ioh, DBRI_REG0, tmp); 1031 1032 chi_reset(sc, CHImaster, 128); 1033 1034 /* control mode */ 1035 pipe_ts_link(sc, 17, PIPEoutput, 16, 32, sc->sc_mm.offset); 1036 pipe_ts_link(sc, 18, PIPEinput, 16, 8, sc->sc_mm.offset); 1037 pipe_ts_link(sc, 19, PIPEinput, 16, 8, sc->sc_mm.offset + 48); 1038 1039 pipe_receive_fixed(sc, 18, &sc->sc_mm.status); 1040 1041 /* wait for the chip to echo back CLB as zero */ 1042 sc->sc_mm.c.bcontrol[0] &= ~CS4215_CLB; 1043 pipe_transmit_fixed(sc, 17, sc->sc_mm.c.lcontrol); 1044 1045 tmp = bus_space_read_4(iot, ioh, DBRI_REG0); 1046 tmp |= DBRI_CHI_ACTIVATE; 1047 bus_space_write_4(iot, ioh, DBRI_REG0, tmp); 1048 1049 #ifdef DBRI_SPIN 1050 i = 1024; 1051 while (((sc->sc_mm.status & 0xe4) != CS4215_ONE) && (i > 0)) { 1052 i--; 1053 delay(125); 1054 } 1055 1056 if (i == 0) { 1057 DPRINTF("%s: cs4215 didn't respond to CLB (0x%02x)\n", 1058 device_xname(sc->sc_dev), sc->sc_mm.status); 1059 ret = -1; 1060 goto fail; 1061 } 1062 #else 1063 while (((sc->sc_mm.status & 0xe4) != CS4215_ONE) && (bail < 10)) { 1064 DPRINTF("%s: cv_wait_sig %p\n", device_xname(sc->sc_dev), sc); 1065 error = cv_timedwait_sig(&sc->sc_cv, &sc->sc_intr_lock, hz); 1066 if (error == EINTR) { 1067 DPRINTF("%s: interrupted\n", device_xname(sc->sc_dev)); 1068 ret = -1; 1069 mutex_spin_exit(&sc->sc_intr_lock); 1070 goto fail; 1071 } 1072 bail++; 1073 } 1074 if (bail >= 10) { 1075 aprint_error("%s: switching to control mode timed out (%x %x)\n", 1076 device_xname(sc->sc_dev), sc->sc_mm.status, 1077 bus_space_read_4(iot, ioh, DBRI_REG2)); 1078 ret = -1; 1079 goto fail; 1080 } 1081 #endif 1082 1083 /* copy the version information before it becomes unreadable again */ 1084 sc->sc_version = sc->sc_mm.version; 1085 sc->sc_whack_codec = 0; 1086 1087 fail: 1088 /* terminate cs4215 control mode */ 1089 sc->sc_mm.c.bcontrol[0] |= CS4215_CLB; 1090 pipe_transmit_fixed(sc, 17, sc->sc_mm.c.lcontrol); 1091 1092 /* two frames of control info @ 8kHz frame rate = 250us delay */ 1093 delay(250); 1094 1095 mmcodec_setgain(sc, 0); 1096 1097 return ret; 1098 1099 } 1100 1101 /* 1102 * CHI combo 1103 */ 1104 static void 1105 chi_reset(struct dbri_softc *sc, enum ms ms, int bpf) 1106 { 1107 volatile uint32_t *cmd; 1108 int val; 1109 int clockrate, divisor; 1110 1111 cmd = dbri_command_lock(sc); 1112 1113 /* set CHI anchor: pipe 16 */ 1114 val = DBRI_DTS_VI | DBRI_DTS_INS | DBRI_DTS_PRVIN(16) | DBRI_PIPE(16); 1115 *(cmd++) = DBRI_CMD(DBRI_COMMAND_DTS, 0, val); 1116 *(cmd++) = DBRI_TS_ANCHOR | DBRI_TS_NEXT(16); 1117 *(cmd++) = 0; 1118 1119 val = DBRI_DTS_VO | DBRI_DTS_INS | DBRI_DTS_PRVOUT(16) | DBRI_PIPE(16); 1120 *(cmd++) = DBRI_CMD(DBRI_COMMAND_DTS, 0, val); 1121 *(cmd++) = 0; 1122 *(cmd++) = DBRI_TS_ANCHOR | DBRI_TS_NEXT(16); 1123 1124 sc->sc_pipe[16].sdp = 1; 1125 sc->sc_pipe[16].next = 16; 1126 sc->sc_chi_pipe_in = 16; 1127 sc->sc_chi_pipe_out = 16; 1128 1129 switch (ms) { 1130 case CHIslave: 1131 *(cmd++) = DBRI_CMD(DBRI_COMMAND_CHI, 0, DBRI_CHI_CHICM(0)); 1132 break; 1133 case CHImaster: 1134 clockrate = bpf * 8; 1135 divisor = 12288 / clockrate; 1136 1137 if (divisor > 255 || divisor * clockrate != 12288) 1138 aprint_error_dev(sc->sc_dev, 1139 "illegal bits-per-frame %d\n", bpf); 1140 1141 *(cmd++) = DBRI_CMD(DBRI_COMMAND_CHI, 0, 1142 DBRI_CHI_CHICM(divisor) | DBRI_CHI_FD | DBRI_CHI_BPF(bpf)); 1143 break; 1144 default: 1145 aprint_error_dev(sc->sc_dev, "unknown value for ms!\n"); 1146 break; 1147 } 1148 1149 sc->sc_chi_bpf = bpf; 1150 1151 /* CHI data mode */ 1152 *(cmd++) = DBRI_CMD(DBRI_COMMAND_PAUSE, 0, 0); 1153 *(cmd++) = DBRI_CMD(DBRI_COMMAND_CDM, 0, 1154 DBRI_CDM_XCE | DBRI_CDM_XEN | DBRI_CDM_REN); 1155 1156 dbri_command_send(sc, cmd); 1157 1158 return; 1159 } 1160 1161 /* 1162 * pipe stuff 1163 */ 1164 static void 1165 pipe_setup(struct dbri_softc *sc, int pipe, int sdp) 1166 { 1167 DPRINTF("pipe setup: %d\n", pipe); 1168 if (pipe < 0 || pipe >= DBRI_PIPE_MAX) { 1169 aprint_error_dev(sc->sc_dev, "illegal pipe number %d\n", 1170 pipe); 1171 return; 1172 } 1173 1174 if ((sdp & 0xf800) != sdp) 1175 aprint_error_dev(sc->sc_dev, "strange SDP value %d\n", 1176 sdp); 1177 1178 if (DBRI_SDP_MODE(sdp) == DBRI_SDP_FIXED && 1179 !(sdp & DBRI_SDP_TO_SER)) 1180 sdp |= DBRI_SDP_CHANGE; 1181 1182 sdp |= DBRI_PIPE(pipe); 1183 1184 sc->sc_pipe[pipe].sdp = sdp; 1185 sc->sc_pipe[pipe].desc = -1; 1186 1187 pipe_reset(sc, pipe); 1188 1189 return; 1190 } 1191 1192 static void 1193 pipe_reset(struct dbri_softc *sc, int pipe) 1194 { 1195 struct dbri_desc *dd; 1196 int sdp; 1197 int desc; 1198 volatile uint32_t *cmd; 1199 1200 if (pipe < 0 || pipe >= DBRI_PIPE_MAX) { 1201 aprint_error_dev(sc->sc_dev, "illegal pipe number %d\n", 1202 pipe); 1203 return; 1204 } 1205 1206 sdp = sc->sc_pipe[pipe].sdp; 1207 if (sdp == 0) { 1208 aprint_error_dev(sc->sc_dev, "can not reset uninitialized pipe %d\n", 1209 pipe); 1210 return; 1211 } 1212 1213 cmd = dbri_command_lock(sc); 1214 *(cmd++) = DBRI_CMD(DBRI_COMMAND_SDP, 0, 1215 sdp | DBRI_SDP_CLEAR | DBRI_SDP_VALID_POINTER); 1216 *(cmd++) = 0; 1217 dbri_command_send(sc, cmd); 1218 1219 desc = sc->sc_pipe[pipe].desc; 1220 1221 dd = &sc->sc_desc[desc]; 1222 1223 dd->busy = 0; 1224 1225 #if 0 1226 if (dd->callback) 1227 softint_schedule(dd->softint); 1228 #endif 1229 1230 sc->sc_pipe[pipe].desc = -1; 1231 1232 return; 1233 } 1234 1235 static void 1236 pipe_receive_fixed(struct dbri_softc *sc, int pipe, volatile uint32_t *prec) 1237 { 1238 1239 if (pipe < DBRI_PIPE_MAX / 2 || pipe >= DBRI_PIPE_MAX) { 1240 aprint_error_dev(sc->sc_dev, "illegal pipe number %d\n", 1241 pipe); 1242 return; 1243 } 1244 1245 if (DBRI_SDP_MODE(sc->sc_pipe[pipe].sdp) != DBRI_SDP_FIXED) { 1246 aprint_error_dev(sc->sc_dev, "non-fixed pipe %d\n", 1247 pipe); 1248 return; 1249 } 1250 1251 if (sc->sc_pipe[pipe].sdp & DBRI_SDP_TO_SER) { 1252 aprint_error_dev(sc->sc_dev, "can not receive on transmit pipe %d\b", 1253 pipe); 1254 return; 1255 } 1256 1257 sc->sc_pipe[pipe].prec = prec; 1258 1259 return; 1260 } 1261 1262 static void 1263 pipe_transmit_fixed(struct dbri_softc *sc, int pipe, uint32_t data) 1264 { 1265 volatile uint32_t *cmd; 1266 1267 if (pipe < DBRI_PIPE_MAX / 2 || pipe >= DBRI_PIPE_MAX) { 1268 aprint_error_dev(sc->sc_dev, "illegal pipe number %d\n", 1269 pipe); 1270 return; 1271 } 1272 1273 if (DBRI_SDP_MODE(sc->sc_pipe[pipe].sdp) == 0) { 1274 aprint_error_dev(sc->sc_dev, "uninitialized pipe %d\n", 1275 pipe); 1276 return; 1277 } 1278 1279 if (DBRI_SDP_MODE(sc->sc_pipe[pipe].sdp) != DBRI_SDP_FIXED) { 1280 aprint_error_dev(sc->sc_dev, "non-fixed pipe %d\n", 1281 pipe); 1282 return; 1283 } 1284 1285 if (!(sc->sc_pipe[pipe].sdp & DBRI_SDP_TO_SER)) { 1286 aprint_error_dev(sc->sc_dev, "called on receive pipe %d\n", 1287 pipe); 1288 return; 1289 } 1290 1291 if (sc->sc_pipe[pipe].sdp & DBRI_SDP_MSB) 1292 data = reverse_bytes(data, sc->sc_pipe[pipe].length); 1293 1294 cmd = dbri_command_lock(sc); 1295 *(cmd++) = DBRI_CMD(DBRI_COMMAND_SSP, 0, pipe); 1296 *(cmd++) = data; 1297 1298 dbri_command_send(sc, cmd); 1299 1300 return; 1301 } 1302 1303 static void 1304 setup_ring_xmit(struct dbri_softc *sc, int pipe, int which, int num, int blksz, 1305 void (*callback)(void *), void *callback_args) 1306 { 1307 volatile uint32_t *cmd; 1308 int i; 1309 #if 0 1310 int td; 1311 int td_first, td_last; 1312 #endif 1313 bus_addr_t dmabuf, dmabase; 1314 struct dbri_desc *dd = &sc->sc_desc[which]; 1315 1316 switch (pipe) { 1317 case 4: 1318 /* output, offset 0 */ 1319 break; 1320 default: 1321 aprint_error("%s: illegal pipe number (%d)\n", 1322 __func__, pipe); 1323 return; 1324 } 1325 1326 #if 0 1327 td = 0; 1328 td_first = td_last = -1; 1329 #endif 1330 1331 if (sc->sc_pipe[pipe].sdp == 0) { 1332 aprint_error_dev(sc->sc_dev, "uninitialized pipe %d\n", 1333 pipe); 1334 return; 1335 } 1336 1337 dmabuf = dd->dmabase; 1338 dmabase = sc->sc_dmabase; 1339 1340 for (i = 0; i < (num - 1); i++) { 1341 1342 sc->sc_dma->xmit[i].flags = TX_BCNT(blksz) 1343 | TX_EOF | TX_BINT; 1344 sc->sc_dma->xmit[i].ba = dmabuf; 1345 sc->sc_dma->xmit[i].nda = dmabase + dbri_dma_off(xmit, i + 1); 1346 sc->sc_dma->xmit[i].status = 0; 1347 1348 #if 0 1349 td_last = td; 1350 #endif 1351 dmabuf += blksz; 1352 } 1353 1354 sc->sc_dma->xmit[i].flags = TX_BCNT(blksz) | TX_EOF | TX_BINT; 1355 1356 sc->sc_dma->xmit[i].ba = dmabuf; 1357 sc->sc_dma->xmit[i].nda = dmabase + dbri_dma_off(xmit, 0); 1358 sc->sc_dma->xmit[i].status = 0; 1359 1360 dd->callback = callback; 1361 dd->callback_args = callback_args; 1362 1363 /* the pipe shouldn't be active */ 1364 if (pipe_active(sc, pipe)) { 1365 aprint_error("pipe active (CDP)\n"); 1366 /* pipe is already active */ 1367 #if 0 1368 td_last = sc->sc_pipe[pipe].desc; 1369 while (sc->sc_desc[td_last].next != -1) 1370 td_last = sc->sc_desc[td_last].next; 1371 1372 sc->sc_desc[td_last].next = td_first; 1373 sc->sc_dma->desc[td_last].nda = 1374 sc->sc_dmabase + dbri_dma_off(desc, td_first); 1375 1376 cmd = dbri_command_lock(sc); 1377 *(cmd++) = DBRI_CMD(DBRI_COMMAND_CDP, 0, pipe); 1378 dbri_command_send(sc, cmd); 1379 #endif 1380 } else { 1381 /* 1382 * pipe isn't active - issue an SDP command to start our 1383 * chain of TDs running 1384 */ 1385 sc->sc_pipe[pipe].desc = which; 1386 cmd = dbri_command_lock(sc); 1387 *(cmd++) = DBRI_CMD(DBRI_COMMAND_SDP, 0, 1388 sc->sc_pipe[pipe].sdp | 1389 DBRI_SDP_VALID_POINTER | 1390 DBRI_SDP_EVERY | 1391 DBRI_SDP_CLEAR); 1392 *(cmd++) = sc->sc_dmabase + dbri_dma_off(xmit, 0); 1393 dbri_command_send(sc, cmd); 1394 DPRINTF("%s: starting DMA\n", __func__); 1395 } 1396 1397 return; 1398 } 1399 1400 static void 1401 setup_ring_recv(struct dbri_softc *sc, int pipe, int which, int num, int blksz, 1402 void (*callback)(void *), void *callback_args) 1403 { 1404 volatile uint32_t *cmd; 1405 int i; 1406 #if 0 1407 int td_first, td_last; 1408 #endif 1409 bus_addr_t dmabuf, dmabase; 1410 struct dbri_desc *dd = &sc->sc_desc[which]; 1411 1412 switch (pipe) { 1413 case 6: 1414 break; 1415 default: 1416 aprint_error("%s: illegal pipe number (%d)\n", 1417 __func__, pipe); 1418 return; 1419 } 1420 1421 #if 0 1422 td_first = td_last = -1; 1423 #endif 1424 1425 if (sc->sc_pipe[pipe].sdp == 0) { 1426 aprint_error_dev(sc->sc_dev, "uninitialized pipe %d\n", 1427 pipe); 1428 return; 1429 } 1430 1431 dmabuf = dd->dmabase; 1432 dmabase = sc->sc_dmabase; 1433 1434 for (i = 0; i < (num - 1); i++) { 1435 1436 sc->sc_dma->recv[i].flags = RX_BSIZE(blksz) | RX_FINAL; 1437 sc->sc_dma->recv[i].ba = dmabuf; 1438 sc->sc_dma->recv[i].nda = dmabase + dbri_dma_off(recv, i + 1); 1439 sc->sc_dma->recv[i].status = RX_EOF; 1440 1441 #if 0 1442 td_last = i; 1443 #endif 1444 dmabuf += blksz; 1445 } 1446 1447 sc->sc_dma->recv[i].flags = RX_BSIZE(blksz) | RX_FINAL; 1448 1449 sc->sc_dma->recv[i].ba = dmabuf; 1450 sc->sc_dma->recv[i].nda = dmabase + dbri_dma_off(recv, 0); 1451 sc->sc_dma->recv[i].status = RX_EOF; 1452 1453 dd->callback = callback; 1454 dd->callback_args = callback_args; 1455 1456 /* the pipe shouldn't be active */ 1457 if (pipe_active(sc, pipe)) { 1458 aprint_error("pipe active (CDP)\n"); 1459 /* pipe is already active */ 1460 #if 0 1461 td_last = sc->sc_pipe[pipe].desc; 1462 while (sc->sc_desc[td_last].next != -1) 1463 td_last = sc->sc_desc[td_last].next; 1464 1465 sc->sc_desc[td_last].next = td_first; 1466 sc->sc_dma->desc[td_last].nda = 1467 sc->sc_dmabase + dbri_dma_off(desc, td_first); 1468 1469 cmd = dbri_command_lock(sc); 1470 *(cmd++) = DBRI_CMD(DBRI_COMMAND_CDP, 0, pipe); 1471 dbri_command_send(sc, cmd); 1472 #endif 1473 } else { 1474 /* 1475 * pipe isn't active - issue an SDP command to start our 1476 * chain of TDs running 1477 */ 1478 sc->sc_pipe[pipe].desc = which; 1479 cmd = dbri_command_lock(sc); 1480 *(cmd++) = DBRI_CMD(DBRI_COMMAND_SDP, 0, 1481 sc->sc_pipe[pipe].sdp | 1482 DBRI_SDP_VALID_POINTER | 1483 DBRI_SDP_EVERY | 1484 DBRI_SDP_CLEAR); 1485 *(cmd++) = sc->sc_dmabase + dbri_dma_off(recv, 0); 1486 dbri_command_send(sc, cmd); 1487 DPRINTF("%s: starting DMA\n", __func__); 1488 } 1489 1490 return; 1491 } 1492 1493 static void 1494 pipe_ts_link(struct dbri_softc *sc, int pipe, enum io dir, int basepipe, 1495 int len, int cycle) 1496 { 1497 volatile uint32_t *cmd; 1498 int prevpipe, nextpipe; 1499 int val; 1500 1501 DPRINTF("%s: %d\n", __func__, pipe); 1502 if (pipe < 0 || pipe >= DBRI_PIPE_MAX || 1503 basepipe < 0 || basepipe >= DBRI_PIPE_MAX) { 1504 aprint_error_dev(sc->sc_dev, "illegal pipe numbers (%d, %d)\n", 1505 pipe, basepipe); 1506 return; 1507 } 1508 1509 if (sc->sc_pipe[pipe].sdp == 0 || sc->sc_pipe[basepipe].sdp == 0) { 1510 aprint_error_dev(sc->sc_dev, "uninitialized pipe (%d, %d)\n", 1511 pipe, basepipe); 1512 return; 1513 } 1514 1515 if (basepipe == 16 && dir == PIPEoutput && cycle == 0) 1516 cycle = sc->sc_chi_bpf; 1517 1518 if (basepipe == pipe) 1519 prevpipe = nextpipe = pipe; 1520 else { 1521 if (basepipe == 16) { 1522 if (dir == PIPEinput) { 1523 prevpipe = sc->sc_chi_pipe_in; 1524 } else { 1525 prevpipe = sc->sc_chi_pipe_out; 1526 } 1527 } else 1528 prevpipe = basepipe; 1529 1530 nextpipe = sc->sc_pipe[prevpipe].next; 1531 1532 while (sc->sc_pipe[nextpipe].cycle < cycle && 1533 sc->sc_pipe[nextpipe].next != basepipe) { 1534 prevpipe = nextpipe; 1535 nextpipe = sc->sc_pipe[nextpipe].next; 1536 } 1537 } 1538 1539 if (prevpipe == 16) { 1540 if (dir == PIPEinput) { 1541 sc->sc_chi_pipe_in = pipe; 1542 } else { 1543 sc->sc_chi_pipe_out = pipe; 1544 } 1545 } else 1546 sc->sc_pipe[prevpipe].next = pipe; 1547 1548 sc->sc_pipe[pipe].next = nextpipe; 1549 sc->sc_pipe[pipe].cycle = cycle; 1550 sc->sc_pipe[pipe].length = len; 1551 1552 cmd = dbri_command_lock(sc); 1553 1554 switch (dir) { 1555 case PIPEinput: 1556 val = DBRI_DTS_VI | DBRI_DTS_INS | DBRI_DTS_PRVIN(prevpipe); 1557 val |= pipe; 1558 *(cmd++) = DBRI_CMD(DBRI_COMMAND_DTS, 0, val); 1559 *(cmd++) = DBRI_TS_LEN(len) | DBRI_TS_CYCLE(cycle) | 1560 DBRI_TS_NEXT(nextpipe); 1561 *(cmd++) = 0; 1562 break; 1563 case PIPEoutput: 1564 val = DBRI_DTS_VO | DBRI_DTS_INS | DBRI_DTS_PRVOUT(prevpipe); 1565 val |= pipe; 1566 *(cmd++) = DBRI_CMD(DBRI_COMMAND_DTS, 0, val); 1567 *(cmd++) = 0; 1568 *(cmd++) = DBRI_TS_LEN(len) | DBRI_TS_CYCLE(cycle) | 1569 DBRI_TS_NEXT(nextpipe); 1570 break; 1571 default: 1572 DPRINTF("%s: should not have happened!\n", 1573 device_xname(sc->sc_dev)); 1574 break; 1575 } 1576 1577 dbri_command_send(sc, cmd); 1578 1579 return; 1580 } 1581 1582 static int 1583 pipe_active(struct dbri_softc *sc, int pipe) 1584 { 1585 1586 return (sc->sc_pipe[pipe].desc != -1); 1587 } 1588 1589 /* 1590 * subroutines required to interface with audio(9) 1591 */ 1592 1593 static int 1594 dbri_query_format(void *hdl, audio_format_query_t *afp) 1595 { 1596 1597 return audio_query_format(dbri_formats, DBRI_NFORMATS, afp); 1598 } 1599 1600 static int 1601 dbri_set_format(void *hdl, int setmode, 1602 const audio_params_t *play, const audio_params_t *rec, 1603 audio_filter_reg_t *pfil, audio_filter_reg_t *rfil) 1604 { 1605 struct dbri_softc *sc = hdl; 1606 int rate; 1607 1608 /* *play and *rec are the identical because !AUDIO_PROP_INDEPENDENT. */ 1609 1610 for (rate = 0; CS4215_FREQ[rate].freq; rate++) 1611 if (CS4215_FREQ[rate].freq == play->sample_rate) 1612 break; 1613 1614 if (CS4215_FREQ[rate].freq == 0) 1615 return EINVAL; 1616 1617 /* set frequency */ 1618 sc->sc_mm.c.bcontrol[1] &= ~0x38; 1619 sc->sc_mm.c.bcontrol[1] |= CS4215_FREQ[rate].csval; 1620 sc->sc_mm.c.bcontrol[2] &= ~0x70; 1621 sc->sc_mm.c.bcontrol[2] |= CS4215_FREQ[rate].xtal; 1622 1623 /* set encoding */ 1624 sc->sc_mm.c.bcontrol[1] &= ~3; 1625 sc->sc_mm.c.bcontrol[1] |= CS4215_DFR_LINEAR16; 1626 1627 /* set channel */ 1628 sc->sc_mm.c.bcontrol[1] |= CS4215_DFR_STEREO; 1629 1630 sc->sc_whack_codec = 1; 1631 return 0; 1632 } 1633 1634 static int 1635 dbri_round_blocksize(void *hdl, int bs, int mode, 1636 const audio_params_t *param) 1637 { 1638 1639 if (bs > 0x1fff) 1640 return 0x1fff; 1641 return bs; 1642 } 1643 1644 static int 1645 dbri_halt_output(void *hdl) 1646 { 1647 struct dbri_softc *sc = hdl; 1648 1649 if (!sc->sc_playing) 1650 return 0; 1651 1652 sc->sc_playing = 0; 1653 pipe_reset(sc, 4); 1654 return (0); 1655 } 1656 1657 static int 1658 dbri_getdev(void *hdl, struct audio_device *ret) 1659 { 1660 1661 *ret = dbri_device; 1662 return (0); 1663 } 1664 1665 static int 1666 dbri_set_port(void *hdl, mixer_ctrl_t *mc) 1667 { 1668 struct dbri_softc *sc = hdl; 1669 int latt = sc->sc_latt, ratt = sc->sc_ratt; 1670 1671 switch (mc->dev) { 1672 case DBRI_VOL_OUTPUT: /* master volume */ 1673 latt = (latt & 0xc0) | (63 - 1674 uimin(mc->un.value.level[AUDIO_MIXER_LEVEL_LEFT] >> 2, 63)); 1675 ratt = (ratt & 0xc0) | (63 - 1676 uimin(mc->un.value.level[AUDIO_MIXER_LEVEL_RIGHT] >> 2, 63)); 1677 break; 1678 case DBRI_ENABLE_MONO: /* built-in speaker */ 1679 if (mc->un.ord == 1) { 1680 ratt |= CS4215_SE; 1681 } else 1682 ratt &= ~CS4215_SE; 1683 break; 1684 case DBRI_ENABLE_HEADPHONE: /* headphones output */ 1685 if (mc->un.ord == 1) { 1686 latt |= CS4215_HE; 1687 } else 1688 latt &= ~CS4215_HE; 1689 break; 1690 case DBRI_ENABLE_LINE: /* line out */ 1691 if (mc->un.ord == 1) { 1692 latt |= CS4215_LE; 1693 } else 1694 latt &= ~CS4215_LE; 1695 break; 1696 case DBRI_VOL_MONITOR: 1697 if (mc->un.value.level[AUDIO_MIXER_LEVEL_LEFT] == 1698 sc->sc_monitor) 1699 return 0; 1700 sc->sc_monitor = mc->un.value.level[AUDIO_MIXER_LEVEL_LEFT]; 1701 break; 1702 case DBRI_INPUT_GAIN: 1703 sc->sc_linp = mc->un.value.level[AUDIO_MIXER_LEVEL_LEFT]; 1704 sc->sc_rinp = mc->un.value.level[AUDIO_MIXER_LEVEL_RIGHT]; 1705 break; 1706 case DBRI_INPUT_SELECT: 1707 if (mc->un.mask == sc->sc_input) 1708 return 0; 1709 sc->sc_input = mc->un.mask; 1710 break; 1711 } 1712 1713 sc->sc_latt = latt; 1714 sc->sc_ratt = ratt; 1715 1716 mutex_spin_enter(&sc->sc_intr_lock); 1717 mmcodec_setgain(sc, 0); 1718 mutex_spin_exit(&sc->sc_intr_lock); 1719 1720 return (0); 1721 } 1722 1723 static int 1724 dbri_get_port(void *hdl, mixer_ctrl_t *mc) 1725 { 1726 struct dbri_softc *sc = hdl; 1727 1728 switch (mc->dev) { 1729 case DBRI_VOL_OUTPUT: /* master volume */ 1730 mc->un.value.level[AUDIO_MIXER_LEVEL_LEFT] = 1731 (63 - (sc->sc_latt & 0x3f)) << 2; 1732 mc->un.value.level[AUDIO_MIXER_LEVEL_RIGHT] = 1733 (63 - (sc->sc_ratt & 0x3f)) << 2; 1734 return (0); 1735 case DBRI_ENABLE_MONO: /* built-in speaker */ 1736 mc->un.ord = (sc->sc_ratt & CS4215_SE) ? 1 : 0; 1737 return 0; 1738 case DBRI_ENABLE_HEADPHONE: /* headphones output */ 1739 mc->un.ord = (sc->sc_latt & CS4215_HE) ? 1 : 0; 1740 return 0; 1741 case DBRI_ENABLE_LINE: /* line out */ 1742 mc->un.ord = (sc->sc_latt & CS4215_LE) ? 1 : 0; 1743 return 0; 1744 case DBRI_VOL_MONITOR: 1745 mc->un.value.level[AUDIO_MIXER_LEVEL_LEFT] = sc->sc_monitor; 1746 return 0; 1747 case DBRI_INPUT_GAIN: 1748 mc->un.value.level[AUDIO_MIXER_LEVEL_LEFT] = sc->sc_linp; 1749 mc->un.value.level[AUDIO_MIXER_LEVEL_RIGHT] = sc->sc_rinp; 1750 return 0; 1751 case DBRI_INPUT_SELECT: 1752 mc->un.mask = sc->sc_input; 1753 return 0; 1754 } 1755 return (EINVAL); 1756 } 1757 1758 static int 1759 dbri_query_devinfo(void *hdl, mixer_devinfo_t *di) 1760 { 1761 1762 switch (di->index) { 1763 case DBRI_MONITOR_CLASS: 1764 di->mixer_class = DBRI_MONITOR_CLASS; 1765 strcpy(di->label.name, AudioCmonitor); 1766 di->type = AUDIO_MIXER_CLASS; 1767 di->next = di->prev = AUDIO_MIXER_LAST; 1768 return 0; 1769 case DBRI_OUTPUT_CLASS: 1770 di->mixer_class = DBRI_OUTPUT_CLASS; 1771 strcpy(di->label.name, AudioCoutputs); 1772 di->type = AUDIO_MIXER_CLASS; 1773 di->next = di->prev = AUDIO_MIXER_LAST; 1774 return 0; 1775 case DBRI_INPUT_CLASS: 1776 di->mixer_class = DBRI_INPUT_CLASS; 1777 strcpy(di->label.name, AudioCinputs); 1778 di->type = AUDIO_MIXER_CLASS; 1779 di->next = di->prev = AUDIO_MIXER_LAST; 1780 return 0; 1781 case DBRI_VOL_OUTPUT: /* master volume */ 1782 di->mixer_class = DBRI_OUTPUT_CLASS; 1783 di->next = di->prev = AUDIO_MIXER_LAST; 1784 strcpy(di->label.name, AudioNmaster); 1785 di->type = AUDIO_MIXER_VALUE; 1786 di->un.v.num_channels = 2; 1787 di->un.v.delta = 16; 1788 strcpy(di->un.v.units.name, AudioNvolume); 1789 return (0); 1790 case DBRI_INPUT_GAIN: /* input gain */ 1791 di->mixer_class = DBRI_INPUT_CLASS; 1792 di->next = di->prev = AUDIO_MIXER_LAST; 1793 strcpy(di->label.name, AudioNrecord); 1794 di->type = AUDIO_MIXER_VALUE; 1795 di->un.v.num_channels = 2; 1796 strcpy(di->un.v.units.name, AudioNvolume); 1797 return (0); 1798 case DBRI_VOL_MONITOR: /* monitor volume */ 1799 di->mixer_class = DBRI_MONITOR_CLASS; 1800 di->next = di->prev = AUDIO_MIXER_LAST; 1801 strcpy(di->label.name, AudioNmonitor); 1802 di->type = AUDIO_MIXER_VALUE; 1803 di->un.v.num_channels = 1; 1804 strcpy(di->un.v.units.name, AudioNvolume); 1805 return (0); 1806 case DBRI_ENABLE_MONO: /* built-in speaker */ 1807 di->mixer_class = DBRI_OUTPUT_CLASS; 1808 di->next = di->prev = AUDIO_MIXER_LAST; 1809 strcpy(di->label.name, AudioNmono); 1810 di->type = AUDIO_MIXER_ENUM; 1811 di->un.e.num_mem = 2; 1812 strcpy(di->un.e.member[0].label.name, AudioNoff); 1813 di->un.e.member[0].ord = 0; 1814 strcpy(di->un.e.member[1].label.name, AudioNon); 1815 di->un.e.member[1].ord = 1; 1816 return (0); 1817 case DBRI_ENABLE_HEADPHONE: /* headphones output */ 1818 di->mixer_class = DBRI_OUTPUT_CLASS; 1819 di->next = di->prev = AUDIO_MIXER_LAST; 1820 strcpy(di->label.name, AudioNheadphone); 1821 di->type = AUDIO_MIXER_ENUM; 1822 di->un.e.num_mem = 2; 1823 strcpy(di->un.e.member[0].label.name, AudioNoff); 1824 di->un.e.member[0].ord = 0; 1825 strcpy(di->un.e.member[1].label.name, AudioNon); 1826 di->un.e.member[1].ord = 1; 1827 return (0); 1828 case DBRI_ENABLE_LINE: /* line out */ 1829 di->mixer_class = DBRI_OUTPUT_CLASS; 1830 di->next = di->prev = AUDIO_MIXER_LAST; 1831 strcpy(di->label.name, AudioNline); 1832 di->type = AUDIO_MIXER_ENUM; 1833 di->un.e.num_mem = 2; 1834 strcpy(di->un.e.member[0].label.name, AudioNoff); 1835 di->un.e.member[0].ord = 0; 1836 strcpy(di->un.e.member[1].label.name, AudioNon); 1837 di->un.e.member[1].ord = 1; 1838 return (0); 1839 case DBRI_INPUT_SELECT: 1840 di->mixer_class = DBRI_INPUT_CLASS; 1841 strcpy(di->label.name, AudioNsource); 1842 di->type = AUDIO_MIXER_SET; 1843 di->prev = di->next = AUDIO_MIXER_LAST; 1844 di->un.s.num_mem = 2; 1845 strcpy(di->un.s.member[0].label.name, AudioNline); 1846 di->un.s.member[0].mask = 1 << 0; 1847 strcpy(di->un.s.member[1].label.name, AudioNmicrophone); 1848 di->un.s.member[1].mask = 1 << 1; 1849 return 0; 1850 } 1851 1852 return (ENXIO); 1853 } 1854 1855 static int 1856 dbri_get_props(void *hdl) 1857 { 1858 1859 return AUDIO_PROP_PLAYBACK | AUDIO_PROP_CAPTURE | 1860 AUDIO_PROP_FULLDUPLEX; 1861 } 1862 1863 static int 1864 dbri_commit(void *hdl) 1865 { 1866 struct dbri_softc *sc = hdl; 1867 int ret = 0; 1868 1869 /* 1870 * we only need to whack the codec if things like sample format or 1871 * frequency changed, not for mixer stuff 1872 */ 1873 if (sc->sc_whack_codec == 0) 1874 return 0; 1875 1876 mutex_spin_enter(&sc->sc_intr_lock); 1877 ret = mmcodec_setcontrol(sc); 1878 if (ret) { 1879 DPRINTF("%s: control mode failed. Mutex %s PIL %x\n", __func__, 1880 mutex_owned(&sc->sc_intr_lock) ? "held" : "free", 1881 (getpsr() & PSR_PIL) >> 8); 1882 } else 1883 DPRINTF("%s: control mode ok\n", __func__); 1884 mmcodec_init_data(sc); 1885 mutex_spin_exit(&sc->sc_intr_lock); 1886 return 0; 1887 } 1888 1889 static int 1890 dbri_trigger_output(void *hdl, void *start, void *end, int blksize, 1891 void (*intr)(void *), void *intrarg, 1892 const struct audio_params *param) 1893 { 1894 struct dbri_softc *sc = hdl; 1895 unsigned long count, num; 1896 1897 if (sc->sc_playing) 1898 return 0; 1899 1900 count = (unsigned long)(((char *)end - (char *)start)); 1901 num = count / blksize; 1902 1903 DPRINTF("trigger_output(%lx %lx) : %d %ld %ld\n", 1904 (unsigned long)intr, 1905 (unsigned long)intrarg, blksize, count, num); 1906 1907 sc->sc_params = *param; 1908 1909 /* 1910 * always use DMA descriptor 0 for output 1911 * no need to allocate them dynamically since we only ever have 1912 * exactly one input stream and exactly one output stream 1913 */ 1914 setup_ring_xmit(sc, 4, 0, num, blksize, intr, intrarg); 1915 sc->sc_playing = 1; 1916 return 0; 1917 } 1918 1919 static int 1920 dbri_halt_input(void *cookie) 1921 { 1922 struct dbri_softc *sc = cookie; 1923 1924 if (!sc->sc_recording) 1925 return 0; 1926 1927 sc->sc_recording = 0; 1928 pipe_reset(sc, 6); 1929 return 0; 1930 } 1931 1932 static int 1933 dbri_trigger_input(void *hdl, void *start, void *end, int blksize, 1934 void (*intr)(void *), void *intrarg, 1935 const struct audio_params *param) 1936 { 1937 struct dbri_softc *sc = hdl; 1938 unsigned long count, num; 1939 1940 if (sc->sc_recording) 1941 return 0; 1942 1943 count = (unsigned long)(((char *)end - (char *)start)); 1944 num = count / blksize; 1945 1946 DPRINTF("trigger_input(%lx %lx) : %d %ld %ld\n", 1947 (unsigned long)intr, 1948 (unsigned long)intrarg, blksize, count, num); 1949 1950 sc->sc_params = *param; 1951 1952 sc->sc_recording = 1; 1953 setup_ring_recv(sc, 6, 1, num, blksize, intr, intrarg); 1954 return 0; 1955 } 1956 1957 static void 1958 dbri_get_locks(void *opaque, kmutex_t **intr, kmutex_t **thread) 1959 { 1960 struct dbri_softc *sc = opaque; 1961 1962 *intr = &sc->sc_intr_lock; 1963 *thread = &sc->sc_lock; 1964 } 1965 1966 static uint32_t 1967 reverse_bytes(uint32_t b, int len) 1968 { 1969 switch (len) { 1970 case 32: 1971 b = ((b & 0xffff0000) >> 16) | ((b & 0x0000ffff) << 16); 1972 case 16: 1973 b = ((b & 0xff00ff00) >> 8) | ((b & 0x00ff00ff) << 8); 1974 case 8: 1975 b = ((b & 0xf0f0f0f0) >> 4) | ((b & 0x0f0f0f0f) << 4); 1976 case 4: 1977 b = ((b & 0xcccccccc) >> 2) | ((b & 0x33333333) << 2); 1978 case 2: 1979 b = ((b & 0xaaaaaaaa) >> 1) | ((b & 0x55555555) << 1); 1980 case 1: 1981 case 0: 1982 break; 1983 default: 1984 DPRINTF("reverse_bytes: unsupported length\n"); 1985 }; 1986 1987 return (b); 1988 } 1989 1990 static void * 1991 dbri_malloc(void *v, int dir, size_t s) 1992 { 1993 struct dbri_softc *sc = v; 1994 struct dbri_desc *dd = &sc->sc_desc[sc->sc_desc_used]; 1995 int rseg; 1996 1997 if (bus_dmamap_create(sc->sc_dmat, s, 1, s, 0, BUS_DMA_NOWAIT, 1998 &dd->dmamap) == 0) { 1999 if (bus_dmamem_alloc(sc->sc_dmat, s, 0, 0, &dd->dmaseg, 2000 1, &rseg, BUS_DMA_NOWAIT) == 0) { 2001 if (bus_dmamem_map(sc->sc_dmat, &dd->dmaseg, rseg, s, 2002 &dd->buf, BUS_DMA_NOWAIT|BUS_DMA_COHERENT) == 0) { 2003 if (dd->buf != NULL) { 2004 if (bus_dmamap_load(sc->sc_dmat, 2005 dd->dmamap, dd->buf, s, NULL, 2006 BUS_DMA_NOWAIT) == 0) { 2007 dd->len = s; 2008 dd->busy = 0; 2009 dd->callback = NULL; 2010 dd->dmabase = 2011 dd->dmamap->dm_segs[0].ds_addr; 2012 DPRINTF("dbri_malloc: using buffer %d %08x\n", 2013 sc->sc_desc_used, (uint32_t)dd->buf); 2014 sc->sc_desc_used++; 2015 return dd->buf; 2016 } else 2017 aprint_error("dbri_malloc: load failed\n"); 2018 } else 2019 aprint_error("dbri_malloc: map returned NULL\n"); 2020 } else 2021 aprint_error("dbri_malloc: map failed\n"); 2022 bus_dmamem_free(sc->sc_dmat, &dd->dmaseg, rseg); 2023 } else 2024 aprint_error("dbri_malloc: malloc() failed\n"); 2025 bus_dmamap_destroy(sc->sc_dmat, dd->dmamap); 2026 } else 2027 aprint_error("dbri_malloc: bus_dmamap_create() failed\n"); 2028 return NULL; 2029 } 2030 2031 static void 2032 dbri_free(void *v, void *p, size_t size) 2033 { 2034 struct dbri_softc *sc = v; 2035 struct dbri_desc *dd; 2036 int i; 2037 2038 for (i = 0; i < sc->sc_desc_used; i++) { 2039 dd = &sc->sc_desc[i]; 2040 if (dd->buf == p) 2041 break; 2042 } 2043 if (i >= sc->sc_desc_used) 2044 return; 2045 bus_dmamap_unload(sc->sc_dmat, dd->dmamap); 2046 bus_dmamap_destroy(sc->sc_dmat, dd->dmamap); 2047 } 2048 2049 static int 2050 dbri_open(void *cookie, int flags) 2051 { 2052 struct dbri_softc *sc = cookie; 2053 2054 DPRINTF("%s: %d\n", __func__, sc->sc_refcount); 2055 2056 if (sc->sc_refcount == 0) { 2057 dbri_bring_up(sc); 2058 } 2059 2060 sc->sc_refcount++; 2061 2062 return 0; 2063 } 2064 2065 static void 2066 dbri_close(void *cookie) 2067 { 2068 struct dbri_softc *sc = cookie; 2069 2070 DPRINTF("%s: %d\n", __func__, sc->sc_refcount); 2071 2072 sc->sc_refcount--; 2073 KASSERT(sc->sc_refcount >= 0); 2074 if (sc->sc_refcount > 0) 2075 return; 2076 2077 dbri_set_power(sc, 0); 2078 sc->sc_playing = 0; 2079 sc->sc_recording = 0; 2080 } 2081 2082 static bool 2083 dbri_suspend(device_t self, const pmf_qual_t *qual) 2084 { 2085 struct dbri_softc *sc = device_private(self); 2086 2087 mutex_spin_enter(&sc->sc_intr_lock); 2088 dbri_set_power(sc, 0); 2089 mutex_spin_exit(&sc->sc_intr_lock); 2090 return true; 2091 } 2092 2093 static bool 2094 dbri_resume(device_t self, const pmf_qual_t *qual) 2095 { 2096 struct dbri_softc *sc = device_private(self); 2097 2098 if (sc->sc_powerstate != 0) 2099 return true; 2100 aprint_verbose("resume: %d\n", sc->sc_refcount); 2101 if (sc->sc_playing) { 2102 volatile uint32_t *cmd; 2103 2104 mutex_spin_enter(&sc->sc_intr_lock); 2105 dbri_bring_up(sc); 2106 cmd = dbri_command_lock(sc); 2107 *(cmd++) = DBRI_CMD(DBRI_COMMAND_SDP, 2108 0, sc->sc_pipe[4].sdp | 2109 DBRI_SDP_VALID_POINTER | 2110 DBRI_SDP_EVERY | DBRI_SDP_CLEAR); 2111 *(cmd++) = sc->sc_dmabase + 2112 dbri_dma_off(xmit, 0); 2113 dbri_command_send(sc, cmd); 2114 mutex_spin_exit(&sc->sc_intr_lock); 2115 } 2116 return true; 2117 } 2118 2119 #endif /* NAUDIO > 0 */ 2120
Indexes created Thu Sep 25 16:09:42 GMT 2025