dbri.c revision 1.44
1 /* $NetBSD: dbri.c,v 1.44 2021/02/06 09:15:11 isaki Exp $ */ 2 3 /* 4 * Copyright (C) 1997 Rudolf Koenig (rfkoenig (at) immd4.informatik.uni-erlangen.de) 5 * Copyright (c) 1998, 1999 Brent Baccala (baccala (at) freesoft.org) 6 * Copyright (c) 2001, 2002 Jared D. McNeill <jmcneill (at) netbsd.org> 7 * Copyright (c) 2005 Michael Lorenz <macallan (at) netbsd.org> 8 * All rights reserved. 9 * 10 * This driver is losely based on a Linux driver written by Rudolf Koenig and 11 * Brent Baccala who kindly gave their permission to use their code in a 12 * BSD-licensed driver. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions 16 * are met: 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in the 21 * documentation and/or other materials provided with the distribution. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 28 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 29 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: dbri.c,v 1.44 2021/02/06 09:15:11 isaki Exp $"); 38 39 #include "audio.h" 40 #if NAUDIO > 0 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/errno.h> 45 #include <sys/device.h> 46 #include <sys/proc.h> 47 #include <sys/kernel.h> 48 #include <sys/bus.h> 49 #include <sys/intr.h> 50 #include <sys/kmem.h> 51 52 #include <dev/sbus/sbusvar.h> 53 #include <sparc/sparc/auxreg.h> 54 #include <machine/autoconf.h> 55 56 #include <sys/audioio.h> 57 #include <dev/audio/audio_if.h> 58 59 #include <dev/ic/cs4215reg.h> 60 #include <dev/ic/cs4215var.h> 61 #include <dev/sbus/dbrireg.h> 62 #include <dev/sbus/dbrivar.h> 63 64 #include "opt_sbus_dbri.h" 65 66 #define DBRI_ROM_NAME_PREFIX "SUNW,DBRI" 67 68 #ifdef DBRI_DEBUG 69 # define DPRINTF aprint_normal 70 #else 71 # define DPRINTF while (0) printf 72 #endif 73 74 static const char *dbri_supported[] = { 75 "e", 76 "s3", 77 "" 78 }; 79 80 enum ms { 81 CHImaster, 82 CHIslave 83 }; 84 85 enum io { 86 PIPEinput, 87 PIPEoutput 88 }; 89 90 /* 91 * Function prototypes 92 */ 93 94 /* softc stuff */ 95 static void dbri_attach_sbus(device_t, device_t, void *); 96 static int dbri_match_sbus(device_t, cfdata_t, void *); 97 98 static int dbri_config_interrupts(device_t); 99 100 /* interrupt handler */ 101 static int dbri_intr(void *); 102 static void dbri_softint(void *); 103 104 /* supporting subroutines */ 105 static int dbri_init(struct dbri_softc *); 106 static int dbri_reset(struct dbri_softc *); 107 static volatile uint32_t *dbri_command_lock(struct dbri_softc *); 108 static void dbri_command_send(struct dbri_softc *, volatile uint32_t *); 109 static void dbri_process_interrupt_buffer(struct dbri_softc *); 110 static void dbri_process_interrupt(struct dbri_softc *, int32_t); 111 112 /* mmcodec subroutines */ 113 static int mmcodec_init(struct dbri_softc *); 114 static void mmcodec_init_data(struct dbri_softc *); 115 static void mmcodec_pipe_init(struct dbri_softc *); 116 static void mmcodec_default(struct dbri_softc *); 117 static void mmcodec_setgain(struct dbri_softc *, int); 118 static int mmcodec_setcontrol(struct dbri_softc *); 119 120 /* chi subroutines */ 121 static void chi_reset(struct dbri_softc *, enum ms, int); 122 123 /* pipe subroutines */ 124 static void pipe_setup(struct dbri_softc *, int, int); 125 static void pipe_reset(struct dbri_softc *, int); 126 static void pipe_receive_fixed(struct dbri_softc *, int, 127 volatile uint32_t *); 128 static void pipe_transmit_fixed(struct dbri_softc *, int, uint32_t); 129 130 static void pipe_ts_link(struct dbri_softc *, int, enum io, int, int, int); 131 static int pipe_active(struct dbri_softc *, int); 132 133 /* audio(9) stuff */ 134 static int dbri_query_format(void *, audio_format_query_t *); 135 static int dbri_set_format(void *, int, 136 const audio_params_t *, const audio_params_t *, 137 audio_filter_reg_t *, audio_filter_reg_t *); 138 static int dbri_round_blocksize(void *, int, int, const audio_params_t *); 139 static int dbri_halt_output(void *); 140 static int dbri_halt_input(void *); 141 static int dbri_getdev(void *, struct audio_device *); 142 static int dbri_set_port(void *, mixer_ctrl_t *); 143 static int dbri_get_port(void *, mixer_ctrl_t *); 144 static int dbri_query_devinfo(void *, mixer_devinfo_t *); 145 static int dbri_get_props(void *); 146 static int dbri_open(void *, int); 147 static void dbri_close(void *); 148 149 static void setup_ring_xmit(struct dbri_softc *, int, int, int, int, 150 void (*)(void *), void *); 151 static void setup_ring_recv(struct dbri_softc *, int, int, int, int, 152 void (*)(void *), void *); 153 154 static int dbri_trigger_output(void *, void *, void *, int, 155 void (*)(void *), void *, const struct audio_params *); 156 static int dbri_trigger_input(void *, void *, void *, int, 157 void (*)(void *), void *, const struct audio_params *); 158 static void dbri_get_locks(void *, kmutex_t **, kmutex_t **); 159 160 static void *dbri_malloc(void *, int, size_t); 161 static void dbri_free(void *, void *, size_t); 162 static void dbri_set_power(struct dbri_softc *, int); 163 static void dbri_bring_up(struct dbri_softc *); 164 static bool dbri_suspend(device_t, const pmf_qual_t *); 165 static bool dbri_resume(device_t, const pmf_qual_t *); 166 static int dbri_commit(void *); 167 168 /* stupid support routines */ 169 static uint32_t reverse_bytes(uint32_t, int); 170 171 struct audio_device dbri_device = { 172 "CS4215", 173 "", 174 "dbri" 175 }; 176 177 struct audio_hw_if dbri_hw_if = { 178 .open = dbri_open, 179 .close = dbri_close, 180 .query_format = dbri_query_format, 181 .set_format = dbri_set_format, 182 .round_blocksize = dbri_round_blocksize, 183 .halt_output = dbri_halt_output, 184 .halt_input = dbri_halt_input, 185 .getdev = dbri_getdev, 186 .set_port = dbri_set_port, 187 .get_port = dbri_get_port, 188 .query_devinfo = dbri_query_devinfo, 189 .allocm = dbri_malloc, 190 .freem = dbri_free, 191 .get_props = dbri_get_props, 192 .trigger_output = dbri_trigger_output, 193 .trigger_input = dbri_trigger_input, 194 .get_locks = dbri_get_locks, 195 .commit_settings = dbri_commit, 196 }; 197 198 CFATTACH_DECL_NEW(dbri, sizeof(struct dbri_softc), 199 dbri_match_sbus, dbri_attach_sbus, NULL, NULL); 200 201 /* The HW actually supports more encodings/frequencies, but it's enough. */ 202 static const struct audio_format dbri_formats[] = { 203 { 204 .mode = AUMODE_PLAY | AUMODE_RECORD, 205 .encoding = AUDIO_ENCODING_SLINEAR_BE, 206 .validbits = 16, 207 .precision = 16, 208 .channels = 2, 209 .channel_mask = AUFMT_STEREO, 210 .frequency_type = 8, 211 .frequency = 212 { 8000, 9600, 11025, 16000, 22050, 32000, 44100, 48000 }, 213 }, 214 }; 215 #define DBRI_NFORMATS __arraycount(dbri_formats) 216 217 enum { 218 DBRI_OUTPUT_CLASS, 219 DBRI_VOL_OUTPUT, 220 DBRI_ENABLE_MONO, 221 DBRI_ENABLE_HEADPHONE, 222 DBRI_ENABLE_LINE, 223 DBRI_MONITOR_CLASS, 224 DBRI_VOL_MONITOR, 225 DBRI_INPUT_CLASS, 226 DBRI_INPUT_GAIN, 227 DBRI_INPUT_SELECT, 228 DBRI_RECORD_CLASS, 229 DBRI_ENUM_LAST 230 }; 231 232 /* 233 * Autoconfig routines 234 */ 235 static int 236 dbri_match_sbus(device_t parent, cfdata_t match, void *aux) 237 { 238 struct sbus_attach_args *sa = aux; 239 char *ver; 240 int i; 241 242 if (strncmp(DBRI_ROM_NAME_PREFIX, sa->sa_name, 9)) 243 return (0); 244 245 ver = &sa->sa_name[9]; 246 247 for (i = 0; dbri_supported[i][0] != '\0'; i++) 248 if (strcmp(dbri_supported[i], ver) == 0) 249 return (1); 250 251 return (0); 252 } 253 254 static void 255 dbri_attach_sbus(device_t parent, device_t self, void *aux) 256 { 257 struct dbri_softc *sc = device_private(self); 258 struct sbus_attach_args *sa = aux; 259 bus_space_handle_t ioh; 260 bus_size_t size; 261 int error, rseg, pwr, i; 262 char *ver = &sa->sa_name[9]; 263 264 sc->sc_dev = self; 265 sc->sc_iot = sa->sa_bustag; 266 sc->sc_dmat = sa->sa_dmatag; 267 sc->sc_powerstate = 1; 268 269 sc->sc_whack_codec = 0; 270 271 pwr = prom_getpropint(sa->sa_node,"pwr-on-auxio",0); 272 aprint_normal(": rev %s\n", ver); 273 274 if (pwr) { 275 /* 276 * we can control DBRI power via auxio and we're initially 277 * powered down 278 */ 279 280 sc->sc_have_powerctl = 1; 281 sc->sc_powerstate = 0; 282 dbri_set_power(sc, 1); 283 if (!pmf_device_register(self, dbri_suspend, dbri_resume)) { 284 aprint_error_dev(self, 285 "cannot set power mgmt handler\n"); 286 } 287 } else { 288 /* we can't control power so we're always up */ 289 sc->sc_have_powerctl = 0; 290 sc->sc_powerstate = 1; 291 } 292 293 for (i = 0; i < DBRI_NUM_DESCRIPTORS; i++) { 294 sc->sc_desc[i].softint = softint_establish(SOFTINT_SERIAL, 295 dbri_softint, &sc->sc_desc[i]); 296 sc->sc_desc[i].sc = sc; 297 } 298 299 if (sa->sa_npromvaddrs) 300 ioh = (bus_space_handle_t)sa->sa_promvaddrs[0]; 301 else { 302 if (sbus_bus_map(sa->sa_bustag, sa->sa_slot, 303 sa->sa_offset, sa->sa_size, 304 BUS_SPACE_MAP_LINEAR, /*0,*/ &ioh) != 0) { 305 aprint_error("%s @ sbus: cannot map registers\n", 306 device_xname(self)); 307 return; 308 } 309 } 310 311 sc->sc_ioh = ioh; 312 313 size = sizeof(struct dbri_dma); 314 315 /* get a DMA handle */ 316 if ((error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, 317 BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) { 318 aprint_error_dev(self, "DMA map create error %d\n", 319 error); 320 return; 321 } 322 323 /* allocate DMA buffer */ 324 if ((error = bus_dmamem_alloc(sc->sc_dmat, size, 0, 0, &sc->sc_dmaseg, 325 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 326 aprint_error_dev(self, "DMA buffer alloc error %d\n", 327 error); 328 return; 329 } 330 331 /* map DMA buffer into CPU addressable space */ 332 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_dmaseg, rseg, size, 333 &sc->sc_membase, 334 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 335 aprint_error_dev(self, "DMA buffer map error %d\n", 336 error); 337 return; 338 } 339 340 /* load the buffer */ 341 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, 342 sc->sc_membase, size, NULL, 343 BUS_DMA_NOWAIT)) != 0) { 344 aprint_error_dev(self, "DMA buffer map load error %d\n", 345 error); 346 bus_dmamem_unmap(sc->sc_dmat, sc->sc_membase, size); 347 bus_dmamem_free(sc->sc_dmat, &sc->sc_dmaseg, rseg); 348 return; 349 } 350 351 /* map the registers into memory */ 352 353 /* kernel virtual address of DMA buffer */ 354 sc->sc_dma = (struct dbri_dma *)sc->sc_membase; 355 /* physical address of DMA buffer */ 356 sc->sc_dmabase = sc->sc_dmamap->dm_segs[0].ds_addr; 357 sc->sc_bufsiz = size; 358 359 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_NONE); 360 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_AUDIO); 361 362 #ifndef DBRI_SPIN 363 cv_init(&sc->sc_cv, "dbricv"); 364 #endif 365 366 bus_intr_establish(sa->sa_bustag, sa->sa_pri, IPL_AUDIO, dbri_intr, 367 sc); 368 369 sc->sc_locked = 0; 370 sc->sc_desc_used = 0; 371 sc->sc_playing = 0; 372 sc->sc_recording = 0; 373 sc->sc_init_done = 0; 374 config_finalize_register(self, dbri_config_interrupts); 375 376 return; 377 } 378 379 /* 380 * lowlevel routine to switch power for the DBRI chip 381 */ 382 static void 383 dbri_set_power(struct dbri_softc *sc, int state) 384 { 385 int s; 386 387 if (sc->sc_have_powerctl == 0) 388 return; 389 if (sc->sc_powerstate == state) 390 return; 391 392 if (state) { 393 DPRINTF("%s: waiting to power up... ", 394 device_xname(sc->sc_dev)); 395 s = splhigh(); 396 *AUXIO4M_REG |= (AUXIO4M_MMX); 397 splx(s); 398 delay(10000); 399 DPRINTF("done (%02x)\n", *AUXIO4M_REG); 400 } else { 401 DPRINTF("%s: powering down\n", device_xname(sc->sc_dev)); 402 s = splhigh(); 403 *AUXIO4M_REG &= ~AUXIO4M_MMX; 404 splx(s); 405 DPRINTF("done (%02x})\n", *AUXIO4M_REG); 406 } 407 sc->sc_powerstate = state; 408 } 409 410 /* 411 * power up and re-initialize the chip 412 */ 413 static void 414 dbri_bring_up(struct dbri_softc *sc) 415 { 416 417 if (sc->sc_have_powerctl == 0) 418 return; 419 420 if (sc->sc_powerstate == 1) 421 return; 422 423 /* ok, we really need to do something */ 424 dbri_set_power(sc, 1); 425 426 /* 427 * re-initialize the chip but skip all the probing, don't overwrite 428 * any other settings either 429 */ 430 dbri_init(sc); 431 mmcodec_setgain(sc, 1); 432 mmcodec_pipe_init(sc); 433 mmcodec_init_data(sc); 434 mmcodec_setgain(sc, 0); 435 } 436 437 static int 438 dbri_config_interrupts(device_t dev) 439 { 440 struct dbri_softc *sc = device_private(dev); 441 442 mutex_spin_enter(&sc->sc_intr_lock); 443 if (sc->sc_init_done != 0) { 444 mutex_spin_exit(&sc->sc_intr_lock); 445 return 0; 446 } 447 sc->sc_init_done = 1; 448 449 dbri_init(sc); 450 451 /* talking to the codec needs working interrupts */ 452 if (mmcodec_init(sc) == -1) { 453 mutex_spin_exit(&sc->sc_intr_lock); 454 printf("%s: no codec detected, aborting\n", 455 device_xname(dev)); 456 return 0; 457 } 458 mutex_spin_exit(&sc->sc_intr_lock); 459 460 /* Attach ourselves to the high level audio interface */ 461 audio_attach_mi(&dbri_hw_if, sc, sc->sc_dev); 462 463 /* power down until open() */ 464 mutex_spin_enter(&sc->sc_intr_lock); 465 dbri_set_power(sc, 0); 466 mutex_spin_exit(&sc->sc_intr_lock); 467 468 return 0; 469 } 470 471 static int 472 dbri_intr(void *hdl) 473 { 474 struct dbri_softc *sc = hdl; 475 bus_space_tag_t iot = sc->sc_iot; 476 bus_space_handle_t ioh = sc->sc_ioh; 477 int x; 478 479 mutex_spin_enter(&sc->sc_intr_lock); 480 481 /* clear interrupt */ 482 x = bus_space_read_4(iot, ioh, DBRI_REG1); 483 if (x & (DBRI_MRR | DBRI_MLE | DBRI_LBG | DBRI_MBE)) { 484 uint32_t tmp; 485 486 if (x & DBRI_MRR) 487 aprint_debug_dev(sc->sc_dev, 488 "multiple ack error on sbus\n"); 489 if (x & DBRI_MLE) 490 aprint_debug_dev(sc->sc_dev, 491 "multiple late error on sbus\n"); 492 if (x & DBRI_LBG) 493 aprint_debug_dev(sc->sc_dev, 494 "lost bus grant on sbus\n"); 495 if (x & DBRI_MBE) 496 aprint_debug_dev(sc->sc_dev, "burst error on sbus\n"); 497 498 /* 499 * Some of these errors disable the chip's circuitry. 500 * Re-enable the circuitry and keep on going. 501 */ 502 503 tmp = bus_space_read_4(iot, ioh, DBRI_REG0); 504 tmp &= ~(DBRI_DISABLE_MASTER); 505 bus_space_write_4(iot, ioh, DBRI_REG0, tmp); 506 } 507 508 #if 0 509 if (!x & 1) /* XXX: DBRI_INTR_REQ */ 510 return (1); 511 #endif 512 513 dbri_process_interrupt_buffer(sc); 514 515 mutex_spin_exit(&sc->sc_intr_lock); 516 517 return (1); 518 } 519 520 static void 521 dbri_softint(void *cookie) 522 { 523 struct dbri_desc *dd = cookie; 524 struct dbri_softc *sc = dd->sc; 525 526 mutex_spin_enter(&sc->sc_intr_lock); 527 if (dd->callback != NULL) 528 dd->callback(dd->callback_args); 529 mutex_spin_exit(&sc->sc_intr_lock); 530 } 531 532 static int 533 dbri_init(struct dbri_softc *sc) 534 { 535 bus_space_tag_t iot = sc->sc_iot; 536 bus_space_handle_t ioh = sc->sc_ioh; 537 uint32_t reg; 538 volatile uint32_t *cmd; 539 bus_addr_t dmaaddr; 540 int n; 541 542 KASSERT(mutex_owned(&sc->sc_intr_lock)); 543 544 dbri_reset(sc); 545 sc->sc_mm.status = 0; 546 547 cmd = dbri_command_lock(sc); 548 549 /* XXX: Initialize interrupt ring buffer */ 550 sc->sc_dma->intr[0] = (uint32_t)sc->sc_dmabase + dbri_dma_off(intr, 0); 551 sc->sc_irqp = 1; 552 553 /* Initialize pipes */ 554 for (n = 0; n < DBRI_PIPE_MAX; n++) 555 sc->sc_pipe[n].desc = sc->sc_pipe[n].next = -1; 556 557 for (n = 1; n < DBRI_INT_BLOCKS; n++) { 558 sc->sc_dma->intr[n] = 0; 559 } 560 561 /* XXX 16 byte bursts cause errors, the rest works */ 562 reg = bus_space_read_4(iot, ioh, DBRI_REG0); 563 564 /*reg &= ~(DBRI_BURST_4 | DBRI_BURST_8 | DBRI_BURST_16);*/ 565 reg |= (DBRI_BURST_4 | DBRI_BURST_8); 566 bus_space_write_4(iot, ioh, DBRI_REG0, reg); 567 568 /* setup interrupt queue */ 569 dmaaddr = (uint32_t)sc->sc_dmabase + dbri_dma_off(intr, 0); 570 *(cmd++) = DBRI_CMD(DBRI_COMMAND_IIQ, 0, 0); 571 *(cmd++) = dmaaddr; 572 573 dbri_command_send(sc, cmd); 574 575 return (0); 576 } 577 578 static int 579 dbri_reset(struct dbri_softc *sc) 580 { 581 int bail = 0; 582 583 bus_space_tag_t iot = sc->sc_iot; 584 bus_space_handle_t ioh = sc->sc_ioh; 585 586 bus_space_write_4(iot, ioh, DBRI_REG0, DBRI_SOFT_RESET); 587 while ((bus_space_read_4(iot, ioh, DBRI_REG0) & DBRI_SOFT_RESET) && 588 (bail < 100000)) { 589 bail++; 590 delay(10); 591 } 592 if (bail == 100000) 593 aprint_error_dev(sc->sc_dev, "reset timed out\n"); 594 return (0); 595 } 596 597 static volatile uint32_t * 598 dbri_command_lock(struct dbri_softc *sc) 599 { 600 601 if (sc->sc_locked) 602 aprint_debug_dev(sc->sc_dev, "command buffer locked\n"); 603 604 sc->sc_locked++; 605 606 return (&sc->sc_dma->command[0]); 607 } 608 609 static void 610 dbri_command_send(struct dbri_softc *sc, volatile uint32_t *cmd) 611 { 612 bus_space_handle_t ioh = sc->sc_ioh; 613 bus_space_tag_t iot = sc->sc_iot; 614 int maxloops = 1000000; 615 616 KASSERT(mutex_owned(&sc->sc_intr_lock)); 617 618 sc->sc_locked--; 619 620 if (sc->sc_locked != 0) { 621 aprint_error_dev(sc->sc_dev, 622 "command buffer improperly locked\n"); 623 } else if ((cmd - &sc->sc_dma->command[0]) >= DBRI_NUM_COMMANDS - 1) { 624 aprint_error_dev(sc->sc_dev, "command buffer overflow\n"); 625 } else { 626 *(cmd++) = DBRI_CMD(DBRI_COMMAND_PAUSE, 0, 0); 627 *(cmd++) = DBRI_CMD(DBRI_COMMAND_WAIT, 1, 0); 628 sc->sc_waitseen = 0; 629 bus_space_write_4(iot, ioh, DBRI_REG8, sc->sc_dmabase); 630 while ((--maxloops) > 0 && 631 (bus_space_read_4(iot, ioh, DBRI_REG0) 632 & DBRI_COMMAND_VALID)) { 633 bus_space_barrier(iot, ioh, DBRI_REG0, 4, 634 BUS_SPACE_BARRIER_READ); 635 delay(1000); 636 } 637 638 if (maxloops == 0) { 639 aprint_error_dev(sc->sc_dev, 640 "chip never completed command buffer\n"); 641 } else { 642 643 DPRINTF("%s: command completed\n", 644 device_xname(sc->sc_dev)); 645 646 while ((--maxloops) > 0 && (!sc->sc_waitseen)) 647 dbri_process_interrupt_buffer(sc); 648 if (maxloops == 0) { 649 aprint_error_dev(sc->sc_dev, "chip never acked WAIT\n"); 650 } 651 } 652 } 653 654 return; 655 } 656 657 static void 658 dbri_process_interrupt_buffer(struct dbri_softc *sc) 659 { 660 int32_t i; 661 int orig_irqp = sc->sc_irqp; 662 663 KASSERT(mutex_owned(&sc->sc_intr_lock)); 664 665 while ((i = sc->sc_dma->intr[sc->sc_irqp]) != 0) { 666 sc->sc_dma->intr[sc->sc_irqp] = 0; 667 sc->sc_irqp++; 668 669 if (sc->sc_irqp == DBRI_INT_BLOCKS) 670 sc->sc_irqp = 1; 671 else if ((sc->sc_irqp & (DBRI_INT_BLOCKS - 1)) == 0) 672 sc->sc_irqp++; 673 674 dbri_process_interrupt(sc, i); 675 676 /* don't loop more than once. */ 677 if (orig_irqp == sc->sc_irqp) 678 break; 679 } 680 681 return; 682 } 683 684 static void 685 dbri_process_interrupt(struct dbri_softc *sc, int32_t i) 686 { 687 #if 0 688 const int liu_states[] = { 1, 0, 8, 3, 4, 5, 6, 7 }; 689 #endif 690 int val = DBRI_INTR_GETVAL(i); 691 int channel = DBRI_INTR_GETCHAN(i); 692 int command = DBRI_INTR_GETCMD(i); 693 int code = DBRI_INTR_GETCODE(i); 694 #if 0 695 int rval = DBRI_INTR_GETRVAL(i); 696 #endif 697 if (channel == DBRI_INTR_CMD && command == DBRI_COMMAND_WAIT) 698 sc->sc_waitseen++; 699 700 switch (code) { 701 case DBRI_INTR_XCMP: /* transmission complete */ 702 { 703 int td; 704 struct dbri_desc *dd; 705 706 DPRINTF("%s:%d tx complete\n", __func__, channel); 707 td = sc->sc_pipe[channel].desc; 708 dd = &sc->sc_desc[td]; 709 710 if (dd->callback != NULL) 711 softint_schedule(dd->softint); 712 break; 713 } 714 case DBRI_INTR_FXDT: /* fixed data change */ 715 DPRINTF("%s:%d: Fixed data change: %x\n", __func__, channel, 716 val); 717 if (sc->sc_pipe[channel].sdp & DBRI_SDP_MSB) 718 val = reverse_bytes(val, sc->sc_pipe[channel].length); 719 if (sc->sc_pipe[channel].prec) 720 *(sc->sc_pipe[channel].prec) = val; 721 #ifndef DBRI_SPIN 722 DPRINTF("%s: cv_broadcast %p\n", device_xname(sc->sc_dev), sc); 723 cv_broadcast(&sc->sc_cv); 724 #endif 725 break; 726 case DBRI_INTR_SBRI: 727 DPRINTF("dbri_intr: SBRI\n"); 728 break; 729 case DBRI_INTR_BRDY: 730 { 731 int td; 732 struct dbri_desc *dd; 733 734 DPRINTF("dbri_intr: buffer ready (%d)\n", channel); 735 td = sc->sc_pipe[channel].desc; 736 dd = &sc->sc_desc[td]; 737 738 if (dd->callback != NULL) 739 softint_schedule(dd->softint); 740 break; 741 } 742 case DBRI_INTR_UNDR: 743 { 744 volatile uint32_t *cmd; 745 int td = sc->sc_pipe[channel].desc; 746 747 DPRINTF("%s: DBRI_INTR_UNDR\n", device_xname(sc->sc_dev)); 748 749 sc->sc_dma->xmit[td].status = 0; 750 751 cmd = dbri_command_lock(sc); 752 *(cmd++) = DBRI_CMD(DBRI_COMMAND_SDP, 0, 753 sc->sc_pipe[channel].sdp | 754 DBRI_SDP_VALID_POINTER | 755 DBRI_SDP_CLEAR | 756 DBRI_SDP_2SAME); 757 *(cmd++) = sc->sc_dmabase + dbri_dma_off(xmit, td); 758 dbri_command_send(sc, cmd); 759 break; 760 } 761 case DBRI_INTR_CMDI: 762 DPRINTF("ok"); 763 break; 764 default: 765 766 aprint_error_dev(sc->sc_dev, "unknown interrupt code %d\n", 767 code); 768 break; 769 } 770 771 return; 772 } 773 774 /* 775 * mmcodec stuff 776 */ 777 778 static int 779 mmcodec_init(struct dbri_softc *sc) 780 { 781 bus_space_handle_t ioh = sc->sc_ioh; 782 bus_space_tag_t iot = sc->sc_iot; 783 uint32_t reg2; 784 int bail; 785 786 reg2 = bus_space_read_4(iot, ioh, DBRI_REG2); 787 DPRINTF("mmcodec_init: PIO reads %x\n", reg2); 788 789 if (reg2 & DBRI_PIO2) { 790 aprint_normal_dev(sc->sc_dev, " onboard CS4215 detected\n"); 791 sc->sc_mm.onboard = 1; 792 } 793 794 if (reg2 & DBRI_PIO0) { 795 aprint_normal_dev(sc->sc_dev, "speakerbox detected\n"); 796 bus_space_write_4(iot, ioh, DBRI_REG2, DBRI_PIO2_ENABLE); 797 sc->sc_mm.onboard = 0; 798 } 799 800 if ((reg2 & DBRI_PIO2) && (reg2 & DBRI_PIO0)) { 801 aprint_normal_dev(sc->sc_dev, "using speakerbox\n"); 802 bus_space_write_4(iot, ioh, DBRI_REG2, DBRI_PIO2_ENABLE); 803 sc->sc_mm.onboard = 0; 804 } 805 806 if (!(reg2 & (DBRI_PIO0|DBRI_PIO2))) { 807 aprint_normal_dev(sc->sc_dev, "no mmcodec found\n"); 808 return -1; 809 } 810 811 sc->sc_version = 0xff; 812 813 mmcodec_pipe_init(sc); 814 mmcodec_default(sc); 815 816 sc->sc_mm.offset = sc->sc_mm.onboard ? 0 : 8; 817 818 /* 819 * mmcodec_setcontrol() sometimes fails right after powerup 820 * so we just try again until we either get a useful response or run 821 * out of time 822 */ 823 bail = 0; 824 while (mmcodec_setcontrol(sc) == -1 || sc->sc_version == 0xff) { 825 826 bail++; 827 if (bail > 100) { 828 DPRINTF("%s: cs4215 probe failed at offset %d\n", 829 device_xname(sc->sc_dev), sc->sc_mm.offset); 830 return (-1); 831 } 832 delay(10000); 833 } 834 835 aprint_normal_dev(sc->sc_dev, "cs4215 rev %c found at offset %d\n", 836 0x43 + (sc->sc_version & 0xf), sc->sc_mm.offset); 837 838 /* set some sane defaults for mmcodec_init_data */ 839 sc->sc_params.channels = 2; 840 sc->sc_params.precision = 16; 841 842 mmcodec_init_data(sc); 843 844 return (0); 845 } 846 847 static void 848 mmcodec_init_data(struct dbri_softc *sc) 849 { 850 bus_space_tag_t iot = sc->sc_iot; 851 bus_space_handle_t ioh = sc->sc_ioh; 852 uint32_t tmp; 853 int data_width; 854 855 tmp = bus_space_read_4(iot, ioh, DBRI_REG0); 856 tmp &= ~(DBRI_CHI_ACTIVATE); /* disable CHI */ 857 bus_space_write_4(iot, ioh, DBRI_REG0, tmp); 858 859 /* switch CS4215 to data mode - set PIO3 to 1 */ 860 tmp = DBRI_PIO_ENABLE_ALL | DBRI_PIO1 | DBRI_PIO3; 861 862 /* XXX */ 863 tmp |= (sc->sc_mm.onboard ? DBRI_PIO0 : DBRI_PIO2); 864 865 bus_space_write_4(iot, ioh, DBRI_REG2, tmp); 866 chi_reset(sc, CHIslave, 128); 867 868 data_width = sc->sc_params.channels * sc->sc_params.precision; 869 870 if ((data_width != 32) && (data_width != 8)) 871 aprint_error("%s: data_width is %d\n", __func__, data_width); 872 873 pipe_ts_link(sc, 20, PIPEoutput, 16, 32, sc->sc_mm.offset + 32); 874 pipe_ts_link(sc, 4, PIPEoutput, 16, data_width, sc->sc_mm.offset); 875 pipe_ts_link(sc, 6, PIPEinput, 16, data_width, sc->sc_mm.offset); 876 #if 0 877 /* readback for the mixer registers - we don't use that */ 878 pipe_ts_link(sc, 21, PIPEinput, 16, 32, sc->sc_mm.offset + 32); 879 880 pipe_receive_fixed(sc, 21, &sc->sc_mm.d.ldata); 881 #endif 882 mmcodec_setgain(sc, 0); 883 884 tmp = bus_space_read_4(iot, ioh, DBRI_REG0); 885 tmp |= DBRI_CHI_ACTIVATE; 886 bus_space_write_4(iot, ioh, DBRI_REG0, tmp); 887 888 return; 889 } 890 891 static void 892 mmcodec_pipe_init(struct dbri_softc *sc) 893 { 894 895 pipe_setup(sc, 4, DBRI_SDP_MEM | DBRI_SDP_TO_SER | DBRI_SDP_MSB); 896 pipe_setup(sc, 20, DBRI_SDP_FIXED | DBRI_SDP_TO_SER | DBRI_SDP_MSB); 897 pipe_setup(sc, 6, DBRI_SDP_MEM | DBRI_SDP_FROM_SER | DBRI_SDP_MSB); 898 #if 0 899 pipe_setup(sc, 21, DBRI_SDP_FIXED | DBRI_SDP_FROM_SER | DBRI_SDP_MSB); 900 #endif 901 pipe_setup(sc, 17, DBRI_SDP_FIXED | DBRI_SDP_TO_SER | DBRI_SDP_MSB); 902 pipe_setup(sc, 18, DBRI_SDP_FIXED | DBRI_SDP_FROM_SER | DBRI_SDP_MSB); 903 pipe_setup(sc, 19, DBRI_SDP_FIXED | DBRI_SDP_FROM_SER | DBRI_SDP_MSB); 904 905 pipe_receive_fixed(sc, 18, &sc->sc_mm.status); 906 pipe_receive_fixed(sc, 19, &sc->sc_mm.version); 907 908 return; 909 } 910 911 static void 912 mmcodec_default(struct dbri_softc *sc) 913 { 914 struct cs4215_state *mm = &sc->sc_mm; 915 916 /* 917 * no action, memory resetting only 918 * 919 * data time slots 5-8 920 * speaker, line and headphone enable. set gain to half. 921 * input is line 922 */ 923 mm->d.bdata[0] = sc->sc_latt = 0x20 | CS4215_HE | CS4215_LE; 924 mm->d.bdata[1] = sc->sc_ratt = 0x20 | CS4215_SE; 925 sc->sc_linp = 128; 926 sc->sc_rinp = 128; 927 sc->sc_monitor = 0; 928 sc->sc_input = 1; /* line */ 929 mm->d.bdata[2] = (CS4215_LG((sc->sc_linp >> 4)) & 0x0f) | 930 ((sc->sc_input == 2) ? CS4215_IS : 0) | CS4215_PIO0 | CS4215_PIO1; 931 mm->d.bdata[3] = (CS4215_RG((sc->sc_rinp >> 4) & 0x0f)) | 932 CS4215_MA(15 - ((sc->sc_monitor >> 4) & 0x0f)); 933 934 935 /* 936 * control time slots 1-4 937 * 938 * 0: default I/O voltage scale 939 * 1: 8 bit ulaw, 8kHz, mono, high pass filter disabled 940 * 2: serial enable, CHI master, 128 bits per frame, clock 1 941 * 3: tests disabled 942 */ 943 mm->c.bcontrol[0] = CS4215_ONE | CS4215_MLB; 944 mm->c.bcontrol[1] = CS4215_DFR_ULAW | CS4215_FREQ[0].csval; 945 mm->c.bcontrol[2] = CS4215_XCLK | CS4215_BSEL_128 | CS4215_FREQ[0].xtal; 946 mm->c.bcontrol[3] = 0; 947 948 return; 949 } 950 951 static void 952 mmcodec_setgain(struct dbri_softc *sc, int mute) 953 { 954 if (mute) { 955 /* disable all outputs, max. attenuation */ 956 sc->sc_mm.d.bdata[0] = sc->sc_latt | 63; 957 sc->sc_mm.d.bdata[1] = sc->sc_ratt | 63; 958 } else { 959 960 sc->sc_mm.d.bdata[0] = sc->sc_latt; 961 sc->sc_mm.d.bdata[1] = sc->sc_ratt; 962 } 963 964 /* input stuff */ 965 sc->sc_mm.d.bdata[2] = CS4215_LG((sc->sc_linp >> 4) & 0x0f) | 966 ((sc->sc_input == 2) ? CS4215_IS : 0) | CS4215_PIO0 | CS4215_PIO1; 967 sc->sc_mm.d.bdata[3] = (CS4215_RG((sc->sc_rinp >> 4)) & 0x0f) | 968 (CS4215_MA(15 - ((sc->sc_monitor >> 4) & 0x0f))); 969 970 if (sc->sc_powerstate == 0) 971 return; 972 pipe_transmit_fixed(sc, 20, sc->sc_mm.d.ldata); 973 974 DPRINTF("mmcodec_setgain: %08x\n", sc->sc_mm.d.ldata); 975 /* give the chip some time to execute the command */ 976 delay(250); 977 978 return; 979 } 980 981 static int 982 mmcodec_setcontrol(struct dbri_softc *sc) 983 { 984 bus_space_tag_t iot = sc->sc_iot; 985 bus_space_handle_t ioh = sc->sc_ioh; 986 uint32_t val; 987 uint32_t tmp; 988 int ret = 0; 989 #ifdef DBRI_SPIN 990 int i; 991 #else 992 int error, bail = 0; 993 #endif 994 995 KASSERT(mutex_owned(&sc->sc_intr_lock)); 996 997 /* 998 * Temporarily mute outputs and wait 125 us to make sure that it 999 * happens. This avoids clicking noises. 1000 */ 1001 mmcodec_setgain(sc, 1); 1002 delay(125); 1003 1004 tmp = bus_space_read_4(iot, ioh, DBRI_REG0); 1005 tmp &= ~(DBRI_CHI_ACTIVATE); /* disable CHI */ 1006 bus_space_write_4(iot, ioh, DBRI_REG0, tmp); 1007 1008 bus_space_write_4(iot, ioh, DBRI_REG2, 0); 1009 delay(125); 1010 1011 /* enable control mode */ 1012 val = DBRI_PIO_ENABLE_ALL | DBRI_PIO1; /* was PIO1 */ 1013 1014 /* XXX */ 1015 val |= (sc->sc_mm.onboard ? DBRI_PIO0 : DBRI_PIO2); 1016 1017 bus_space_write_4(iot, ioh, DBRI_REG2, val); 1018 delay(34); 1019 1020 /* 1021 * in control mode, the cs4215 is the slave device, so the 1022 * DBRI must act as the CHI master. 1023 * 1024 * in data mode, the cs4215 must be the CHI master to insure 1025 * that the data stream is in sync with its codec 1026 */ 1027 tmp = bus_space_read_4(iot, ioh, DBRI_REG0); 1028 tmp &= ~DBRI_COMMAND_CHI; 1029 bus_space_write_4(iot, ioh, DBRI_REG0, tmp); 1030 1031 chi_reset(sc, CHImaster, 128); 1032 1033 /* control mode */ 1034 pipe_ts_link(sc, 17, PIPEoutput, 16, 32, sc->sc_mm.offset); 1035 pipe_ts_link(sc, 18, PIPEinput, 16, 8, sc->sc_mm.offset); 1036 pipe_ts_link(sc, 19, PIPEinput, 16, 8, sc->sc_mm.offset + 48); 1037 1038 pipe_receive_fixed(sc, 18, &sc->sc_mm.status); 1039 1040 /* wait for the chip to echo back CLB as zero */ 1041 sc->sc_mm.c.bcontrol[0] &= ~CS4215_CLB; 1042 pipe_transmit_fixed(sc, 17, sc->sc_mm.c.lcontrol); 1043 1044 tmp = bus_space_read_4(iot, ioh, DBRI_REG0); 1045 tmp |= DBRI_CHI_ACTIVATE; 1046 bus_space_write_4(iot, ioh, DBRI_REG0, tmp); 1047 1048 #ifdef DBRI_SPIN 1049 i = 1024; 1050 while (((sc->sc_mm.status & 0xe4) != CS4215_ONE) && (i > 0)) { 1051 i--; 1052 delay(125); 1053 } 1054 1055 if (i == 0) { 1056 DPRINTF("%s: cs4215 didn't respond to CLB (0x%02x)\n", 1057 device_xname(sc->sc_dev), sc->sc_mm.status); 1058 ret = -1; 1059 goto fail; 1060 } 1061 #else 1062 while (((sc->sc_mm.status & 0xe4) != CS4215_ONE) && (bail < 10)) { 1063 DPRINTF("%s: cv_wait_sig %p\n", device_xname(sc->sc_dev), sc); 1064 error = cv_timedwait_sig(&sc->sc_cv, &sc->sc_intr_lock, hz); 1065 if (error == EINTR) { 1066 DPRINTF("%s: interrupted\n", device_xname(sc->sc_dev)); 1067 ret = -1; 1068 mutex_spin_exit(&sc->sc_intr_lock); 1069 goto fail; 1070 } 1071 bail++; 1072 } 1073 if (bail >= 10) { 1074 aprint_error("%s: switching to control mode timed out (%x %x)\n", 1075 device_xname(sc->sc_dev), sc->sc_mm.status, 1076 bus_space_read_4(iot, ioh, DBRI_REG2)); 1077 ret = -1; 1078 goto fail; 1079 } 1080 #endif 1081 1082 /* copy the version information before it becomes unreadable again */ 1083 sc->sc_version = sc->sc_mm.version; 1084 sc->sc_whack_codec = 0; 1085 1086 fail: 1087 /* terminate cs4215 control mode */ 1088 sc->sc_mm.c.bcontrol[0] |= CS4215_CLB; 1089 pipe_transmit_fixed(sc, 17, sc->sc_mm.c.lcontrol); 1090 1091 /* two frames of control info @ 8kHz frame rate = 250us delay */ 1092 delay(250); 1093 1094 mmcodec_setgain(sc, 0); 1095 1096 return ret; 1097 1098 } 1099 1100 /* 1101 * CHI combo 1102 */ 1103 static void 1104 chi_reset(struct dbri_softc *sc, enum ms ms, int bpf) 1105 { 1106 volatile uint32_t *cmd; 1107 int val; 1108 int clockrate, divisor; 1109 1110 cmd = dbri_command_lock(sc); 1111 1112 /* set CHI anchor: pipe 16 */ 1113 val = DBRI_DTS_VI | DBRI_DTS_INS | DBRI_DTS_PRVIN(16) | DBRI_PIPE(16); 1114 *(cmd++) = DBRI_CMD(DBRI_COMMAND_DTS, 0, val); 1115 *(cmd++) = DBRI_TS_ANCHOR | DBRI_TS_NEXT(16); 1116 *(cmd++) = 0; 1117 1118 val = DBRI_DTS_VO | DBRI_DTS_INS | DBRI_DTS_PRVOUT(16) | DBRI_PIPE(16); 1119 *(cmd++) = DBRI_CMD(DBRI_COMMAND_DTS, 0, val); 1120 *(cmd++) = 0; 1121 *(cmd++) = DBRI_TS_ANCHOR | DBRI_TS_NEXT(16); 1122 1123 sc->sc_pipe[16].sdp = 1; 1124 sc->sc_pipe[16].next = 16; 1125 sc->sc_chi_pipe_in = 16; 1126 sc->sc_chi_pipe_out = 16; 1127 1128 switch (ms) { 1129 case CHIslave: 1130 *(cmd++) = DBRI_CMD(DBRI_COMMAND_CHI, 0, DBRI_CHI_CHICM(0)); 1131 break; 1132 case CHImaster: 1133 clockrate = bpf * 8; 1134 divisor = 12288 / clockrate; 1135 1136 if (divisor > 255 || divisor * clockrate != 12288) 1137 aprint_error_dev(sc->sc_dev, 1138 "illegal bits-per-frame %d\n", bpf); 1139 1140 *(cmd++) = DBRI_CMD(DBRI_COMMAND_CHI, 0, 1141 DBRI_CHI_CHICM(divisor) | DBRI_CHI_FD | DBRI_CHI_BPF(bpf)); 1142 break; 1143 default: 1144 aprint_error_dev(sc->sc_dev, "unknown value for ms!\n"); 1145 break; 1146 } 1147 1148 sc->sc_chi_bpf = bpf; 1149 1150 /* CHI data mode */ 1151 *(cmd++) = DBRI_CMD(DBRI_COMMAND_PAUSE, 0, 0); 1152 *(cmd++) = DBRI_CMD(DBRI_COMMAND_CDM, 0, 1153 DBRI_CDM_XCE | DBRI_CDM_XEN | DBRI_CDM_REN); 1154 1155 dbri_command_send(sc, cmd); 1156 1157 return; 1158 } 1159 1160 /* 1161 * pipe stuff 1162 */ 1163 static void 1164 pipe_setup(struct dbri_softc *sc, int pipe, int sdp) 1165 { 1166 DPRINTF("pipe setup: %d\n", pipe); 1167 if (pipe < 0 || pipe >= DBRI_PIPE_MAX) { 1168 aprint_error_dev(sc->sc_dev, "illegal pipe number %d\n", 1169 pipe); 1170 return; 1171 } 1172 1173 if ((sdp & 0xf800) != sdp) 1174 aprint_error_dev(sc->sc_dev, "strange SDP value %d\n", 1175 sdp); 1176 1177 if (DBRI_SDP_MODE(sdp) == DBRI_SDP_FIXED && 1178 !(sdp & DBRI_SDP_TO_SER)) 1179 sdp |= DBRI_SDP_CHANGE; 1180 1181 sdp |= DBRI_PIPE(pipe); 1182 1183 sc->sc_pipe[pipe].sdp = sdp; 1184 sc->sc_pipe[pipe].desc = -1; 1185 1186 pipe_reset(sc, pipe); 1187 1188 return; 1189 } 1190 1191 static void 1192 pipe_reset(struct dbri_softc *sc, int pipe) 1193 { 1194 struct dbri_desc *dd; 1195 int sdp; 1196 int desc; 1197 volatile uint32_t *cmd; 1198 1199 if (pipe < 0 || pipe >= DBRI_PIPE_MAX) { 1200 aprint_error_dev(sc->sc_dev, "illegal pipe number %d\n", 1201 pipe); 1202 return; 1203 } 1204 1205 sdp = sc->sc_pipe[pipe].sdp; 1206 if (sdp == 0) { 1207 aprint_error_dev(sc->sc_dev, "can not reset uninitialized pipe %d\n", 1208 pipe); 1209 return; 1210 } 1211 1212 cmd = dbri_command_lock(sc); 1213 *(cmd++) = DBRI_CMD(DBRI_COMMAND_SDP, 0, 1214 sdp | DBRI_SDP_CLEAR | DBRI_SDP_VALID_POINTER); 1215 *(cmd++) = 0; 1216 dbri_command_send(sc, cmd); 1217 1218 desc = sc->sc_pipe[pipe].desc; 1219 1220 dd = &sc->sc_desc[desc]; 1221 1222 dd->busy = 0; 1223 1224 #if 0 1225 if (dd->callback) 1226 softint_schedule(dd->softint); 1227 #endif 1228 1229 sc->sc_pipe[pipe].desc = -1; 1230 1231 return; 1232 } 1233 1234 static void 1235 pipe_receive_fixed(struct dbri_softc *sc, int pipe, volatile uint32_t *prec) 1236 { 1237 1238 if (pipe < DBRI_PIPE_MAX / 2 || pipe >= DBRI_PIPE_MAX) { 1239 aprint_error_dev(sc->sc_dev, "illegal pipe number %d\n", 1240 pipe); 1241 return; 1242 } 1243 1244 if (DBRI_SDP_MODE(sc->sc_pipe[pipe].sdp) != DBRI_SDP_FIXED) { 1245 aprint_error_dev(sc->sc_dev, "non-fixed pipe %d\n", 1246 pipe); 1247 return; 1248 } 1249 1250 if (sc->sc_pipe[pipe].sdp & DBRI_SDP_TO_SER) { 1251 aprint_error_dev(sc->sc_dev, "can not receive on transmit pipe %d\b", 1252 pipe); 1253 return; 1254 } 1255 1256 sc->sc_pipe[pipe].prec = prec; 1257 1258 return; 1259 } 1260 1261 static void 1262 pipe_transmit_fixed(struct dbri_softc *sc, int pipe, uint32_t data) 1263 { 1264 volatile uint32_t *cmd; 1265 1266 if (pipe < DBRI_PIPE_MAX / 2 || pipe >= DBRI_PIPE_MAX) { 1267 aprint_error_dev(sc->sc_dev, "illegal pipe number %d\n", 1268 pipe); 1269 return; 1270 } 1271 1272 if (DBRI_SDP_MODE(sc->sc_pipe[pipe].sdp) == 0) { 1273 aprint_error_dev(sc->sc_dev, "uninitialized pipe %d\n", 1274 pipe); 1275 return; 1276 } 1277 1278 if (DBRI_SDP_MODE(sc->sc_pipe[pipe].sdp) != DBRI_SDP_FIXED) { 1279 aprint_error_dev(sc->sc_dev, "non-fixed pipe %d\n", 1280 pipe); 1281 return; 1282 } 1283 1284 if (!(sc->sc_pipe[pipe].sdp & DBRI_SDP_TO_SER)) { 1285 aprint_error_dev(sc->sc_dev, "called on receive pipe %d\n", 1286 pipe); 1287 return; 1288 } 1289 1290 if (sc->sc_pipe[pipe].sdp & DBRI_SDP_MSB) 1291 data = reverse_bytes(data, sc->sc_pipe[pipe].length); 1292 1293 cmd = dbri_command_lock(sc); 1294 *(cmd++) = DBRI_CMD(DBRI_COMMAND_SSP, 0, pipe); 1295 *(cmd++) = data; 1296 1297 dbri_command_send(sc, cmd); 1298 1299 return; 1300 } 1301 1302 static void 1303 setup_ring_xmit(struct dbri_softc *sc, int pipe, int which, int num, int blksz, 1304 void (*callback)(void *), void *callback_args) 1305 { 1306 volatile uint32_t *cmd; 1307 int i; 1308 #if 0 1309 int td; 1310 int td_first, td_last; 1311 #endif 1312 bus_addr_t dmabuf, dmabase; 1313 struct dbri_desc *dd = &sc->sc_desc[which]; 1314 1315 switch (pipe) { 1316 case 4: 1317 /* output, offset 0 */ 1318 break; 1319 default: 1320 aprint_error("%s: illegal pipe number (%d)\n", 1321 __func__, pipe); 1322 return; 1323 } 1324 1325 #if 0 1326 td = 0; 1327 td_first = td_last = -1; 1328 #endif 1329 1330 if (sc->sc_pipe[pipe].sdp == 0) { 1331 aprint_error_dev(sc->sc_dev, "uninitialized pipe %d\n", 1332 pipe); 1333 return; 1334 } 1335 1336 dmabuf = dd->dmabase; 1337 dmabase = sc->sc_dmabase; 1338 1339 for (i = 0; i < (num - 1); i++) { 1340 1341 sc->sc_dma->xmit[i].flags = TX_BCNT(blksz) 1342 | TX_EOF | TX_BINT; 1343 sc->sc_dma->xmit[i].ba = dmabuf; 1344 sc->sc_dma->xmit[i].nda = dmabase + dbri_dma_off(xmit, i + 1); 1345 sc->sc_dma->xmit[i].status = 0; 1346 1347 #if 0 1348 td_last = td; 1349 #endif 1350 dmabuf += blksz; 1351 } 1352 1353 sc->sc_dma->xmit[i].flags = TX_BCNT(blksz) | TX_EOF | TX_BINT; 1354 1355 sc->sc_dma->xmit[i].ba = dmabuf; 1356 sc->sc_dma->xmit[i].nda = dmabase + dbri_dma_off(xmit, 0); 1357 sc->sc_dma->xmit[i].status = 0; 1358 1359 dd->callback = callback; 1360 dd->callback_args = callback_args; 1361 1362 /* the pipe shouldn't be active */ 1363 if (pipe_active(sc, pipe)) { 1364 aprint_error("pipe active (CDP)\n"); 1365 /* pipe is already active */ 1366 #if 0 1367 td_last = sc->sc_pipe[pipe].desc; 1368 while (sc->sc_desc[td_last].next != -1) 1369 td_last = sc->sc_desc[td_last].next; 1370 1371 sc->sc_desc[td_last].next = td_first; 1372 sc->sc_dma->desc[td_last].nda = 1373 sc->sc_dmabase + dbri_dma_off(desc, td_first); 1374 1375 cmd = dbri_command_lock(sc); 1376 *(cmd++) = DBRI_CMD(DBRI_COMMAND_CDP, 0, pipe); 1377 dbri_command_send(sc, cmd); 1378 #endif 1379 } else { 1380 /* 1381 * pipe isn't active - issue an SDP command to start our 1382 * chain of TDs running 1383 */ 1384 sc->sc_pipe[pipe].desc = which; 1385 cmd = dbri_command_lock(sc); 1386 *(cmd++) = DBRI_CMD(DBRI_COMMAND_SDP, 0, 1387 sc->sc_pipe[pipe].sdp | 1388 DBRI_SDP_VALID_POINTER | 1389 DBRI_SDP_EVERY | 1390 DBRI_SDP_CLEAR); 1391 *(cmd++) = sc->sc_dmabase + dbri_dma_off(xmit, 0); 1392 dbri_command_send(sc, cmd); 1393 DPRINTF("%s: starting DMA\n", __func__); 1394 } 1395 1396 return; 1397 } 1398 1399 static void 1400 setup_ring_recv(struct dbri_softc *sc, int pipe, int which, int num, int blksz, 1401 void (*callback)(void *), void *callback_args) 1402 { 1403 volatile uint32_t *cmd; 1404 int i; 1405 #if 0 1406 int td_first, td_last; 1407 #endif 1408 bus_addr_t dmabuf, dmabase; 1409 struct dbri_desc *dd = &sc->sc_desc[which]; 1410 1411 switch (pipe) { 1412 case 6: 1413 break; 1414 default: 1415 aprint_error("%s: illegal pipe number (%d)\n", 1416 __func__, pipe); 1417 return; 1418 } 1419 1420 #if 0 1421 td_first = td_last = -1; 1422 #endif 1423 1424 if (sc->sc_pipe[pipe].sdp == 0) { 1425 aprint_error_dev(sc->sc_dev, "uninitialized pipe %d\n", 1426 pipe); 1427 return; 1428 } 1429 1430 dmabuf = dd->dmabase; 1431 dmabase = sc->sc_dmabase; 1432 1433 for (i = 0; i < (num - 1); i++) { 1434 1435 sc->sc_dma->recv[i].flags = RX_BSIZE(blksz) | RX_FINAL; 1436 sc->sc_dma->recv[i].ba = dmabuf; 1437 sc->sc_dma->recv[i].nda = dmabase + dbri_dma_off(recv, i + 1); 1438 sc->sc_dma->recv[i].status = RX_EOF; 1439 1440 #if 0 1441 td_last = i; 1442 #endif 1443 dmabuf += blksz; 1444 } 1445 1446 sc->sc_dma->recv[i].flags = RX_BSIZE(blksz) | RX_FINAL; 1447 1448 sc->sc_dma->recv[i].ba = dmabuf; 1449 sc->sc_dma->recv[i].nda = dmabase + dbri_dma_off(recv, 0); 1450 sc->sc_dma->recv[i].status = RX_EOF; 1451 1452 dd->callback = callback; 1453 dd->callback_args = callback_args; 1454 1455 /* the pipe shouldn't be active */ 1456 if (pipe_active(sc, pipe)) { 1457 aprint_error("pipe active (CDP)\n"); 1458 /* pipe is already active */ 1459 #if 0 1460 td_last = sc->sc_pipe[pipe].desc; 1461 while (sc->sc_desc[td_last].next != -1) 1462 td_last = sc->sc_desc[td_last].next; 1463 1464 sc->sc_desc[td_last].next = td_first; 1465 sc->sc_dma->desc[td_last].nda = 1466 sc->sc_dmabase + dbri_dma_off(desc, td_first); 1467 1468 cmd = dbri_command_lock(sc); 1469 *(cmd++) = DBRI_CMD(DBRI_COMMAND_CDP, 0, pipe); 1470 dbri_command_send(sc, cmd); 1471 #endif 1472 } else { 1473 /* 1474 * pipe isn't active - issue an SDP command to start our 1475 * chain of TDs running 1476 */ 1477 sc->sc_pipe[pipe].desc = which; 1478 cmd = dbri_command_lock(sc); 1479 *(cmd++) = DBRI_CMD(DBRI_COMMAND_SDP, 0, 1480 sc->sc_pipe[pipe].sdp | 1481 DBRI_SDP_VALID_POINTER | 1482 DBRI_SDP_EVERY | 1483 DBRI_SDP_CLEAR); 1484 *(cmd++) = sc->sc_dmabase + dbri_dma_off(recv, 0); 1485 dbri_command_send(sc, cmd); 1486 DPRINTF("%s: starting DMA\n", __func__); 1487 } 1488 1489 return; 1490 } 1491 1492 static void 1493 pipe_ts_link(struct dbri_softc *sc, int pipe, enum io dir, int basepipe, 1494 int len, int cycle) 1495 { 1496 volatile uint32_t *cmd; 1497 int prevpipe, nextpipe; 1498 int val; 1499 1500 DPRINTF("%s: %d\n", __func__, pipe); 1501 if (pipe < 0 || pipe >= DBRI_PIPE_MAX || 1502 basepipe < 0 || basepipe >= DBRI_PIPE_MAX) { 1503 aprint_error_dev(sc->sc_dev, "illegal pipe numbers (%d, %d)\n", 1504 pipe, basepipe); 1505 return; 1506 } 1507 1508 if (sc->sc_pipe[pipe].sdp == 0 || sc->sc_pipe[basepipe].sdp == 0) { 1509 aprint_error_dev(sc->sc_dev, "uninitialized pipe (%d, %d)\n", 1510 pipe, basepipe); 1511 return; 1512 } 1513 1514 if (basepipe == 16 && dir == PIPEoutput && cycle == 0) 1515 cycle = sc->sc_chi_bpf; 1516 1517 if (basepipe == pipe) 1518 prevpipe = nextpipe = pipe; 1519 else { 1520 if (basepipe == 16) { 1521 if (dir == PIPEinput) { 1522 prevpipe = sc->sc_chi_pipe_in; 1523 } else { 1524 prevpipe = sc->sc_chi_pipe_out; 1525 } 1526 } else 1527 prevpipe = basepipe; 1528 1529 nextpipe = sc->sc_pipe[prevpipe].next; 1530 1531 while (sc->sc_pipe[nextpipe].cycle < cycle && 1532 sc->sc_pipe[nextpipe].next != basepipe) { 1533 prevpipe = nextpipe; 1534 nextpipe = sc->sc_pipe[nextpipe].next; 1535 } 1536 } 1537 1538 if (prevpipe == 16) { 1539 if (dir == PIPEinput) { 1540 sc->sc_chi_pipe_in = pipe; 1541 } else { 1542 sc->sc_chi_pipe_out = pipe; 1543 } 1544 } else 1545 sc->sc_pipe[prevpipe].next = pipe; 1546 1547 sc->sc_pipe[pipe].next = nextpipe; 1548 sc->sc_pipe[pipe].cycle = cycle; 1549 sc->sc_pipe[pipe].length = len; 1550 1551 cmd = dbri_command_lock(sc); 1552 1553 switch (dir) { 1554 case PIPEinput: 1555 val = DBRI_DTS_VI | DBRI_DTS_INS | DBRI_DTS_PRVIN(prevpipe); 1556 val |= pipe; 1557 *(cmd++) = DBRI_CMD(DBRI_COMMAND_DTS, 0, val); 1558 *(cmd++) = DBRI_TS_LEN(len) | DBRI_TS_CYCLE(cycle) | 1559 DBRI_TS_NEXT(nextpipe); 1560 *(cmd++) = 0; 1561 break; 1562 case PIPEoutput: 1563 val = DBRI_DTS_VO | DBRI_DTS_INS | DBRI_DTS_PRVOUT(prevpipe); 1564 val |= pipe; 1565 *(cmd++) = DBRI_CMD(DBRI_COMMAND_DTS, 0, val); 1566 *(cmd++) = 0; 1567 *(cmd++) = DBRI_TS_LEN(len) | DBRI_TS_CYCLE(cycle) | 1568 DBRI_TS_NEXT(nextpipe); 1569 break; 1570 default: 1571 DPRINTF("%s: should not have happened!\n", 1572 device_xname(sc->sc_dev)); 1573 break; 1574 } 1575 1576 dbri_command_send(sc, cmd); 1577 1578 return; 1579 } 1580 1581 static int 1582 pipe_active(struct dbri_softc *sc, int pipe) 1583 { 1584 1585 return (sc->sc_pipe[pipe].desc != -1); 1586 } 1587 1588 /* 1589 * subroutines required to interface with audio(9) 1590 */ 1591 1592 static int 1593 dbri_query_format(void *hdl, audio_format_query_t *afp) 1594 { 1595 1596 return audio_query_format(dbri_formats, DBRI_NFORMATS, afp); 1597 } 1598 1599 static int 1600 dbri_set_format(void *hdl, int setmode, 1601 const audio_params_t *play, const audio_params_t *rec, 1602 audio_filter_reg_t *pfil, audio_filter_reg_t *rfil) 1603 { 1604 struct dbri_softc *sc = hdl; 1605 int rate; 1606 1607 /* *play and *rec are the identical because !AUDIO_PROP_INDEPENDENT. */ 1608 1609 for (rate = 0; CS4215_FREQ[rate].freq; rate++) 1610 if (CS4215_FREQ[rate].freq == play->sample_rate) 1611 break; 1612 1613 if (CS4215_FREQ[rate].freq == 0) 1614 return EINVAL; 1615 1616 /* set frequency */ 1617 sc->sc_mm.c.bcontrol[1] &= ~0x38; 1618 sc->sc_mm.c.bcontrol[1] |= CS4215_FREQ[rate].csval; 1619 sc->sc_mm.c.bcontrol[2] &= ~0x70; 1620 sc->sc_mm.c.bcontrol[2] |= CS4215_FREQ[rate].xtal; 1621 1622 /* set encoding */ 1623 sc->sc_mm.c.bcontrol[1] &= ~3; 1624 sc->sc_mm.c.bcontrol[1] |= CS4215_DFR_LINEAR16; 1625 1626 /* set channel */ 1627 sc->sc_mm.c.bcontrol[1] |= CS4215_DFR_STEREO; 1628 1629 sc->sc_whack_codec = 1; 1630 return 0; 1631 } 1632 1633 static int 1634 dbri_round_blocksize(void *hdl, int bs, int mode, 1635 const audio_params_t *param) 1636 { 1637 1638 if (bs > 0x1ffc) 1639 return 0x1ffc; 1640 return bs; 1641 } 1642 1643 static int 1644 dbri_halt_output(void *hdl) 1645 { 1646 struct dbri_softc *sc = hdl; 1647 1648 if (!sc->sc_playing) 1649 return 0; 1650 1651 sc->sc_playing = 0; 1652 pipe_reset(sc, 4); 1653 return (0); 1654 } 1655 1656 static int 1657 dbri_getdev(void *hdl, struct audio_device *ret) 1658 { 1659 1660 *ret = dbri_device; 1661 return (0); 1662 } 1663 1664 static int 1665 dbri_set_port(void *hdl, mixer_ctrl_t *mc) 1666 { 1667 struct dbri_softc *sc = hdl; 1668 int latt = sc->sc_latt, ratt = sc->sc_ratt; 1669 1670 switch (mc->dev) { 1671 case DBRI_VOL_OUTPUT: /* master volume */ 1672 latt = (latt & 0xc0) | (63 - 1673 uimin(mc->un.value.level[AUDIO_MIXER_LEVEL_LEFT] >> 2, 63)); 1674 ratt = (ratt & 0xc0) | (63 - 1675 uimin(mc->un.value.level[AUDIO_MIXER_LEVEL_RIGHT] >> 2, 63)); 1676 break; 1677 case DBRI_ENABLE_MONO: /* built-in speaker */ 1678 if (mc->un.ord == 1) { 1679 ratt |= CS4215_SE; 1680 } else 1681 ratt &= ~CS4215_SE; 1682 break; 1683 case DBRI_ENABLE_HEADPHONE: /* headphones output */ 1684 if (mc->un.ord == 1) { 1685 latt |= CS4215_HE; 1686 } else 1687 latt &= ~CS4215_HE; 1688 break; 1689 case DBRI_ENABLE_LINE: /* line out */ 1690 if (mc->un.ord == 1) { 1691 latt |= CS4215_LE; 1692 } else 1693 latt &= ~CS4215_LE; 1694 break; 1695 case DBRI_VOL_MONITOR: 1696 if (mc->un.value.level[AUDIO_MIXER_LEVEL_LEFT] == 1697 sc->sc_monitor) 1698 return 0; 1699 sc->sc_monitor = mc->un.value.level[AUDIO_MIXER_LEVEL_LEFT]; 1700 break; 1701 case DBRI_INPUT_GAIN: 1702 sc->sc_linp = mc->un.value.level[AUDIO_MIXER_LEVEL_LEFT]; 1703 sc->sc_rinp = mc->un.value.level[AUDIO_MIXER_LEVEL_RIGHT]; 1704 break; 1705 case DBRI_INPUT_SELECT: 1706 if (mc->un.mask == sc->sc_input) 1707 return 0; 1708 sc->sc_input = mc->un.mask; 1709 break; 1710 } 1711 1712 sc->sc_latt = latt; 1713 sc->sc_ratt = ratt; 1714 1715 mutex_spin_enter(&sc->sc_intr_lock); 1716 mmcodec_setgain(sc, 0); 1717 mutex_spin_exit(&sc->sc_intr_lock); 1718 1719 return (0); 1720 } 1721 1722 static int 1723 dbri_get_port(void *hdl, mixer_ctrl_t *mc) 1724 { 1725 struct dbri_softc *sc = hdl; 1726 1727 switch (mc->dev) { 1728 case DBRI_VOL_OUTPUT: /* master volume */ 1729 mc->un.value.level[AUDIO_MIXER_LEVEL_LEFT] = 1730 (63 - (sc->sc_latt & 0x3f)) << 2; 1731 mc->un.value.level[AUDIO_MIXER_LEVEL_RIGHT] = 1732 (63 - (sc->sc_ratt & 0x3f)) << 2; 1733 return (0); 1734 case DBRI_ENABLE_MONO: /* built-in speaker */ 1735 mc->un.ord = (sc->sc_ratt & CS4215_SE) ? 1 : 0; 1736 return 0; 1737 case DBRI_ENABLE_HEADPHONE: /* headphones output */ 1738 mc->un.ord = (sc->sc_latt & CS4215_HE) ? 1 : 0; 1739 return 0; 1740 case DBRI_ENABLE_LINE: /* line out */ 1741 mc->un.ord = (sc->sc_latt & CS4215_LE) ? 1 : 0; 1742 return 0; 1743 case DBRI_VOL_MONITOR: 1744 mc->un.value.level[AUDIO_MIXER_LEVEL_LEFT] = sc->sc_monitor; 1745 return 0; 1746 case DBRI_INPUT_GAIN: 1747 mc->un.value.level[AUDIO_MIXER_LEVEL_LEFT] = sc->sc_linp; 1748 mc->un.value.level[AUDIO_MIXER_LEVEL_RIGHT] = sc->sc_rinp; 1749 return 0; 1750 case DBRI_INPUT_SELECT: 1751 mc->un.mask = sc->sc_input; 1752 return 0; 1753 } 1754 return (EINVAL); 1755 } 1756 1757 static int 1758 dbri_query_devinfo(void *hdl, mixer_devinfo_t *di) 1759 { 1760 1761 switch (di->index) { 1762 case DBRI_MONITOR_CLASS: 1763 di->mixer_class = DBRI_MONITOR_CLASS; 1764 strcpy(di->label.name, AudioCmonitor); 1765 di->type = AUDIO_MIXER_CLASS; 1766 di->next = di->prev = AUDIO_MIXER_LAST; 1767 return 0; 1768 case DBRI_OUTPUT_CLASS: 1769 di->mixer_class = DBRI_OUTPUT_CLASS; 1770 strcpy(di->label.name, AudioCoutputs); 1771 di->type = AUDIO_MIXER_CLASS; 1772 di->next = di->prev = AUDIO_MIXER_LAST; 1773 return 0; 1774 case DBRI_INPUT_CLASS: 1775 di->mixer_class = DBRI_INPUT_CLASS; 1776 strcpy(di->label.name, AudioCinputs); 1777 di->type = AUDIO_MIXER_CLASS; 1778 di->next = di->prev = AUDIO_MIXER_LAST; 1779 return 0; 1780 case DBRI_VOL_OUTPUT: /* master volume */ 1781 di->mixer_class = DBRI_OUTPUT_CLASS; 1782 di->next = di->prev = AUDIO_MIXER_LAST; 1783 strcpy(di->label.name, AudioNmaster); 1784 di->type = AUDIO_MIXER_VALUE; 1785 di->un.v.num_channels = 2; 1786 di->un.v.delta = 16; 1787 strcpy(di->un.v.units.name, AudioNvolume); 1788 return (0); 1789 case DBRI_INPUT_GAIN: /* input gain */ 1790 di->mixer_class = DBRI_INPUT_CLASS; 1791 di->next = di->prev = AUDIO_MIXER_LAST; 1792 strcpy(di->label.name, AudioNrecord); 1793 di->type = AUDIO_MIXER_VALUE; 1794 di->un.v.num_channels = 2; 1795 strcpy(di->un.v.units.name, AudioNvolume); 1796 return (0); 1797 case DBRI_VOL_MONITOR: /* monitor volume */ 1798 di->mixer_class = DBRI_MONITOR_CLASS; 1799 di->next = di->prev = AUDIO_MIXER_LAST; 1800 strcpy(di->label.name, AudioNmonitor); 1801 di->type = AUDIO_MIXER_VALUE; 1802 di->un.v.num_channels = 1; 1803 strcpy(di->un.v.units.name, AudioNvolume); 1804 return (0); 1805 case DBRI_ENABLE_MONO: /* built-in speaker */ 1806 di->mixer_class = DBRI_OUTPUT_CLASS; 1807 di->next = di->prev = AUDIO_MIXER_LAST; 1808 strcpy(di->label.name, AudioNmono); 1809 di->type = AUDIO_MIXER_ENUM; 1810 di->un.e.num_mem = 2; 1811 strcpy(di->un.e.member[0].label.name, AudioNoff); 1812 di->un.e.member[0].ord = 0; 1813 strcpy(di->un.e.member[1].label.name, AudioNon); 1814 di->un.e.member[1].ord = 1; 1815 return (0); 1816 case DBRI_ENABLE_HEADPHONE: /* headphones output */ 1817 di->mixer_class = DBRI_OUTPUT_CLASS; 1818 di->next = di->prev = AUDIO_MIXER_LAST; 1819 strcpy(di->label.name, AudioNheadphone); 1820 di->type = AUDIO_MIXER_ENUM; 1821 di->un.e.num_mem = 2; 1822 strcpy(di->un.e.member[0].label.name, AudioNoff); 1823 di->un.e.member[0].ord = 0; 1824 strcpy(di->un.e.member[1].label.name, AudioNon); 1825 di->un.e.member[1].ord = 1; 1826 return (0); 1827 case DBRI_ENABLE_LINE: /* line out */ 1828 di->mixer_class = DBRI_OUTPUT_CLASS; 1829 di->next = di->prev = AUDIO_MIXER_LAST; 1830 strcpy(di->label.name, AudioNline); 1831 di->type = AUDIO_MIXER_ENUM; 1832 di->un.e.num_mem = 2; 1833 strcpy(di->un.e.member[0].label.name, AudioNoff); 1834 di->un.e.member[0].ord = 0; 1835 strcpy(di->un.e.member[1].label.name, AudioNon); 1836 di->un.e.member[1].ord = 1; 1837 return (0); 1838 case DBRI_INPUT_SELECT: 1839 di->mixer_class = DBRI_INPUT_CLASS; 1840 strcpy(di->label.name, AudioNsource); 1841 di->type = AUDIO_MIXER_SET; 1842 di->prev = di->next = AUDIO_MIXER_LAST; 1843 di->un.s.num_mem = 2; 1844 strcpy(di->un.s.member[0].label.name, AudioNline); 1845 di->un.s.member[0].mask = 1 << 0; 1846 strcpy(di->un.s.member[1].label.name, AudioNmicrophone); 1847 di->un.s.member[1].mask = 1 << 1; 1848 return 0; 1849 } 1850 1851 return (ENXIO); 1852 } 1853 1854 static int 1855 dbri_get_props(void *hdl) 1856 { 1857 1858 return AUDIO_PROP_PLAYBACK | AUDIO_PROP_CAPTURE | 1859 AUDIO_PROP_FULLDUPLEX; 1860 } 1861 1862 static int 1863 dbri_commit(void *hdl) 1864 { 1865 struct dbri_softc *sc = hdl; 1866 int ret = 0; 1867 1868 /* 1869 * we only need to whack the codec if things like sample format or 1870 * frequency changed, not for mixer stuff 1871 */ 1872 if (sc->sc_whack_codec == 0) 1873 return 0; 1874 1875 mutex_spin_enter(&sc->sc_intr_lock); 1876 ret = mmcodec_setcontrol(sc); 1877 if (ret) { 1878 DPRINTF("%s: control mode failed. Mutex %s PIL %x\n", __func__, 1879 mutex_owned(&sc->sc_intr_lock) ? "held" : "free", 1880 (getpsr() & PSR_PIL) >> 8); 1881 } else 1882 DPRINTF("%s: control mode ok\n", __func__); 1883 mmcodec_init_data(sc); 1884 mutex_spin_exit(&sc->sc_intr_lock); 1885 return 0; 1886 } 1887 1888 static int 1889 dbri_trigger_output(void *hdl, void *start, void *end, int blksize, 1890 void (*intr)(void *), void *intrarg, 1891 const struct audio_params *param) 1892 { 1893 struct dbri_softc *sc = hdl; 1894 unsigned long count, num; 1895 1896 KASSERT(sc->sc_playing == 0); 1897 1898 count = (unsigned long)(((char *)end - (char *)start)); 1899 num = count / blksize; 1900 1901 DPRINTF("trigger_output(%lx %lx) : %d %ld %ld\n", 1902 (unsigned long)intr, 1903 (unsigned long)intrarg, blksize, count, num); 1904 1905 sc->sc_params = *param; 1906 1907 /* 1908 * always use DMA descriptor 0 for output 1909 * no need to allocate them dynamically since we only ever have 1910 * exactly one input stream and exactly one output stream 1911 */ 1912 setup_ring_xmit(sc, 4, 0, num, blksize, intr, intrarg); 1913 sc->sc_playing = 1; 1914 return 0; 1915 } 1916 1917 static int 1918 dbri_halt_input(void *cookie) 1919 { 1920 struct dbri_softc *sc = cookie; 1921 1922 if (!sc->sc_recording) 1923 return 0; 1924 1925 sc->sc_recording = 0; 1926 pipe_reset(sc, 6); 1927 return 0; 1928 } 1929 1930 static int 1931 dbri_trigger_input(void *hdl, void *start, void *end, int blksize, 1932 void (*intr)(void *), void *intrarg, 1933 const struct audio_params *param) 1934 { 1935 struct dbri_softc *sc = hdl; 1936 unsigned long count, num; 1937 1938 KASSERT(sc->sc_recording == 0); 1939 1940 count = (unsigned long)(((char *)end - (char *)start)); 1941 num = count / blksize; 1942 1943 DPRINTF("trigger_input(%lx %lx) : %d %ld %ld\n", 1944 (unsigned long)intr, 1945 (unsigned long)intrarg, blksize, count, num); 1946 1947 sc->sc_params = *param; 1948 1949 sc->sc_recording = 1; 1950 setup_ring_recv(sc, 6, 1, num, blksize, intr, intrarg); 1951 return 0; 1952 } 1953 1954 static void 1955 dbri_get_locks(void *opaque, kmutex_t **intr, kmutex_t **thread) 1956 { 1957 struct dbri_softc *sc = opaque; 1958 1959 *intr = &sc->sc_intr_lock; 1960 *thread = &sc->sc_lock; 1961 } 1962 1963 static uint32_t 1964 reverse_bytes(uint32_t b, int len) 1965 { 1966 switch (len) { 1967 case 32: 1968 b = ((b & 0xffff0000) >> 16) | ((b & 0x0000ffff) << 16); 1969 case 16: 1970 b = ((b & 0xff00ff00) >> 8) | ((b & 0x00ff00ff) << 8); 1971 case 8: 1972 b = ((b & 0xf0f0f0f0) >> 4) | ((b & 0x0f0f0f0f) << 4); 1973 case 4: 1974 b = ((b & 0xcccccccc) >> 2) | ((b & 0x33333333) << 2); 1975 case 2: 1976 b = ((b & 0xaaaaaaaa) >> 1) | ((b & 0x55555555) << 1); 1977 case 1: 1978 case 0: 1979 break; 1980 default: 1981 DPRINTF("reverse_bytes: unsupported length\n"); 1982 }; 1983 1984 return (b); 1985 } 1986 1987 static void * 1988 dbri_malloc(void *v, int dir, size_t s) 1989 { 1990 struct dbri_softc *sc = v; 1991 struct dbri_desc *dd = &sc->sc_desc[sc->sc_desc_used]; 1992 int rseg; 1993 1994 if (bus_dmamap_create(sc->sc_dmat, s, 1, s, 0, BUS_DMA_NOWAIT, 1995 &dd->dmamap) == 0) { 1996 if (bus_dmamem_alloc(sc->sc_dmat, s, 0, 0, &dd->dmaseg, 1997 1, &rseg, BUS_DMA_NOWAIT) == 0) { 1998 if (bus_dmamem_map(sc->sc_dmat, &dd->dmaseg, rseg, s, 1999 &dd->buf, BUS_DMA_NOWAIT|BUS_DMA_COHERENT) == 0) { 2000 if (dd->buf != NULL) { 2001 if (bus_dmamap_load(sc->sc_dmat, 2002 dd->dmamap, dd->buf, s, NULL, 2003 BUS_DMA_NOWAIT) == 0) { 2004 dd->len = s; 2005 dd->busy = 0; 2006 dd->callback = NULL; 2007 dd->dmabase = 2008 dd->dmamap->dm_segs[0].ds_addr; 2009 DPRINTF("dbri_malloc: using buffer %d %08x\n", 2010 sc->sc_desc_used, (uint32_t)dd->buf); 2011 sc->sc_desc_used++; 2012 return dd->buf; 2013 } else 2014 aprint_error("dbri_malloc: load failed\n"); 2015 } else 2016 aprint_error("dbri_malloc: map returned NULL\n"); 2017 } else 2018 aprint_error("dbri_malloc: map failed\n"); 2019 bus_dmamem_free(sc->sc_dmat, &dd->dmaseg, rseg); 2020 } else 2021 aprint_error("dbri_malloc: malloc() failed\n"); 2022 bus_dmamap_destroy(sc->sc_dmat, dd->dmamap); 2023 } else 2024 aprint_error("dbri_malloc: bus_dmamap_create() failed\n"); 2025 return NULL; 2026 } 2027 2028 static void 2029 dbri_free(void *v, void *p, size_t size) 2030 { 2031 struct dbri_softc *sc = v; 2032 struct dbri_desc *dd; 2033 int i; 2034 2035 for (i = 0; i < sc->sc_desc_used; i++) { 2036 dd = &sc->sc_desc[i]; 2037 if (dd->buf == p) 2038 break; 2039 } 2040 if (i >= sc->sc_desc_used) 2041 return; 2042 bus_dmamap_unload(sc->sc_dmat, dd->dmamap); 2043 bus_dmamap_destroy(sc->sc_dmat, dd->dmamap); 2044 } 2045 2046 static int 2047 dbri_open(void *cookie, int flags) 2048 { 2049 struct dbri_softc *sc = cookie; 2050 2051 DPRINTF("%s\n", __func__); 2052 2053 dbri_bring_up(sc); 2054 return 0; 2055 } 2056 2057 static void 2058 dbri_close(void *cookie) 2059 { 2060 struct dbri_softc *sc = cookie; 2061 2062 DPRINTF("%s\n", __func__); 2063 KASSERT(sc->sc_playing == 0); 2064 KASSERT(sc->sc_recording == 0); 2065 2066 dbri_set_power(sc, 0); 2067 } 2068 2069 static bool 2070 dbri_suspend(device_t self, const pmf_qual_t *qual) 2071 { 2072 struct dbri_softc *sc = device_private(self); 2073 2074 mutex_spin_enter(&sc->sc_intr_lock); 2075 dbri_set_power(sc, 0); 2076 mutex_spin_exit(&sc->sc_intr_lock); 2077 return true; 2078 } 2079 2080 static bool 2081 dbri_resume(device_t self, const pmf_qual_t *qual) 2082 { 2083 struct dbri_softc *sc = device_private(self); 2084 2085 if (sc->sc_powerstate != 0) 2086 return true; 2087 aprint_verbose("resume\n"); 2088 if (sc->sc_playing) { 2089 volatile uint32_t *cmd; 2090 2091 mutex_spin_enter(&sc->sc_intr_lock); 2092 dbri_bring_up(sc); 2093 cmd = dbri_command_lock(sc); 2094 *(cmd++) = DBRI_CMD(DBRI_COMMAND_SDP, 2095 0, sc->sc_pipe[4].sdp | 2096 DBRI_SDP_VALID_POINTER | 2097 DBRI_SDP_EVERY | DBRI_SDP_CLEAR); 2098 *(cmd++) = sc->sc_dmabase + 2099 dbri_dma_off(xmit, 0); 2100 dbri_command_send(sc, cmd); 2101 mutex_spin_exit(&sc->sc_intr_lock); 2102 } 2103 return true; 2104 } 2105 2106 #endif /* NAUDIO > 0 */ 2107
Indexes created Fri Sep 26 08:10:20 GMT 2025