dbri.c revision 1.9
1 /* $NetBSD: dbri.c,v 1.9 2007/03/08 21:15:20 macallan Exp $ */ 2 3 /* 4 * Copyright (C) 1997 Rudolf Koenig (rfkoenig (at) immd4.informatik.uni-erlangen.de) 5 * Copyright (c) 1998, 1999 Brent Baccala (baccala (at) freesoft.org) 6 * Copyright (c) 2001, 2002 Jared D. McNeill <jmcneill (at) netbsd.org> 7 * Copyright (c) 2005 Michael Lorenz <macallan (at) netbsd.org> 8 * All rights reserved. 9 * 10 * This driver is losely based on a Linux driver written by Rudolf Koenig and 11 * Brent Baccala who kindly gave their permission to use their code in a 12 * BSD-licensed driver. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions 16 * are met: 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in the 21 * documentation and/or other materials provided with the distribution. 22 * 3. All advertising materials mentioning features or use of this software 23 * must display the following acknowledgement: 24 * This product includes software developed by Rudolf Koenig, Brent 25 * Baccala, Jared D. McNeill. 26 * 4. Neither the name of the author nor the names of any contributors may 27 * be used to endorse or promote products derived from this software 28 * without specific prior written permission. 29 * 30 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 31 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 33 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 36 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 37 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 38 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 39 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 40 * SUCH DAMAGE. 41 * 42 */ 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: dbri.c,v 1.9 2007/03/08 21:15:20 macallan Exp $"); 46 47 #include "audio.h" 48 #if NAUDIO > 0 49 50 #include <sys/param.h> 51 #include <sys/systm.h> 52 #include <sys/errno.h> 53 #include <sys/device.h> 54 #include <sys/malloc.h> 55 #include <sys/proc.h> 56 57 #include <machine/bus.h> 58 #include <machine/intr.h> 59 60 #include <dev/sbus/sbusvar.h> 61 #include <sparc/sparc/auxreg.h> 62 #include <machine/autoconf.h> 63 64 #include <sys/audioio.h> 65 #include <dev/audio_if.h> 66 #include <dev/auconv.h> 67 68 #include <dev/ic/cs4215reg.h> 69 #include <dev/ic/cs4215var.h> 70 #include <dev/sbus/dbrireg.h> 71 #include <dev/sbus/dbrivar.h> 72 73 #include "opt_sbus_dbri.h" 74 75 #define DBRI_ROM_NAME_PREFIX "SUNW,DBRI" 76 77 #ifdef DBRI_DEBUG 78 #define DPRINTF(x) printf x 79 #else 80 #define DPRINTF(x) 81 #endif 82 83 static const char *dbri_supported[] = { 84 "e", 85 "s3", 86 "" 87 }; 88 89 enum ms { 90 CHImaster, 91 CHIslave 92 }; 93 94 enum io { 95 PIPEinput, 96 PIPEoutput 97 }; 98 99 /* 100 * Function prototypes 101 */ 102 103 /* softc stuff */ 104 static void dbri_attach_sbus(struct device *, struct device *, void *); 105 static int dbri_match_sbus(struct device *, struct cfdata *, void *); 106 107 static void dbri_config_interrupts(struct device *); 108 109 /* interrupt handler */ 110 static int dbri_intr(void *); 111 112 /* supporting subroutines */ 113 static int dbri_init(struct dbri_softc *); 114 static int dbri_reset(struct dbri_softc *); 115 static volatile u_int32_t *dbri_command_lock(struct dbri_softc *); 116 static void dbri_command_send(struct dbri_softc *, volatile u_int32_t *); 117 static void dbri_process_interrupt_buffer(struct dbri_softc *); 118 static void dbri_process_interrupt(struct dbri_softc *, int32_t); 119 120 /* mmcodec subroutines */ 121 static int mmcodec_init(struct dbri_softc *); 122 static void mmcodec_init_data(struct dbri_softc *); 123 static void mmcodec_pipe_init(struct dbri_softc *); 124 static void mmcodec_default(struct dbri_softc *); 125 static void mmcodec_setgain(struct dbri_softc *, int); 126 static int mmcodec_setcontrol(struct dbri_softc *); 127 128 /* chi subroutines */ 129 static void chi_reset(struct dbri_softc *, enum ms, int); 130 131 /* pipe subroutines */ 132 static void pipe_setup(struct dbri_softc *, int, int); 133 static void pipe_reset(struct dbri_softc *, int); 134 static void pipe_receive_fixed(struct dbri_softc *, int, 135 volatile u_int32_t *); 136 static void pipe_transmit_fixed(struct dbri_softc *, int, u_int32_t); 137 138 static void pipe_ts_link(struct dbri_softc *, int, enum io, int, int, int); 139 static int pipe_active(struct dbri_softc *, int); 140 141 /* audio(9) stuff */ 142 static int dbri_query_encoding(void *, struct audio_encoding *); 143 static int dbri_set_params(void *, int, int, struct audio_params *, 144 struct audio_params *,stream_filter_list_t *, stream_filter_list_t *); 145 static int dbri_round_blocksize(void *, int, int, const audio_params_t *); 146 static int dbri_halt_output(void *); 147 static int dbri_getdev(void *, struct audio_device *); 148 static int dbri_set_port(void *, mixer_ctrl_t *); 149 static int dbri_get_port(void *, mixer_ctrl_t *); 150 static int dbri_query_devinfo(void *, mixer_devinfo_t *); 151 static size_t dbri_round_buffersize(void *, int, size_t); 152 static int dbri_get_props(void *); 153 static int dbri_open(void *, int); 154 static void dbri_close(void *); 155 156 static void 157 setup_ring(struct dbri_softc *, int, int, int, int, void (*)(void *), void *); 158 159 static int dbri_trigger_output(void *, void *, void *, int, 160 void (*)(void *), void *, const struct audio_params *); 161 162 static void *dbri_malloc(void *, int, size_t, struct malloc_type *, int); 163 static void dbri_free(void *, void *, struct malloc_type *); 164 static paddr_t dbri_mappage(void *, void *, off_t, int); 165 static void dbri_set_power(struct dbri_softc *, int); 166 static void dbri_bring_up(struct dbri_softc *); 167 static void dbri_powerhook(int, void *); 168 169 /* stupid support routines */ 170 static u_int32_t reverse_bytes(u_int32_t, int); 171 172 struct audio_device dbri_device = { 173 "CS4215", 174 "", 175 "dbri" 176 }; 177 178 struct audio_hw_if dbri_hw_if = { 179 dbri_open, 180 dbri_close, 181 NULL, /* drain */ 182 dbri_query_encoding, 183 dbri_set_params, 184 dbri_round_blocksize, 185 NULL, /* commit_settings */ 186 NULL, /* init_output */ 187 NULL, /* init_input */ 188 NULL, /* start_output */ 189 NULL, /* start_input */ 190 dbri_halt_output, 191 NULL, /* halt_input */ 192 NULL, /* speaker_ctl */ 193 dbri_getdev, 194 NULL, /* setfd */ 195 dbri_set_port, 196 dbri_get_port, 197 dbri_query_devinfo, 198 dbri_malloc, 199 dbri_free, 200 dbri_round_buffersize, 201 dbri_mappage, 202 dbri_get_props, 203 dbri_trigger_output, 204 NULL /* trigger_input */ 205 }; 206 207 CFATTACH_DECL(dbri, sizeof(struct dbri_softc), 208 dbri_match_sbus, dbri_attach_sbus, NULL, NULL); 209 210 enum { 211 DBRI_MONITOR_CLASS, 212 DBRI_VOL_OUTPUT, 213 DBRI_ENABLE_MONO, 214 DBRI_ENABLE_HEADPHONE, 215 DBRI_ENABLE_LINE 216 /* 217 DBRI_INPUT_CLASS, 218 DBRI_RECORD_CLASS, 219 DBRI_INPUT_GAIN, 220 DBRI_INPUT_SELECT, 221 DBRI_ENUM_LAST 222 */ 223 }; 224 225 /* 226 * Autoconfig routines 227 */ 228 int 229 dbri_match_sbus(struct device *parent, struct cfdata *match, void *aux) 230 { 231 struct sbus_attach_args *sa = aux; 232 char *ver; 233 int i; 234 235 if (strncmp(DBRI_ROM_NAME_PREFIX, sa->sa_name, 9)) 236 return (0); 237 238 ver = &sa->sa_name[9]; 239 240 for (i = 0; dbri_supported[i][0] != '\0'; i++) 241 if (strcmp(dbri_supported[i], ver) == 0) 242 return (1); 243 244 return (0); 245 } 246 247 void 248 dbri_attach_sbus(struct device *parent, struct device *self, void *aux) 249 { 250 struct dbri_softc *sc = (struct dbri_softc *)self; 251 struct sbus_attach_args *sa = aux; 252 bus_space_handle_t ioh; 253 bus_size_t size; 254 int error, rseg, pwr; 255 char *ver = &sa->sa_name[9]; 256 257 sc->sc_iot = sa->sa_bustag; 258 sc->sc_dmat = sa->sa_dmatag; 259 sc->sc_powerstate = PWR_RESUME; 260 261 pwr = prom_getpropint(sa->sa_node,"pwr-on-auxio",0); 262 if(pwr) { 263 /* 264 * we can control DBRI power via auxio and we're initially 265 * powered down 266 */ 267 268 sc->sc_have_powerctl = 1; 269 sc->sc_powerstate = 0; 270 printf("\n"); 271 dbri_set_power(sc, 1); 272 powerhook_establish(self->dv_xname, dbri_powerhook, sc); 273 } else { 274 /* we can't control power so we're always up */ 275 sc->sc_have_powerctl = 0; 276 sc->sc_powerstate = 1; 277 printf(": rev %s\n", ver); 278 } 279 280 if (sa->sa_npromvaddrs) 281 ioh = (bus_space_handle_t)sa->sa_promvaddrs[0]; 282 else { 283 if (sbus_bus_map(sa->sa_bustag, sa->sa_slot, 284 sa->sa_offset, sa->sa_size, 285 BUS_SPACE_MAP_LINEAR, /*0,*/ &ioh) != 0) { 286 printf("%s @ sbus: cannot map registers\n", 287 self->dv_xname); 288 return; 289 } 290 } 291 292 sc->sc_ioh = ioh; 293 294 size = sizeof(struct dbri_dma); 295 296 /* get a DMA handle */ 297 if ((error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, 298 BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) { 299 printf("%s: DMA map create error %d\n", self->dv_xname, error); 300 return; 301 } 302 303 /* allocate DMA buffer */ 304 if ((error = bus_dmamem_alloc(sc->sc_dmat, size, 0, 0, &sc->sc_dmaseg, 305 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 306 printf("%s: DMA buffer alloc error %d\n", 307 self->dv_xname, error); 308 return; 309 } 310 311 /* map DMA buffer into CPU addressable space */ 312 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_dmaseg, rseg, size, 313 &sc->sc_membase, 314 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 315 printf("%s: DMA buffer map error %d\n", 316 self->dv_xname, error); 317 return; 318 } 319 320 /* load the buffer */ 321 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, 322 sc->sc_membase, size, NULL, 323 BUS_DMA_NOWAIT)) != 0) { 324 printf("%s: DMA buffer map load error %d\n", 325 self->dv_xname, error); 326 bus_dmamem_unmap(sc->sc_dmat, sc->sc_membase, size); 327 bus_dmamem_free(sc->sc_dmat, &sc->sc_dmaseg, rseg); 328 return; 329 } 330 331 /* map the registers into memory */ 332 333 /* kernel virtual address of DMA buffer */ 334 sc->sc_dma = (struct dbri_dma *)sc->sc_membase; 335 /* physical address of DMA buffer */ 336 sc->sc_dmabase = sc->sc_dmamap->dm_segs[0].ds_addr; 337 sc->sc_bufsiz = size; 338 339 sbus_establish(&sc->sc_sd, &sc->sc_dev); 340 341 bus_intr_establish(sa->sa_bustag, sa->sa_pri, IPL_AUDIO, /*0,*/ 342 dbri_intr, sc); 343 344 sc->sc_locked = 0; 345 sc->sc_desc_used = 0; 346 347 config_interrupts(self, &dbri_config_interrupts); 348 349 return; 350 } 351 352 /* 353 * lowlevel routine to switch power for the DBRI chip 354 */ 355 static void 356 dbri_set_power(struct dbri_softc *sc, int state) 357 { 358 int s; 359 360 if (sc->sc_have_powerctl == 0) 361 return; 362 if (sc->sc_powerstate == state) 363 return; 364 365 if (state) { 366 DPRINTF(("%s: waiting to power up... ", sc->sc_dev.dv_xname)); 367 s = splhigh(); 368 *AUXIO4M_REG |= (AUXIO4M_MMX); 369 splx(s); 370 delay(10000); 371 DPRINTF(("done (%02x})\n", *AUXIO4M_REG)); 372 } else { 373 DPRINTF(("%s: powering down\n", sc->sc_dev.dv_xname)); 374 s = splhigh(); 375 *AUXIO4M_REG &= ~AUXIO4M_MMX; 376 splx(s); 377 DPRINTF(("done (%02x})\n", *AUXIO4M_REG)); 378 } 379 sc->sc_powerstate = state; 380 } 381 382 /* 383 * power up and re-initialize the chip 384 */ 385 static void 386 dbri_bring_up(struct dbri_softc *sc) 387 { 388 389 if (sc->sc_have_powerctl == 0) 390 return; 391 if (sc->sc_powerstate == 1) 392 return; 393 394 /* ok, we really need to do something */ 395 dbri_set_power(sc, 1); 396 397 /* 398 * re-initialize the chip but skip all the probing, don't overwrite 399 * any other settings either 400 */ 401 dbri_init(sc); 402 mmcodec_setgain(sc, 1); 403 mmcodec_pipe_init(sc); 404 mmcodec_init_data(sc); 405 mmcodec_setgain(sc, 0); 406 } 407 408 void 409 dbri_config_interrupts(struct device *dev) 410 { 411 struct dbri_softc *sc = (struct dbri_softc *)dev; 412 413 dbri_init(sc); 414 mmcodec_init(sc); 415 416 /* Attach ourselves to the high level audio interface */ 417 audio_attach_mi(&dbri_hw_if, sc, &sc->sc_dev); 418 419 /* power down until open() */ 420 dbri_set_power(sc, 0); 421 return; 422 } 423 424 int 425 dbri_intr(void *hdl) 426 { 427 struct dbri_softc *sc = hdl; 428 bus_space_tag_t iot = sc->sc_iot; 429 bus_space_handle_t ioh = sc->sc_ioh; 430 int x; 431 432 /* clear interrupt */ 433 x = bus_space_read_4(iot, ioh, DBRI_REG1); 434 if (x & (DBRI_MRR | DBRI_MLE | DBRI_LBG | DBRI_MBE)) { 435 u_int32_t tmp; 436 437 if (x & DBRI_MRR) 438 printf("%s: multiple ack error on sbus\n", 439 sc->sc_dev.dv_xname); 440 if (x & DBRI_MLE) 441 printf("%s: multiple late error on sbus\n", 442 sc->sc_dev.dv_xname); 443 if (x & DBRI_LBG) 444 printf("%s: lost bus grant on sbus\n", 445 sc->sc_dev.dv_xname); 446 if (x & DBRI_MBE) 447 printf("%s: burst error on sbus\n", 448 sc->sc_dev.dv_xname); 449 450 /* 451 * Some of these errors disable the chip's circuitry. 452 * Re-enable the circuitry and keep on going. 453 */ 454 455 tmp = bus_space_read_4(iot, ioh, DBRI_REG0); 456 tmp &= ~(DBRI_DISABLE_MASTER); 457 bus_space_write_4(iot, ioh, DBRI_REG0, tmp); 458 } 459 460 #if 0 461 if (!x & 1) /* XXX: DBRI_INTR_REQ */ 462 return (1); 463 #endif 464 465 dbri_process_interrupt_buffer(sc); 466 467 return (1); 468 } 469 470 int 471 dbri_init(struct dbri_softc *sc) 472 { 473 bus_space_tag_t iot = sc->sc_iot; 474 bus_space_handle_t ioh = sc->sc_ioh; 475 u_int32_t reg; 476 volatile u_int32_t *cmd; 477 bus_addr_t dmaaddr; 478 int n; 479 480 dbri_reset(sc); 481 482 cmd = dbri_command_lock(sc); 483 484 /* XXX: Initialize interrupt ring buffer */ 485 sc->sc_dma->intr[0] = (u_int32_t)sc->sc_dmabase + dbri_dma_off(intr, 0); 486 sc->sc_irqp = 1; 487 488 /* Initialize pipes */ 489 for (n = 0; n < DBRI_PIPE_MAX; n++) 490 sc->sc_pipe[n].desc = sc->sc_pipe[n].next = -1; 491 492 for(n=1;n<DBRI_INT_BLOCKS;n++) { 493 sc->sc_dma->intr[n]=0; 494 } 495 496 /* Disable all SBus bursts */ 497 /* XXX 16 byte bursts cause errors, the rest works */ 498 reg = bus_space_read_4(iot, ioh, DBRI_REG0); 499 500 /*reg &= ~(DBRI_BURST_4 | DBRI_BURST_8 | DBRI_BURST_16);*/ 501 reg |= (DBRI_BURST_4 | DBRI_BURST_8); 502 bus_space_write_4(iot, ioh, DBRI_REG0, reg); 503 504 /* setup interrupt queue */ 505 dmaaddr = (u_int32_t)sc->sc_dmabase + dbri_dma_off(intr, 0); 506 *(cmd++) = DBRI_CMD(DBRI_COMMAND_IIQ, 0, 0); 507 *(cmd++) = dmaaddr; 508 509 dbri_command_send(sc, cmd); 510 return (0); 511 } 512 513 int 514 dbri_reset(struct dbri_softc *sc) 515 { 516 int bail=0; 517 bus_space_tag_t iot = sc->sc_iot; 518 bus_space_handle_t ioh = sc->sc_ioh; 519 520 bus_space_write_4(iot, ioh, DBRI_REG0, DBRI_SOFT_RESET); 521 while ((bus_space_read_4(iot, ioh, DBRI_REG0) & DBRI_SOFT_RESET) && 522 (bail < 100000)) { 523 bail++; 524 delay(10); 525 } 526 if (bail == 100000) printf("%s: reset timed out\n",sc->sc_dev.dv_xname); 527 return (0); 528 } 529 530 volatile u_int32_t * 531 dbri_command_lock(struct dbri_softc *sc) 532 { 533 534 if (sc->sc_locked) 535 printf("%s: command buffer locked\n", sc->sc_dev.dv_xname); 536 537 sc->sc_locked++; 538 539 return (&sc->sc_dma->command[0]); 540 } 541 542 void 543 dbri_command_send(struct dbri_softc *sc, volatile u_int32_t *cmd) 544 { 545 bus_space_handle_t ioh = sc->sc_ioh; 546 bus_space_tag_t iot = sc->sc_iot; 547 int maxloops = 1000000; 548 int x; 549 550 x = splaudio(); 551 //x = splhigh(); 552 553 sc->sc_locked--; 554 555 if (sc->sc_locked != 0) { 556 printf("%s: command buffer improperly locked\n", 557 sc->sc_dev.dv_xname); 558 } else if ((cmd - &sc->sc_dma->command[0]) >= DBRI_NUM_COMMANDS - 1) { 559 printf("%s: command buffer overflow\n", sc->sc_dev.dv_xname); 560 } else { 561 *(cmd++) = DBRI_CMD(DBRI_COMMAND_PAUSE, 0, 0); 562 *(cmd++) = DBRI_CMD(DBRI_COMMAND_WAIT, 1, 0); 563 sc->sc_waitseen = 0; 564 bus_space_write_4(iot, ioh, DBRI_REG8, sc->sc_dmabase); 565 while ((--maxloops) > 0 && 566 (bus_space_read_4(iot, ioh, DBRI_REG0) 567 & DBRI_COMMAND_VALID)) { 568 bus_space_barrier(iot, ioh, DBRI_REG0, 4, 569 BUS_SPACE_BARRIER_READ); 570 delay(1000); 571 } 572 573 if (maxloops == 0) { 574 printf("%s: chip never completed command buffer\n", 575 sc->sc_dev.dv_xname); 576 } else { 577 578 DPRINTF(("%s: command completed\n", 579 sc->sc_dev.dv_xname)); 580 581 while ((--maxloops) > 0 && (!sc->sc_waitseen)) 582 dbri_process_interrupt_buffer(sc); 583 if (maxloops == 0) { 584 printf("%s: chip never acked WAIT\n", 585 sc->sc_dev.dv_xname); 586 } 587 } 588 } 589 590 splx(x); 591 592 return; 593 } 594 595 void 596 dbri_process_interrupt_buffer(struct dbri_softc *sc) 597 { 598 int32_t i; 599 600 while ((i = sc->sc_dma->intr[sc->sc_irqp]) != 0) { 601 sc->sc_dma->intr[sc->sc_irqp] = 0; 602 sc->sc_irqp++; 603 604 if (sc->sc_irqp == DBRI_INT_BLOCKS) 605 sc->sc_irqp = 1; 606 else if ((sc->sc_irqp & (DBRI_INT_BLOCKS - 1)) == 0) 607 sc->sc_irqp++; 608 609 dbri_process_interrupt(sc, i); 610 } 611 612 return; 613 } 614 615 void 616 dbri_process_interrupt(struct dbri_softc *sc, int32_t i) 617 { 618 #if 0 619 const int liu_states[] = { 1, 0, 8, 3, 4, 5, 6, 7 }; 620 #endif 621 int val = DBRI_INTR_GETVAL(i); 622 int channel = DBRI_INTR_GETCHAN(i); 623 int command = DBRI_INTR_GETCMD(i); 624 int code = DBRI_INTR_GETCODE(i); 625 #if 0 626 int rval = DBRI_INTR_GETRVAL(i); 627 #endif 628 if (channel == DBRI_INTR_CMD && command == DBRI_COMMAND_WAIT) 629 sc->sc_waitseen++; 630 631 switch (code) { 632 case DBRI_INTR_XCMP: /* transmission complete */ 633 { 634 int td; 635 struct dbri_desc *dd; 636 637 td = sc->sc_pipe[channel].desc; 638 dd = &sc->sc_desc[td]; 639 640 if (dd->callback != NULL) 641 dd->callback(dd->callback_args); 642 break; 643 } 644 case DBRI_INTR_FXDT: /* fixed data change */ 645 DPRINTF(("dbri_intr: Fixed data change (%d: %x)\n", channel, 646 val)); 647 648 if (sc->sc_pipe[channel].sdp & DBRI_SDP_MSB) 649 val = reverse_bytes(val, sc->sc_pipe[channel].length); 650 if (sc->sc_pipe[channel].prec) 651 *(sc->sc_pipe[channel].prec) = val; 652 DPRINTF(("%s: wakeup %p\n", sc->sc_dev.dv_xname, sc)); 653 #if 0 654 wakeup(sc); 655 #endif 656 break; 657 case DBRI_INTR_SBRI: 658 DPRINTF(("dbri_intr: SBRI\n")); 659 break; 660 case DBRI_INTR_BRDY: 661 { 662 /* XXX no input (yet) */ 663 #if 0 664 int rd = sc->sc_pipe[channel].desc; 665 u_int32_t status; 666 667 printf("dbri_intr: BRDY\n"); 668 if (rd < 0 || rd >= DBRI_NUM_DESCRIPTORS) { 669 printf("%s: invalid rd on pipe\n", sc->sc_dev.dv_xname); 670 break; 671 } 672 673 sc->sc_desc[rd].busy = 0; 674 sc->sc_pipe[channel].desc = sc->sc_desc[rd].next; 675 status = sc->sc_dma->desc[rd].word1; 676 #endif 677 /* XXX: callback ??? */ 678 679 break; 680 } 681 case DBRI_INTR_UNDR: 682 { 683 volatile u_int32_t *cmd; 684 int td = sc->sc_pipe[channel].desc; 685 686 printf("%s: DBRI_INTR_UNDR\n", sc->sc_dev.dv_xname); 687 688 sc->sc_dma->desc[td].status = 0; 689 690 cmd = dbri_command_lock(sc); 691 *(cmd++) = DBRI_CMD(DBRI_COMMAND_SDP, 0, 692 sc->sc_pipe[channel].sdp | 693 DBRI_SDP_VALID_POINTER | 694 DBRI_SDP_CLEAR | 695 DBRI_SDP_2SAME); 696 *(cmd++) = sc->sc_dmabase + dbri_dma_off(desc, td); 697 dbri_command_send(sc, cmd); 698 break; 699 } 700 case DBRI_INTR_CMDI: 701 break; 702 default: 703 704 DPRINTF(("%s: unknown interrupt code %d\n", 705 sc->sc_dev.dv_xname, code)); 706 break; 707 } 708 709 return; 710 } 711 712 /* 713 * mmcodec stuff 714 */ 715 716 int 717 mmcodec_init(struct dbri_softc *sc) 718 { 719 bus_space_handle_t ioh = sc->sc_ioh; 720 bus_space_tag_t iot = sc->sc_iot; 721 u_int32_t reg2; 722 int bail; 723 724 reg2 = bus_space_read_4(iot, ioh, DBRI_REG2); 725 DPRINTF(("mmcodec_init: PIO reads %x\n", reg2)); 726 727 if (reg2 & DBRI_PIO2) { 728 printf("%s: onboard CS4215 detected\n", 729 sc->sc_dev.dv_xname); 730 sc->sc_mm.onboard = 1; 731 } 732 733 if (reg2 & DBRI_PIO0) { 734 printf("%s: speakerbox detected\n", 735 sc->sc_dev.dv_xname); 736 sc->sc_mm.onboard = 0; 737 } 738 739 if ((reg2 & DBRI_PIO2) && (reg2 & DBRI_PIO0)) { 740 printf("%s: using speakerbox\n", 741 sc->sc_dev.dv_xname); 742 bus_space_write_4(iot, ioh, DBRI_REG2, DBRI_PIO2_ENABLE); 743 sc->sc_mm.onboard = 0; 744 } 745 746 if (!(reg2 & (DBRI_PIO0|DBRI_PIO2))) { 747 printf("%s: no mmcodec found\n", sc->sc_dev.dv_xname); 748 return -1; 749 } 750 751 sc->sc_version = 0xff; 752 753 mmcodec_pipe_init(sc); 754 mmcodec_default(sc); 755 756 sc->sc_mm.offset = sc->sc_mm.onboard ? 0 : 8; 757 758 /* 759 * mmcodec_setcontrol() sometimes fails right after powerup 760 * so we just try again until we either get a useful response or run 761 * out of time 762 */ 763 bail = 0; 764 while (mmcodec_setcontrol(sc) == -1 || sc->sc_version == 0xff) { 765 766 bail++; 767 if (bail > 100) { 768 printf("%s: cs4215 probe failed at offset %d\n", 769 sc->sc_dev.dv_xname, sc->sc_mm.offset); 770 return (-1); 771 } 772 delay(10000); 773 } 774 775 printf("%s: cs4215 ver %d found at offset %d\n", 776 sc->sc_dev.dv_xname, sc->sc_version & 0xf, sc->sc_mm.offset); 777 778 /* set some sane defaults for mmcodec_init_data */ 779 sc->sc_params.channels = 2; 780 sc->sc_params.precision = 16; 781 782 mmcodec_init_data(sc); 783 784 sc->sc_open = 0; 785 786 return (0); 787 } 788 789 void 790 mmcodec_init_data(struct dbri_softc *sc) 791 { 792 bus_space_tag_t iot = sc->sc_iot; 793 bus_space_handle_t ioh = sc->sc_ioh; 794 u_int32_t tmp; 795 int data_width; 796 797 tmp = bus_space_read_4(iot, ioh, DBRI_REG0); 798 tmp &= ~(DBRI_CHI_ACTIVATE); /* disable CHI */ 799 bus_space_write_4(iot, ioh, DBRI_REG0, tmp); 800 801 /* switch CS4215 to data mode - set PIO3 to 1 */ 802 tmp = DBRI_PIO_ENABLE_ALL | DBRI_PIO1 | DBRI_PIO3; 803 /* XXX */ 804 tmp |= (sc->sc_mm.onboard ? DBRI_PIO0 : DBRI_PIO2); 805 806 bus_space_write_4(iot, ioh, DBRI_REG2, tmp); 807 chi_reset(sc, CHIslave, 128); 808 809 data_width = sc->sc_params.channels 810 * sc->sc_params.precision; 811 pipe_ts_link(sc, 20, PIPEoutput, 16, 32, sc->sc_mm.offset + 32); 812 pipe_ts_link(sc, 4, PIPEoutput, 16, data_width, sc->sc_mm.offset); 813 pipe_ts_link(sc, 6, PIPEinput, 16, data_width, sc->sc_mm.offset); 814 pipe_ts_link(sc, 21, PIPEinput, 16, 16, sc->sc_mm.offset + 40); 815 816 mmcodec_setgain(sc, 0); 817 818 tmp = bus_space_read_4(iot, ioh, DBRI_REG0); 819 tmp |= DBRI_CHI_ACTIVATE; 820 bus_space_write_4(iot, ioh, DBRI_REG0, tmp); 821 822 return; 823 } 824 825 void 826 mmcodec_pipe_init(struct dbri_softc *sc) 827 { 828 829 pipe_setup(sc, 4, DBRI_SDP_MEM | DBRI_SDP_TO_SER | DBRI_SDP_MSB); 830 pipe_setup(sc, 20, DBRI_SDP_FIXED | DBRI_SDP_TO_SER | DBRI_SDP_MSB); 831 pipe_setup(sc, 6, DBRI_SDP_MEM | DBRI_SDP_FROM_SER | DBRI_SDP_MSB); 832 pipe_setup(sc, 21, DBRI_SDP_FIXED | DBRI_SDP_FROM_SER | DBRI_SDP_MSB); 833 834 pipe_setup(sc, 17, DBRI_SDP_FIXED | DBRI_SDP_TO_SER | DBRI_SDP_MSB); 835 pipe_setup(sc, 18, DBRI_SDP_FIXED | DBRI_SDP_FROM_SER | DBRI_SDP_MSB); 836 pipe_setup(sc, 19, DBRI_SDP_FIXED | DBRI_SDP_FROM_SER | DBRI_SDP_MSB); 837 838 sc->sc_mm.status = 0; 839 840 pipe_receive_fixed(sc, 18, &sc->sc_mm.status); 841 pipe_receive_fixed(sc, 19, &sc->sc_mm.version); 842 843 return; 844 } 845 846 void 847 mmcodec_default(struct dbri_softc *sc) 848 { 849 struct cs4215_state *mm = &sc->sc_mm; 850 851 /* 852 * no action, memory resetting only 853 * 854 * data time slots 5-8 855 * speaker, line and headphone enable. set gain to half. 856 * input is mic 857 */ 858 mm->d.bdata[0] = sc->sc_latt = 0x20 | CS4215_HE | CS4215_LE; 859 mm->d.bdata[1] = sc->sc_ratt = 0x20 | CS4215_SE; 860 mm->d.bdata[2] = CS4215_LG(0x08) | CS4215_IS | CS4215_PIO0 | CS4215_PIO1; 861 mm->d.bdata[3] = CS4215_RG(0x08) | CS4215_MA(0x0f); 862 863 /* 864 * control time slots 1-4 865 * 866 * 0: default I/O voltage scale 867 * 1: 8 bit ulaw, 8kHz, mono, high pass filter disabled 868 * 2: serial enable, CHI master, 128 bits per frame, clock 1 869 * 3: tests disabled 870 */ 871 mm->c.bcontrol[0] = CS4215_RSRVD_1 | CS4215_MLB; 872 mm->c.bcontrol[1] = CS4215_DFR_ULAW | CS4215_FREQ[0].csval; 873 mm->c.bcontrol[2] = CS4215_XCLK | CS4215_BSEL_128 | CS4215_FREQ[0].xtal; 874 mm->c.bcontrol[3] = 0; 875 876 return; 877 } 878 879 void 880 mmcodec_setgain(struct dbri_softc *sc, int mute) 881 { 882 if (mute) { 883 /* disable all outputs, max. attenuation */ 884 sc->sc_mm.d.bdata[0] = sc->sc_latt | 63; 885 sc->sc_mm.d.bdata[1] = sc->sc_ratt | 63; 886 } else { 887 /* 888 * We should be setting the proper output here.. for now, 889 * use the speaker. Possible outputs: 890 * Headphones: 891 * data[0] |= CS4215_HE; 892 * Line out: 893 * data[0] |= CS4215_LE; 894 * Speaker: 895 * data[1] |= CS4215_SE; 896 */ 897 sc->sc_mm.d.bdata[0] = sc->sc_latt; 898 sc->sc_mm.d.bdata[1] = sc->sc_ratt; 899 } 900 901 if (sc->sc_powerstate == 0) 902 return; 903 pipe_transmit_fixed(sc, 20, sc->sc_mm.d.ldata); 904 905 /* give the chip some time to execure the command */ 906 delay(250); 907 908 return; 909 } 910 911 int 912 mmcodec_setcontrol(struct dbri_softc *sc) 913 { 914 bus_space_tag_t iot = sc->sc_iot; 915 bus_space_handle_t ioh = sc->sc_ioh; 916 u_int32_t val; 917 u_int32_t tmp; 918 #if 1 919 int i; 920 #endif 921 922 /* 923 * Temporarily mute outputs and wait 125 us to make sure that it 924 * happens. This avoids clicking noises. 925 */ 926 mmcodec_setgain(sc, 1); 927 delay(125); 928 929 /* enable control mode */ 930 val = DBRI_PIO_ENABLE_ALL | DBRI_PIO1; /* was PIO1 */ 931 932 /* XXX */ 933 val |= (sc->sc_mm.onboard ? DBRI_PIO0 : DBRI_PIO2); 934 935 bus_space_write_4(iot, ioh, DBRI_REG2, val); 936 937 delay(34); 938 939 /* 940 * in control mode, the cs4215 is the slave device, so the 941 * DBRI must act as the CHI master. 942 * 943 * in data mode, the cs4215 must be the CHI master to insure 944 * that the data stream is in sync with its codec 945 */ 946 tmp = bus_space_read_4(iot, ioh, DBRI_REG0); 947 tmp &= ~DBRI_COMMAND_CHI; 948 bus_space_write_4(iot, ioh, DBRI_REG0, tmp); 949 950 chi_reset(sc, CHImaster, 128); 951 952 /* control mode */ 953 pipe_ts_link(sc, 17, PIPEoutput, 16, 32, sc->sc_mm.offset); 954 pipe_ts_link(sc, 18, PIPEinput, 16, 8, sc->sc_mm.offset); 955 pipe_ts_link(sc, 19, PIPEinput, 16, 8, sc->sc_mm.offset + 48); 956 957 /* wait for the chip to echo back CLB as zero */ 958 sc->sc_mm.c.bcontrol[0] &= ~CS4215_CLB; 959 pipe_transmit_fixed(sc, 17, sc->sc_mm.c.lcontrol); 960 961 tmp = bus_space_read_4(iot, ioh, DBRI_REG0); 962 tmp |= DBRI_CHI_ACTIVATE; 963 bus_space_write_4(iot, ioh, DBRI_REG0, tmp); 964 965 #if 1 966 i = 1024; 967 while (((sc->sc_mm.status & 0xe4) != 0x20) && --i) { 968 delay(125); 969 } 970 971 if (i == 0) { 972 printf("%s: cs4215 didn't respond to CLB (0x%02x)\n", 973 sc->sc_dev.dv_xname, sc->sc_mm.status); 974 return (-1); 975 } 976 #else 977 while ((sc->sc_mm.status & 0xe4) != 0x20) { 978 printf("%s: tsleep %p\n", sc->sc_dev.dv_xname, sc); 979 tsleep(sc, PCATCH | PZERO, "dbrifxdt", 0); 980 } 981 #endif 982 983 /* copy the version information before it becomes unreadable again */ 984 sc->sc_version = sc->sc_mm.version; 985 986 /* terminate cs4215 control mode */ 987 sc->sc_mm.c.bcontrol[0] |= CS4215_CLB; 988 pipe_transmit_fixed(sc, 17, sc->sc_mm.c.lcontrol); 989 990 /* two frames of control info @ 8kHz frame rate = 250us delay */ 991 delay(250); 992 993 mmcodec_setgain(sc, 0); 994 995 return (0); 996 997 } 998 999 /* 1000 * CHI combo 1001 */ 1002 void 1003 chi_reset(struct dbri_softc *sc, enum ms ms, int bpf) 1004 { 1005 volatile u_int32_t *cmd; 1006 int val; 1007 int clockrate, divisor; 1008 1009 cmd = dbri_command_lock(sc); 1010 1011 /* set CHI anchor: pipe 16 */ 1012 val = DBRI_DTS_VI | DBRI_DTS_INS | DBRI_DTS_PRVIN(16) | DBRI_PIPE(16); 1013 *(cmd++) = DBRI_CMD(DBRI_COMMAND_DTS, 0, val); 1014 *(cmd++) = DBRI_TS_ANCHOR | DBRI_TS_NEXT(16); 1015 *(cmd++) = 0; 1016 1017 val = DBRI_DTS_VO | DBRI_DTS_INS | DBRI_DTS_PRVOUT(16) | DBRI_PIPE(16); 1018 *(cmd++) = DBRI_CMD(DBRI_COMMAND_DTS, 0, val); 1019 *(cmd++) = 0; 1020 *(cmd++) = DBRI_TS_ANCHOR | DBRI_TS_NEXT(16); 1021 1022 sc->sc_pipe[16].sdp = 1; 1023 sc->sc_pipe[16].next = 16; 1024 sc->sc_chi_pipe_in = 16; 1025 sc->sc_chi_pipe_out = 16; 1026 1027 switch (ms) { 1028 case CHIslave: 1029 *(cmd++) = DBRI_CMD(DBRI_COMMAND_CHI, 0, DBRI_CHI_CHICM(0)); 1030 break; 1031 case CHImaster: 1032 clockrate = bpf * 8; 1033 divisor = 12288 / clockrate; 1034 1035 if (divisor > 255 || divisor * clockrate != 12288) 1036 printf("%s: illegal bits-per-frame %d\n", 1037 sc->sc_dev.dv_xname, bpf); 1038 1039 *(cmd++) = DBRI_CMD(DBRI_COMMAND_CHI, 0, 1040 DBRI_CHI_CHICM(divisor) | DBRI_CHI_FD | DBRI_CHI_BPF(bpf)); 1041 break; 1042 default: 1043 printf("%s: unknown value for ms!\n", sc->sc_dev.dv_xname); 1044 break; 1045 } 1046 1047 sc->sc_chi_bpf = bpf; 1048 1049 /* CHI data mode */ 1050 *(cmd++) = DBRI_CMD(DBRI_COMMAND_PAUSE, 0, 0); 1051 *(cmd++) = DBRI_CMD(DBRI_COMMAND_CDM, 0, 1052 DBRI_CDM_XCE | DBRI_CDM_XEN | DBRI_CDM_REN); 1053 1054 dbri_command_send(sc, cmd); 1055 1056 return; 1057 } 1058 1059 /* 1060 * pipe stuff 1061 */ 1062 void 1063 pipe_setup(struct dbri_softc *sc, int pipe, int sdp) 1064 { 1065 DPRINTF(("pipe setup: %d\n", pipe)); 1066 if (pipe < 0 || pipe >= DBRI_PIPE_MAX) { 1067 printf("%s: illegal pipe number %d\n", sc->sc_dev.dv_xname, 1068 pipe); 1069 return; 1070 } 1071 1072 if ((sdp & 0xf800) != sdp) 1073 printf("%s: strange SDP value %d\n", sc->sc_dev.dv_xname, sdp); 1074 1075 if (DBRI_SDP_MODE(sdp) == DBRI_SDP_FIXED && 1076 !(sdp & DBRI_SDP_TO_SER)) 1077 sdp |= DBRI_SDP_CHANGE; 1078 1079 sdp |= DBRI_PIPE(pipe); 1080 1081 sc->sc_pipe[pipe].sdp = sdp; 1082 sc->sc_pipe[pipe].desc = -1; 1083 1084 pipe_reset(sc, pipe); 1085 1086 return; 1087 } 1088 1089 void 1090 pipe_reset(struct dbri_softc *sc, int pipe) 1091 { 1092 struct dbri_desc *dd; 1093 int sdp; 1094 int desc; 1095 volatile u_int32_t *cmd; 1096 1097 if (pipe < 0 || pipe >= DBRI_PIPE_MAX) { 1098 printf("%s: illegal pipe number %d\n", sc->sc_dev.dv_xname, 1099 pipe); 1100 return; 1101 } 1102 1103 sdp = sc->sc_pipe[pipe].sdp; 1104 if (sdp == 0) { 1105 printf("%s: can not reset uninitialized pipe %d\n", 1106 sc->sc_dev.dv_xname, pipe); 1107 return; 1108 } 1109 1110 cmd = dbri_command_lock(sc); 1111 *(cmd++) = DBRI_CMD(DBRI_COMMAND_SDP, 0, 1112 sdp | DBRI_SDP_CLEAR | DBRI_SDP_VALID_POINTER); 1113 *(cmd++) = 0; 1114 dbri_command_send(sc, cmd); 1115 1116 desc = sc->sc_pipe[pipe].desc; 1117 1118 dd = &sc->sc_desc[desc]; 1119 1120 dd->busy = 0; 1121 1122 #if 0 1123 if (dd->callback) 1124 (*dd->callback)(dd->callback_args); 1125 #endif 1126 1127 sc->sc_pipe[pipe].desc = -1; 1128 1129 return; 1130 } 1131 1132 void 1133 pipe_receive_fixed(struct dbri_softc *sc, int pipe, volatile u_int32_t *prec) 1134 { 1135 1136 if (pipe < DBRI_PIPE_MAX / 2 || pipe >= DBRI_PIPE_MAX) { 1137 printf("%s: illegal pipe number %d\n", sc->sc_dev.dv_xname, 1138 pipe); 1139 return; 1140 } 1141 1142 if (DBRI_SDP_MODE(sc->sc_pipe[pipe].sdp) != DBRI_SDP_FIXED) { 1143 printf("%s: non-fixed pipe %d\n", sc->sc_dev.dv_xname, 1144 pipe); 1145 return; 1146 } 1147 1148 if (sc->sc_pipe[pipe].sdp & DBRI_SDP_TO_SER) { 1149 printf("%s: can not receive on transmit pipe %d\b", 1150 sc->sc_dev.dv_xname, pipe); 1151 return; 1152 } 1153 1154 sc->sc_pipe[pipe].prec = prec; 1155 1156 return; 1157 } 1158 1159 void 1160 pipe_transmit_fixed(struct dbri_softc *sc, int pipe, u_int32_t data) 1161 { 1162 volatile u_int32_t *cmd; 1163 1164 if (pipe < DBRI_PIPE_MAX / 2 || pipe >= DBRI_PIPE_MAX) { 1165 printf("%s: illegal pipe number %d\n", sc->sc_dev.dv_xname, 1166 pipe); 1167 return; 1168 } 1169 1170 if (DBRI_SDP_MODE(sc->sc_pipe[pipe].sdp) == 0) { 1171 printf("%s: uninitialized pipe %d\n", sc->sc_dev.dv_xname, 1172 pipe); 1173 return; 1174 } 1175 1176 if (DBRI_SDP_MODE(sc->sc_pipe[pipe].sdp) != DBRI_SDP_FIXED) { 1177 printf("%s: non-fixed pipe %d\n", sc->sc_dev.dv_xname, pipe); 1178 return; 1179 } 1180 1181 if (!(sc->sc_pipe[pipe].sdp & DBRI_SDP_TO_SER)) { 1182 printf("%s: called on receive pipe %d\n", sc->sc_dev.dv_xname, 1183 pipe); 1184 return; 1185 } 1186 1187 if (sc->sc_pipe[pipe].sdp & DBRI_SDP_MSB) 1188 data = reverse_bytes(data, sc->sc_pipe[pipe].length); 1189 1190 cmd = dbri_command_lock(sc); 1191 *(cmd++) = DBRI_CMD(DBRI_COMMAND_SSP, 0, pipe); 1192 *(cmd++) = data; 1193 1194 dbri_command_send(sc, cmd); 1195 1196 return; 1197 } 1198 1199 void 1200 setup_ring(struct dbri_softc *sc, int pipe, int which, int num, int blksz, 1201 void (*callback)(void *), void *callback_args) 1202 { 1203 volatile u_int32_t *cmd; 1204 int x, i; 1205 int td; 1206 int td_first, td_last; 1207 bus_addr_t dmabuf, dmabase; 1208 struct dbri_desc *dd = &sc->sc_desc[which]; 1209 1210 td = 0; 1211 td_first = td_last = -1; 1212 1213 if (pipe < 0 || pipe >= DBRI_PIPE_MAX / 2) { 1214 printf("%s: illegal pipe number %d\n", sc->sc_dev.dv_xname, 1215 pipe); 1216 return; 1217 } 1218 1219 if (sc->sc_pipe[pipe].sdp == 0) { 1220 printf("%s: uninitialized pipe %d\n", sc->sc_dev.dv_xname, 1221 pipe); 1222 return; 1223 } 1224 1225 if (!(sc->sc_pipe[pipe].sdp & DBRI_SDP_TO_SER)) { 1226 printf("%s: called on receive pipe %d\n", 1227 sc->sc_dev.dv_xname, pipe); 1228 return; 1229 } 1230 1231 1232 dmabuf = dd->dmabase; 1233 dmabase = sc->sc_dmabase; 1234 td = 0; 1235 1236 for (i = 0; i < (num-1); i++) { 1237 1238 sc->sc_dma->desc[i].flags = TX_BCNT(blksz) 1239 | TX_EOF | TX_BINT; 1240 sc->sc_dma->desc[i].ba = dmabuf; 1241 sc->sc_dma->desc[i].nda = dmabase + dbri_dma_off(desc, i + 1); 1242 sc->sc_dma->desc[i].status = 0; 1243 1244 td_last = td; 1245 dmabuf += blksz; 1246 } 1247 1248 sc->sc_dma->desc[i].flags = TX_BCNT(blksz) | TX_EOF | TX_BINT; 1249 sc->sc_dma->desc[i].ba = dmabuf; 1250 sc->sc_dma->desc[i].nda = dmabase + dbri_dma_off(desc, 0); 1251 sc->sc_dma->desc[i].status = 0; 1252 1253 dd->callback = callback; //sc->intr; 1254 dd->callback_args = callback_args; //sc->intrarg; 1255 1256 x = splaudio(); 1257 1258 /* the pipe shouldn't be active */ 1259 if (pipe_active(sc, pipe)) { 1260 printf("pipe active (CDP)\n"); 1261 /* pipe is already active */ 1262 #if 0 1263 td_last = sc->sc_pipe[pipe].desc; 1264 while (sc->sc_desc[td_last].next != -1) 1265 td_last = sc->sc_desc[td_last].next; 1266 1267 sc->sc_desc[td_last].next = td_first; 1268 sc->sc_dma->desc[td_last].nda = 1269 sc->sc_dmabase + dbri_dma_off(desc, td_first); 1270 1271 cmd = dbri_command_lock(sc); 1272 *(cmd++) = DBRI_CMD(DBRI_COMMAND_CDP, 0, pipe); 1273 dbri_command_send(sc, cmd); 1274 #endif 1275 } else { 1276 /* 1277 * pipe isn't active - issue an SDP command to start our 1278 * chain of TDs running 1279 */ 1280 sc->sc_pipe[pipe].desc = which; 1281 cmd = dbri_command_lock(sc); 1282 *(cmd++) = DBRI_CMD(DBRI_COMMAND_SDP, 0, 1283 sc->sc_pipe[pipe].sdp | 1284 DBRI_SDP_VALID_POINTER | 1285 DBRI_SDP_EVERY | 1286 DBRI_SDP_CLEAR); 1287 *(cmd++) = sc->sc_dmabase + dbri_dma_off(desc, 0); 1288 dbri_command_send(sc, cmd); 1289 } 1290 1291 splx(x); 1292 1293 return; 1294 } 1295 1296 void 1297 pipe_ts_link(struct dbri_softc *sc, int pipe, enum io dir, int basepipe, 1298 int len, int cycle) 1299 { 1300 volatile u_int32_t *cmd; 1301 int prevpipe, nextpipe; 1302 int val; 1303 1304 if (pipe < 0 || pipe >= DBRI_PIPE_MAX || 1305 basepipe < 0 || basepipe >= DBRI_PIPE_MAX) { 1306 printf("%s: illegal pipe numbers (%d, %d)\n", 1307 sc->sc_dev.dv_xname, pipe, basepipe); 1308 return; 1309 } 1310 1311 if (sc->sc_pipe[pipe].sdp == 0 || sc->sc_pipe[basepipe].sdp == 0) { 1312 printf("%s: uninitialized pipe (%d, %d)\n", 1313 sc->sc_dev.dv_xname, pipe, basepipe); 1314 return; 1315 } 1316 1317 if (basepipe == 16 && dir == PIPEoutput && cycle == 0) 1318 cycle = sc->sc_chi_bpf; 1319 1320 if (basepipe == pipe) 1321 prevpipe = nextpipe = pipe; 1322 else { 1323 if (basepipe == 16) { 1324 if (dir == PIPEinput) { 1325 prevpipe = sc->sc_chi_pipe_in; 1326 } else { 1327 prevpipe = sc->sc_chi_pipe_out; 1328 } 1329 } else 1330 prevpipe = basepipe; 1331 1332 nextpipe = sc->sc_pipe[prevpipe].next; 1333 1334 while (sc->sc_pipe[nextpipe].cycle < cycle && 1335 sc->sc_pipe[nextpipe].next != basepipe) { 1336 prevpipe = nextpipe; 1337 nextpipe = sc->sc_pipe[nextpipe].next; 1338 } 1339 } 1340 1341 if (prevpipe == 16) { 1342 if (dir == PIPEinput) { 1343 sc->sc_chi_pipe_in = pipe; 1344 } else { 1345 sc->sc_chi_pipe_out = pipe; 1346 } 1347 } else 1348 sc->sc_pipe[prevpipe].next = pipe; 1349 1350 sc->sc_pipe[pipe].next = nextpipe; 1351 sc->sc_pipe[pipe].cycle = cycle; 1352 sc->sc_pipe[pipe].length = len; 1353 1354 cmd = dbri_command_lock(sc); 1355 1356 switch (dir) { 1357 case PIPEinput: 1358 val = DBRI_DTS_VI | DBRI_DTS_INS | DBRI_DTS_PRVIN(prevpipe); 1359 val |= pipe; 1360 *(cmd++) = DBRI_CMD(DBRI_COMMAND_DTS, 0, val); 1361 *(cmd++) = DBRI_TS_LEN(len) | DBRI_TS_CYCLE(cycle) | 1362 DBRI_TS_NEXT(nextpipe); 1363 *(cmd++) = 0; 1364 break; 1365 case PIPEoutput: 1366 val = DBRI_DTS_VO | DBRI_DTS_INS | DBRI_DTS_PRVOUT(prevpipe); 1367 val |= pipe; 1368 *(cmd++) = DBRI_CMD(DBRI_COMMAND_DTS, 0, val); 1369 *(cmd++) = 0; 1370 *(cmd++) = DBRI_TS_LEN(len) | DBRI_TS_CYCLE(cycle) | 1371 DBRI_TS_NEXT(nextpipe); 1372 break; 1373 default: 1374 printf("%s: should not have happened!\n", 1375 sc->sc_dev.dv_xname); 1376 break; 1377 } 1378 1379 dbri_command_send(sc, cmd); 1380 1381 return; 1382 } 1383 1384 int 1385 pipe_active(struct dbri_softc *sc, int pipe) 1386 { 1387 1388 return (sc->sc_pipe[pipe].desc != -1); 1389 } 1390 1391 /* 1392 * subroutines required to interface with audio(9) 1393 */ 1394 1395 int 1396 dbri_query_encoding(void *hdl, struct audio_encoding *ae) 1397 { 1398 1399 /* XXX we shouldn't claim we support LE samples */ 1400 switch (ae->index) { 1401 case 0: 1402 strcpy(ae->name, AudioEulinear); 1403 ae->encoding = AUDIO_ENCODING_ULINEAR; 1404 ae->precision = 8; 1405 ae->flags = AUDIO_ENCODINGFLAG_EMULATED; 1406 break; 1407 case 1: 1408 strcpy(ae->name, AudioEmulaw); 1409 ae->encoding = AUDIO_ENCODING_ULAW; 1410 ae->precision = 8; 1411 ae->flags = 0; 1412 break; 1413 case 2: 1414 strcpy(ae->name, AudioEalaw); 1415 ae->encoding = AUDIO_ENCODING_ALAW; 1416 ae->precision = 8; 1417 ae->flags = 0; 1418 break; 1419 case 3: 1420 strcpy(ae->name, AudioEslinear); 1421 ae->encoding = AUDIO_ENCODING_SLINEAR; 1422 ae->precision = 8; 1423 ae->flags = AUDIO_ENCODINGFLAG_EMULATED; 1424 break; 1425 case 4: 1426 strcpy(ae->name, AudioEslinear_le); 1427 ae->encoding = AUDIO_ENCODING_SLINEAR_LE; 1428 ae->precision = 16; 1429 ae->flags = AUDIO_ENCODINGFLAG_EMULATED; 1430 break; 1431 case 5: 1432 strcpy(ae->name, AudioEulinear_le); 1433 ae->encoding = AUDIO_ENCODING_ULINEAR_LE; 1434 ae->precision = 16; 1435 ae->flags = AUDIO_ENCODINGFLAG_EMULATED; 1436 break; 1437 case 6: 1438 strcpy(ae->name, AudioEslinear_be); 1439 ae->encoding = AUDIO_ENCODING_SLINEAR_BE; 1440 ae->precision = 16; 1441 ae->flags = 0; 1442 break; 1443 case 7: 1444 strcpy(ae->name, AudioEulinear_be); 1445 ae->encoding = AUDIO_ENCODING_ULINEAR_BE; 1446 ae->precision = 16; 1447 ae->flags = 0; 1448 break; 1449 default: 1450 return (EINVAL); 1451 } 1452 1453 return (0); 1454 } 1455 1456 /* 1457 * XXX: recording isn't supported - jmcneill 1458 */ 1459 int 1460 dbri_set_params(void *hdl, int setmode, int usemode, 1461 struct audio_params *play, struct audio_params *rec, 1462 stream_filter_list_t *pfil, stream_filter_list_t *rfil) 1463 { 1464 struct dbri_softc *sc = hdl; 1465 int i; 1466 1467 if ((play->precision != 8 && play->precision != 16) || 1468 (play->channels != 1 && play->channels != 2)) 1469 return (EINVAL); 1470 1471 for (i = 0; CS4215_FREQ[i].freq; i++) 1472 if (CS4215_FREQ[i].freq == play->sample_rate) 1473 break; 1474 1475 if (CS4215_FREQ[i].freq == 0) 1476 return (EINVAL); 1477 1478 /* set frequency */ 1479 sc->sc_mm.c.bcontrol[1] &= ~0x38; 1480 sc->sc_mm.c.bcontrol[1] |= CS4215_FREQ[i].csval; 1481 sc->sc_mm.c.bcontrol[2] &= ~0x70; 1482 sc->sc_mm.c.bcontrol[2] |= CS4215_FREQ[i].xtal; 1483 1484 /*play->factor = 1; 1485 play->sw_code = NULL;*/ 1486 1487 switch (play->encoding) { 1488 case AUDIO_ENCODING_ULAW: 1489 sc->sc_mm.c.bcontrol[1] &= ~3; 1490 sc->sc_mm.c.bcontrol[1] |= CS4215_DFR_ULAW; 1491 break; 1492 case AUDIO_ENCODING_ALAW: 1493 sc->sc_mm.c.bcontrol[1] &= ~3; 1494 sc->sc_mm.c.bcontrol[1] |= CS4215_DFR_ALAW; 1495 break; 1496 case AUDIO_ENCODING_SLINEAR_LE: 1497 case AUDIO_ENCODING_ULINEAR_LE: 1498 if (play->precision == 16) { 1499 /* XXX this surely needs some changes elsewhere */ 1500 /*play->sw_code = swap_bytes;*/ 1501 sc->sc_mm.c.bcontrol[1] &= ~3; 1502 sc->sc_mm.c.bcontrol[1] |= CS4215_DFR_LINEAR16; 1503 } 1504 break; 1505 case AUDIO_ENCODING_ULINEAR: 1506 case AUDIO_ENCODING_SLINEAR: 1507 sc->sc_mm.c.bcontrol[1] &= ~3; 1508 if (play->precision == 8) { 1509 sc->sc_mm.c.bcontrol[1] |= CS4215_DFR_LINEAR8; 1510 } else { 1511 sc->sc_mm.c.bcontrol[1] |= CS4215_DFR_LINEAR16; 1512 } 1513 break; 1514 case AUDIO_ENCODING_ULINEAR_BE: 1515 case AUDIO_ENCODING_SLINEAR_BE: 1516 sc->sc_mm.c.bcontrol[1] &= ~3; 1517 sc->sc_mm.c.bcontrol[1] |= CS4215_DFR_LINEAR16; 1518 break; 1519 } 1520 1521 switch (play->channels) { 1522 case 1: 1523 sc->sc_mm.c.bcontrol[1] &= ~CS4215_DFR_STEREO; 1524 break; 1525 case 2: 1526 sc->sc_mm.c.bcontrol[1] |= CS4215_DFR_STEREO; 1527 break; 1528 } 1529 1530 return (0); 1531 } 1532 1533 int 1534 dbri_round_blocksize(void *hdl, int bs, int mode, 1535 const audio_params_t *param) 1536 { 1537 1538 /* DBRI DMA segment size, rounded town to 32bit alignment */ 1539 return 0x1ffc; 1540 } 1541 1542 int 1543 dbri_halt_output(void *hdl) 1544 { 1545 struct dbri_softc *sc = hdl; 1546 1547 pipe_reset(sc, 4); 1548 1549 return (0); 1550 } 1551 1552 int 1553 dbri_getdev(void *hdl, struct audio_device *ret) 1554 { 1555 1556 *ret = dbri_device; 1557 return (0); 1558 } 1559 1560 int 1561 dbri_set_port(void *hdl, mixer_ctrl_t *mc) 1562 { 1563 struct dbri_softc *sc = hdl; 1564 int latt = sc->sc_latt, ratt = sc->sc_ratt; 1565 1566 switch (mc->dev) { 1567 case DBRI_VOL_OUTPUT: /* master volume */ 1568 latt = (latt & 0xc0) | (63 - 1569 min(mc->un.value.level[AUDIO_MIXER_LEVEL_LEFT] >> 2, 63)); 1570 ratt = (ratt & 0xc0) | (63 - 1571 min(mc->un.value.level[AUDIO_MIXER_LEVEL_RIGHT] >> 2, 63)); 1572 break; 1573 case DBRI_ENABLE_MONO: /* built-in speaker */ 1574 if (mc->un.ord == 1) { 1575 ratt |= CS4215_SE; 1576 } else 1577 ratt &= ~CS4215_SE; 1578 break; 1579 case DBRI_ENABLE_HEADPHONE: /* headphones output */ 1580 if (mc->un.ord == 1) { 1581 latt |= CS4215_HE; 1582 } else 1583 latt &= ~CS4215_HE; 1584 break; 1585 case DBRI_ENABLE_LINE: /* line out */ 1586 if (mc->un.ord == 1) { 1587 latt |= CS4215_LE; 1588 } else 1589 latt &= ~CS4215_LE; 1590 break; 1591 } 1592 1593 sc->sc_latt = latt; 1594 sc->sc_ratt = ratt; 1595 1596 /* no need to do that here - mmcodec_setgain does it anyway */ 1597 /*pipe_transmit_fixed(sc, 20, *(int *)__UNVOLATILE(sc->sc_mm.data));*/ 1598 1599 mmcodec_setgain(sc, 0); 1600 1601 return (0); 1602 } 1603 1604 int 1605 dbri_get_port(void *hdl, mixer_ctrl_t *mc) 1606 { 1607 struct dbri_softc *sc = hdl; 1608 1609 switch (mc->dev) { 1610 case DBRI_VOL_OUTPUT: /* master volume */ 1611 mc->un.value.level[AUDIO_MIXER_LEVEL_LEFT] = 1612 (63 - (sc->sc_latt & 0x3f)) << 2; 1613 mc->un.value.level[AUDIO_MIXER_LEVEL_RIGHT] = 1614 (63 - (sc->sc_ratt & 0x3f)) << 2; 1615 return (0); 1616 case DBRI_ENABLE_MONO: /* built-in speaker */ 1617 mc->un.ord = (sc->sc_ratt & CS4215_SE) ? 1 : 0; 1618 return 0; 1619 case DBRI_ENABLE_HEADPHONE: /* headphones output */ 1620 mc->un.ord = (sc->sc_latt & CS4215_HE) ? 1 : 0; 1621 return 0; 1622 case DBRI_ENABLE_LINE: /* line out */ 1623 mc->un.ord = (sc->sc_latt & CS4215_LE) ? 1 : 0; 1624 return 0; 1625 } 1626 return (EINVAL); 1627 } 1628 1629 int 1630 dbri_query_devinfo(void *hdl, mixer_devinfo_t *di) 1631 { 1632 1633 switch (di->index) { 1634 case DBRI_MONITOR_CLASS: 1635 di->mixer_class = DBRI_MONITOR_CLASS; 1636 strcpy(di->label.name, AudioCmonitor); 1637 di->type = AUDIO_MIXER_CLASS; 1638 di->next = di->prev = AUDIO_MIXER_LAST; 1639 return 0; 1640 case DBRI_VOL_OUTPUT: /* master volume */ 1641 di->mixer_class = DBRI_MONITOR_CLASS; 1642 di->next = di->prev = AUDIO_MIXER_LAST; 1643 strcpy(di->label.name, AudioNmaster); 1644 di->type = AUDIO_MIXER_VALUE; 1645 di->un.v.num_channels = 2; 1646 strcpy(di->un.v.units.name, AudioNvolume); 1647 return (0); 1648 case DBRI_ENABLE_MONO: /* built-in speaker */ 1649 di->mixer_class = DBRI_MONITOR_CLASS; 1650 di->next = di->prev = AUDIO_MIXER_LAST; 1651 strcpy(di->label.name, AudioNmono); 1652 di->type = AUDIO_MIXER_ENUM; 1653 di->un.e.num_mem = 2; 1654 strcpy(di->un.e.member[0].label.name, AudioNoff); 1655 di->un.e.member[0].ord = 0; 1656 strcpy(di->un.e.member[1].label.name, AudioNon); 1657 di->un.e.member[1].ord = 1; 1658 return (0); 1659 case DBRI_ENABLE_HEADPHONE: /* headphones output */ 1660 di->mixer_class = DBRI_MONITOR_CLASS; 1661 di->next = di->prev = AUDIO_MIXER_LAST; 1662 strcpy(di->label.name, AudioNheadphone); 1663 di->type = AUDIO_MIXER_ENUM; 1664 di->un.e.num_mem = 2; 1665 strcpy(di->un.e.member[0].label.name, AudioNoff); 1666 di->un.e.member[0].ord = 0; 1667 strcpy(di->un.e.member[1].label.name, AudioNon); 1668 di->un.e.member[1].ord = 1; 1669 return (0); 1670 case DBRI_ENABLE_LINE: /* line out */ 1671 di->mixer_class = DBRI_MONITOR_CLASS; 1672 di->next = di->prev = AUDIO_MIXER_LAST; 1673 strcpy(di->label.name, AudioNline); 1674 di->type = AUDIO_MIXER_ENUM; 1675 di->un.e.num_mem = 2; 1676 strcpy(di->un.e.member[0].label.name, AudioNoff); 1677 di->un.e.member[0].ord = 0; 1678 strcpy(di->un.e.member[1].label.name, AudioNon); 1679 di->un.e.member[1].ord = 1; 1680 return (0); 1681 } 1682 1683 return (ENXIO); 1684 } 1685 1686 size_t 1687 dbri_round_buffersize(void *hdl, int dir, size_t bufsize) 1688 { 1689 #ifdef DBRI_BIG_BUFFER 1690 return 16*0x1ffc; /* use ~128KB buffer */ 1691 #else 1692 return bufsize; 1693 #endif 1694 } 1695 1696 int 1697 dbri_get_props(void *hdl) 1698 { 1699 1700 return (AUDIO_PROP_MMAP/* | AUDIO_PROP_INDEPENDENT*/); 1701 //return (0); 1702 } 1703 1704 int 1705 dbri_trigger_output(void *hdl, void *start, void *end, int blksize, 1706 void (*intr)(void *), void *intrarg, 1707 const struct audio_params *param) 1708 { 1709 struct dbri_softc *sc = hdl; 1710 unsigned long count, current, num; 1711 1712 count = (unsigned long)(((char *)end - (char *)start)); 1713 num = count / blksize; 1714 1715 DPRINTF(("trigger_output(%lx %lx) : %d %ld %ld\n", 1716 (unsigned long)intr, 1717 (unsigned long)intrarg, blksize, count, num)); 1718 1719 sc->sc_params = *param; 1720 1721 mmcodec_setcontrol(sc); 1722 mmcodec_init_data(sc); 1723 current = 0; 1724 while ((current < sc->sc_desc_used) && 1725 (sc->sc_desc[current].buf != start)) 1726 current++; 1727 1728 if (current < sc->sc_desc_used) { 1729 setup_ring(sc, 4, current, num, blksize, intr, intrarg); 1730 return 0; 1731 } 1732 return EINVAL; 1733 } 1734 1735 u_int32_t 1736 reverse_bytes(u_int32_t b, int len) 1737 { 1738 switch (len) { 1739 case 32: 1740 b = ((b & 0xffff0000) >> 16) | ((b & 0x0000ffff) << 16); 1741 case 16: 1742 b = ((b & 0xff00ff00) >> 8) | ((b & 0x00ff00ff) << 8); 1743 case 8: 1744 b = ((b & 0xf0f0f0f0) >> 4) | ((b & 0x0f0f0f0f) << 4); 1745 case 4: 1746 b = ((b & 0xcccccccc) >> 2) | ((b & 0x33333333) << 2); 1747 case 2: 1748 b = ((b & 0xaaaaaaaa) >> 1) | ((b & 0x55555555) << 1); 1749 case 1: 1750 case 0: 1751 break; 1752 default: 1753 printf("reverse_bytes: unsupported length\n"); 1754 }; 1755 1756 return (b); 1757 } 1758 1759 static void 1760 *dbri_malloc(void *v, int dir, size_t s, struct malloc_type *mt, int flags) 1761 { 1762 struct dbri_softc *sc = v; 1763 struct dbri_desc *dd = &sc->sc_desc[sc->sc_desc_used]; 1764 int rseg; 1765 1766 if (bus_dmamap_create(sc->sc_dmat, s, 1, s, 0, BUS_DMA_NOWAIT, 1767 &dd->dmamap) == 0) { 1768 if (bus_dmamem_alloc(sc->sc_dmat, s, 0, 0, &dd->dmaseg, 1769 1, &rseg, BUS_DMA_NOWAIT) == 0) { 1770 if (bus_dmamem_map(sc->sc_dmat, &dd->dmaseg, rseg, s, 1771 &dd->buf, BUS_DMA_NOWAIT|BUS_DMA_COHERENT) == 0) { 1772 if (dd->buf!=NULL) { 1773 if (bus_dmamap_load(sc->sc_dmat, 1774 dd->dmamap, dd->buf, s, NULL, 1775 BUS_DMA_NOWAIT) == 0) { 1776 dd->len = s; 1777 dd->busy = 0; 1778 dd->callback = NULL; 1779 dd->dmabase = 1780 dd->dmamap->dm_segs[0].ds_addr; 1781 DPRINTF(("dbri_malloc: using buffer %d\n", 1782 sc->sc_desc_used)); 1783 sc->sc_desc_used++; 1784 return dd->buf; 1785 } else 1786 printf("dbri_malloc: load failed\n"); 1787 } else 1788 printf("dbri_malloc: map returned NULL\n"); 1789 } else 1790 printf("dbri_malloc: map failed\n"); 1791 bus_dmamem_free(sc->sc_dmat, &dd->dmaseg, rseg); 1792 } else 1793 printf("dbri_malloc: malloc() failed\n"); 1794 bus_dmamap_destroy(sc->sc_dmat, dd->dmamap); 1795 } else 1796 printf("dbri_malloc: bus_dmamap_create() failed\n"); 1797 return NULL; 1798 } 1799 1800 static void 1801 dbri_free(void *v, void *p, struct malloc_type *mt) 1802 { 1803 free(p, mt); 1804 } 1805 1806 static paddr_t 1807 dbri_mappage(void *v, void *mem, off_t off, int prot) 1808 { 1809 struct dbri_softc *sc = v;; 1810 int current; 1811 1812 if (off < 0) 1813 return -1; 1814 1815 current = 0; 1816 while ((current < sc->sc_desc_used) && 1817 (sc->sc_desc[current].buf != mem)) 1818 current++; 1819 1820 if (current < sc->sc_desc_used) { 1821 return bus_dmamem_mmap(sc->sc_dmat, 1822 &sc->sc_desc[current].dmaseg, 1, off, prot, BUS_DMA_WAITOK); 1823 } 1824 1825 return -1; 1826 } 1827 1828 static int 1829 dbri_open(void *cookie, int flags) 1830 { 1831 struct dbri_softc *sc = cookie; 1832 1833 dbri_bring_up(sc); 1834 return 0; 1835 } 1836 1837 static void 1838 dbri_close(void *cookie) 1839 { 1840 struct dbri_softc *sc = cookie; 1841 1842 dbri_set_power(sc, 0); 1843 } 1844 1845 static void 1846 dbri_powerhook(int why, void *cookie) 1847 { 1848 struct dbri_softc *sc = cookie; 1849 1850 switch(why) 1851 { 1852 case PWR_SUSPEND: 1853 case PWR_STANDBY: 1854 dbri_set_power(sc, 0); 1855 break; 1856 case PWR_RESUME: 1857 dbri_bring_up(sc); 1858 break; 1859 } 1860 } 1861 1862 #endif /* NAUDIO > 0 */ 1863
Indexes created Thu Sep 25 16:09:42 GMT 2025