dbrireg.h revision 1.4
1 /* $NetBSD: dbrireg.h,v 1.4 2006/03/09 20:44:18 macallan Exp $ */ 2 3 /* 4 * Copyright (C) 1997 Rudolf Koenig (rfkoenig (at) immd4.informatik.uni-erlangen.de) 5 * Copyright (c) 1998, 1999 Brent Baccala (baccala (at) freesoft.org) 6 * Copyright (c) 2001, 2002 Jared D. McNeill <jmcneill (at) netbsd.org> 7 * Copyright (c) 2005 Michael Lorenz <macallan (at) netbsd.org> 8 * All rights reserved. 9 * 10 * This driver is losely based on a Linux driver written by Rudolf Koenig and 11 * Brent Baccala who kindly gave their permission to use their code in a 12 * BSD-licensed driver. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions 16 * are met: 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in the 21 * documentation and/or other materials provided with the distribution. 22 * 3. All advertising materials mentioning features or use of this software 23 * must display the following acknowledgement: 24 * This product includes software developed by Rudolf Koenig, Brent 25 * Baccala, Jared D. McNeill. 26 * 4. Neither the name of the author nor the names of any contributors may 27 * be used to endorse or promote products derived from this software 28 * without specific prior written permission. 29 * 30 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 31 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 33 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 36 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 37 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 38 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 39 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 40 * SUCH DAMAGE. 41 * 42 */ 43 44 #ifndef DBRI_REG_H 45 #define DBRI_REG_H 46 47 #define DBRI_REG0 0x00L /* status and control */ 48 #define DBRI_COMMAND_VALID (1<<15) 49 #define DBRI_BURST_4 (1<<14) /* allow 4-word sbus bursts */ 50 #define DBRI_BURST_16 (1<<13) /* allow 16-word sbus bursts */ 51 #define DBRI_BURST_8 (1<<12) /* allow 8-word sbus bursts */ 52 #define DBRI_CHI_ACTIVATE (1<<4) /* allow activation of CHI interface */ 53 #define DBRI_DISABLE_MASTER (1<<2) /* disable master mode */ 54 #define DBRI_SOFT_RESET (1<<0) /* soft reset */ 55 #define DBRI_REG1 0x04UL /* mode and interrupt */ 56 #define DBRI_MRR (1<<4) /* multiple error ack on sbus */ 57 #define DBRI_MLE (1<<3) /* multiple late error on sbus */ 58 #define DBRI_LBG (1<<2) /* lost bus grant on sbus */ 59 #define DBRI_MBE (1<<1) /* burst error on sbus */ 60 #define DBRI_REG2 0x08UL /* parallel I/O */ 61 #define DBRI_PIO2_ENABLE (1<<6) /* enable pin 2 */ 62 #define DBRI_PIO_ENABLE_ALL (0xf0) /* enable all the pins */ 63 #define DBRI_PIO3 (1<<3) /* pin 3: 1: data mode, 0: ctrl mode */ 64 #define DBRI_PIO2 (1<<2) /* pin 2: 1: onboard PDN */ /* XXX according to SPARCbook manual this is RESET */ 65 #define DBRI_PIO1 (1<<1) /* pin 1: 0: reset */ /* XXX according to SPARCbook manual this is PDN */ 66 #define DBRI_PIO0 (1<<0) /* pin 0: 1: speakerbox PDN */ 67 #define DBRI_REG8 0x20UL /* command queue pointer */ 68 #define DBRI_COMMAND_WAIT 0x0 69 #define DBRI_COMMAND_PAUSE 0x1 70 #define DBRI_COMMAND_IIQ 0x3 71 #define DBRI_COMMAND_SDP 0x5 72 #define DBRI_COMMAND_CDP 0x6 73 #define DBRI_COMMAND_DTS 0x7 74 #define DBRI_COMMAND_SSP 0x8 75 #define DBRI_COMMAND_CHI 0x9 76 #define DBRI_COMMAND_CDM 0xe /* CHI data mode */ 77 78 /* interrupts */ 79 #define DBRI_INTR_BRDY 1 /* buffer ready for processing */ 80 #define DBRI_INTR_XCMP 8 /* transmission of frame complete */ 81 #define DBRI_INTR_SBRI 9 /* BRI status change info */ 82 #define DBRI_INTR_FXDT 10 /* fixed data change */ 83 #define DBRI_INTR_UNDR 15 /* DMA underrun */ 84 85 #define DBRI_INTR_CMD 38 86 87 /* setup data pipe */ 88 /* IRM */ 89 #define DBRI_SDP_2SAME (1<<18) /* report 2nd time in a row recv val */ 90 #define DBRI_SDP_CHANGE (2<<18) /* report any changes */ 91 #define DBRI_SDP_EVERY (3<<18) /* report any changes */ 92 /* pipe data mode */ 93 #define DBRI_SDP_FIXED (6<<13) /* short only */ 94 #define DBRI_SDP_TO_SER (1<<12) /* direction */ 95 #define DBRI_SDP_FROM_SER (0<<12) /* direction */ 96 #define DBRI_SDP_CLEAR (1<<7) /* clear */ 97 #define DBRI_SDP_VALID_POINTER (1<<10) /* pointer valid */ 98 #define DBRI_SDP_MEM (0<<13) /* to/from memory */ 99 #define DBRI_SDP_MSB (1<<11) /* bit order */ 100 #define DBRI_SDP_LSB (0<<11) /* bit order */ 101 102 /* define time slot */ 103 #define DBRI_DTS_VI (1<<17) /* valid input time-slot descriptor */ 104 #define DBRI_DTS_VO (1<<16) /* valid output time-slot descriptor */ 105 #define DBRI_DTS_INS (1<<15) /* insert time-slot */ 106 #define DBRI_DTS_DEL (0<<15) /* delete time-slot */ 107 #define DBRI_DTS_PRVIN(v) ((v)<<10) /* previous in-pipe */ 108 #define DBRI_DTS_PRVOUT(v) ((v)<<5) /* previous out-pipe */ 109 110 /* time slot defines */ 111 #define DBRI_TS_ANCHOR (7<<10) /* starting short pipes */ 112 #define DBRI_TS_NEXT(v) ((v)<<0) /* pipe #: 0-15 long, 16-21 short */ 113 #define DBRI_TS_LEN(v) ((v)<<24) /* # of bits in this timeslot */ 114 #define DBRI_TS_CYCLE(v) ((v)<<14) /* bit count at start of cycle */ 115 116 /* concentration highway interface (CHI) modes */ 117 #define DBRI_CHI_CHICM(v) ((v)<<16) /* clock mode */ 118 #define DBRI_CHI_BPF(v) ((v)<<0) /* bits per frame */ 119 #define DBRI_CHI_FD (1<<11) /* frame drive */ 120 121 /* CHI data mode */ 122 #define DBRI_CDM_XCE (1<<2) /* transmit on rising edge of CHICK */ 123 #define DBRI_CDM_XEN (1<<1) /* transmit highway enable */ 124 #define DBRI_CDM_REN (1<<0) /* receive highway enable */ 125 126 /* transmit descriptor defines */ 127 #define DBRI_TD_CNT(v) ((v)<<16) /* # valid bytes in buffer */ 128 #define DBRI_TD_STATUS(v) ((v)&0xff) /* transmit status */ 129 #define DBRI_TD_EOF (1<<31) /* end of frame */ 130 #define DBRI_TD_FINAL (1<<15) /* final interrupt */ 131 #define DBRI_TD_IDLE (1<<13) /* transmit idle characters */ 132 #define DBRI_TD_TBC (1<<0) /* transmit buffer complete */ 133 134 #endif /* DBRI_REG_H */ 135
Indexes created Tue Sep 30 11:09:46 GMT 2025