dbrivar.h revision 1.2 1 1.2 macallan /* $NetBSD: dbrivar.h,v 1.2 2005/07/28 21:36:48 macallan Exp $ */
2 1.1 macallan
3 1.1 macallan /*
4 1.2 macallan * Copyright (C) 1997 Rudolf Koenig (rfkoenig (at) immd4.informatik.uni-erlangen.de)
5 1.2 macallan * Copyright (c) 1998, 1999 Brent Baccala (baccala (at) freesoft.org)
6 1.2 macallan * Copyright (c) 2001, 2002 Jared D. McNeill <jmcneill (at) netbsd.org>
7 1.2 macallan * Copyright (c) 2005 Michael Lorenz <macallan (at) netbsd.org>
8 1.1 macallan * All rights reserved.
9 1.1 macallan *
10 1.2 macallan * This driver is losely based on a Linux driver written by Rudolf Koenig and
11 1.2 macallan * Brent Baccala who kindly gave their permission to use their code in a
12 1.2 macallan * BSD-licensed driver.
13 1.2 macallan *
14 1.1 macallan * Redistribution and use in source and binary forms, with or without
15 1.1 macallan * modification, are permitted provided that the following conditions
16 1.1 macallan * are met:
17 1.1 macallan * 1. Redistributions of source code must retain the above copyright
18 1.1 macallan * notice, this list of conditions and the following disclaimer.
19 1.1 macallan * 2. Redistributions in binary form must reproduce the above copyright
20 1.1 macallan * notice, this list of conditions and the following disclaimer in the
21 1.1 macallan * documentation and/or other materials provided with the distribution.
22 1.1 macallan * 3. All advertising materials mentioning features or use of this software
23 1.1 macallan * must display the following acknowledgement:
24 1.2 macallan * This product includes software developed by Rudolf Koenig, Brent
25 1.2 macallan * Baccala, Jared D. McNeill.
26 1.1 macallan * 4. Neither the name of the author nor the names of any contributors may
27 1.1 macallan * be used to endorse or promote products derived from this software
28 1.1 macallan * without specific prior written permission.
29 1.1 macallan *
30 1.1 macallan * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
31 1.1 macallan * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
32 1.1 macallan * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
33 1.1 macallan * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
34 1.1 macallan * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
35 1.1 macallan * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
36 1.1 macallan * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
37 1.1 macallan * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
38 1.1 macallan * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
39 1.1 macallan * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
40 1.1 macallan * SUCH DAMAGE.
41 1.1 macallan *
42 1.1 macallan */
43 1.1 macallan
44 1.2 macallan
45 1.1 macallan #define DBRI_NUM_COMMANDS 64
46 1.1 macallan #define DBRI_NUM_DESCRIPTORS 64
47 1.1 macallan #define DBRI_INT_BLOCKS 64
48 1.1 macallan
49 1.1 macallan #define DBRI_PIPE_MAX 32
50 1.1 macallan
51 1.1 macallan enum direction {
52 1.1 macallan in,
53 1.1 macallan out
54 1.1 macallan };
55 1.1 macallan
56 1.1 macallan /* DBRI DMA transmit descriptor */
57 1.1 macallan struct dbri_mem {
58 1.1 macallan volatile u_int32_t flags;
59 1.1 macallan #define TX_EOF 0x80000000 /* End of frame marker */
60 1.1 macallan #define TX_BCNT(x) ((x&0x3fff)<<16)
61 1.1 macallan #define TX_BINT 0x00008000 /* interrupt when EOF */
62 1.1 macallan #define TX_MINT 0x00004000 /* marker interrupt */
63 1.1 macallan #define TX_IDLE 0x00002000 /* send idles after data */
64 1.1 macallan #define TX_FCNT(x) (x&0x1fff)
65 1.1 macallan
66 1.1 macallan volatile u_int32_t ba; /* tx/rx buffer address */
67 1.1 macallan volatile u_int32_t nda; /* next descriptor address */
68 1.1 macallan volatile u_int32_t status;
69 1.1 macallan #define TS_OK 0x0001 /* transmission completed */
70 1.1 macallan #define TS_ABORT 0x0004 /* transmission aborted */
71 1.1 macallan #define TS_UNDERRUN 0x0008 /* DMA underrun */
72 1.1 macallan };
73 1.1 macallan
74 1.1 macallan struct dbri_pipe {
75 1.1 macallan u_int32_t sdp; /* SDP command word */
76 1.1 macallan enum direction direction;
77 1.1 macallan int next; /* next pipe in linked list */
78 1.1 macallan int prev; /* previous pipe in linked list */
79 1.1 macallan int cycle; /* offset of timeslot (bits) */
80 1.1 macallan int length; /* length of timeslot (bits) */
81 1.1 macallan int desc; /* index of active descriptor */
82 1.1 macallan volatile u_int32_t *prec; /* pointer to received fixed data */
83 1.1 macallan };
84 1.1 macallan
85 1.1 macallan struct dbri_desc {
86 1.1 macallan int busy;
87 1.1 macallan caddr_t buf; /* cpu view of buffer */
88 1.1 macallan caddr_t buf_dvma; /* device view */
89 1.1 macallan bus_addr_t dmabase;
90 1.1 macallan bus_dma_segment_t dmaseg;
91 1.1 macallan bus_dmamap_t dmamap;
92 1.1 macallan size_t len;
93 1.1 macallan void (*callback)(void *);
94 1.1 macallan void *callback_args;
95 1.1 macallan };
96 1.1 macallan
97 1.1 macallan struct dbri_dma {
98 1.1 macallan volatile u_int32_t command[DBRI_NUM_COMMANDS];
99 1.1 macallan volatile int32_t intr[DBRI_INT_BLOCKS];
100 1.1 macallan struct dbri_mem desc[DBRI_NUM_DESCRIPTORS];
101 1.1 macallan bus_dmamap_t dmamap;
102 1.1 macallan };
103 1.1 macallan
104 1.1 macallan struct dbri_softc {
105 1.1 macallan struct device sc_dev; /* base device */
106 1.1 macallan
107 1.1 macallan struct sbusdev sc_sd; /* sbus device */
108 1.1 macallan bus_space_handle_t sc_ioh;
109 1.1 macallan bus_space_tag_t sc_iot;
110 1.1 macallan bus_dma_tag_t sc_dmat;
111 1.1 macallan bus_dmamap_t sc_dmamap;
112 1.1 macallan bus_dma_segment_t sc_dmaseg;
113 1.1 macallan
114 1.1 macallan int sc_burst; /* DVMA burst size in effect */
115 1.1 macallan
116 1.1 macallan bus_addr_t sc_dmabase; /* VA of buffer we provide */
117 1.1 macallan caddr_t sc_membase;
118 1.1 macallan int sc_bufsiz; /* size of the buffer */
119 1.1 macallan int sc_locked;
120 1.1 macallan int sc_irqp;
121 1.1 macallan
122 1.1 macallan int sc_waitseen;
123 1.1 macallan
124 1.1 macallan int sc_open;
125 1.1 macallan
126 1.1 macallan int sc_liu_state;
127 1.1 macallan void (*sc_liu)(void *);
128 1.1 macallan void *sc_liu_args;
129 1.1 macallan
130 1.1 macallan struct dbri_pipe sc_pipe[DBRI_PIPE_MAX];
131 1.1 macallan struct dbri_desc sc_desc[DBRI_NUM_DESCRIPTORS];
132 1.1 macallan
133 1.1 macallan struct cs4215_state sc_mm;
134 1.1 macallan int sc_latt, sc_ratt;
135 1.1 macallan int sc_ctl_mode;
136 1.1 macallan
137 1.1 macallan u_int32_t sc_version;
138 1.1 macallan int sc_chi_pipe_in;
139 1.1 macallan int sc_chi_pipe_out;
140 1.1 macallan int sc_chi_bpf;
141 1.1 macallan
142 1.1 macallan int sc_desc_used;
143 1.1 macallan
144 1.1 macallan struct audio_params sc_params;
145 1.1 macallan
146 1.1 macallan struct dbri_dma *sc_dma;
147 1.1 macallan };
148 1.1 macallan
149 1.1 macallan #define dbri_dma_off(member, elem) \
150 1.1 macallan ((u_int32_t)(unsigned long) \
151 1.1 macallan (&(((struct dbri_dma *)0)->member[elem])))
152 1.1 macallan
153 1.1 macallan #if 1
154 1.1 macallan #define DBRI_CMD(cmd, intr, value) ((cmd << 28) | (intr << 27) | value)
155 1.1 macallan #else
156 1.1 macallan #define DBRI_CMD(cmd, intr, value) ((cmd << 28) | (1 << 27) | value)
157 1.1 macallan #endif
158 1.1 macallan #define DBRI_INTR_GETCHAN(v) (((v) >> 24) & 0x3f)
159 1.1 macallan #define DBRI_INTR_GETCODE(v) (((v) >> 20) & 0xf)
160 1.1 macallan #define DBRI_INTR_GETCMD(v) (((v) >> 16) & 0xf)
161 1.1 macallan #define DBRI_INTR_GETVAL(v) ((v) & 0xffff)
162 1.1 macallan #define DBRI_INTR_GETRVAL(v) ((v) & 0xfffff)
163 1.1 macallan
164 1.1 macallan #define DBRI_SDP_MODE(v) ((v) & (7 << 13))
165 1.1 macallan #define DBRI_PIPE(v) ((v) << 0)
166