dbrivar.h revision 1.2
1 /* $NetBSD: dbrivar.h,v 1.2 2005/07/28 21:36:48 macallan Exp $ */ 2 3 /* 4 * Copyright (C) 1997 Rudolf Koenig (rfkoenig (at) immd4.informatik.uni-erlangen.de) 5 * Copyright (c) 1998, 1999 Brent Baccala (baccala (at) freesoft.org) 6 * Copyright (c) 2001, 2002 Jared D. McNeill <jmcneill (at) netbsd.org> 7 * Copyright (c) 2005 Michael Lorenz <macallan (at) netbsd.org> 8 * All rights reserved. 9 * 10 * This driver is losely based on a Linux driver written by Rudolf Koenig and 11 * Brent Baccala who kindly gave their permission to use their code in a 12 * BSD-licensed driver. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions 16 * are met: 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in the 21 * documentation and/or other materials provided with the distribution. 22 * 3. All advertising materials mentioning features or use of this software 23 * must display the following acknowledgement: 24 * This product includes software developed by Rudolf Koenig, Brent 25 * Baccala, Jared D. McNeill. 26 * 4. Neither the name of the author nor the names of any contributors may 27 * be used to endorse or promote products derived from this software 28 * without specific prior written permission. 29 * 30 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 31 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 33 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 36 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 37 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 38 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 39 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 40 * SUCH DAMAGE. 41 * 42 */ 43 44 45 #define DBRI_NUM_COMMANDS 64 46 #define DBRI_NUM_DESCRIPTORS 64 47 #define DBRI_INT_BLOCKS 64 48 49 #define DBRI_PIPE_MAX 32 50 51 enum direction { 52 in, 53 out 54 }; 55 56 /* DBRI DMA transmit descriptor */ 57 struct dbri_mem { 58 volatile u_int32_t flags; 59 #define TX_EOF 0x80000000 /* End of frame marker */ 60 #define TX_BCNT(x) ((x&0x3fff)<<16) 61 #define TX_BINT 0x00008000 /* interrupt when EOF */ 62 #define TX_MINT 0x00004000 /* marker interrupt */ 63 #define TX_IDLE 0x00002000 /* send idles after data */ 64 #define TX_FCNT(x) (x&0x1fff) 65 66 volatile u_int32_t ba; /* tx/rx buffer address */ 67 volatile u_int32_t nda; /* next descriptor address */ 68 volatile u_int32_t status; 69 #define TS_OK 0x0001 /* transmission completed */ 70 #define TS_ABORT 0x0004 /* transmission aborted */ 71 #define TS_UNDERRUN 0x0008 /* DMA underrun */ 72 }; 73 74 struct dbri_pipe { 75 u_int32_t sdp; /* SDP command word */ 76 enum direction direction; 77 int next; /* next pipe in linked list */ 78 int prev; /* previous pipe in linked list */ 79 int cycle; /* offset of timeslot (bits) */ 80 int length; /* length of timeslot (bits) */ 81 int desc; /* index of active descriptor */ 82 volatile u_int32_t *prec; /* pointer to received fixed data */ 83 }; 84 85 struct dbri_desc { 86 int busy; 87 caddr_t buf; /* cpu view of buffer */ 88 caddr_t buf_dvma; /* device view */ 89 bus_addr_t dmabase; 90 bus_dma_segment_t dmaseg; 91 bus_dmamap_t dmamap; 92 size_t len; 93 void (*callback)(void *); 94 void *callback_args; 95 }; 96 97 struct dbri_dma { 98 volatile u_int32_t command[DBRI_NUM_COMMANDS]; 99 volatile int32_t intr[DBRI_INT_BLOCKS]; 100 struct dbri_mem desc[DBRI_NUM_DESCRIPTORS]; 101 bus_dmamap_t dmamap; 102 }; 103 104 struct dbri_softc { 105 struct device sc_dev; /* base device */ 106 107 struct sbusdev sc_sd; /* sbus device */ 108 bus_space_handle_t sc_ioh; 109 bus_space_tag_t sc_iot; 110 bus_dma_tag_t sc_dmat; 111 bus_dmamap_t sc_dmamap; 112 bus_dma_segment_t sc_dmaseg; 113 114 int sc_burst; /* DVMA burst size in effect */ 115 116 bus_addr_t sc_dmabase; /* VA of buffer we provide */ 117 caddr_t sc_membase; 118 int sc_bufsiz; /* size of the buffer */ 119 int sc_locked; 120 int sc_irqp; 121 122 int sc_waitseen; 123 124 int sc_open; 125 126 int sc_liu_state; 127 void (*sc_liu)(void *); 128 void *sc_liu_args; 129 130 struct dbri_pipe sc_pipe[DBRI_PIPE_MAX]; 131 struct dbri_desc sc_desc[DBRI_NUM_DESCRIPTORS]; 132 133 struct cs4215_state sc_mm; 134 int sc_latt, sc_ratt; 135 int sc_ctl_mode; 136 137 u_int32_t sc_version; 138 int sc_chi_pipe_in; 139 int sc_chi_pipe_out; 140 int sc_chi_bpf; 141 142 int sc_desc_used; 143 144 struct audio_params sc_params; 145 146 struct dbri_dma *sc_dma; 147 }; 148 149 #define dbri_dma_off(member, elem) \ 150 ((u_int32_t)(unsigned long) \ 151 (&(((struct dbri_dma *)0)->member[elem]))) 152 153 #if 1 154 #define DBRI_CMD(cmd, intr, value) ((cmd << 28) | (intr << 27) | value) 155 #else 156 #define DBRI_CMD(cmd, intr, value) ((cmd << 28) | (1 << 27) | value) 157 #endif 158 #define DBRI_INTR_GETCHAN(v) (((v) >> 24) & 0x3f) 159 #define DBRI_INTR_GETCODE(v) (((v) >> 20) & 0xf) 160 #define DBRI_INTR_GETCMD(v) (((v) >> 16) & 0xf) 161 #define DBRI_INTR_GETVAL(v) ((v) & 0xffff) 162 #define DBRI_INTR_GETRVAL(v) ((v) & 0xfffff) 163 164 #define DBRI_SDP_MODE(v) ((v) & (7 << 13)) 165 #define DBRI_PIPE(v) ((v) << 0) 166
Indexes created Thu Sep 25 16:09:42 GMT 2025