dbrivar.h revision 1.8
1 /* $NetBSD: dbrivar.h,v 1.8 2007/12/03 15:34:33 ad Exp $ */ 2 3 /* 4 * Copyright (C) 1997 Rudolf Koenig (rfkoenig (at) immd4.informatik.uni-erlangen.de) 5 * Copyright (c) 1998, 1999 Brent Baccala (baccala (at) freesoft.org) 6 * Copyright (c) 2001, 2002 Jared D. McNeill <jmcneill (at) netbsd.org> 7 * Copyright (c) 2005 Michael Lorenz <macallan (at) netbsd.org> 8 * All rights reserved. 9 * 10 * This driver is losely based on a Linux driver written by Rudolf Koenig and 11 * Brent Baccala who kindly gave their permission to use their code in a 12 * BSD-licensed driver. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions 16 * are met: 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in the 21 * documentation and/or other materials provided with the distribution. 22 * 3. All advertising materials mentioning features or use of this software 23 * must display the following acknowledgement: 24 * This product includes software developed by Rudolf Koenig, Brent 25 * Baccala, Jared D. McNeill. 26 * 4. Neither the name of the author nor the names of any contributors may 27 * be used to endorse or promote products derived from this software 28 * without specific prior written permission. 29 * 30 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 31 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 33 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 36 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 37 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 38 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 39 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 40 * SUCH DAMAGE. 41 * 42 */ 43 44 #ifndef DBRI_VAR_H 45 #define DBRI_VAR_H 46 47 #define DBRI_NUM_COMMANDS 64 48 #define DBRI_NUM_DESCRIPTORS 32 49 #define DBRI_INT_BLOCKS 64 50 51 #define DBRI_PIPE_MAX 32 52 53 enum direction { 54 in, 55 out 56 }; 57 58 /* DBRI DMA transmit descriptor */ 59 struct dbri_xmit { 60 volatile uint32_t flags; 61 #define TX_EOF 0x80000000 /* End of frame marker */ 62 #define TX_BCNT(x) ((x&0x3fff)<<16) 63 #define TX_BINT 0x00008000 /* interrupt when EOF */ 64 #define TX_MINT 0x00004000 /* marker interrupt */ 65 #define TX_IDLE 0x00002000 /* send idles after data */ 66 #define TX_FCNT(x) (x&0x1fff) 67 68 volatile uint32_t ba; /* tx/rx buffer address */ 69 volatile uint32_t nda; /* next descriptor address */ 70 volatile uint32_t status; 71 #define TS_OK 0x0001 /* transmission completed */ 72 #define TS_ABORT 0x0004 /* transmission aborted */ 73 #define TS_UNDERRUN 0x0008 /* DMA underrun */ 74 }; 75 76 struct dbri_recv { 77 volatile uint32_t status; 78 #define RX_EOF 0x80000000 79 #define RX_COMPLETED 0x40000000 80 #define RX_BCNT(x) ((x & 0x3fff) << 16) 81 #define RX_CRCERROR 0x00000080 82 #define RX_BBC 0x00000040 /* bad byte count */ 83 #define RX_ABORT 0x00000020 84 #define RX_OVERRUN 0x00000008 85 volatile uint32_t ba; 86 volatile uint32_t nda; 87 volatile uint32_t flags; 88 #define RX_BSIZE(x) (x & 0x3fff) 89 #define RX_FINAL 0x00008000 90 #define RX_MARKER 0x00004000 91 }; 92 93 struct dbri_pipe { 94 uint32_t sdp; /* SDP command word */ 95 enum direction direction; 96 int next; /* next pipe in linked list */ 97 int prev; /* previous pipe in linked list */ 98 int cycle; /* offset of timeslot (bits) */ 99 int length; /* length of timeslot (bits) */ 100 int desc; /* index of active descriptor */ 101 volatile uint32_t *prec; /* pointer to received fixed data */ 102 }; 103 104 struct dbri_desc { 105 int busy; 106 void * buf; /* cpu view of buffer */ 107 void * buf_dvma; /* device view */ 108 bus_addr_t dmabase; 109 bus_dma_segment_t dmaseg; 110 bus_dmamap_t dmamap; 111 size_t len; 112 void (*callback)(void *); 113 void *callback_args; 114 void *softint; 115 }; 116 117 struct dbri_dma { 118 volatile uint32_t command[DBRI_NUM_COMMANDS]; 119 volatile int32_t intr[DBRI_INT_BLOCKS]; 120 struct dbri_xmit xmit[DBRI_NUM_DESCRIPTORS]; 121 struct dbri_recv recv[DBRI_NUM_DESCRIPTORS]; 122 }; 123 124 struct dbri_softc { 125 struct device sc_dev; /* base device */ 126 127 struct sbusdev sc_sd; /* sbus device */ 128 bus_space_handle_t sc_ioh; 129 bus_space_tag_t sc_iot; 130 /* DMA buffer for sending commands to the chip */ 131 bus_dma_tag_t sc_dmat; 132 bus_dmamap_t sc_dmamap; 133 bus_dma_segment_t sc_dmaseg; 134 135 int sc_have_powerctl; 136 int sc_powerstate; /* DBRI's powered up or not */ 137 int sc_pmgrstate; /* PWR_RESUME etc. */ 138 int sc_burst; /* DVMA burst size in effect */ 139 140 bus_addr_t sc_dmabase; /* VA of buffer we provide */ 141 void * sc_membase; 142 int sc_bufsiz; /* size of the buffer */ 143 int sc_locked; 144 int sc_irqp; 145 146 int sc_waitseen; 147 148 int sc_refcount; 149 int sc_playing; 150 int sc_recording; 151 152 int sc_liu_state; 153 void (*sc_liu)(void *); 154 void *sc_liu_args; 155 156 struct dbri_pipe sc_pipe[DBRI_PIPE_MAX]; 157 struct dbri_desc sc_desc[DBRI_NUM_DESCRIPTORS]; 158 159 struct cs4215_state sc_mm; 160 int sc_latt, sc_ratt; /* output attenuation */ 161 int sc_linp, sc_rinp; /* input volume */ 162 int sc_monitor; /* monitor volume */ 163 int sc_input; /* 0 - line, 1 - mic */ 164 165 int sc_ctl_mode; 166 167 uint32_t sc_version; 168 int sc_chi_pipe_in; 169 int sc_chi_pipe_out; 170 int sc_chi_bpf; 171 172 int sc_desc_used; 173 174 struct audio_params sc_params; 175 176 struct dbri_dma *sc_dma; 177 }; 178 179 #define dbri_dma_off(member, elem) \ 180 ((uint32_t)(unsigned long) \ 181 (&(((struct dbri_dma *)0)->member[elem]))) 182 183 #if 1 184 #define DBRI_CMD(cmd, intr, value) ((cmd << 28) | (intr << 27) | value) 185 #else 186 #define DBRI_CMD(cmd, intr, value) ((cmd << 28) | (1 << 27) | value) 187 #endif 188 #define DBRI_INTR_GETCHAN(v) (((v) >> 24) & 0x3f) 189 #define DBRI_INTR_GETCODE(v) (((v) >> 20) & 0xf) 190 #define DBRI_INTR_GETCMD(v) (((v) >> 16) & 0xf) 191 #define DBRI_INTR_GETVAL(v) ((v) & 0xffff) 192 #define DBRI_INTR_GETRVAL(v) ((v) & 0xfffff) 193 194 #define DBRI_SDP_MODE(v) ((v) & (7 << 13)) 195 #define DBRI_PIPE(v) ((v) << 0) 196 197 #endif /* DBRI_VAR_H */ 198
Indexes created Mon Sep 29 15:09:53 GMT 2025