esp_sbus.c revision 1.1
1 /* $NetBSD: esp_sbus.c,v 1.1 1998/08/29 20:32:10 pk Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum; Jason R. Thorpe of the Numerical Aerospace 9 * Simulation Facility, NASA Ames Research Center; Paul Kranenburg. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 #include <sys/types.h> 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/kernel.h> 44 #include <sys/errno.h> 45 #include <sys/device.h> 46 #include <sys/buf.h> 47 48 #include <dev/scsipi/scsi_all.h> 49 #include <dev/scsipi/scsipi_all.h> 50 #include <dev/scsipi/scsiconf.h> 51 #include <dev/scsipi/scsi_message.h> 52 53 #include <machine/bus.h> 54 #include <machine/autoconf.h> 55 #include <machine/cpu.h> 56 57 #include <dev/ic/lsi64854reg.h> 58 #include <dev/ic/lsi64854var.h> 59 60 #include <dev/ic/ncr53c9xreg.h> 61 #include <dev/ic/ncr53c9xvar.h> 62 63 #include <dev/sbus/sbusvar.h> 64 65 struct esp_softc { 66 struct ncr53c9x_softc sc_ncr53c9x; /* glue to MI code */ 67 struct sbusdev sc_sd; /* sbus device */ 68 69 bus_space_tag_t sc_bustag; 70 bus_dma_tag_t sc_dmatag; 71 72 bus_space_handle_t sc_reg; /* the registers */ 73 struct lsi64854_softc *sc_dma; /* pointer to my dma */ 74 75 int sc_pri; /* SBUS priority */ 76 }; 77 78 #define SAME_ESP(sc, bp, sa) \ 79 (bp->val[0] == sa->sa_slot && bp->val[1] == sa->sa_offset) 80 81 void espattach_sbus __P((struct device *, struct device *, void *)); 82 void espattach_dma __P((struct device *, struct device *, void *)); 83 int espmatch_sbus __P((struct device *, struct cfdata *, void *)); 84 85 static void espattach __P((struct esp_softc *)); 86 87 /* Linkup to the rest of the kernel */ 88 struct cfattach esp_sbus_ca = { 89 sizeof(struct esp_softc), espmatch_sbus, espattach_sbus 90 }; 91 struct cfattach esp_dma_ca = { 92 sizeof(struct esp_softc), espmatch_sbus, espattach_dma 93 }; 94 95 static struct scsipi_adapter esp_sbus_switch = { 96 ncr53c9x_scsi_cmd, 97 minphys, /* no max at this level; handled by DMA code */ 98 NULL, 99 NULL, 100 }; 101 102 static struct scsipi_device esp_sbus_dev = { 103 NULL, /* Use default error handler */ 104 NULL, /* have a queue, served by this */ 105 NULL, /* have no async handler */ 106 NULL, /* Use default 'done' routine */ 107 }; 108 109 /* 110 * Functions and the switch for the MI code. 111 */ 112 static u_char esp_read_reg __P((struct ncr53c9x_softc *, int)); 113 static void esp_write_reg __P((struct ncr53c9x_softc *, int, u_char)); 114 static int esp_dma_isintr __P((struct ncr53c9x_softc *)); 115 static void esp_dma_reset __P((struct ncr53c9x_softc *)); 116 static int esp_dma_intr __P((struct ncr53c9x_softc *)); 117 static int esp_dma_setup __P((struct ncr53c9x_softc *, caddr_t *, 118 size_t *, int, size_t *)); 119 static void esp_dma_go __P((struct ncr53c9x_softc *)); 120 static void esp_dma_stop __P((struct ncr53c9x_softc *)); 121 static int esp_dma_isactive __P((struct ncr53c9x_softc *)); 122 123 static struct ncr53c9x_glue esp_sbus_glue = { 124 esp_read_reg, 125 esp_write_reg, 126 esp_dma_isintr, 127 esp_dma_reset, 128 esp_dma_intr, 129 esp_dma_setup, 130 esp_dma_go, 131 esp_dma_stop, 132 esp_dma_isactive, 133 NULL, /* gl_clear_latched_intr */ 134 }; 135 136 int 137 espmatch_sbus(parent, cf, aux) 138 struct device *parent; 139 struct cfdata *cf; 140 void *aux; 141 { 142 struct sbus_attach_args *sa = aux; 143 144 return (strcmp(cf->cf_driver->cd_name, sa->sa_name) == 0); 145 } 146 147 void 148 espattach_sbus(parent, self, aux) 149 struct device *parent, *self; 150 void *aux; 151 { 152 struct esp_softc *esc = (void *)self; 153 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 154 struct sbus_attach_args *sa = aux; 155 156 esc->sc_bustag = sa->sa_bustag; 157 esc->sc_dmatag = sa->sa_dmatag; 158 159 sc->sc_id = getpropint(sa->sa_node, "initiator-id", 7); 160 sc->sc_freq = getpropint(sa->sa_node, "clock-frequency", -1); 161 if (sc->sc_freq < 0) 162 sc->sc_freq = ((struct sbus_softc *) 163 sc->sc_dev.dv_parent)->sc_clockfreq; 164 165 /* 166 * Find the DMA by poking around the dma device structures 167 * 168 * What happens here is that if the dma driver has not been 169 * configured, then this returns a NULL pointer. Then when the 170 * dma actually gets configured, it does the opposing test, and 171 * if the sc->sc_esp field in it's softc is NULL, then tries to 172 * find the matching esp driver. 173 */ 174 esc->sc_dma = (struct lsi64854_softc *) 175 getdevunit("dma", sc->sc_dev.dv_unit); 176 177 /* 178 * and a back pointer to us, for DMA 179 */ 180 if (esc->sc_dma) 181 esc->sc_dma->sc_ncr53c9x = sc; 182 else { 183 printf("\n"); 184 panic("espattach: no dma found"); 185 } 186 187 /* 188 * Map my registers in, if they aren't already in virtual 189 * address space. 190 */ 191 if (sa->sa_npromvaddrs) 192 esc->sc_reg = (bus_space_handle_t)sa->sa_promvaddrs[0]; 193 else { 194 bus_space_handle_t bh; 195 if (sbus_bus_map(sa->sa_bustag, sa->sa_slot, 196 sa->sa_offset, 197 sa->sa_size, 198 BUS_SPACE_MAP_LINEAR, 199 0, &bh) != 0) { 200 printf("%s @ sbus: cannot map registers\n", 201 self->dv_xname); 202 return; 203 } 204 esc->sc_reg = bh; 205 } 206 207 esc->sc_pri = sa->sa_pri; 208 209 /* add me to the sbus structures */ 210 esc->sc_sd.sd_reset = (void *) ncr53c9x_reset; 211 sbus_establish(&esc->sc_sd, &sc->sc_dev); 212 213 if (sa->sa_bp != NULL && strcmp(sa->sa_bp->name, "esp") == 0 && 214 SAME_ESP(sc, sa->sa_bp, sa)) 215 bootpath_store(1, sa->sa_bp + 1); 216 217 espattach(esc); 218 } 219 220 void 221 espattach_dma(parent, self, aux) 222 struct device *parent, *self; 223 void *aux; 224 { 225 struct esp_softc *esc = (void *)self; 226 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 227 struct sbus_attach_args *sa = aux; 228 229 esc->sc_bustag = sa->sa_bustag; 230 esc->sc_dmatag = sa->sa_dmatag; 231 232 sc->sc_id = getpropint(sa->sa_node, "initiator-id", 7); 233 sc->sc_freq = getpropint(sa->sa_node, "clock-frequency", -1); 234 235 esc->sc_dma = (struct lsi64854_softc *)parent; 236 esc->sc_dma->sc_ncr53c9x = sc; 237 238 /* 239 * Map my registers in, if they aren't already in virtual 240 * address space. 241 */ 242 if (sa->sa_npromvaddrs) 243 esc->sc_reg = (bus_space_handle_t)sa->sa_promvaddrs[0]; 244 else { 245 bus_space_handle_t bh; 246 if (bus_space_map2(sa->sa_bustag, 247 sa->sa_slot, 248 sa->sa_offset, 249 sa->sa_size, 250 BUS_SPACE_MAP_LINEAR, 251 0, &bh) != 0) { 252 printf("%s @ dma: cannot map registers\n", 253 self->dv_xname); 254 return; 255 } 256 esc->sc_reg = bh; 257 } 258 259 /* Establish interrupt handler */ 260 esc->sc_pri = sa->sa_pri; 261 262 /* Assume SBus is grandparent */ 263 esc->sc_sd.sd_reset = (void *) ncr53c9x_reset; 264 sbus_establish(&esc->sc_sd, parent); 265 266 if (sa->sa_bp != NULL && strcmp(sa->sa_bp->name, "esp") == 0 && 267 SAME_ESP(sc, sa->sa_bp, sa)) 268 bootpath_store(1, sa->sa_bp + 1); 269 270 espattach(esc); 271 } 272 273 274 /* 275 * Attach this instance, and then all the sub-devices 276 */ 277 void 278 espattach(esc) 279 struct esp_softc *esc; 280 { 281 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 282 void *icookie; 283 284 /* 285 * Set up glue for MI code early; we use some of it here. 286 */ 287 sc->sc_glue = &esp_sbus_glue; 288 289 /* gimme Mhz */ 290 sc->sc_freq /= 1000000; 291 292 /* 293 * XXX More of this should be in ncr53c9x_attach(), but 294 * XXX should we really poke around the chip that much in 295 * XXX the MI code? Think about this more... 296 */ 297 298 /* 299 * It is necessary to try to load the 2nd config register here, 300 * to find out what rev the esp chip is, else the ncr53c9x_reset 301 * will not set up the defaults correctly. 302 */ 303 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 304 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_RPE; 305 sc->sc_cfg3 = NCRCFG3_CDB; 306 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 307 308 if ((NCR_READ_REG(sc, NCR_CFG2) & ~NCRCFG2_RSVD) != 309 (NCRCFG2_SCSI2 | NCRCFG2_RPE)) { 310 sc->sc_rev = NCR_VARIANT_ESP100; 311 } else { 312 sc->sc_cfg2 = NCRCFG2_SCSI2; 313 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 314 sc->sc_cfg3 = 0; 315 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 316 sc->sc_cfg3 = (NCRCFG3_CDB | NCRCFG3_FCLK); 317 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 318 if (NCR_READ_REG(sc, NCR_CFG3) != 319 (NCRCFG3_CDB | NCRCFG3_FCLK)) { 320 sc->sc_rev = NCR_VARIANT_ESP100A; 321 } else { 322 /* NCRCFG2_FE enables > 64K transfers */ 323 sc->sc_cfg2 |= NCRCFG2_FE; 324 sc->sc_cfg3 = 0; 325 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 326 sc->sc_rev = NCR_VARIANT_ESP200; 327 } 328 } 329 330 /* 331 * XXX minsync and maxxfer _should_ be set up in MI code, 332 * XXX but it appears to have some dependency on what sort 333 * XXX of DMA we're hooked up to, etc. 334 */ 335 336 /* 337 * This is the value used to start sync negotiations 338 * Note that the NCR register "SYNCTP" is programmed 339 * in "clocks per byte", and has a minimum value of 4. 340 * The SCSI period used in negotiation is one-fourth 341 * of the time (in nanoseconds) needed to transfer one byte. 342 * Since the chip's clock is given in MHz, we have the following 343 * formula: 4 * period = (1000 / freq) * 4 344 */ 345 sc->sc_minsync = 1000 / sc->sc_freq; 346 347 /* 348 * Alas, we must now modify the value a bit, because it's 349 * only valid when can switch on FASTCLK and FASTSCSI bits 350 * in config register 3... 351 */ 352 switch (sc->sc_rev) { 353 case NCR_VARIANT_ESP100: 354 sc->sc_maxxfer = 64 * 1024; 355 sc->sc_minsync = 0; /* No synch on old chip? */ 356 break; 357 358 case NCR_VARIANT_ESP100A: 359 sc->sc_maxxfer = 64 * 1024; 360 /* Min clocks/byte is 5 */ 361 sc->sc_minsync = ncr53c9x_cpb2stp(sc, 5); 362 break; 363 364 case NCR_VARIANT_ESP200: 365 sc->sc_maxxfer = 16 * 1024 * 1024; 366 /* XXX - do actually set FAST* bits */ 367 break; 368 } 369 370 /* Establish interrupt channel */ 371 icookie = bus_intr_establish(esc->sc_bustag, 372 esc->sc_pri, 0, 373 (int(*)__P((void*)))ncr53c9x_intr, sc); 374 375 /* register interrupt stats */ 376 evcnt_attach(&sc->sc_dev, "intr", &sc->sc_intrcnt); 377 378 /* Do the common parts of attachment. */ 379 ncr53c9x_attach(sc, &esp_sbus_switch, &esp_sbus_dev); 380 381 /* Turn on target selection using the `dma' method */ 382 ncr53c9x_dmaselect = 1; 383 384 bootpath_store(1, NULL); 385 } 386 387 /* 388 * Glue functions. 389 */ 390 391 u_char 392 esp_read_reg(sc, reg) 393 struct ncr53c9x_softc *sc; 394 int reg; 395 { 396 struct esp_softc *esc = (struct esp_softc *)sc; 397 398 return (bus_space_read_1(esc->sc_bustag, esc->sc_reg, reg * 4)); 399 } 400 401 void 402 esp_write_reg(sc, reg, v) 403 struct ncr53c9x_softc *sc; 404 int reg; 405 u_char v; 406 { 407 struct esp_softc *esc = (struct esp_softc *)sc; 408 409 bus_space_write_1(esc->sc_bustag, esc->sc_reg, reg * 4, v); 410 } 411 412 int 413 esp_dma_isintr(sc) 414 struct ncr53c9x_softc *sc; 415 { 416 struct esp_softc *esc = (struct esp_softc *)sc; 417 418 return (DMA_ISINTR(esc->sc_dma)); 419 } 420 421 void 422 esp_dma_reset(sc) 423 struct ncr53c9x_softc *sc; 424 { 425 struct esp_softc *esc = (struct esp_softc *)sc; 426 427 DMA_RESET(esc->sc_dma); 428 } 429 430 int 431 esp_dma_intr(sc) 432 struct ncr53c9x_softc *sc; 433 { 434 struct esp_softc *esc = (struct esp_softc *)sc; 435 436 return (DMA_INTR(esc->sc_dma)); 437 } 438 439 int 440 esp_dma_setup(sc, addr, len, datain, dmasize) 441 struct ncr53c9x_softc *sc; 442 caddr_t *addr; 443 size_t *len; 444 int datain; 445 size_t *dmasize; 446 { 447 struct esp_softc *esc = (struct esp_softc *)sc; 448 449 return (DMA_SETUP(esc->sc_dma, addr, len, datain, dmasize)); 450 } 451 452 void 453 esp_dma_go(sc) 454 struct ncr53c9x_softc *sc; 455 { 456 struct esp_softc *esc = (struct esp_softc *)sc; 457 458 DMA_GO(esc->sc_dma); 459 } 460 461 void 462 esp_dma_stop(sc) 463 struct ncr53c9x_softc *sc; 464 { 465 struct esp_softc *esc = (struct esp_softc *)sc; 466 u_int32_t csr; 467 468 csr = L64854_GCSR(esc->sc_dma); 469 csr &= ~D_EN_DMA; 470 L64854_SCSR(esc->sc_dma, csr); 471 } 472 473 int 474 esp_dma_isactive(sc) 475 struct ncr53c9x_softc *sc; 476 { 477 struct esp_softc *esc = (struct esp_softc *)sc; 478 479 return (DMA_ISACTIVE(esc->sc_dma)); 480 } 481
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