esp_sbus.c revision 1.14
1 /* $NetBSD: esp_sbus.c,v 1.14 2001/04/25 17:53:37 bouyer Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum; Jason R. Thorpe of the Numerical Aerospace 9 * Simulation Facility, NASA Ames Research Center; Paul Kranenburg. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 #include <sys/types.h> 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/device.h> 44 #include <sys/buf.h> 45 #include <sys/malloc.h> 46 47 #include <dev/scsipi/scsi_all.h> 48 #include <dev/scsipi/scsipi_all.h> 49 #include <dev/scsipi/scsiconf.h> 50 #include <dev/scsipi/scsi_message.h> 51 52 #include <machine/bus.h> 53 #include <machine/intr.h> 54 #include <machine/autoconf.h> 55 56 #include <dev/ic/lsi64854reg.h> 57 #include <dev/ic/lsi64854var.h> 58 59 #include <dev/ic/ncr53c9xreg.h> 60 #include <dev/ic/ncr53c9xvar.h> 61 62 #include <dev/sbus/sbusvar.h> 63 64 /* #define ESP_SBUS_DEBUG */ 65 66 struct esp_softc { 67 struct ncr53c9x_softc sc_ncr53c9x; /* glue to MI code */ 68 struct sbusdev sc_sd; /* sbus device */ 69 70 bus_space_tag_t sc_bustag; 71 bus_dma_tag_t sc_dmatag; 72 73 bus_space_handle_t sc_reg; /* the registers */ 74 struct lsi64854_softc *sc_dma; /* pointer to my dma */ 75 76 int sc_pri; /* SBUS priority */ 77 }; 78 79 void espattach_sbus __P((struct device *, struct device *, void *)); 80 void espattach_dma __P((struct device *, struct device *, void *)); 81 int espmatch_sbus __P((struct device *, struct cfdata *, void *)); 82 83 84 /* Linkup to the rest of the kernel */ 85 struct cfattach esp_sbus_ca = { 86 sizeof(struct esp_softc), espmatch_sbus, espattach_sbus 87 }; 88 struct cfattach esp_dma_ca = { 89 sizeof(struct esp_softc), espmatch_sbus, espattach_dma 90 }; 91 92 /* 93 * Functions and the switch for the MI code. 94 */ 95 static u_char esp_read_reg __P((struct ncr53c9x_softc *, int)); 96 static void esp_write_reg __P((struct ncr53c9x_softc *, int, u_char)); 97 static u_char esp_rdreg1 __P((struct ncr53c9x_softc *, int)); 98 static void esp_wrreg1 __P((struct ncr53c9x_softc *, int, u_char)); 99 static int esp_dma_isintr __P((struct ncr53c9x_softc *)); 100 static void esp_dma_reset __P((struct ncr53c9x_softc *)); 101 static int esp_dma_intr __P((struct ncr53c9x_softc *)); 102 static int esp_dma_setup __P((struct ncr53c9x_softc *, caddr_t *, 103 size_t *, int, size_t *)); 104 static void esp_dma_go __P((struct ncr53c9x_softc *)); 105 static void esp_dma_stop __P((struct ncr53c9x_softc *)); 106 static int esp_dma_isactive __P((struct ncr53c9x_softc *)); 107 108 static struct ncr53c9x_glue esp_sbus_glue = { 109 esp_read_reg, 110 esp_write_reg, 111 esp_dma_isintr, 112 esp_dma_reset, 113 esp_dma_intr, 114 esp_dma_setup, 115 esp_dma_go, 116 esp_dma_stop, 117 esp_dma_isactive, 118 NULL, /* gl_clear_latched_intr */ 119 }; 120 121 static struct ncr53c9x_glue esp_sbus_glue1 = { 122 esp_rdreg1, 123 esp_wrreg1, 124 esp_dma_isintr, 125 esp_dma_reset, 126 esp_dma_intr, 127 esp_dma_setup, 128 esp_dma_go, 129 esp_dma_stop, 130 esp_dma_isactive, 131 NULL, /* gl_clear_latched_intr */ 132 }; 133 134 static void espattach __P((struct esp_softc *, struct ncr53c9x_glue *)); 135 136 int 137 espmatch_sbus(parent, cf, aux) 138 struct device *parent; 139 struct cfdata *cf; 140 void *aux; 141 { 142 int rv; 143 struct sbus_attach_args *sa = aux; 144 145 if (strcmp("SUNW,fas", sa->sa_name) == 0) 146 return 1; 147 148 rv = (strcmp(cf->cf_driver->cd_name, sa->sa_name) == 0 || 149 strcmp("ptscII", sa->sa_name) == 0); 150 return (rv); 151 } 152 153 void 154 espattach_sbus(parent, self, aux) 155 struct device *parent, *self; 156 void *aux; 157 { 158 struct esp_softc *esc = (void *)self; 159 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 160 struct sbus_attach_args *sa = aux; 161 struct lsi64854_softc *lsc; 162 int burst, sbusburst; 163 164 esc->sc_bustag = sa->sa_bustag; 165 esc->sc_dmatag = sa->sa_dmatag; 166 167 sc->sc_id = getpropint(sa->sa_node, "initiator-id", 7); 168 sc->sc_freq = getpropint(sa->sa_node, "clock-frequency", -1); 169 if (sc->sc_freq < 0) 170 sc->sc_freq = ((struct sbus_softc *) 171 sc->sc_dev.dv_parent)->sc_clockfreq; 172 173 #ifdef ESP_SBUS_DEBUG 174 printf("%s: espattach_sbus: sc_id %d, freq %d\n", 175 self->dv_xname, sc->sc_id, sc->sc_freq); 176 #endif 177 178 if (strcmp("SUNW,fas", sa->sa_name) == 0) { 179 180 /* 181 * fas has 2 register spaces: dma(lsi64854) and SCSI core (ncr53c9x) 182 */ 183 if (sa->sa_nreg != 2) { 184 printf("%s: %d register spaces\n", self->dv_xname, sa->sa_nreg); 185 return; 186 } 187 188 /* 189 * allocate space for dma, in SUNW,fas there are no separate 190 * dma device 191 */ 192 lsc = malloc(sizeof (struct lsi64854_softc), M_DEVBUF, M_NOWAIT); 193 194 if (lsc == NULL) { 195 printf("%s: out of memory (lsi64854_softc)\n", 196 self->dv_xname); 197 return; 198 } 199 esc->sc_dma = lsc; 200 201 lsc->sc_bustag = sa->sa_bustag; 202 lsc->sc_dmatag = sa->sa_dmatag; 203 204 bcopy(sc->sc_dev.dv_xname, lsc->sc_dev.dv_xname, 205 sizeof (lsc->sc_dev.dv_xname)); 206 207 /* Map dma registers */ 208 if (bus_space_map2(sa->sa_bustag, 209 sa->sa_reg[0].sbr_slot, 210 sa->sa_reg[0].sbr_offset, 211 sa->sa_reg[0].sbr_size, 212 BUS_SPACE_MAP_LINEAR, 213 0, &lsc->sc_regs) != 0) { 214 printf("%s: cannot map dma registers\n", self->dv_xname); 215 return; 216 } 217 218 /* 219 * XXX is this common(from bpp.c), the same in dma_sbus...etc. 220 * 221 * Get transfer burst size from PROM and plug it into the 222 * controller registers. This is needed on the Sun4m; do 223 * others need it too? 224 */ 225 sbusburst = ((struct sbus_softc *)parent)->sc_burst; 226 if (sbusburst == 0) 227 sbusburst = SBUS_BURST_32 - 1; /* 1->16 */ 228 229 burst = getpropint(sa->sa_node, "burst-sizes", -1); 230 231 #if ESP_SBUS_DEBUG 232 printf("espattach_sbus: burst 0x%x, sbus 0x%x\n", 233 burst, sbusburst); 234 #endif 235 236 if (burst == -1) 237 /* take SBus burst sizes */ 238 burst = sbusburst; 239 240 /* Clamp at parent's burst sizes */ 241 burst &= sbusburst; 242 lsc->sc_burst = (burst & SBUS_BURST_32) ? 32 : 243 (burst & SBUS_BURST_16) ? 16 : 0; 244 245 lsc->sc_channel = L64854_CHANNEL_SCSI; 246 lsc->sc_client = sc; 247 248 lsi64854_attach(lsc); 249 250 /* 251 * map SCSI core registers 252 */ 253 if (sbus_bus_map(sa->sa_bustag, 254 sa->sa_reg[1].sbr_slot, 255 sa->sa_reg[1].sbr_offset, 256 sa->sa_reg[1].sbr_size, 257 BUS_SPACE_MAP_LINEAR, 258 0, &esc->sc_reg) != 0) { 259 printf("%s @ sbus: cannot map scsi core registers\n", 260 self->dv_xname); 261 return; 262 } 263 264 if (sa->sa_nintr == 0) { 265 printf("\n%s: no interrupt property\n", self->dv_xname); 266 return; 267 } 268 269 esc->sc_pri = sa->sa_pri; 270 271 /* add me to the sbus structures */ 272 esc->sc_sd.sd_reset = (void *) ncr53c9x_reset; 273 sbus_establish(&esc->sc_sd, &sc->sc_dev); 274 275 espattach(esc, &esp_sbus_glue); 276 277 return; 278 } 279 280 /* 281 * Find the DMA by poking around the dma device structures 282 * 283 * What happens here is that if the dma driver has not been 284 * configured, then this returns a NULL pointer. Then when the 285 * dma actually gets configured, it does the opposing test, and 286 * if the sc->sc_esp field in it's softc is NULL, then tries to 287 * find the matching esp driver. 288 */ 289 esc->sc_dma = (struct lsi64854_softc *) 290 getdevunit("dma", sc->sc_dev.dv_unit); 291 292 /* 293 * and a back pointer to us, for DMA 294 */ 295 if (esc->sc_dma) 296 esc->sc_dma->sc_client = sc; 297 else { 298 printf("\n"); 299 panic("espattach: no dma found"); 300 } 301 302 /* 303 * Map my registers in, if they aren't already in virtual 304 * address space. 305 */ 306 if (sa->sa_npromvaddrs) 307 esc->sc_reg = (bus_space_handle_t)sa->sa_promvaddrs[0]; 308 else { 309 if (sbus_bus_map(sa->sa_bustag, sa->sa_slot, 310 sa->sa_offset, 311 sa->sa_size, 312 BUS_SPACE_MAP_LINEAR, 313 0, &esc->sc_reg) != 0) { 314 printf("%s @ sbus: cannot map registers\n", 315 self->dv_xname); 316 return; 317 } 318 } 319 320 if (sa->sa_nintr == 0) { 321 /* 322 * No interrupt properties: we quit; this might 323 * happen on e.g. a Sparc X terminal. 324 */ 325 printf("\n%s: no interrupt property\n", self->dv_xname); 326 return; 327 } 328 329 esc->sc_pri = sa->sa_pri; 330 331 /* add me to the sbus structures */ 332 esc->sc_sd.sd_reset = (void *) ncr53c9x_reset; 333 sbus_establish(&esc->sc_sd, &sc->sc_dev); 334 335 if (strcmp("ptscII", sa->sa_name) == 0) { 336 espattach(esc, &esp_sbus_glue1); 337 } else { 338 espattach(esc, &esp_sbus_glue); 339 } 340 } 341 342 void 343 espattach_dma(parent, self, aux) 344 struct device *parent, *self; 345 void *aux; 346 { 347 struct esp_softc *esc = (void *)self; 348 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 349 struct sbus_attach_args *sa = aux; 350 351 if (strcmp("ptscII", sa->sa_name) == 0) { 352 return; 353 } 354 355 esc->sc_bustag = sa->sa_bustag; 356 esc->sc_dmatag = sa->sa_dmatag; 357 358 sc->sc_id = getpropint(sa->sa_node, "initiator-id", 7); 359 sc->sc_freq = getpropint(sa->sa_node, "clock-frequency", -1); 360 361 esc->sc_dma = (struct lsi64854_softc *)parent; 362 esc->sc_dma->sc_client = sc; 363 364 /* 365 * Map my registers in, if they aren't already in virtual 366 * address space. 367 */ 368 if (sa->sa_npromvaddrs) 369 esc->sc_reg = (bus_space_handle_t)sa->sa_promvaddrs[0]; 370 else { 371 if (bus_space_map2(sa->sa_bustag, 372 sa->sa_slot, 373 sa->sa_offset, 374 sa->sa_size, 375 BUS_SPACE_MAP_LINEAR, 376 0, &esc->sc_reg) != 0) { 377 printf("%s @ dma: cannot map registers\n", 378 self->dv_xname); 379 return; 380 } 381 } 382 383 if (sa->sa_nintr == 0) { 384 /* 385 * No interrupt properties: we quit; this might 386 * happen on e.g. a Sparc X terminal. 387 */ 388 printf("\n%s: no interrupt property\n", self->dv_xname); 389 return; 390 } 391 392 esc->sc_pri = sa->sa_pri; 393 394 /* Assume SBus is grandparent */ 395 esc->sc_sd.sd_reset = (void *) ncr53c9x_reset; 396 sbus_establish(&esc->sc_sd, parent); 397 398 espattach(esc, &esp_sbus_glue); 399 } 400 401 402 /* 403 * Attach this instance, and then all the sub-devices 404 */ 405 void 406 espattach(esc, gluep) 407 struct esp_softc *esc; 408 struct ncr53c9x_glue *gluep; 409 { 410 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 411 void *icookie; 412 unsigned int uid = 0; 413 414 /* 415 * Set up glue for MI code early; we use some of it here. 416 */ 417 sc->sc_glue = gluep; 418 419 /* gimme Mhz */ 420 sc->sc_freq /= 1000000; 421 422 /* 423 * XXX More of this should be in ncr53c9x_attach(), but 424 * XXX should we really poke around the chip that much in 425 * XXX the MI code? Think about this more... 426 */ 427 428 /* 429 * It is necessary to try to load the 2nd config register here, 430 * to find out what rev the esp chip is, else the ncr53c9x_reset 431 * will not set up the defaults correctly. 432 */ 433 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 434 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_RPE; 435 sc->sc_cfg3 = NCRCFG3_CDB; 436 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 437 438 if ((NCR_READ_REG(sc, NCR_CFG2) & ~NCRCFG2_RSVD) != 439 (NCRCFG2_SCSI2 | NCRCFG2_RPE)) { 440 sc->sc_rev = NCR_VARIANT_ESP100; 441 } else { 442 sc->sc_cfg2 = NCRCFG2_SCSI2; 443 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 444 sc->sc_cfg3 = 0; 445 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 446 sc->sc_cfg3 = (NCRCFG3_CDB | NCRCFG3_FCLK); 447 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 448 if (NCR_READ_REG(sc, NCR_CFG3) != 449 (NCRCFG3_CDB | NCRCFG3_FCLK)) { 450 sc->sc_rev = NCR_VARIANT_ESP100A; 451 } else { 452 /* NCRCFG2_FE enables > 64K transfers */ 453 sc->sc_cfg2 |= NCRCFG2_FE; 454 sc->sc_cfg3 = 0; 455 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 456 sc->sc_rev = NCR_VARIANT_ESP200; 457 458 /* XXX spec says it's valid after power up or chip reset */ 459 uid = NCR_READ_REG(sc, NCR_UID); 460 if (((uid & 0xf8) >> 3) == 0x0a) /* XXX */ 461 sc->sc_rev = NCR_VARIANT_FAS366; 462 } 463 } 464 465 #ifdef ESP_SBUS_DEBUG 466 printf("espattach: revision %d, uid 0x%x\n", sc->sc_rev, uid); 467 #endif 468 469 /* 470 * XXX minsync and maxxfer _should_ be set up in MI code, 471 * XXX but it appears to have some dependency on what sort 472 * XXX of DMA we're hooked up to, etc. 473 */ 474 475 /* 476 * This is the value used to start sync negotiations 477 * Note that the NCR register "SYNCTP" is programmed 478 * in "clocks per byte", and has a minimum value of 4. 479 * The SCSI period used in negotiation is one-fourth 480 * of the time (in nanoseconds) needed to transfer one byte. 481 * Since the chip's clock is given in MHz, we have the following 482 * formula: 4 * period = (1000 / freq) * 4 483 */ 484 sc->sc_minsync = 1000 / sc->sc_freq; 485 486 /* 487 * Alas, we must now modify the value a bit, because it's 488 * only valid when can switch on FASTCLK and FASTSCSI bits 489 * in config register 3... 490 */ 491 switch (sc->sc_rev) { 492 case NCR_VARIANT_ESP100: 493 sc->sc_maxxfer = 64 * 1024; 494 sc->sc_minsync = 0; /* No synch on old chip? */ 495 break; 496 497 case NCR_VARIANT_ESP100A: 498 sc->sc_maxxfer = 64 * 1024; 499 /* Min clocks/byte is 5 */ 500 sc->sc_minsync = ncr53c9x_cpb2stp(sc, 5); 501 break; 502 503 case NCR_VARIANT_ESP200: 504 case NCR_VARIANT_FAS366: 505 sc->sc_maxxfer = 16 * 1024 * 1024; 506 /* XXX - do actually set FAST* bits */ 507 break; 508 } 509 510 /* Establish interrupt channel */ 511 icookie = bus_intr_establish(esc->sc_bustag, esc->sc_pri, IPL_BIO, 0, 512 ncr53c9x_intr, sc); 513 514 /* register interrupt stats */ 515 evcnt_attach_dynamic(&sc->sc_intrcnt, EVCNT_TYPE_INTR, NULL, 516 sc->sc_dev.dv_xname, "intr"); 517 518 /* Turn on target selection using the `dma' method */ 519 if (sc->sc_rev != NCR_VARIANT_FAS366) 520 sc->sc_features |= NCR_F_DMASELECT; 521 522 /* Do the common parts of attachment. */ 523 sc->sc_adapter.adapt_minphys = minphys; 524 sc->sc_adapter.adapt_request = ncr53c9x_scsipi_request; 525 ncr53c9x_attach(sc); 526 527 } 528 529 /* 530 * Glue functions. 531 */ 532 533 #ifdef ESP_SBUS_DEBUG 534 int esp_sbus_debug = 0; 535 536 static struct { 537 char *r_name; 538 int r_flag; 539 } esp__read_regnames [] = { 540 { "TCL", 0}, /* 0/00 */ 541 { "TCM", 0}, /* 1/04 */ 542 { "FIFO", 0}, /* 2/08 */ 543 { "CMD", 0}, /* 3/0c */ 544 { "STAT", 0}, /* 4/10 */ 545 { "INTR", 0}, /* 5/14 */ 546 { "STEP", 0}, /* 6/18 */ 547 { "FFLAGS", 1}, /* 7/1c */ 548 { "CFG1", 1}, /* 8/20 */ 549 { "STAT2", 0}, /* 9/24 */ 550 { "CFG4", 1}, /* a/28 */ 551 { "CFG2", 1}, /* b/2c */ 552 { "CFG3", 1}, /* c/30 */ 553 { "-none", 1}, /* d/34 */ 554 { "TCH", 1}, /* e/38 */ 555 { "TCX", 1}, /* f/3c */ 556 }; 557 558 static struct { 559 char *r_name; 560 int r_flag; 561 } esp__write_regnames[] = { 562 { "TCL", 1}, /* 0/00 */ 563 { "TCM", 1}, /* 1/04 */ 564 { "FIFO", 0}, /* 2/08 */ 565 { "CMD", 0}, /* 3/0c */ 566 { "SELID", 1}, /* 4/10 */ 567 { "TIMEOUT", 1}, /* 5/14 */ 568 { "SYNCTP", 1}, /* 6/18 */ 569 { "SYNCOFF", 1}, /* 7/1c */ 570 { "CFG1", 1}, /* 8/20 */ 571 { "CCF", 1}, /* 9/24 */ 572 { "TEST", 1}, /* a/28 */ 573 { "CFG2", 1}, /* b/2c */ 574 { "CFG3", 1}, /* c/30 */ 575 { "-none", 1}, /* d/34 */ 576 { "TCH", 1}, /* e/38 */ 577 { "TCX", 1}, /* f/3c */ 578 }; 579 #endif 580 581 u_char 582 esp_read_reg(sc, reg) 583 struct ncr53c9x_softc *sc; 584 int reg; 585 { 586 struct esp_softc *esc = (struct esp_softc *)sc; 587 u_char v; 588 589 v = bus_space_read_1(esc->sc_bustag, esc->sc_reg, reg * 4); 590 #ifdef ESP_SBUS_DEBUG 591 if (esp_sbus_debug && (reg < 0x10) && esp__read_regnames[reg].r_flag) 592 printf("RD:%x <%s> %x\n", reg * 4, 593 ((unsigned)reg < 0x10) ? esp__read_regnames[reg].r_name : "<***>", v); 594 #endif 595 return v; 596 } 597 598 void 599 esp_write_reg(sc, reg, v) 600 struct ncr53c9x_softc *sc; 601 int reg; 602 u_char v; 603 { 604 struct esp_softc *esc = (struct esp_softc *)sc; 605 606 #ifdef ESP_SBUS_DEBUG 607 if (esp_sbus_debug && (reg < 0x10) && esp__write_regnames[reg].r_flag) 608 printf("WR:%x <%s> %x\n", reg * 4, 609 ((unsigned)reg < 0x10) ? esp__write_regnames[reg].r_name : "<***>", v); 610 #endif 611 bus_space_write_1(esc->sc_bustag, esc->sc_reg, reg * 4, v); 612 } 613 614 u_char 615 esp_rdreg1(sc, reg) 616 struct ncr53c9x_softc *sc; 617 int reg; 618 { 619 struct esp_softc *esc = (struct esp_softc *)sc; 620 621 return (bus_space_read_1(esc->sc_bustag, esc->sc_reg, reg)); 622 } 623 624 void 625 esp_wrreg1(sc, reg, v) 626 struct ncr53c9x_softc *sc; 627 int reg; 628 u_char v; 629 { 630 struct esp_softc *esc = (struct esp_softc *)sc; 631 632 bus_space_write_1(esc->sc_bustag, esc->sc_reg, reg, v); 633 } 634 635 int 636 esp_dma_isintr(sc) 637 struct ncr53c9x_softc *sc; 638 { 639 struct esp_softc *esc = (struct esp_softc *)sc; 640 641 return (DMA_ISINTR(esc->sc_dma)); 642 } 643 644 void 645 esp_dma_reset(sc) 646 struct ncr53c9x_softc *sc; 647 { 648 struct esp_softc *esc = (struct esp_softc *)sc; 649 650 DMA_RESET(esc->sc_dma); 651 } 652 653 int 654 esp_dma_intr(sc) 655 struct ncr53c9x_softc *sc; 656 { 657 struct esp_softc *esc = (struct esp_softc *)sc; 658 659 return (DMA_INTR(esc->sc_dma)); 660 } 661 662 int 663 esp_dma_setup(sc, addr, len, datain, dmasize) 664 struct ncr53c9x_softc *sc; 665 caddr_t *addr; 666 size_t *len; 667 int datain; 668 size_t *dmasize; 669 { 670 struct esp_softc *esc = (struct esp_softc *)sc; 671 672 return (DMA_SETUP(esc->sc_dma, addr, len, datain, dmasize)); 673 } 674 675 void 676 esp_dma_go(sc) 677 struct ncr53c9x_softc *sc; 678 { 679 struct esp_softc *esc = (struct esp_softc *)sc; 680 681 DMA_GO(esc->sc_dma); 682 } 683 684 void 685 esp_dma_stop(sc) 686 struct ncr53c9x_softc *sc; 687 { 688 struct esp_softc *esc = (struct esp_softc *)sc; 689 u_int32_t csr; 690 691 csr = L64854_GCSR(esc->sc_dma); 692 csr &= ~D_EN_DMA; 693 L64854_SCSR(esc->sc_dma, csr); 694 } 695 696 int 697 esp_dma_isactive(sc) 698 struct ncr53c9x_softc *sc; 699 { 700 struct esp_softc *esc = (struct esp_softc *)sc; 701 702 return (DMA_ISACTIVE(esc->sc_dma)); 703 } 704 705 #include "opt_ddb.h" 706 #ifdef DDB 707 #include <machine/db_machdep.h> 708 #include <ddb/db_output.h> 709 710 void db_esp __P((db_expr_t, int, db_expr_t, char*)); 711 712 void 713 db_esp(addr, have_addr, count, modif) 714 db_expr_t addr; 715 int have_addr; 716 db_expr_t count; 717 char *modif; 718 { 719 struct ncr53c9x_softc *sc; 720 struct ncr53c9x_ecb *ecb; 721 struct ncr53c9x_linfo *li; 722 int u, t, i; 723 724 for (u=0; u<10; u++) { 725 sc = (struct ncr53c9x_softc *) 726 getdevunit("esp", u); 727 if (!sc) continue; 728 729 db_printf("esp%d: nexus %p phase %x prev %x dp %p dleft %lx ify %x\n", 730 u, sc->sc_nexus, sc->sc_phase, sc->sc_prevphase, 731 sc->sc_dp, sc->sc_dleft, sc->sc_msgify); 732 db_printf("\tmsgout %x msgpriq %x msgin %x:%x:%x:%x:%x\n", 733 sc->sc_msgout, sc->sc_msgpriq, sc->sc_imess[0], 734 sc->sc_imess[1], sc->sc_imess[2], sc->sc_imess[3], 735 sc->sc_imess[0]); 736 db_printf("ready: "); 737 for (ecb = sc->ready_list.tqh_first; ecb; ecb = ecb->chain.tqe_next) { 738 db_printf("ecb %p ", ecb); 739 if (ecb == ecb->chain.tqe_next) { 740 db_printf("\nWARNING: tailq loop on ecb %p", ecb); 741 break; 742 } 743 } 744 db_printf("\n"); 745 746 for (t=0; t<NCR_NTARG; t++) { 747 LIST_FOREACH(li, &sc->sc_tinfo[t].luns, link) { 748 db_printf("t%d lun %d untagged %p busy %d used %x\n", 749 t, (int)li->lun, li->untagged, li->busy, 750 li->used); 751 for (i=0; i<256; i++) 752 if ((ecb = li->queued[i])) { 753 db_printf("ecb %p tag %x\n", ecb, i); 754 } 755 } 756 } 757 } 758 } 759 #endif 760 761
Indexes created Mon Sep 29 21:09:56 GMT 2025