esp_sbus.c revision 1.3
1 /* $NetBSD: esp_sbus.c,v 1.3 1998/09/15 20:26:25 pk Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum; Jason R. Thorpe of the Numerical Aerospace 9 * Simulation Facility, NASA Ames Research Center; Paul Kranenburg. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 #include <sys/types.h> 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/kernel.h> 44 #include <sys/errno.h> 45 #include <sys/device.h> 46 #include <sys/buf.h> 47 48 #include <dev/scsipi/scsi_all.h> 49 #include <dev/scsipi/scsipi_all.h> 50 #include <dev/scsipi/scsiconf.h> 51 #include <dev/scsipi/scsi_message.h> 52 53 #include <machine/bus.h> 54 #include <machine/autoconf.h> 55 #include <machine/cpu.h> 56 57 #include <dev/ic/lsi64854reg.h> 58 #include <dev/ic/lsi64854var.h> 59 60 #include <dev/ic/ncr53c9xreg.h> 61 #include <dev/ic/ncr53c9xvar.h> 62 63 #include <dev/sbus/sbusvar.h> 64 65 struct esp_softc { 66 struct ncr53c9x_softc sc_ncr53c9x; /* glue to MI code */ 67 struct sbusdev sc_sd; /* sbus device */ 68 69 bus_space_tag_t sc_bustag; 70 bus_dma_tag_t sc_dmatag; 71 72 bus_space_handle_t sc_reg; /* the registers */ 73 struct lsi64854_softc *sc_dma; /* pointer to my dma */ 74 75 int sc_pri; /* SBUS priority */ 76 }; 77 78 /* 79 * Is this esp on the bootpath? 80 * We may get two forms of the bootpath: 81 * (1) ../sbus (at) .../esp@<offset>,<slot>/sd@.. (PROM v3 style) 82 * (2) /sbus0/esp0/sd@.. (PROM v2 style) 83 */ 84 #define SAME_ESP(sc, bp, sa) \ 85 ((bp->val[0] == sa->sa_slot && bp->val[1] == sa->sa_offset) || \ 86 (bp->val[0] == -1 && bp->val[1] == sc->sc_dev.dv_unit)) 87 88 void espattach_sbus __P((struct device *, struct device *, void *)); 89 void espattach_dma __P((struct device *, struct device *, void *)); 90 int espmatch_sbus __P((struct device *, struct cfdata *, void *)); 91 92 static void espattach __P((struct esp_softc *)); 93 94 /* Linkup to the rest of the kernel */ 95 struct cfattach esp_sbus_ca = { 96 sizeof(struct esp_softc), espmatch_sbus, espattach_sbus 97 }; 98 struct cfattach esp_dma_ca = { 99 sizeof(struct esp_softc), espmatch_sbus, espattach_dma 100 }; 101 102 static struct scsipi_adapter esp_sbus_switch = { 103 ncr53c9x_scsi_cmd, 104 minphys, /* no max at this level; handled by DMA code */ 105 NULL, 106 NULL, 107 }; 108 109 static struct scsipi_device esp_sbus_dev = { 110 NULL, /* Use default error handler */ 111 NULL, /* have a queue, served by this */ 112 NULL, /* have no async handler */ 113 NULL, /* Use default 'done' routine */ 114 }; 115 116 /* 117 * Functions and the switch for the MI code. 118 */ 119 static u_char esp_read_reg __P((struct ncr53c9x_softc *, int)); 120 static void esp_write_reg __P((struct ncr53c9x_softc *, int, u_char)); 121 static int esp_dma_isintr __P((struct ncr53c9x_softc *)); 122 static void esp_dma_reset __P((struct ncr53c9x_softc *)); 123 static int esp_dma_intr __P((struct ncr53c9x_softc *)); 124 static int esp_dma_setup __P((struct ncr53c9x_softc *, caddr_t *, 125 size_t *, int, size_t *)); 126 static void esp_dma_go __P((struct ncr53c9x_softc *)); 127 static void esp_dma_stop __P((struct ncr53c9x_softc *)); 128 static int esp_dma_isactive __P((struct ncr53c9x_softc *)); 129 130 static struct ncr53c9x_glue esp_sbus_glue = { 131 esp_read_reg, 132 esp_write_reg, 133 esp_dma_isintr, 134 esp_dma_reset, 135 esp_dma_intr, 136 esp_dma_setup, 137 esp_dma_go, 138 esp_dma_stop, 139 esp_dma_isactive, 140 NULL, /* gl_clear_latched_intr */ 141 }; 142 143 int 144 espmatch_sbus(parent, cf, aux) 145 struct device *parent; 146 struct cfdata *cf; 147 void *aux; 148 { 149 struct sbus_attach_args *sa = aux; 150 151 return (strcmp(cf->cf_driver->cd_name, sa->sa_name) == 0); 152 } 153 154 void 155 espattach_sbus(parent, self, aux) 156 struct device *parent, *self; 157 void *aux; 158 { 159 struct esp_softc *esc = (void *)self; 160 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 161 struct sbus_attach_args *sa = aux; 162 163 esc->sc_bustag = sa->sa_bustag; 164 esc->sc_dmatag = sa->sa_dmatag; 165 166 sc->sc_id = getpropint(sa->sa_node, "initiator-id", 7); 167 sc->sc_freq = getpropint(sa->sa_node, "clock-frequency", -1); 168 if (sc->sc_freq < 0) 169 sc->sc_freq = ((struct sbus_softc *) 170 sc->sc_dev.dv_parent)->sc_clockfreq; 171 172 /* 173 * Find the DMA by poking around the dma device structures 174 * 175 * What happens here is that if the dma driver has not been 176 * configured, then this returns a NULL pointer. Then when the 177 * dma actually gets configured, it does the opposing test, and 178 * if the sc->sc_esp field in it's softc is NULL, then tries to 179 * find the matching esp driver. 180 */ 181 esc->sc_dma = (struct lsi64854_softc *) 182 getdevunit("dma", sc->sc_dev.dv_unit); 183 184 /* 185 * and a back pointer to us, for DMA 186 */ 187 if (esc->sc_dma) 188 esc->sc_dma->sc_client = sc; 189 else { 190 printf("\n"); 191 panic("espattach: no dma found"); 192 } 193 194 /* 195 * Map my registers in, if they aren't already in virtual 196 * address space. 197 */ 198 if (sa->sa_npromvaddrs) 199 esc->sc_reg = (bus_space_handle_t)sa->sa_promvaddrs[0]; 200 else { 201 if (sbus_bus_map(sa->sa_bustag, sa->sa_slot, 202 sa->sa_offset, 203 sa->sa_size, 204 BUS_SPACE_MAP_LINEAR, 205 0, &esc->sc_reg) != 0) { 206 printf("%s @ sbus: cannot map registers\n", 207 self->dv_xname); 208 return; 209 } 210 } 211 212 esc->sc_pri = sa->sa_pri; 213 214 /* add me to the sbus structures */ 215 esc->sc_sd.sd_reset = (void *) ncr53c9x_reset; 216 sbus_establish(&esc->sc_sd, &sc->sc_dev); 217 218 if (sa->sa_bp != NULL && strcmp(sa->sa_bp->name, "esp") == 0 && 219 SAME_ESP(sc, sa->sa_bp, sa)) 220 bootpath_store(1, sa->sa_bp + 1); 221 222 espattach(esc); 223 } 224 225 void 226 espattach_dma(parent, self, aux) 227 struct device *parent, *self; 228 void *aux; 229 { 230 struct esp_softc *esc = (void *)self; 231 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 232 struct sbus_attach_args *sa = aux; 233 234 esc->sc_bustag = sa->sa_bustag; 235 esc->sc_dmatag = sa->sa_dmatag; 236 237 sc->sc_id = getpropint(sa->sa_node, "initiator-id", 7); 238 sc->sc_freq = getpropint(sa->sa_node, "clock-frequency", -1); 239 240 esc->sc_dma = (struct lsi64854_softc *)parent; 241 esc->sc_dma->sc_client = sc; 242 243 /* 244 * Map my registers in, if they aren't already in virtual 245 * address space. 246 */ 247 if (sa->sa_npromvaddrs) 248 esc->sc_reg = (bus_space_handle_t)sa->sa_promvaddrs[0]; 249 else { 250 if (bus_space_map2(sa->sa_bustag, 251 sa->sa_slot, 252 sa->sa_offset, 253 sa->sa_size, 254 BUS_SPACE_MAP_LINEAR, 255 0, &esc->sc_reg) != 0) { 256 printf("%s @ dma: cannot map registers\n", 257 self->dv_xname); 258 return; 259 } 260 } 261 262 /* Establish interrupt handler */ 263 esc->sc_pri = sa->sa_pri; 264 265 /* Assume SBus is grandparent */ 266 esc->sc_sd.sd_reset = (void *) ncr53c9x_reset; 267 sbus_establish(&esc->sc_sd, parent); 268 269 if (sa->sa_bp != NULL && strcmp(sa->sa_bp->name, "esp") == 0 && 270 SAME_ESP(sc, sa->sa_bp, sa)) 271 bootpath_store(1, sa->sa_bp + 1); 272 273 espattach(esc); 274 } 275 276 277 /* 278 * Attach this instance, and then all the sub-devices 279 */ 280 void 281 espattach(esc) 282 struct esp_softc *esc; 283 { 284 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 285 void *icookie; 286 287 /* 288 * Set up glue for MI code early; we use some of it here. 289 */ 290 sc->sc_glue = &esp_sbus_glue; 291 292 /* gimme Mhz */ 293 sc->sc_freq /= 1000000; 294 295 /* 296 * XXX More of this should be in ncr53c9x_attach(), but 297 * XXX should we really poke around the chip that much in 298 * XXX the MI code? Think about this more... 299 */ 300 301 /* 302 * It is necessary to try to load the 2nd config register here, 303 * to find out what rev the esp chip is, else the ncr53c9x_reset 304 * will not set up the defaults correctly. 305 */ 306 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 307 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_RPE; 308 sc->sc_cfg3 = NCRCFG3_CDB; 309 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 310 311 if ((NCR_READ_REG(sc, NCR_CFG2) & ~NCRCFG2_RSVD) != 312 (NCRCFG2_SCSI2 | NCRCFG2_RPE)) { 313 sc->sc_rev = NCR_VARIANT_ESP100; 314 } else { 315 sc->sc_cfg2 = NCRCFG2_SCSI2; 316 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 317 sc->sc_cfg3 = 0; 318 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 319 sc->sc_cfg3 = (NCRCFG3_CDB | NCRCFG3_FCLK); 320 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 321 if (NCR_READ_REG(sc, NCR_CFG3) != 322 (NCRCFG3_CDB | NCRCFG3_FCLK)) { 323 sc->sc_rev = NCR_VARIANT_ESP100A; 324 } else { 325 /* NCRCFG2_FE enables > 64K transfers */ 326 sc->sc_cfg2 |= NCRCFG2_FE; 327 sc->sc_cfg3 = 0; 328 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 329 sc->sc_rev = NCR_VARIANT_ESP200; 330 } 331 } 332 333 /* 334 * XXX minsync and maxxfer _should_ be set up in MI code, 335 * XXX but it appears to have some dependency on what sort 336 * XXX of DMA we're hooked up to, etc. 337 */ 338 339 /* 340 * This is the value used to start sync negotiations 341 * Note that the NCR register "SYNCTP" is programmed 342 * in "clocks per byte", and has a minimum value of 4. 343 * The SCSI period used in negotiation is one-fourth 344 * of the time (in nanoseconds) needed to transfer one byte. 345 * Since the chip's clock is given in MHz, we have the following 346 * formula: 4 * period = (1000 / freq) * 4 347 */ 348 sc->sc_minsync = 1000 / sc->sc_freq; 349 350 /* 351 * Alas, we must now modify the value a bit, because it's 352 * only valid when can switch on FASTCLK and FASTSCSI bits 353 * in config register 3... 354 */ 355 switch (sc->sc_rev) { 356 case NCR_VARIANT_ESP100: 357 sc->sc_maxxfer = 64 * 1024; 358 sc->sc_minsync = 0; /* No synch on old chip? */ 359 break; 360 361 case NCR_VARIANT_ESP100A: 362 sc->sc_maxxfer = 64 * 1024; 363 /* Min clocks/byte is 5 */ 364 sc->sc_minsync = ncr53c9x_cpb2stp(sc, 5); 365 break; 366 367 case NCR_VARIANT_ESP200: 368 sc->sc_maxxfer = 16 * 1024 * 1024; 369 /* XXX - do actually set FAST* bits */ 370 break; 371 } 372 373 /* Establish interrupt channel */ 374 icookie = bus_intr_establish(esc->sc_bustag, 375 esc->sc_pri, 0, 376 (int(*)__P((void*)))ncr53c9x_intr, sc); 377 378 /* register interrupt stats */ 379 evcnt_attach(&sc->sc_dev, "intr", &sc->sc_intrcnt); 380 381 /* Do the common parts of attachment. */ 382 ncr53c9x_attach(sc, &esp_sbus_switch, &esp_sbus_dev); 383 384 /* Turn on target selection using the `dma' method */ 385 ncr53c9x_dmaselect = 1; 386 387 bootpath_store(1, NULL); 388 } 389 390 /* 391 * Glue functions. 392 */ 393 394 u_char 395 esp_read_reg(sc, reg) 396 struct ncr53c9x_softc *sc; 397 int reg; 398 { 399 struct esp_softc *esc = (struct esp_softc *)sc; 400 401 return (bus_space_read_1(esc->sc_bustag, esc->sc_reg, reg * 4)); 402 } 403 404 void 405 esp_write_reg(sc, reg, v) 406 struct ncr53c9x_softc *sc; 407 int reg; 408 u_char v; 409 { 410 struct esp_softc *esc = (struct esp_softc *)sc; 411 412 bus_space_write_1(esc->sc_bustag, esc->sc_reg, reg * 4, v); 413 } 414 415 int 416 esp_dma_isintr(sc) 417 struct ncr53c9x_softc *sc; 418 { 419 struct esp_softc *esc = (struct esp_softc *)sc; 420 421 return (DMA_ISINTR(esc->sc_dma)); 422 } 423 424 void 425 esp_dma_reset(sc) 426 struct ncr53c9x_softc *sc; 427 { 428 struct esp_softc *esc = (struct esp_softc *)sc; 429 430 DMA_RESET(esc->sc_dma); 431 } 432 433 int 434 esp_dma_intr(sc) 435 struct ncr53c9x_softc *sc; 436 { 437 struct esp_softc *esc = (struct esp_softc *)sc; 438 439 return (DMA_INTR(esc->sc_dma)); 440 } 441 442 int 443 esp_dma_setup(sc, addr, len, datain, dmasize) 444 struct ncr53c9x_softc *sc; 445 caddr_t *addr; 446 size_t *len; 447 int datain; 448 size_t *dmasize; 449 { 450 struct esp_softc *esc = (struct esp_softc *)sc; 451 452 return (DMA_SETUP(esc->sc_dma, addr, len, datain, dmasize)); 453 } 454 455 void 456 esp_dma_go(sc) 457 struct ncr53c9x_softc *sc; 458 { 459 struct esp_softc *esc = (struct esp_softc *)sc; 460 461 DMA_GO(esc->sc_dma); 462 } 463 464 void 465 esp_dma_stop(sc) 466 struct ncr53c9x_softc *sc; 467 { 468 struct esp_softc *esc = (struct esp_softc *)sc; 469 u_int32_t csr; 470 471 csr = L64854_GCSR(esc->sc_dma); 472 csr &= ~D_EN_DMA; 473 L64854_SCSR(esc->sc_dma, csr); 474 } 475 476 int 477 esp_dma_isactive(sc) 478 struct ncr53c9x_softc *sc; 479 { 480 struct esp_softc *esc = (struct esp_softc *)sc; 481 482 return (DMA_ISACTIVE(esc->sc_dma)); 483 } 484
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