esp_sbus.c revision 1.5
1 /* $NetBSD: esp_sbus.c,v 1.5 1998/11/19 21:54:02 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum; Jason R. Thorpe of the Numerical Aerospace 9 * Simulation Facility, NASA Ames Research Center; Paul Kranenburg. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 #include <sys/types.h> 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/kernel.h> 44 #include <sys/errno.h> 45 #include <sys/device.h> 46 #include <sys/buf.h> 47 48 #include <dev/scsipi/scsi_all.h> 49 #include <dev/scsipi/scsipi_all.h> 50 #include <dev/scsipi/scsiconf.h> 51 #include <dev/scsipi/scsi_message.h> 52 53 #include <machine/bus.h> 54 #include <machine/autoconf.h> 55 #include <machine/cpu.h> 56 57 #include <dev/ic/lsi64854reg.h> 58 #include <dev/ic/lsi64854var.h> 59 60 #include <dev/ic/ncr53c9xreg.h> 61 #include <dev/ic/ncr53c9xvar.h> 62 63 #include <dev/sbus/sbusvar.h> 64 65 struct esp_softc { 66 struct ncr53c9x_softc sc_ncr53c9x; /* glue to MI code */ 67 struct sbusdev sc_sd; /* sbus device */ 68 69 bus_space_tag_t sc_bustag; 70 bus_dma_tag_t sc_dmatag; 71 72 bus_space_handle_t sc_reg; /* the registers */ 73 struct lsi64854_softc *sc_dma; /* pointer to my dma */ 74 75 int sc_pri; /* SBUS priority */ 76 }; 77 78 /* 79 * Is this esp on the bootpath? 80 * We may get two forms of the bootpath: 81 * (1) ../sbus (at) .../esp@<offset>,<slot>/sd@.. (PROM v3 style) 82 * (2) /sbus0/esp0/sd@.. (PROM v2 style) 83 */ 84 #define SAME_ESP(sc, bp, sa) \ 85 ((bp->val[0] == sa->sa_slot && bp->val[1] == sa->sa_offset) || \ 86 (bp->val[0] == -1 && bp->val[1] == sc->sc_dev.dv_unit)) 87 88 void espattach_sbus __P((struct device *, struct device *, void *)); 89 void espattach_dma __P((struct device *, struct device *, void *)); 90 int espmatch_sbus __P((struct device *, struct cfdata *, void *)); 91 92 static void espattach __P((struct esp_softc *)); 93 94 /* Linkup to the rest of the kernel */ 95 struct cfattach esp_sbus_ca = { 96 sizeof(struct esp_softc), espmatch_sbus, espattach_sbus 97 }; 98 struct cfattach esp_dma_ca = { 99 sizeof(struct esp_softc), espmatch_sbus, espattach_dma 100 }; 101 102 static struct scsipi_device esp_sbus_dev = { 103 NULL, /* Use default error handler */ 104 NULL, /* have a queue, served by this */ 105 NULL, /* have no async handler */ 106 NULL, /* Use default 'done' routine */ 107 }; 108 109 /* 110 * Functions and the switch for the MI code. 111 */ 112 static u_char esp_read_reg __P((struct ncr53c9x_softc *, int)); 113 static void esp_write_reg __P((struct ncr53c9x_softc *, int, u_char)); 114 static int esp_dma_isintr __P((struct ncr53c9x_softc *)); 115 static void esp_dma_reset __P((struct ncr53c9x_softc *)); 116 static int esp_dma_intr __P((struct ncr53c9x_softc *)); 117 static int esp_dma_setup __P((struct ncr53c9x_softc *, caddr_t *, 118 size_t *, int, size_t *)); 119 static void esp_dma_go __P((struct ncr53c9x_softc *)); 120 static void esp_dma_stop __P((struct ncr53c9x_softc *)); 121 static int esp_dma_isactive __P((struct ncr53c9x_softc *)); 122 123 static struct ncr53c9x_glue esp_sbus_glue = { 124 esp_read_reg, 125 esp_write_reg, 126 esp_dma_isintr, 127 esp_dma_reset, 128 esp_dma_intr, 129 esp_dma_setup, 130 esp_dma_go, 131 esp_dma_stop, 132 esp_dma_isactive, 133 NULL, /* gl_clear_latched_intr */ 134 }; 135 136 int 137 espmatch_sbus(parent, cf, aux) 138 struct device *parent; 139 struct cfdata *cf; 140 void *aux; 141 { 142 struct sbus_attach_args *sa = aux; 143 144 return (strcmp(cf->cf_driver->cd_name, sa->sa_name) == 0); 145 } 146 147 void 148 espattach_sbus(parent, self, aux) 149 struct device *parent, *self; 150 void *aux; 151 { 152 struct esp_softc *esc = (void *)self; 153 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 154 struct sbus_attach_args *sa = aux; 155 156 esc->sc_bustag = sa->sa_bustag; 157 esc->sc_dmatag = sa->sa_dmatag; 158 159 sc->sc_id = getpropint(sa->sa_node, "initiator-id", 7); 160 sc->sc_freq = getpropint(sa->sa_node, "clock-frequency", -1); 161 if (sc->sc_freq < 0) 162 sc->sc_freq = ((struct sbus_softc *) 163 sc->sc_dev.dv_parent)->sc_clockfreq; 164 165 /* 166 * Find the DMA by poking around the dma device structures 167 * 168 * What happens here is that if the dma driver has not been 169 * configured, then this returns a NULL pointer. Then when the 170 * dma actually gets configured, it does the opposing test, and 171 * if the sc->sc_esp field in it's softc is NULL, then tries to 172 * find the matching esp driver. 173 */ 174 esc->sc_dma = (struct lsi64854_softc *) 175 getdevunit("dma", sc->sc_dev.dv_unit); 176 177 /* 178 * and a back pointer to us, for DMA 179 */ 180 if (esc->sc_dma) 181 esc->sc_dma->sc_client = sc; 182 else { 183 printf("\n"); 184 panic("espattach: no dma found"); 185 } 186 187 /* 188 * Map my registers in, if they aren't already in virtual 189 * address space. 190 */ 191 if (sa->sa_npromvaddrs) 192 esc->sc_reg = (bus_space_handle_t)sa->sa_promvaddrs[0]; 193 else { 194 if (sbus_bus_map(sa->sa_bustag, sa->sa_slot, 195 sa->sa_offset, 196 sa->sa_size, 197 BUS_SPACE_MAP_LINEAR, 198 0, &esc->sc_reg) != 0) { 199 printf("%s @ sbus: cannot map registers\n", 200 self->dv_xname); 201 return; 202 } 203 } 204 205 esc->sc_pri = sa->sa_pri; 206 207 /* add me to the sbus structures */ 208 esc->sc_sd.sd_reset = (void *) ncr53c9x_reset; 209 sbus_establish(&esc->sc_sd, &sc->sc_dev); 210 211 if (sa->sa_bp != NULL && strcmp(sa->sa_bp->name, "esp") == 0 && 212 SAME_ESP(sc, sa->sa_bp, sa)) 213 bootpath_store(1, sa->sa_bp + 1); 214 215 espattach(esc); 216 } 217 218 void 219 espattach_dma(parent, self, aux) 220 struct device *parent, *self; 221 void *aux; 222 { 223 struct esp_softc *esc = (void *)self; 224 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 225 struct sbus_attach_args *sa = aux; 226 227 esc->sc_bustag = sa->sa_bustag; 228 esc->sc_dmatag = sa->sa_dmatag; 229 230 sc->sc_id = getpropint(sa->sa_node, "initiator-id", 7); 231 sc->sc_freq = getpropint(sa->sa_node, "clock-frequency", -1); 232 233 esc->sc_dma = (struct lsi64854_softc *)parent; 234 esc->sc_dma->sc_client = sc; 235 236 /* 237 * Map my registers in, if they aren't already in virtual 238 * address space. 239 */ 240 if (sa->sa_npromvaddrs) 241 esc->sc_reg = (bus_space_handle_t)sa->sa_promvaddrs[0]; 242 else { 243 if (bus_space_map2(sa->sa_bustag, 244 sa->sa_slot, 245 sa->sa_offset, 246 sa->sa_size, 247 BUS_SPACE_MAP_LINEAR, 248 0, &esc->sc_reg) != 0) { 249 printf("%s @ dma: cannot map registers\n", 250 self->dv_xname); 251 return; 252 } 253 } 254 255 /* Establish interrupt handler */ 256 esc->sc_pri = sa->sa_pri; 257 258 /* Assume SBus is grandparent */ 259 esc->sc_sd.sd_reset = (void *) ncr53c9x_reset; 260 sbus_establish(&esc->sc_sd, parent); 261 262 if (sa->sa_bp != NULL && strcmp(sa->sa_bp->name, "esp") == 0 && 263 SAME_ESP(sc, sa->sa_bp, sa)) 264 bootpath_store(1, sa->sa_bp + 1); 265 266 espattach(esc); 267 } 268 269 270 /* 271 * Attach this instance, and then all the sub-devices 272 */ 273 void 274 espattach(esc) 275 struct esp_softc *esc; 276 { 277 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 278 void *icookie; 279 280 /* 281 * Set up glue for MI code early; we use some of it here. 282 */ 283 sc->sc_glue = &esp_sbus_glue; 284 285 /* gimme Mhz */ 286 sc->sc_freq /= 1000000; 287 288 /* 289 * XXX More of this should be in ncr53c9x_attach(), but 290 * XXX should we really poke around the chip that much in 291 * XXX the MI code? Think about this more... 292 */ 293 294 /* 295 * It is necessary to try to load the 2nd config register here, 296 * to find out what rev the esp chip is, else the ncr53c9x_reset 297 * will not set up the defaults correctly. 298 */ 299 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 300 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_RPE; 301 sc->sc_cfg3 = NCRCFG3_CDB; 302 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 303 304 if ((NCR_READ_REG(sc, NCR_CFG2) & ~NCRCFG2_RSVD) != 305 (NCRCFG2_SCSI2 | NCRCFG2_RPE)) { 306 sc->sc_rev = NCR_VARIANT_ESP100; 307 } else { 308 sc->sc_cfg2 = NCRCFG2_SCSI2; 309 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 310 sc->sc_cfg3 = 0; 311 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 312 sc->sc_cfg3 = (NCRCFG3_CDB | NCRCFG3_FCLK); 313 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 314 if (NCR_READ_REG(sc, NCR_CFG3) != 315 (NCRCFG3_CDB | NCRCFG3_FCLK)) { 316 sc->sc_rev = NCR_VARIANT_ESP100A; 317 } else { 318 /* NCRCFG2_FE enables > 64K transfers */ 319 sc->sc_cfg2 |= NCRCFG2_FE; 320 sc->sc_cfg3 = 0; 321 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 322 sc->sc_rev = NCR_VARIANT_ESP200; 323 } 324 } 325 326 /* 327 * XXX minsync and maxxfer _should_ be set up in MI code, 328 * XXX but it appears to have some dependency on what sort 329 * XXX of DMA we're hooked up to, etc. 330 */ 331 332 /* 333 * This is the value used to start sync negotiations 334 * Note that the NCR register "SYNCTP" is programmed 335 * in "clocks per byte", and has a minimum value of 4. 336 * The SCSI period used in negotiation is one-fourth 337 * of the time (in nanoseconds) needed to transfer one byte. 338 * Since the chip's clock is given in MHz, we have the following 339 * formula: 4 * period = (1000 / freq) * 4 340 */ 341 sc->sc_minsync = 1000 / sc->sc_freq; 342 343 /* 344 * Alas, we must now modify the value a bit, because it's 345 * only valid when can switch on FASTCLK and FASTSCSI bits 346 * in config register 3... 347 */ 348 switch (sc->sc_rev) { 349 case NCR_VARIANT_ESP100: 350 sc->sc_maxxfer = 64 * 1024; 351 sc->sc_minsync = 0; /* No synch on old chip? */ 352 break; 353 354 case NCR_VARIANT_ESP100A: 355 sc->sc_maxxfer = 64 * 1024; 356 /* Min clocks/byte is 5 */ 357 sc->sc_minsync = ncr53c9x_cpb2stp(sc, 5); 358 break; 359 360 case NCR_VARIANT_ESP200: 361 sc->sc_maxxfer = 16 * 1024 * 1024; 362 /* XXX - do actually set FAST* bits */ 363 break; 364 } 365 366 /* Establish interrupt channel */ 367 icookie = bus_intr_establish(esc->sc_bustag, 368 esc->sc_pri, 0, 369 (int(*)__P((void*)))ncr53c9x_intr, sc); 370 371 /* register interrupt stats */ 372 evcnt_attach(&sc->sc_dev, "intr", &sc->sc_intrcnt); 373 374 /* Do the common parts of attachment. */ 375 sc->sc_adapter.scsipi_cmd = ncr53c9x_scsi_cmd; 376 sc->sc_adapter.scsipi_minphys = minphys; 377 ncr53c9x_attach(sc, &esp_sbus_dev); 378 379 /* Turn on target selection using the `dma' method */ 380 ncr53c9x_dmaselect = 1; 381 382 bootpath_store(1, NULL); 383 } 384 385 /* 386 * Glue functions. 387 */ 388 389 u_char 390 esp_read_reg(sc, reg) 391 struct ncr53c9x_softc *sc; 392 int reg; 393 { 394 struct esp_softc *esc = (struct esp_softc *)sc; 395 396 return (bus_space_read_1(esc->sc_bustag, esc->sc_reg, reg * 4)); 397 } 398 399 void 400 esp_write_reg(sc, reg, v) 401 struct ncr53c9x_softc *sc; 402 int reg; 403 u_char v; 404 { 405 struct esp_softc *esc = (struct esp_softc *)sc; 406 407 bus_space_write_1(esc->sc_bustag, esc->sc_reg, reg * 4, v); 408 } 409 410 int 411 esp_dma_isintr(sc) 412 struct ncr53c9x_softc *sc; 413 { 414 struct esp_softc *esc = (struct esp_softc *)sc; 415 416 return (DMA_ISINTR(esc->sc_dma)); 417 } 418 419 void 420 esp_dma_reset(sc) 421 struct ncr53c9x_softc *sc; 422 { 423 struct esp_softc *esc = (struct esp_softc *)sc; 424 425 DMA_RESET(esc->sc_dma); 426 } 427 428 int 429 esp_dma_intr(sc) 430 struct ncr53c9x_softc *sc; 431 { 432 struct esp_softc *esc = (struct esp_softc *)sc; 433 434 return (DMA_INTR(esc->sc_dma)); 435 } 436 437 int 438 esp_dma_setup(sc, addr, len, datain, dmasize) 439 struct ncr53c9x_softc *sc; 440 caddr_t *addr; 441 size_t *len; 442 int datain; 443 size_t *dmasize; 444 { 445 struct esp_softc *esc = (struct esp_softc *)sc; 446 447 return (DMA_SETUP(esc->sc_dma, addr, len, datain, dmasize)); 448 } 449 450 void 451 esp_dma_go(sc) 452 struct ncr53c9x_softc *sc; 453 { 454 struct esp_softc *esc = (struct esp_softc *)sc; 455 456 DMA_GO(esc->sc_dma); 457 } 458 459 void 460 esp_dma_stop(sc) 461 struct ncr53c9x_softc *sc; 462 { 463 struct esp_softc *esc = (struct esp_softc *)sc; 464 u_int32_t csr; 465 466 csr = L64854_GCSR(esc->sc_dma); 467 csr &= ~D_EN_DMA; 468 L64854_SCSR(esc->sc_dma, csr); 469 } 470 471 int 472 esp_dma_isactive(sc) 473 struct ncr53c9x_softc *sc; 474 { 475 struct esp_softc *esc = (struct esp_softc *)sc; 476 477 return (DMA_ISACTIVE(esc->sc_dma)); 478 } 479
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