esp_sbus.c revision 1.55
1 /* $NetBSD: esp_sbus.c,v 1.55 2019/11/10 21:16:37 chs Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum; Jason R. Thorpe of the Numerical Aerospace 9 * Simulation Facility, NASA Ames Research Center; Paul Kranenburg. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: esp_sbus.c,v 1.55 2019/11/10 21:16:37 chs Exp $"); 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/device.h> 39 #include <sys/buf.h> 40 #include <sys/malloc.h> 41 42 #include <dev/scsipi/scsi_all.h> 43 #include <dev/scsipi/scsipi_all.h> 44 #include <dev/scsipi/scsiconf.h> 45 #include <dev/scsipi/scsi_message.h> 46 47 #include <sys/bus.h> 48 #include <sys/intr.h> 49 #include <machine/autoconf.h> 50 51 #include <dev/ic/lsi64854reg.h> 52 #include <dev/ic/lsi64854var.h> 53 54 #include <dev/ic/ncr53c9xreg.h> 55 #include <dev/ic/ncr53c9xvar.h> 56 57 #include <dev/sbus/sbusvar.h> 58 59 #include "opt_ddb.h" 60 61 /* #define ESP_SBUS_DEBUG */ 62 63 struct esp_softc { 64 struct ncr53c9x_softc sc_ncr53c9x; /* glue to MI code */ 65 66 bus_space_tag_t sc_bustag; 67 bus_dma_tag_t sc_dmatag; 68 69 bus_space_handle_t sc_reg; /* the registers */ 70 struct lsi64854_softc *sc_dma; /* pointer to my dma */ 71 72 int sc_pri; /* SBUS priority */ 73 }; 74 75 int espmatch_sbus(device_t, cfdata_t, void *); 76 void espattach_sbus(device_t, device_t, void *); 77 void espattach_dma(device_t, device_t, void *); 78 79 static void espattach(struct esp_softc *, struct ncr53c9x_glue *); 80 81 CFATTACH_DECL_NEW(esp_sbus, sizeof(struct esp_softc), 82 espmatch_sbus, espattach_sbus, NULL, NULL); 83 84 CFATTACH_DECL_NEW(esp_dma, sizeof(struct esp_softc), 85 espmatch_sbus, espattach_dma, NULL, NULL); 86 87 /* 88 * Functions and the switch for the MI code. 89 */ 90 static uint8_t esp_read_reg(struct ncr53c9x_softc *, int); 91 static void esp_write_reg(struct ncr53c9x_softc *, int, uint8_t); 92 static uint8_t esp_rdreg1(struct ncr53c9x_softc *, int); 93 static void esp_wrreg1(struct ncr53c9x_softc *, int, uint8_t); 94 static int esp_dma_isintr(struct ncr53c9x_softc *); 95 static void esp_dma_reset(struct ncr53c9x_softc *); 96 static int esp_dma_intr(struct ncr53c9x_softc *); 97 static int esp_dma_setup(struct ncr53c9x_softc *, uint8_t **, 98 size_t *, int, size_t *); 99 static void esp_dma_go(struct ncr53c9x_softc *); 100 static void esp_dma_stop(struct ncr53c9x_softc *); 101 static int esp_dma_isactive(struct ncr53c9x_softc *); 102 103 #ifdef DDB 104 static void esp_init_ddb_cmds(void); 105 #endif 106 107 static struct ncr53c9x_glue esp_sbus_glue = { 108 esp_read_reg, 109 esp_write_reg, 110 esp_dma_isintr, 111 esp_dma_reset, 112 esp_dma_intr, 113 esp_dma_setup, 114 esp_dma_go, 115 esp_dma_stop, 116 esp_dma_isactive, 117 NULL, /* gl_clear_latched_intr */ 118 }; 119 120 static struct ncr53c9x_glue esp_sbus_glue1 = { 121 esp_rdreg1, 122 esp_wrreg1, 123 esp_dma_isintr, 124 esp_dma_reset, 125 esp_dma_intr, 126 esp_dma_setup, 127 esp_dma_go, 128 esp_dma_stop, 129 esp_dma_isactive, 130 NULL, /* gl_clear_latched_intr */ 131 }; 132 133 int 134 espmatch_sbus(device_t parent, cfdata_t cf, void *aux) 135 { 136 int rv; 137 struct sbus_attach_args *sa = aux; 138 139 if (strcmp("SUNW,fas", sa->sa_name) == 0) 140 return 1; 141 142 rv = (strcmp(cf->cf_name, sa->sa_name) == 0 || 143 strcmp("ptscII", sa->sa_name) == 0); 144 return rv; 145 } 146 147 void 148 espattach_sbus(device_t parent, device_t self, void *aux) 149 { 150 struct esp_softc *esc = device_private(self); 151 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 152 struct sbus_softc *sbsc = device_private(parent); 153 struct sbus_attach_args *sa = aux; 154 struct lsi64854_softc *lsc; 155 device_t dma_dev; 156 int burst, sbusburst; 157 158 sc->sc_dev = self; 159 160 #ifdef DDB 161 esp_init_ddb_cmds(); 162 #endif 163 164 esc->sc_bustag = sa->sa_bustag; 165 esc->sc_dmatag = sa->sa_dmatag; 166 167 sc->sc_id = prom_getpropint(sa->sa_node, "initiator-id", 7); 168 sc->sc_freq = prom_getpropint(sa->sa_node, "clock-frequency", -1); 169 if (sc->sc_freq < 0) 170 sc->sc_freq = sbsc->sc_clockfreq; 171 172 #ifdef ESP_SBUS_DEBUG 173 aprint_normal("\n"); 174 aprint_normal_dev(self, "%s: sc_id %d, freq %d\n", 175 __func__, sc->sc_id, sc->sc_freq); 176 aprint_normal("%s", device_xname(self)); 177 #endif 178 179 if (strcmp("SUNW,fas", sa->sa_name) == 0) { 180 181 /* 182 * fas has 2 register spaces: dma(lsi64854) and 183 * SCSI core (ncr53c9x) 184 */ 185 if (sa->sa_nreg != 2) { 186 aprint_error(": %d register spaces\n", sa->sa_nreg); 187 return; 188 } 189 190 /* 191 * allocate space for dma, in SUNW,fas there are no separate 192 * dma device 193 */ 194 lsc = malloc(sizeof(struct lsi64854_softc), M_DEVBUF, M_WAITOK); 195 lsc->sc_dev = malloc(sizeof(struct device), M_DEVBUF, 196 M_WAITOK | M_ZERO); 197 esc->sc_dma = lsc; 198 199 lsc->sc_bustag = sa->sa_bustag; 200 lsc->sc_dmatag = sa->sa_dmatag; 201 202 strlcpy(lsc->sc_dev->dv_xname, device_xname(sc->sc_dev), 203 sizeof(lsc->sc_dev->dv_xname)); 204 205 /* Map dma registers */ 206 if (sa->sa_npromvaddrs) { 207 sbus_promaddr_to_handle(sa->sa_bustag, 208 sa->sa_promvaddrs[0], &lsc->sc_regs); 209 } else { 210 if (sbus_bus_map(sa->sa_bustag, 211 sa->sa_reg[0].oa_space, 212 sa->sa_reg[0].oa_base, 213 sa->sa_reg[0].oa_size, 214 0, &lsc->sc_regs) != 0) { 215 aprint_error(": cannot map dma registers\n"); 216 return; 217 } 218 } 219 220 /* 221 * XXX is this common(from bpp.c), the same in dma_sbus...etc. 222 * 223 * Get transfer burst size from PROM and plug it into the 224 * controller registers. This is needed on the Sun4m; do 225 * others need it too? 226 */ 227 sbusburst = sbsc->sc_burst; 228 if (sbusburst == 0) 229 sbusburst = SBUS_BURST_32 - 1; /* 1->16 */ 230 231 burst = prom_getpropint(sa->sa_node, "burst-sizes", -1); 232 233 #if ESP_SBUS_DEBUG 234 aprint_normal("%s: burst 0x%x, sbus 0x%x\n", 235 __func__, burst, sbusburst); 236 aprint_normal("%s", device_xname(self)); 237 #endif 238 239 if (burst == -1) 240 /* take SBus burst sizes */ 241 burst = sbusburst; 242 243 /* Clamp at parent's burst sizes */ 244 burst &= sbusburst; 245 lsc->sc_burst = (burst & SBUS_BURST_32) ? 32 : 246 (burst & SBUS_BURST_16) ? 16 : 0; 247 248 lsc->sc_channel = L64854_CHANNEL_SCSI; 249 lsc->sc_client = sc; 250 251 lsi64854_attach(lsc); 252 253 /* 254 * map SCSI core registers 255 */ 256 if (sa->sa_npromvaddrs > 1) { 257 sbus_promaddr_to_handle(sa->sa_bustag, 258 sa->sa_promvaddrs[1], &esc->sc_reg); 259 } else { 260 if (sbus_bus_map(sa->sa_bustag, 261 sa->sa_reg[1].oa_space, 262 sa->sa_reg[1].oa_base, 263 sa->sa_reg[1].oa_size, 264 0, &esc->sc_reg) != 0) { 265 aprint_error(": cannot map " 266 "scsi core registers\n"); 267 return; 268 } 269 } 270 271 if (sa->sa_nintr == 0) { 272 aprint_error(": no interrupt property\n"); 273 return; 274 } 275 276 esc->sc_pri = sa->sa_pri; 277 278 espattach(esc, &esp_sbus_glue); 279 280 return; 281 } 282 283 /* 284 * Find the DMA by poking around the dma device structures 285 * 286 * What happens here is that if the dma driver has not been 287 * configured, then this returns a NULL pointer. Then when the 288 * dma actually gets configured, it does the opposing test, and 289 * if the sc->sc_esp field in its softc is NULL, then tries to 290 * find the matching esp driver. 291 */ 292 dma_dev = device_find_by_driver_unit("dma", device_unit(self)); 293 if (dma_dev == NULL) { 294 aprint_error(": no corresponding DMA device\n"); 295 return; 296 } 297 esc->sc_dma = device_private(dma_dev); 298 esc->sc_dma->sc_client = sc; 299 300 /* 301 * The `ESC' DMA chip must be reset before we can access 302 * the esp registers. 303 */ 304 if (esc->sc_dma->sc_rev == DMAREV_ESC) 305 DMA_RESET(esc->sc_dma); 306 307 /* 308 * Map my registers in, if they aren't already in virtual 309 * address space. 310 */ 311 if (sa->sa_npromvaddrs) { 312 sbus_promaddr_to_handle(sa->sa_bustag, 313 sa->sa_promvaddrs[0], &esc->sc_reg); 314 } else { 315 if (sbus_bus_map(sa->sa_bustag, 316 sa->sa_slot, sa->sa_offset, sa->sa_size, 317 0, &esc->sc_reg) != 0) { 318 aprint_error(": cannot map registers\n"); 319 return; 320 } 321 } 322 323 if (sa->sa_nintr == 0) { 324 /* 325 * No interrupt properties: we quit; this might 326 * happen on e.g. a Sparc X terminal. 327 */ 328 aprint_error(": no interrupt property\n"); 329 return; 330 } 331 332 esc->sc_pri = sa->sa_pri; 333 334 if (strcmp("ptscII", sa->sa_name) == 0) { 335 espattach(esc, &esp_sbus_glue1); 336 } else { 337 espattach(esc, &esp_sbus_glue); 338 } 339 } 340 341 void 342 espattach_dma(device_t parent, device_t self, void *aux) 343 { 344 struct esp_softc *esc = device_private(self); 345 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 346 struct sbus_attach_args *sa = aux; 347 348 if (strcmp("ptscII", sa->sa_name) == 0) { 349 return; 350 } 351 352 sc->sc_dev = self; 353 354 esc->sc_bustag = sa->sa_bustag; 355 esc->sc_dmatag = sa->sa_dmatag; 356 357 sc->sc_id = prom_getpropint(sa->sa_node, "initiator-id", 7); 358 sc->sc_freq = prom_getpropint(sa->sa_node, "clock-frequency", -1); 359 360 esc->sc_dma = device_private(parent); 361 esc->sc_dma->sc_client = sc; 362 363 /* 364 * Map my registers in, if they aren't already in virtual 365 * address space. 366 */ 367 if (sa->sa_npromvaddrs) { 368 sbus_promaddr_to_handle(sa->sa_bustag, 369 sa->sa_promvaddrs[0], &esc->sc_reg); 370 } else { 371 if (sbus_bus_map(sa->sa_bustag, 372 sa->sa_slot, sa->sa_offset, sa->sa_size, 373 0, &esc->sc_reg) != 0) { 374 aprint_error(": cannot map registers\n"); 375 return; 376 } 377 } 378 379 if (sa->sa_nintr == 0) { 380 /* 381 * No interrupt properties: we quit; this might 382 * happen on e.g. a Sparc X terminal. 383 */ 384 aprint_error(": no interrupt property\n"); 385 return; 386 } 387 388 esc->sc_pri = sa->sa_pri; 389 390 espattach(esc, &esp_sbus_glue); 391 } 392 393 394 /* 395 * Attach this instance, and then all the sub-devices 396 */ 397 void 398 espattach(struct esp_softc *esc, struct ncr53c9x_glue *gluep) 399 { 400 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 401 unsigned int uid = 0; 402 403 /* 404 * Set up glue for MI code early; we use some of it here. 405 */ 406 sc->sc_glue = gluep; 407 408 /* gimme MHz */ 409 sc->sc_freq /= 1000000; 410 411 /* 412 * XXX More of this should be in ncr53c9x_attach(), but 413 * XXX should we really poke around the chip that much in 414 * XXX the MI code? Think about this more... 415 */ 416 417 /* 418 * It is necessary to try to load the 2nd config register here, 419 * to find out what rev the esp chip is, else the ncr53c9x_reset 420 * will not set up the defaults correctly. 421 */ 422 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 423 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_RPE; 424 sc->sc_cfg3 = NCRCFG3_CDB; 425 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 426 427 if ((NCR_READ_REG(sc, NCR_CFG2) & ~NCRCFG2_RSVD) != 428 (NCRCFG2_SCSI2 | NCRCFG2_RPE)) { 429 sc->sc_rev = NCR_VARIANT_ESP100; 430 } else { 431 sc->sc_cfg2 = NCRCFG2_SCSI2; 432 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 433 sc->sc_cfg3 = 0; 434 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 435 sc->sc_cfg3 = (NCRCFG3_CDB | NCRCFG3_FCLK); 436 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 437 if (NCR_READ_REG(sc, NCR_CFG3) != 438 (NCRCFG3_CDB | NCRCFG3_FCLK)) { 439 sc->sc_rev = NCR_VARIANT_ESP100A; 440 } else { 441 /* NCRCFG2_FE enables > 64K transfers */ 442 sc->sc_cfg2 |= NCRCFG2_FE; 443 sc->sc_cfg3 = 0; 444 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 445 sc->sc_rev = NCR_VARIANT_ESP200; 446 447 /* 448 * XXX spec says it's valid after power up or 449 * chip reset 450 */ 451 uid = NCR_READ_REG(sc, NCR_UID); 452 if (((uid & 0xf8) >> 3) == 0x0a) /* XXX */ 453 sc->sc_rev = NCR_VARIANT_FAS366; 454 } 455 } 456 457 #ifdef ESP_SBUS_DEBUG 458 aprint_debug("%s: revision %d, uid 0x%x\n", __func__, sc->sc_rev, uid); 459 aprint_normal("%s", device_xname(sc->sc_dev)); 460 #endif 461 462 /* 463 * XXX minsync and maxxfer _should_ be set up in MI code, 464 * XXX but it appears to have some dependency on what sort 465 * XXX of DMA we're hooked up to, etc. 466 */ 467 468 /* 469 * This is the value used to start sync negotiations 470 * Note that the NCR register "SYNCTP" is programmed 471 * in "clocks per byte", and has a minimum value of 4. 472 * The SCSI period used in negotiation is one-fourth 473 * of the time (in nanoseconds) needed to transfer one byte. 474 * Since the chip's clock is given in MHz, we have the following 475 * formula: 4 * period = (1000 / freq) * 4 476 */ 477 sc->sc_minsync = 1000 / sc->sc_freq; 478 479 /* 480 * Alas, we must now modify the value a bit, because it's 481 * only valid when can switch on FASTCLK and FASTSCSI bits 482 * in config register 3... 483 */ 484 switch (sc->sc_rev) { 485 case NCR_VARIANT_ESP100: 486 sc->sc_maxxfer = 64 * 1024; 487 sc->sc_minsync = 0; /* No synch on old chip? */ 488 break; 489 490 case NCR_VARIANT_ESP100A: 491 sc->sc_maxxfer = 64 * 1024; 492 /* Min clocks/byte is 5 */ 493 sc->sc_minsync = ncr53c9x_cpb2stp(sc, 5); 494 break; 495 496 case NCR_VARIANT_ESP200: 497 case NCR_VARIANT_FAS366: 498 sc->sc_maxxfer = 16 * 1024 * 1024; 499 /* XXX - do actually set FAST* bits */ 500 break; 501 } 502 503 /* Establish interrupt channel */ 504 bus_intr_establish(esc->sc_bustag, esc->sc_pri, IPL_BIO, 505 ncr53c9x_intr, sc); 506 507 /* register interrupt stats */ 508 evcnt_attach_dynamic(&sc->sc_intrcnt, EVCNT_TYPE_INTR, NULL, 509 device_xname(sc->sc_dev), "intr"); 510 511 /* Turn on target selection using the `dma' method */ 512 if (sc->sc_rev != NCR_VARIANT_FAS366) 513 sc->sc_features |= NCR_F_DMASELECT; 514 515 /* Do the common parts of attachment. */ 516 sc->sc_adapter.adapt_minphys = minphys; 517 sc->sc_adapter.adapt_request = ncr53c9x_scsipi_request; 518 ncr53c9x_attach(sc); 519 } 520 521 /* 522 * Glue functions. 523 */ 524 525 #ifdef ESP_SBUS_DEBUG 526 int esp_sbus_debug = 0; 527 528 static struct { 529 char *r_name; 530 int r_flag; 531 } esp__read_regnames [] = { 532 { "TCL", 0}, /* 0/00 */ 533 { "TCM", 0}, /* 1/04 */ 534 { "FIFO", 0}, /* 2/08 */ 535 { "CMD", 0}, /* 3/0c */ 536 { "STAT", 0}, /* 4/10 */ 537 { "INTR", 0}, /* 5/14 */ 538 { "STEP", 0}, /* 6/18 */ 539 { "FFLAGS", 1}, /* 7/1c */ 540 { "CFG1", 1}, /* 8/20 */ 541 { "STAT2", 0}, /* 9/24 */ 542 { "CFG4", 1}, /* a/28 */ 543 { "CFG2", 1}, /* b/2c */ 544 { "CFG3", 1}, /* c/30 */ 545 { "-none", 1}, /* d/34 */ 546 { "TCH", 1}, /* e/38 */ 547 { "TCX", 1}, /* f/3c */ 548 }; 549 550 static struct { 551 char *r_name; 552 int r_flag; 553 } esp__write_regnames[] = { 554 { "TCL", 1}, /* 0/00 */ 555 { "TCM", 1}, /* 1/04 */ 556 { "FIFO", 0}, /* 2/08 */ 557 { "CMD", 0}, /* 3/0c */ 558 { "SELID", 1}, /* 4/10 */ 559 { "TIMEOUT", 1}, /* 5/14 */ 560 { "SYNCTP", 1}, /* 6/18 */ 561 { "SYNCOFF", 1}, /* 7/1c */ 562 { "CFG1", 1}, /* 8/20 */ 563 { "CCF", 1}, /* 9/24 */ 564 { "TEST", 1}, /* a/28 */ 565 { "CFG2", 1}, /* b/2c */ 566 { "CFG3", 1}, /* c/30 */ 567 { "-none", 1}, /* d/34 */ 568 { "TCH", 1}, /* e/38 */ 569 { "TCX", 1}, /* f/3c */ 570 }; 571 #endif 572 573 uint8_t 574 esp_read_reg(struct ncr53c9x_softc *sc, int reg) 575 { 576 struct esp_softc *esc = (struct esp_softc *)sc; 577 uint8_t v; 578 579 v = bus_space_read_1(esc->sc_bustag, esc->sc_reg, reg * 4); 580 #ifdef ESP_SBUS_DEBUG 581 if (esp_sbus_debug && (reg < 0x10) && esp__read_regnames[reg].r_flag) 582 printf("RD:%x <%s> %x\n", reg * 4, 583 ((unsigned int)reg < 0x10) ? 584 esp__read_regnames[reg].r_name : "<***>", v); 585 #endif 586 return v; 587 } 588 589 void 590 esp_write_reg(struct ncr53c9x_softc *sc, int reg, uint8_t v) 591 { 592 struct esp_softc *esc = (struct esp_softc *)sc; 593 594 #ifdef ESP_SBUS_DEBUG 595 if (esp_sbus_debug && (reg < 0x10) && esp__write_regnames[reg].r_flag) 596 printf("WR:%x <%s> %x\n", reg * 4, 597 ((unsigned int)reg < 0x10) ? 598 esp__write_regnames[reg].r_name : "<***>", v); 599 #endif 600 bus_space_write_1(esc->sc_bustag, esc->sc_reg, reg * 4, v); 601 } 602 603 uint8_t 604 esp_rdreg1(struct ncr53c9x_softc *sc, int reg) 605 { 606 struct esp_softc *esc = (struct esp_softc *)sc; 607 608 return bus_space_read_1(esc->sc_bustag, esc->sc_reg, reg); 609 } 610 611 void 612 esp_wrreg1(struct ncr53c9x_softc *sc, int reg, uint8_t v) 613 { 614 struct esp_softc *esc = (struct esp_softc *)sc; 615 616 bus_space_write_1(esc->sc_bustag, esc->sc_reg, reg, v); 617 } 618 619 int 620 esp_dma_isintr(struct ncr53c9x_softc *sc) 621 { 622 struct esp_softc *esc = (struct esp_softc *)sc; 623 624 return DMA_ISINTR(esc->sc_dma); 625 } 626 627 void 628 esp_dma_reset(struct ncr53c9x_softc *sc) 629 { 630 struct esp_softc *esc = (struct esp_softc *)sc; 631 632 DMA_RESET(esc->sc_dma); 633 } 634 635 int 636 esp_dma_intr(struct ncr53c9x_softc *sc) 637 { 638 struct esp_softc *esc = (struct esp_softc *)sc; 639 640 return DMA_INTR(esc->sc_dma); 641 } 642 643 int 644 esp_dma_setup(struct ncr53c9x_softc *sc, uint8_t **addr, size_t *len, 645 int datain, size_t *dmasize) 646 { 647 struct esp_softc *esc = (struct esp_softc *)sc; 648 649 return DMA_SETUP(esc->sc_dma, addr, len, datain, dmasize); 650 } 651 652 void 653 esp_dma_go(struct ncr53c9x_softc *sc) 654 { 655 struct esp_softc *esc = (struct esp_softc *)sc; 656 657 DMA_GO(esc->sc_dma); 658 } 659 660 void 661 esp_dma_stop(struct ncr53c9x_softc *sc) 662 { 663 struct esp_softc *esc = (struct esp_softc *)sc; 664 uint32_t csr; 665 666 csr = L64854_GCSR(esc->sc_dma); 667 csr &= ~D_EN_DMA; 668 L64854_SCSR(esc->sc_dma, csr); 669 } 670 671 int 672 esp_dma_isactive(struct ncr53c9x_softc *sc) 673 { 674 struct esp_softc *esc = (struct esp_softc *)sc; 675 676 return DMA_ISACTIVE(esc->sc_dma); 677 } 678 679 #ifdef DDB 680 #include <machine/db_machdep.h> 681 #include <ddb/db_output.h> 682 #include <ddb/db_command.h> 683 684 void db_esp(db_expr_t, bool, db_expr_t, const char*); 685 686 const struct db_command db_esp_command_table[] = { 687 { DDB_ADD_CMD("esp", db_esp, 0, 688 "display status of all esp SCSI controllers and their devices", 689 NULL, NULL) }, 690 { DDB_ADD_CMD(NULL, NULL, 0, NULL, NULL, NULL) } 691 }; 692 693 static void 694 esp_init_ddb_cmds(void) 695 { 696 static int db_cmds_initialized = 0; 697 698 if (db_cmds_initialized) 699 return; 700 db_cmds_initialized = 1; 701 (void)db_register_tbl(DDB_MACH_CMD, db_esp_command_table); 702 } 703 704 void 705 db_esp(db_expr_t addr, bool have_addr, db_expr_t count, const char *modif) 706 { 707 device_t dv; 708 struct ncr53c9x_softc *sc; 709 struct ncr53c9x_ecb *ecb; 710 struct ncr53c9x_linfo *li; 711 int u, t, i; 712 713 for (u = 0; u < 10; u++) { 714 dv = device_find_by_driver_unit("esp", u); 715 if (dv == NULL) 716 continue; 717 sc = device_private(dv); 718 719 db_printf("%s: nexus %p phase %x prev %x" 720 " dp %p dleft %lx ify %x\n", device_xname(dv), 721 sc->sc_nexus, sc->sc_phase, sc->sc_prevphase, 722 sc->sc_dp, sc->sc_dleft, sc->sc_msgify); 723 db_printf("\tmsgout %x msgpriq %x msgin %x:%x:%x:%x:%x\n", 724 sc->sc_msgout, sc->sc_msgpriq, sc->sc_imess[0], 725 sc->sc_imess[1], sc->sc_imess[2], sc->sc_imess[3], 726 sc->sc_imess[0]); 727 db_printf("ready: "); 728 for (ecb = TAILQ_FIRST(&sc->ready_list); ecb != NULL; 729 ecb = TAILQ_NEXT(ecb, chain)) { 730 db_printf("ecb %p ", ecb); 731 if (ecb == TAILQ_NEXT(ecb, chain)) { 732 db_printf("\nWARNING: tailq loop on ecb %p", 733 ecb); 734 break; 735 } 736 } 737 db_printf("\n"); 738 739 for (t = 0; t < sc->sc_ntarg; t++) { 740 LIST_FOREACH(li, &sc->sc_tinfo[t].luns, link) { 741 db_printf("t%d lun %d untagged %p" 742 " busy %d used %x\n", 743 t, (int)li->lun, li->untagged, li->busy, 744 li->used); 745 for (i = 0; i < 256; i++) { 746 ecb = li->queued[i]; 747 if (ecb != NULL) { 748 db_printf("ecb %p tag %x\n", 749 ecb, i); 750 } 751 } 752 } 753 } 754 } 755 } 756 #endif 757
Indexes created Mon Sep 29 21:09:56 GMT 2025