esp_sbus.c revision 1.6.8.4
1 /* $NetBSD: esp_sbus.c,v 1.6.8.4 2000/12/08 09:12:40 bouyer Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum; Jason R. Thorpe of the Numerical Aerospace 9 * Simulation Facility, NASA Ames Research Center; Paul Kranenburg. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 #include <sys/types.h> 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/kernel.h> 44 #include <sys/errno.h> 45 #include <sys/device.h> 46 #include <sys/buf.h> 47 48 #include <dev/scsipi/scsi_all.h> 49 #include <dev/scsipi/scsipi_all.h> 50 #include <dev/scsipi/scsiconf.h> 51 #include <dev/scsipi/scsi_message.h> 52 53 #include <machine/bus.h> 54 #include <machine/intr.h> 55 #include <machine/autoconf.h> 56 57 #include <dev/ic/lsi64854reg.h> 58 #include <dev/ic/lsi64854var.h> 59 60 #include <dev/ic/ncr53c9xreg.h> 61 #include <dev/ic/ncr53c9xvar.h> 62 63 #include <dev/sbus/sbusvar.h> 64 65 struct esp_softc { 66 struct ncr53c9x_softc sc_ncr53c9x; /* glue to MI code */ 67 struct sbusdev sc_sd; /* sbus device */ 68 69 bus_space_tag_t sc_bustag; 70 bus_dma_tag_t sc_dmatag; 71 72 bus_space_handle_t sc_reg; /* the registers */ 73 struct lsi64854_softc *sc_dma; /* pointer to my dma */ 74 75 int sc_pri; /* SBUS priority */ 76 }; 77 78 void espattach_sbus __P((struct device *, struct device *, void *)); 79 void espattach_dma __P((struct device *, struct device *, void *)); 80 int espmatch_sbus __P((struct device *, struct cfdata *, void *)); 81 82 83 /* Linkup to the rest of the kernel */ 84 struct cfattach esp_sbus_ca = { 85 sizeof(struct esp_softc), espmatch_sbus, espattach_sbus 86 }; 87 struct cfattach esp_dma_ca = { 88 sizeof(struct esp_softc), espmatch_sbus, espattach_dma 89 }; 90 91 /* 92 * Functions and the switch for the MI code. 93 */ 94 static u_char esp_read_reg __P((struct ncr53c9x_softc *, int)); 95 static void esp_write_reg __P((struct ncr53c9x_softc *, int, u_char)); 96 static u_char esp_rdreg1 __P((struct ncr53c9x_softc *, int)); 97 static void esp_wrreg1 __P((struct ncr53c9x_softc *, int, u_char)); 98 static int esp_dma_isintr __P((struct ncr53c9x_softc *)); 99 static void esp_dma_reset __P((struct ncr53c9x_softc *)); 100 static int esp_dma_intr __P((struct ncr53c9x_softc *)); 101 static int esp_dma_setup __P((struct ncr53c9x_softc *, caddr_t *, 102 size_t *, int, size_t *)); 103 static void esp_dma_go __P((struct ncr53c9x_softc *)); 104 static void esp_dma_stop __P((struct ncr53c9x_softc *)); 105 static int esp_dma_isactive __P((struct ncr53c9x_softc *)); 106 107 static struct ncr53c9x_glue esp_sbus_glue = { 108 esp_read_reg, 109 esp_write_reg, 110 esp_dma_isintr, 111 esp_dma_reset, 112 esp_dma_intr, 113 esp_dma_setup, 114 esp_dma_go, 115 esp_dma_stop, 116 esp_dma_isactive, 117 NULL, /* gl_clear_latched_intr */ 118 }; 119 120 static struct ncr53c9x_glue esp_sbus_glue1 = { 121 esp_rdreg1, 122 esp_wrreg1, 123 esp_dma_isintr, 124 esp_dma_reset, 125 esp_dma_intr, 126 esp_dma_setup, 127 esp_dma_go, 128 esp_dma_stop, 129 esp_dma_isactive, 130 NULL, /* gl_clear_latched_intr */ 131 }; 132 133 static void espattach __P((struct esp_softc *, struct ncr53c9x_glue *)); 134 135 int 136 espmatch_sbus(parent, cf, aux) 137 struct device *parent; 138 struct cfdata *cf; 139 void *aux; 140 { 141 int rv; 142 struct sbus_attach_args *sa = aux; 143 144 rv = (strcmp(cf->cf_driver->cd_name, sa->sa_name) == 0 || 145 strcmp("ptscII", sa->sa_name) == 0); 146 return (rv); 147 } 148 149 void 150 espattach_sbus(parent, self, aux) 151 struct device *parent, *self; 152 void *aux; 153 { 154 struct esp_softc *esc = (void *)self; 155 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 156 struct sbus_attach_args *sa = aux; 157 158 esc->sc_bustag = sa->sa_bustag; 159 esc->sc_dmatag = sa->sa_dmatag; 160 161 sc->sc_id = getpropint(sa->sa_node, "initiator-id", 7); 162 sc->sc_freq = getpropint(sa->sa_node, "clock-frequency", -1); 163 if (sc->sc_freq < 0) 164 sc->sc_freq = ((struct sbus_softc *) 165 sc->sc_dev.dv_parent)->sc_clockfreq; 166 167 /* 168 * Find the DMA by poking around the dma device structures 169 * 170 * What happens here is that if the dma driver has not been 171 * configured, then this returns a NULL pointer. Then when the 172 * dma actually gets configured, it does the opposing test, and 173 * if the sc->sc_esp field in it's softc is NULL, then tries to 174 * find the matching esp driver. 175 */ 176 esc->sc_dma = (struct lsi64854_softc *) 177 getdevunit("dma", sc->sc_dev.dv_unit); 178 179 /* 180 * and a back pointer to us, for DMA 181 */ 182 if (esc->sc_dma) 183 esc->sc_dma->sc_client = sc; 184 else { 185 printf("\n"); 186 panic("espattach: no dma found"); 187 } 188 189 /* 190 * Map my registers in, if they aren't already in virtual 191 * address space. 192 */ 193 if (sa->sa_npromvaddrs) 194 esc->sc_reg = (bus_space_handle_t)sa->sa_promvaddrs[0]; 195 else { 196 if (sbus_bus_map(sa->sa_bustag, sa->sa_slot, 197 sa->sa_offset, 198 sa->sa_size, 199 BUS_SPACE_MAP_LINEAR, 200 0, &esc->sc_reg) != 0) { 201 printf("%s @ sbus: cannot map registers\n", 202 self->dv_xname); 203 return; 204 } 205 } 206 207 if (sa->sa_nintr == 0) { 208 /* 209 * No interrupt properties: we quit; this might 210 * happen on e.g. a Sparc X terminal. 211 */ 212 printf("\n%s: no interrupt property\n", self->dv_xname); 213 return; 214 } 215 216 esc->sc_pri = sa->sa_pri; 217 218 /* add me to the sbus structures */ 219 esc->sc_sd.sd_reset = (void *) ncr53c9x_reset; 220 sbus_establish(&esc->sc_sd, &sc->sc_dev); 221 222 if (strcmp("ptscII", sa->sa_name) == 0) { 223 espattach(esc, &esp_sbus_glue1); 224 } else { 225 espattach(esc, &esp_sbus_glue); 226 } 227 } 228 229 void 230 espattach_dma(parent, self, aux) 231 struct device *parent, *self; 232 void *aux; 233 { 234 struct esp_softc *esc = (void *)self; 235 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 236 struct sbus_attach_args *sa = aux; 237 238 if (strcmp("ptscII", sa->sa_name) == 0) { 239 return; 240 } 241 242 esc->sc_bustag = sa->sa_bustag; 243 esc->sc_dmatag = sa->sa_dmatag; 244 245 sc->sc_id = getpropint(sa->sa_node, "initiator-id", 7); 246 sc->sc_freq = getpropint(sa->sa_node, "clock-frequency", -1); 247 248 esc->sc_dma = (struct lsi64854_softc *)parent; 249 esc->sc_dma->sc_client = sc; 250 251 /* 252 * Map my registers in, if they aren't already in virtual 253 * address space. 254 */ 255 if (sa->sa_npromvaddrs) 256 esc->sc_reg = (bus_space_handle_t)sa->sa_promvaddrs[0]; 257 else { 258 if (bus_space_map2(sa->sa_bustag, 259 sa->sa_slot, 260 sa->sa_offset, 261 sa->sa_size, 262 BUS_SPACE_MAP_LINEAR, 263 0, &esc->sc_reg) != 0) { 264 printf("%s @ dma: cannot map registers\n", 265 self->dv_xname); 266 return; 267 } 268 } 269 270 if (sa->sa_nintr == 0) { 271 /* 272 * No interrupt properties: we quit; this might 273 * happen on e.g. a Sparc X terminal. 274 */ 275 printf("\n%s: no interrupt property\n", self->dv_xname); 276 return; 277 } 278 279 esc->sc_pri = sa->sa_pri; 280 281 /* Assume SBus is grandparent */ 282 esc->sc_sd.sd_reset = (void *) ncr53c9x_reset; 283 sbus_establish(&esc->sc_sd, parent); 284 285 espattach(esc, &esp_sbus_glue); 286 } 287 288 289 /* 290 * Attach this instance, and then all the sub-devices 291 */ 292 void 293 espattach(esc, gluep) 294 struct esp_softc *esc; 295 struct ncr53c9x_glue *gluep; 296 { 297 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 298 void *icookie; 299 300 /* 301 * Set up glue for MI code early; we use some of it here. 302 */ 303 sc->sc_glue = gluep; 304 305 /* gimme Mhz */ 306 sc->sc_freq /= 1000000; 307 308 /* 309 * XXX More of this should be in ncr53c9x_attach(), but 310 * XXX should we really poke around the chip that much in 311 * XXX the MI code? Think about this more... 312 */ 313 314 /* 315 * It is necessary to try to load the 2nd config register here, 316 * to find out what rev the esp chip is, else the ncr53c9x_reset 317 * will not set up the defaults correctly. 318 */ 319 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 320 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_RPE; 321 sc->sc_cfg3 = NCRCFG3_CDB | NCRCFG3_QTE; 322 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 323 324 if ((NCR_READ_REG(sc, NCR_CFG2) & ~NCRCFG2_RSVD) != 325 (NCRCFG2_SCSI2 | NCRCFG2_RPE)) { 326 sc->sc_rev = NCR_VARIANT_ESP100; 327 } else { 328 sc->sc_cfg2 = NCRCFG2_SCSI2; 329 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 330 sc->sc_cfg3 = 0; 331 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 332 sc->sc_cfg3 = (NCRCFG3_CDB | NCRCFG3_FCLK | NCRCFG3_QTE); 333 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 334 if (NCR_READ_REG(sc, NCR_CFG3) != 335 (NCRCFG3_CDB | NCRCFG3_FCLK)) { 336 sc->sc_rev = NCR_VARIANT_ESP100A; 337 } else { 338 /* NCRCFG2_FE enables > 64K transfers */ 339 sc->sc_cfg2 |= NCRCFG2_FE; 340 sc->sc_cfg3 = 0 | NCRF9XCFG3_QTE; 341 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 342 sc->sc_rev = NCR_VARIANT_ESP200; 343 } 344 } 345 346 /* 347 * XXX minsync and maxxfer _should_ be set up in MI code, 348 * XXX but it appears to have some dependency on what sort 349 * XXX of DMA we're hooked up to, etc. 350 */ 351 352 /* 353 * This is the value used to start sync negotiations 354 * Note that the NCR register "SYNCTP" is programmed 355 * in "clocks per byte", and has a minimum value of 4. 356 * The SCSI period used in negotiation is one-fourth 357 * of the time (in nanoseconds) needed to transfer one byte. 358 * Since the chip's clock is given in MHz, we have the following 359 * formula: 4 * period = (1000 / freq) * 4 360 */ 361 sc->sc_minsync = 1000 / sc->sc_freq; 362 363 /* 364 * Alas, we must now modify the value a bit, because it's 365 * only valid when can switch on FASTCLK and FASTSCSI bits 366 * in config register 3... 367 */ 368 switch (sc->sc_rev) { 369 case NCR_VARIANT_ESP100: 370 sc->sc_maxxfer = 64 * 1024; 371 sc->sc_minsync = 0; /* No synch on old chip? */ 372 break; 373 374 case NCR_VARIANT_ESP100A: 375 sc->sc_maxxfer = 64 * 1024; 376 /* Min clocks/byte is 5 */ 377 sc->sc_minsync = ncr53c9x_cpb2stp(sc, 5); 378 break; 379 380 case NCR_VARIANT_ESP200: 381 sc->sc_maxxfer = 16 * 1024 * 1024; 382 /* XXX - do actually set FAST* bits */ 383 break; 384 } 385 386 /* Establish interrupt channel */ 387 icookie = bus_intr_establish(esc->sc_bustag, esc->sc_pri, IPL_BIO, 0, 388 ncr53c9x_intr, sc); 389 390 /* register interrupt stats */ 391 evcnt_attach_dynamic(&sc->sc_intrcnt, EVCNT_TYPE_INTR, NULL, 392 sc->sc_dev.dv_xname, "intr"); 393 394 /* Turn on target selection using the `dma' method */ 395 ncr53c9x_dmaselect = 1; 396 397 /* Do the common parts of attachment. */ 398 sc->sc_adapter.adapt_minphys = minphys; 399 sc->sc_adapter.adapt_request = ncr53c9x_scsipi_request; 400 ncr53c9x_attach(sc); 401 402 } 403 404 /* 405 * Glue functions. 406 */ 407 408 u_char 409 esp_read_reg(sc, reg) 410 struct ncr53c9x_softc *sc; 411 int reg; 412 { 413 struct esp_softc *esc = (struct esp_softc *)sc; 414 415 return (bus_space_read_1(esc->sc_bustag, esc->sc_reg, reg * 4)); 416 } 417 418 void 419 esp_write_reg(sc, reg, v) 420 struct ncr53c9x_softc *sc; 421 int reg; 422 u_char v; 423 { 424 struct esp_softc *esc = (struct esp_softc *)sc; 425 426 bus_space_write_1(esc->sc_bustag, esc->sc_reg, reg * 4, v); 427 } 428 429 u_char 430 esp_rdreg1(sc, reg) 431 struct ncr53c9x_softc *sc; 432 int reg; 433 { 434 struct esp_softc *esc = (struct esp_softc *)sc; 435 436 return (bus_space_read_1(esc->sc_bustag, esc->sc_reg, reg)); 437 } 438 439 void 440 esp_wrreg1(sc, reg, v) 441 struct ncr53c9x_softc *sc; 442 int reg; 443 u_char v; 444 { 445 struct esp_softc *esc = (struct esp_softc *)sc; 446 447 bus_space_write_1(esc->sc_bustag, esc->sc_reg, reg, v); 448 } 449 450 int 451 esp_dma_isintr(sc) 452 struct ncr53c9x_softc *sc; 453 { 454 struct esp_softc *esc = (struct esp_softc *)sc; 455 456 return (DMA_ISINTR(esc->sc_dma)); 457 } 458 459 void 460 esp_dma_reset(sc) 461 struct ncr53c9x_softc *sc; 462 { 463 struct esp_softc *esc = (struct esp_softc *)sc; 464 465 DMA_RESET(esc->sc_dma); 466 } 467 468 int 469 esp_dma_intr(sc) 470 struct ncr53c9x_softc *sc; 471 { 472 struct esp_softc *esc = (struct esp_softc *)sc; 473 474 return (DMA_INTR(esc->sc_dma)); 475 } 476 477 int 478 esp_dma_setup(sc, addr, len, datain, dmasize) 479 struct ncr53c9x_softc *sc; 480 caddr_t *addr; 481 size_t *len; 482 int datain; 483 size_t *dmasize; 484 { 485 struct esp_softc *esc = (struct esp_softc *)sc; 486 487 return (DMA_SETUP(esc->sc_dma, addr, len, datain, dmasize)); 488 } 489 490 void 491 esp_dma_go(sc) 492 struct ncr53c9x_softc *sc; 493 { 494 struct esp_softc *esc = (struct esp_softc *)sc; 495 496 DMA_GO(esc->sc_dma); 497 } 498 499 void 500 esp_dma_stop(sc) 501 struct ncr53c9x_softc *sc; 502 { 503 struct esp_softc *esc = (struct esp_softc *)sc; 504 u_int32_t csr; 505 506 csr = L64854_GCSR(esc->sc_dma); 507 csr &= ~D_EN_DMA; 508 L64854_SCSR(esc->sc_dma, csr); 509 } 510 511 int 512 esp_dma_isactive(sc) 513 struct ncr53c9x_softc *sc; 514 { 515 struct esp_softc *esc = (struct esp_softc *)sc; 516 517 return (DMA_ISACTIVE(esc->sc_dma)); 518 } 519 520 #include "opt_ddb.h" 521 #ifdef DDB 522 #include <machine/db_machdep.h> 523 #include <ddb/db_output.h> 524 525 void db_esp __P((db_expr_t, int, db_expr_t, char*)); 526 527 void 528 db_esp(addr, have_addr, count, modif) 529 db_expr_t addr; 530 int have_addr; 531 db_expr_t count; 532 char *modif; 533 { 534 struct ncr53c9x_softc *sc; 535 struct ncr53c9x_ecb *ecb; 536 struct ncr53c9x_linfo *li; 537 int u, t, i; 538 539 for (u=0; u<10; u++) { 540 sc = (struct ncr53c9x_softc *) 541 getdevunit("esp", u); 542 if (!sc) continue; 543 544 db_printf("esp%d: nexus %p phase %x prev %x dp %p dleft %lx ify %x\n", 545 u, sc->sc_nexus, sc->sc_phase, sc->sc_prevphase, 546 sc->sc_dp, sc->sc_dleft, sc->sc_msgify); 547 db_printf("\tmsgout %x msgpriq %x msgin %x:%x:%x:%x:%x\n", 548 sc->sc_msgout, sc->sc_msgpriq, sc->sc_imess[0], 549 sc->sc_imess[1], sc->sc_imess[2], sc->sc_imess[3], 550 sc->sc_imess[0]); 551 db_printf("ready: "); 552 for (ecb = sc->ready_list.tqh_first; ecb; ecb = ecb->chain.tqe_next) { 553 db_printf("ecb %p ", ecb); 554 if (ecb == ecb->chain.tqe_next) { 555 db_printf("\nWARNING: tailq loop on ecb %p", ecb); 556 break; 557 } 558 } 559 db_printf("\n"); 560 561 for (t=0; t<NCR_NTARG; t++) { 562 LIST_FOREACH(li, &sc->sc_tinfo[t].luns, link) { 563 db_printf("t%d lun %d untagged %p busy %d used %x\n", 564 t, (int)li->lun, li->untagged, li->busy, 565 li->used); 566 for (i=0; i<256; i++) 567 if ((ecb = li->queued[i])) { 568 db_printf("ecb %p tag %x\n", ecb, i); 569 } 570 } 571 } 572 } 573 } 574 #endif 575
Indexes created Wed Oct 22 13:09:56 GMT 2025