esp_sbus.c revision 1.7
1 /* $NetBSD: esp_sbus.c,v 1.7 1999/11/21 15:01:51 pk Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum; Jason R. Thorpe of the Numerical Aerospace 9 * Simulation Facility, NASA Ames Research Center; Paul Kranenburg. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 #include <sys/types.h> 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/kernel.h> 44 #include <sys/errno.h> 45 #include <sys/device.h> 46 #include <sys/buf.h> 47 48 #include <dev/scsipi/scsi_all.h> 49 #include <dev/scsipi/scsipi_all.h> 50 #include <dev/scsipi/scsiconf.h> 51 #include <dev/scsipi/scsi_message.h> 52 53 #include <machine/bus.h> 54 #include <machine/autoconf.h> 55 #include <machine/cpu.h> 56 57 #include <dev/ic/lsi64854reg.h> 58 #include <dev/ic/lsi64854var.h> 59 60 #include <dev/ic/ncr53c9xreg.h> 61 #include <dev/ic/ncr53c9xvar.h> 62 63 #include <dev/sbus/sbusvar.h> 64 65 struct esp_softc { 66 struct ncr53c9x_softc sc_ncr53c9x; /* glue to MI code */ 67 struct sbusdev sc_sd; /* sbus device */ 68 69 bus_space_tag_t sc_bustag; 70 bus_dma_tag_t sc_dmatag; 71 72 bus_space_handle_t sc_reg; /* the registers */ 73 struct lsi64854_softc *sc_dma; /* pointer to my dma */ 74 75 int sc_pri; /* SBUS priority */ 76 }; 77 78 /* 79 * Is this esp on the bootpath? 80 * We may get two forms of the bootpath: 81 * (1) ../sbus (at) .../esp@<offset>,<slot>/sd@.. (PROM v3 style) 82 * (2) /sbus0/esp0/sd@.. (PROM v2 style) 83 */ 84 #define SAME_ESP(sc, bp, sa) \ 85 ((bp->val[0] == sa->sa_slot && bp->val[1] == sa->sa_offset) || \ 86 (bp->val[0] == -1 && bp->val[1] == sc->sc_dev.dv_unit)) 87 88 void espattach_sbus __P((struct device *, struct device *, void *)); 89 void espattach_dma __P((struct device *, struct device *, void *)); 90 int espmatch_sbus __P((struct device *, struct cfdata *, void *)); 91 92 93 /* Linkup to the rest of the kernel */ 94 struct cfattach esp_sbus_ca = { 95 sizeof(struct esp_softc), espmatch_sbus, espattach_sbus 96 }; 97 struct cfattach esp_dma_ca = { 98 sizeof(struct esp_softc), espmatch_sbus, espattach_dma 99 }; 100 101 static struct scsipi_device esp_sbus_dev = { 102 NULL, /* Use default error handler */ 103 NULL, /* have a queue, served by this */ 104 NULL, /* have no async handler */ 105 NULL, /* Use default 'done' routine */ 106 }; 107 108 /* 109 * Functions and the switch for the MI code. 110 */ 111 static u_char esp_read_reg __P((struct ncr53c9x_softc *, int)); 112 static void esp_write_reg __P((struct ncr53c9x_softc *, int, u_char)); 113 static u_char esp_rdreg1 __P((struct ncr53c9x_softc *, int)); 114 static void esp_wrreg1 __P((struct ncr53c9x_softc *, int, u_char)); 115 static int esp_dma_isintr __P((struct ncr53c9x_softc *)); 116 static void esp_dma_reset __P((struct ncr53c9x_softc *)); 117 static int esp_dma_intr __P((struct ncr53c9x_softc *)); 118 static int esp_dma_setup __P((struct ncr53c9x_softc *, caddr_t *, 119 size_t *, int, size_t *)); 120 static void esp_dma_go __P((struct ncr53c9x_softc *)); 121 static void esp_dma_stop __P((struct ncr53c9x_softc *)); 122 static int esp_dma_isactive __P((struct ncr53c9x_softc *)); 123 124 static struct ncr53c9x_glue esp_sbus_glue = { 125 esp_read_reg, 126 esp_write_reg, 127 esp_dma_isintr, 128 esp_dma_reset, 129 esp_dma_intr, 130 esp_dma_setup, 131 esp_dma_go, 132 esp_dma_stop, 133 esp_dma_isactive, 134 NULL, /* gl_clear_latched_intr */ 135 }; 136 137 static struct ncr53c9x_glue esp_sbus_glue1 = { 138 esp_rdreg1, 139 esp_wrreg1, 140 esp_dma_isintr, 141 esp_dma_reset, 142 esp_dma_intr, 143 esp_dma_setup, 144 esp_dma_go, 145 esp_dma_stop, 146 esp_dma_isactive, 147 NULL, /* gl_clear_latched_intr */ 148 }; 149 150 static void espattach __P((struct esp_softc *, struct ncr53c9x_glue *)); 151 152 int 153 espmatch_sbus(parent, cf, aux) 154 struct device *parent; 155 struct cfdata *cf; 156 void *aux; 157 { 158 int rv; 159 struct sbus_attach_args *sa = aux; 160 161 rv = (strcmp(cf->cf_driver->cd_name, sa->sa_name) == 0 || 162 strcmp("ptscII", sa->sa_name) == 0); 163 return (rv); 164 } 165 166 void 167 espattach_sbus(parent, self, aux) 168 struct device *parent, *self; 169 void *aux; 170 { 171 struct esp_softc *esc = (void *)self; 172 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 173 struct sbus_attach_args *sa = aux; 174 175 esc->sc_bustag = sa->sa_bustag; 176 esc->sc_dmatag = sa->sa_dmatag; 177 178 sc->sc_id = getpropint(sa->sa_node, "initiator-id", 7); 179 sc->sc_freq = getpropint(sa->sa_node, "clock-frequency", -1); 180 if (sc->sc_freq < 0) 181 sc->sc_freq = ((struct sbus_softc *) 182 sc->sc_dev.dv_parent)->sc_clockfreq; 183 184 /* 185 * Find the DMA by poking around the dma device structures 186 * 187 * What happens here is that if the dma driver has not been 188 * configured, then this returns a NULL pointer. Then when the 189 * dma actually gets configured, it does the opposing test, and 190 * if the sc->sc_esp field in it's softc is NULL, then tries to 191 * find the matching esp driver. 192 */ 193 esc->sc_dma = (struct lsi64854_softc *) 194 getdevunit("dma", sc->sc_dev.dv_unit); 195 196 /* 197 * and a back pointer to us, for DMA 198 */ 199 if (esc->sc_dma) 200 esc->sc_dma->sc_client = sc; 201 else { 202 printf("\n"); 203 panic("espattach: no dma found"); 204 } 205 206 /* 207 * Map my registers in, if they aren't already in virtual 208 * address space. 209 */ 210 if (sa->sa_npromvaddrs) 211 esc->sc_reg = (bus_space_handle_t)sa->sa_promvaddrs[0]; 212 else { 213 if (sbus_bus_map(sa->sa_bustag, sa->sa_slot, 214 sa->sa_offset, 215 sa->sa_size, 216 BUS_SPACE_MAP_LINEAR, 217 0, &esc->sc_reg) != 0) { 218 printf("%s @ sbus: cannot map registers\n", 219 self->dv_xname); 220 return; 221 } 222 } 223 224 if (sa->sa_nintr == 0) { 225 /* 226 * No interrupt properties: we quit; this might 227 * happen on e.g. a Sparc X terminal. 228 */ 229 printf("\n%s: no interrupt property\n", self->dv_xname); 230 return; 231 } 232 233 esc->sc_pri = sa->sa_pri; 234 235 /* add me to the sbus structures */ 236 esc->sc_sd.sd_reset = (void *) ncr53c9x_reset; 237 sbus_establish(&esc->sc_sd, &sc->sc_dev); 238 239 if (sa->sa_bp != NULL && strcmp("esp", sa->sa_bp->name) == 0 && 240 SAME_ESP(sc, sa->sa_bp, sa)) 241 bootpath_store(1, sa->sa_bp + 1); 242 243 if (strcmp("ptscII", sa->sa_name) == 0) { 244 espattach(esc, &esp_sbus_glue1); 245 } else { 246 espattach(esc, &esp_sbus_glue); 247 } 248 } 249 250 void 251 espattach_dma(parent, self, aux) 252 struct device *parent, *self; 253 void *aux; 254 { 255 struct esp_softc *esc = (void *)self; 256 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 257 struct sbus_attach_args *sa = aux; 258 259 if (strcmp("ptscII", sa->sa_name) == 0) { 260 return; 261 } 262 263 esc->sc_bustag = sa->sa_bustag; 264 esc->sc_dmatag = sa->sa_dmatag; 265 266 sc->sc_id = getpropint(sa->sa_node, "initiator-id", 7); 267 sc->sc_freq = getpropint(sa->sa_node, "clock-frequency", -1); 268 269 esc->sc_dma = (struct lsi64854_softc *)parent; 270 esc->sc_dma->sc_client = sc; 271 272 /* 273 * Map my registers in, if they aren't already in virtual 274 * address space. 275 */ 276 if (sa->sa_npromvaddrs) 277 esc->sc_reg = (bus_space_handle_t)sa->sa_promvaddrs[0]; 278 else { 279 if (bus_space_map2(sa->sa_bustag, 280 sa->sa_slot, 281 sa->sa_offset, 282 sa->sa_size, 283 BUS_SPACE_MAP_LINEAR, 284 0, &esc->sc_reg) != 0) { 285 printf("%s @ dma: cannot map registers\n", 286 self->dv_xname); 287 return; 288 } 289 } 290 291 if (sa->sa_nintr == 0) { 292 /* 293 * No interrupt properties: we quit; this might 294 * happen on e.g. a Sparc X terminal. 295 */ 296 printf("\n%s: no interrupt property\n", self->dv_xname); 297 return; 298 } 299 300 esc->sc_pri = sa->sa_pri; 301 302 /* Assume SBus is grandparent */ 303 esc->sc_sd.sd_reset = (void *) ncr53c9x_reset; 304 sbus_establish(&esc->sc_sd, parent); 305 306 if (sa->sa_bp != NULL && strcmp("esp", sa->sa_bp->name) == 0 && 307 SAME_ESP(sc, sa->sa_bp, sa)) 308 bootpath_store(1, sa->sa_bp + 1); 309 310 espattach(esc, &esp_sbus_glue); 311 } 312 313 314 /* 315 * Attach this instance, and then all the sub-devices 316 */ 317 void 318 espattach(esc, gluep) 319 struct esp_softc *esc; 320 struct ncr53c9x_glue *gluep; 321 { 322 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 323 void *icookie; 324 325 /* 326 * Set up glue for MI code early; we use some of it here. 327 */ 328 sc->sc_glue = gluep; 329 330 /* gimme Mhz */ 331 sc->sc_freq /= 1000000; 332 333 /* 334 * XXX More of this should be in ncr53c9x_attach(), but 335 * XXX should we really poke around the chip that much in 336 * XXX the MI code? Think about this more... 337 */ 338 339 /* 340 * It is necessary to try to load the 2nd config register here, 341 * to find out what rev the esp chip is, else the ncr53c9x_reset 342 * will not set up the defaults correctly. 343 */ 344 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 345 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_RPE; 346 sc->sc_cfg3 = NCRCFG3_CDB; 347 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 348 349 if ((NCR_READ_REG(sc, NCR_CFG2) & ~NCRCFG2_RSVD) != 350 (NCRCFG2_SCSI2 | NCRCFG2_RPE)) { 351 sc->sc_rev = NCR_VARIANT_ESP100; 352 } else { 353 sc->sc_cfg2 = NCRCFG2_SCSI2; 354 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 355 sc->sc_cfg3 = 0; 356 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 357 sc->sc_cfg3 = (NCRCFG3_CDB | NCRCFG3_FCLK); 358 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 359 if (NCR_READ_REG(sc, NCR_CFG3) != 360 (NCRCFG3_CDB | NCRCFG3_FCLK)) { 361 sc->sc_rev = NCR_VARIANT_ESP100A; 362 } else { 363 /* NCRCFG2_FE enables > 64K transfers */ 364 sc->sc_cfg2 |= NCRCFG2_FE; 365 sc->sc_cfg3 = 0; 366 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 367 sc->sc_rev = NCR_VARIANT_ESP200; 368 } 369 } 370 371 /* 372 * XXX minsync and maxxfer _should_ be set up in MI code, 373 * XXX but it appears to have some dependency on what sort 374 * XXX of DMA we're hooked up to, etc. 375 */ 376 377 /* 378 * This is the value used to start sync negotiations 379 * Note that the NCR register "SYNCTP" is programmed 380 * in "clocks per byte", and has a minimum value of 4. 381 * The SCSI period used in negotiation is one-fourth 382 * of the time (in nanoseconds) needed to transfer one byte. 383 * Since the chip's clock is given in MHz, we have the following 384 * formula: 4 * period = (1000 / freq) * 4 385 */ 386 sc->sc_minsync = 1000 / sc->sc_freq; 387 388 /* 389 * Alas, we must now modify the value a bit, because it's 390 * only valid when can switch on FASTCLK and FASTSCSI bits 391 * in config register 3... 392 */ 393 switch (sc->sc_rev) { 394 case NCR_VARIANT_ESP100: 395 sc->sc_maxxfer = 64 * 1024; 396 sc->sc_minsync = 0; /* No synch on old chip? */ 397 break; 398 399 case NCR_VARIANT_ESP100A: 400 sc->sc_maxxfer = 64 * 1024; 401 /* Min clocks/byte is 5 */ 402 sc->sc_minsync = ncr53c9x_cpb2stp(sc, 5); 403 break; 404 405 case NCR_VARIANT_ESP200: 406 sc->sc_maxxfer = 16 * 1024 * 1024; 407 /* XXX - do actually set FAST* bits */ 408 break; 409 } 410 411 /* Establish interrupt channel */ 412 icookie = bus_intr_establish(esc->sc_bustag, 413 esc->sc_pri, 0, 414 (int(*)__P((void*)))ncr53c9x_intr, sc); 415 416 /* register interrupt stats */ 417 evcnt_attach(&sc->sc_dev, "intr", &sc->sc_intrcnt); 418 419 /* Do the common parts of attachment. */ 420 sc->sc_adapter.scsipi_cmd = ncr53c9x_scsi_cmd; 421 sc->sc_adapter.scsipi_minphys = minphys; 422 ncr53c9x_attach(sc, &esp_sbus_dev); 423 424 /* Turn on target selection using the `dma' method */ 425 ncr53c9x_dmaselect = 1; 426 427 bootpath_store(1, NULL); 428 } 429 430 /* 431 * Glue functions. 432 */ 433 434 u_char 435 esp_read_reg(sc, reg) 436 struct ncr53c9x_softc *sc; 437 int reg; 438 { 439 struct esp_softc *esc = (struct esp_softc *)sc; 440 441 return (bus_space_read_1(esc->sc_bustag, esc->sc_reg, reg * 4)); 442 } 443 444 void 445 esp_write_reg(sc, reg, v) 446 struct ncr53c9x_softc *sc; 447 int reg; 448 u_char v; 449 { 450 struct esp_softc *esc = (struct esp_softc *)sc; 451 452 bus_space_write_1(esc->sc_bustag, esc->sc_reg, reg * 4, v); 453 } 454 455 u_char 456 esp_rdreg1(sc, reg) 457 struct ncr53c9x_softc *sc; 458 int reg; 459 { 460 struct esp_softc *esc = (struct esp_softc *)sc; 461 462 return (bus_space_read_1(esc->sc_bustag, esc->sc_reg, reg)); 463 } 464 465 void 466 esp_wrreg1(sc, reg, v) 467 struct ncr53c9x_softc *sc; 468 int reg; 469 u_char v; 470 { 471 struct esp_softc *esc = (struct esp_softc *)sc; 472 473 bus_space_write_1(esc->sc_bustag, esc->sc_reg, reg, v); 474 } 475 476 int 477 esp_dma_isintr(sc) 478 struct ncr53c9x_softc *sc; 479 { 480 struct esp_softc *esc = (struct esp_softc *)sc; 481 482 return (DMA_ISINTR(esc->sc_dma)); 483 } 484 485 void 486 esp_dma_reset(sc) 487 struct ncr53c9x_softc *sc; 488 { 489 struct esp_softc *esc = (struct esp_softc *)sc; 490 491 DMA_RESET(esc->sc_dma); 492 } 493 494 int 495 esp_dma_intr(sc) 496 struct ncr53c9x_softc *sc; 497 { 498 struct esp_softc *esc = (struct esp_softc *)sc; 499 500 return (DMA_INTR(esc->sc_dma)); 501 } 502 503 int 504 esp_dma_setup(sc, addr, len, datain, dmasize) 505 struct ncr53c9x_softc *sc; 506 caddr_t *addr; 507 size_t *len; 508 int datain; 509 size_t *dmasize; 510 { 511 struct esp_softc *esc = (struct esp_softc *)sc; 512 513 return (DMA_SETUP(esc->sc_dma, addr, len, datain, dmasize)); 514 } 515 516 void 517 esp_dma_go(sc) 518 struct ncr53c9x_softc *sc; 519 { 520 struct esp_softc *esc = (struct esp_softc *)sc; 521 522 DMA_GO(esc->sc_dma); 523 } 524 525 void 526 esp_dma_stop(sc) 527 struct ncr53c9x_softc *sc; 528 { 529 struct esp_softc *esc = (struct esp_softc *)sc; 530 u_int32_t csr; 531 532 csr = L64854_GCSR(esc->sc_dma); 533 csr &= ~D_EN_DMA; 534 L64854_SCSR(esc->sc_dma, csr); 535 } 536 537 int 538 esp_dma_isactive(sc) 539 struct ncr53c9x_softc *sc; 540 { 541 struct esp_softc *esc = (struct esp_softc *)sc; 542 543 return (DMA_ISACTIVE(esc->sc_dma)); 544 } 545
Indexes created Mon Sep 29 21:09:56 GMT 2025