esp_sbus.c revision 1.9
1 /* $NetBSD: esp_sbus.c,v 1.9 2000/06/04 19:15:13 cgd Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum; Jason R. Thorpe of the Numerical Aerospace 9 * Simulation Facility, NASA Ames Research Center; Paul Kranenburg. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 #include <sys/types.h> 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/kernel.h> 44 #include <sys/errno.h> 45 #include <sys/device.h> 46 #include <sys/buf.h> 47 48 #include <dev/scsipi/scsi_all.h> 49 #include <dev/scsipi/scsipi_all.h> 50 #include <dev/scsipi/scsiconf.h> 51 #include <dev/scsipi/scsi_message.h> 52 53 #include <machine/bus.h> 54 #include <machine/autoconf.h> 55 #include <machine/cpu.h> 56 57 #include <dev/ic/lsi64854reg.h> 58 #include <dev/ic/lsi64854var.h> 59 60 #include <dev/ic/ncr53c9xreg.h> 61 #include <dev/ic/ncr53c9xvar.h> 62 63 #include <dev/sbus/sbusvar.h> 64 65 struct esp_softc { 66 struct ncr53c9x_softc sc_ncr53c9x; /* glue to MI code */ 67 struct sbusdev sc_sd; /* sbus device */ 68 69 bus_space_tag_t sc_bustag; 70 bus_dma_tag_t sc_dmatag; 71 72 bus_space_handle_t sc_reg; /* the registers */ 73 struct lsi64854_softc *sc_dma; /* pointer to my dma */ 74 75 int sc_pri; /* SBUS priority */ 76 }; 77 78 void espattach_sbus __P((struct device *, struct device *, void *)); 79 void espattach_dma __P((struct device *, struct device *, void *)); 80 int espmatch_sbus __P((struct device *, struct cfdata *, void *)); 81 82 83 /* Linkup to the rest of the kernel */ 84 struct cfattach esp_sbus_ca = { 85 sizeof(struct esp_softc), espmatch_sbus, espattach_sbus 86 }; 87 struct cfattach esp_dma_ca = { 88 sizeof(struct esp_softc), espmatch_sbus, espattach_dma 89 }; 90 91 static struct scsipi_device esp_sbus_dev = { 92 NULL, /* Use default error handler */ 93 NULL, /* have a queue, served by this */ 94 NULL, /* have no async handler */ 95 NULL, /* Use default 'done' routine */ 96 }; 97 98 /* 99 * Functions and the switch for the MI code. 100 */ 101 static u_char esp_read_reg __P((struct ncr53c9x_softc *, int)); 102 static void esp_write_reg __P((struct ncr53c9x_softc *, int, u_char)); 103 static u_char esp_rdreg1 __P((struct ncr53c9x_softc *, int)); 104 static void esp_wrreg1 __P((struct ncr53c9x_softc *, int, u_char)); 105 static int esp_dma_isintr __P((struct ncr53c9x_softc *)); 106 static void esp_dma_reset __P((struct ncr53c9x_softc *)); 107 static int esp_dma_intr __P((struct ncr53c9x_softc *)); 108 static int esp_dma_setup __P((struct ncr53c9x_softc *, caddr_t *, 109 size_t *, int, size_t *)); 110 static void esp_dma_go __P((struct ncr53c9x_softc *)); 111 static void esp_dma_stop __P((struct ncr53c9x_softc *)); 112 static int esp_dma_isactive __P((struct ncr53c9x_softc *)); 113 114 static struct ncr53c9x_glue esp_sbus_glue = { 115 esp_read_reg, 116 esp_write_reg, 117 esp_dma_isintr, 118 esp_dma_reset, 119 esp_dma_intr, 120 esp_dma_setup, 121 esp_dma_go, 122 esp_dma_stop, 123 esp_dma_isactive, 124 NULL, /* gl_clear_latched_intr */ 125 }; 126 127 static struct ncr53c9x_glue esp_sbus_glue1 = { 128 esp_rdreg1, 129 esp_wrreg1, 130 esp_dma_isintr, 131 esp_dma_reset, 132 esp_dma_intr, 133 esp_dma_setup, 134 esp_dma_go, 135 esp_dma_stop, 136 esp_dma_isactive, 137 NULL, /* gl_clear_latched_intr */ 138 }; 139 140 static void espattach __P((struct esp_softc *, struct ncr53c9x_glue *)); 141 142 int 143 espmatch_sbus(parent, cf, aux) 144 struct device *parent; 145 struct cfdata *cf; 146 void *aux; 147 { 148 int rv; 149 struct sbus_attach_args *sa = aux; 150 151 rv = (strcmp(cf->cf_driver->cd_name, sa->sa_name) == 0 || 152 strcmp("ptscII", sa->sa_name) == 0); 153 return (rv); 154 } 155 156 void 157 espattach_sbus(parent, self, aux) 158 struct device *parent, *self; 159 void *aux; 160 { 161 struct esp_softc *esc = (void *)self; 162 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 163 struct sbus_attach_args *sa = aux; 164 165 esc->sc_bustag = sa->sa_bustag; 166 esc->sc_dmatag = sa->sa_dmatag; 167 168 sc->sc_id = getpropint(sa->sa_node, "initiator-id", 7); 169 sc->sc_freq = getpropint(sa->sa_node, "clock-frequency", -1); 170 if (sc->sc_freq < 0) 171 sc->sc_freq = ((struct sbus_softc *) 172 sc->sc_dev.dv_parent)->sc_clockfreq; 173 174 /* 175 * Find the DMA by poking around the dma device structures 176 * 177 * What happens here is that if the dma driver has not been 178 * configured, then this returns a NULL pointer. Then when the 179 * dma actually gets configured, it does the opposing test, and 180 * if the sc->sc_esp field in it's softc is NULL, then tries to 181 * find the matching esp driver. 182 */ 183 esc->sc_dma = (struct lsi64854_softc *) 184 getdevunit("dma", sc->sc_dev.dv_unit); 185 186 /* 187 * and a back pointer to us, for DMA 188 */ 189 if (esc->sc_dma) 190 esc->sc_dma->sc_client = sc; 191 else { 192 printf("\n"); 193 panic("espattach: no dma found"); 194 } 195 196 /* 197 * Map my registers in, if they aren't already in virtual 198 * address space. 199 */ 200 if (sa->sa_npromvaddrs) 201 esc->sc_reg = (bus_space_handle_t)sa->sa_promvaddrs[0]; 202 else { 203 if (sbus_bus_map(sa->sa_bustag, sa->sa_slot, 204 sa->sa_offset, 205 sa->sa_size, 206 BUS_SPACE_MAP_LINEAR, 207 0, &esc->sc_reg) != 0) { 208 printf("%s @ sbus: cannot map registers\n", 209 self->dv_xname); 210 return; 211 } 212 } 213 214 if (sa->sa_nintr == 0) { 215 /* 216 * No interrupt properties: we quit; this might 217 * happen on e.g. a Sparc X terminal. 218 */ 219 printf("\n%s: no interrupt property\n", self->dv_xname); 220 return; 221 } 222 223 esc->sc_pri = sa->sa_pri; 224 225 /* add me to the sbus structures */ 226 esc->sc_sd.sd_reset = (void *) ncr53c9x_reset; 227 sbus_establish(&esc->sc_sd, &sc->sc_dev); 228 229 if (strcmp("ptscII", sa->sa_name) == 0) { 230 espattach(esc, &esp_sbus_glue1); 231 } else { 232 espattach(esc, &esp_sbus_glue); 233 } 234 } 235 236 void 237 espattach_dma(parent, self, aux) 238 struct device *parent, *self; 239 void *aux; 240 { 241 struct esp_softc *esc = (void *)self; 242 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 243 struct sbus_attach_args *sa = aux; 244 245 if (strcmp("ptscII", sa->sa_name) == 0) { 246 return; 247 } 248 249 esc->sc_bustag = sa->sa_bustag; 250 esc->sc_dmatag = sa->sa_dmatag; 251 252 sc->sc_id = getpropint(sa->sa_node, "initiator-id", 7); 253 sc->sc_freq = getpropint(sa->sa_node, "clock-frequency", -1); 254 255 esc->sc_dma = (struct lsi64854_softc *)parent; 256 esc->sc_dma->sc_client = sc; 257 258 /* 259 * Map my registers in, if they aren't already in virtual 260 * address space. 261 */ 262 if (sa->sa_npromvaddrs) 263 esc->sc_reg = (bus_space_handle_t)sa->sa_promvaddrs[0]; 264 else { 265 if (bus_space_map2(sa->sa_bustag, 266 sa->sa_slot, 267 sa->sa_offset, 268 sa->sa_size, 269 BUS_SPACE_MAP_LINEAR, 270 0, &esc->sc_reg) != 0) { 271 printf("%s @ dma: cannot map registers\n", 272 self->dv_xname); 273 return; 274 } 275 } 276 277 if (sa->sa_nintr == 0) { 278 /* 279 * No interrupt properties: we quit; this might 280 * happen on e.g. a Sparc X terminal. 281 */ 282 printf("\n%s: no interrupt property\n", self->dv_xname); 283 return; 284 } 285 286 esc->sc_pri = sa->sa_pri; 287 288 /* Assume SBus is grandparent */ 289 esc->sc_sd.sd_reset = (void *) ncr53c9x_reset; 290 sbus_establish(&esc->sc_sd, parent); 291 292 espattach(esc, &esp_sbus_glue); 293 } 294 295 296 /* 297 * Attach this instance, and then all the sub-devices 298 */ 299 void 300 espattach(esc, gluep) 301 struct esp_softc *esc; 302 struct ncr53c9x_glue *gluep; 303 { 304 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 305 void *icookie; 306 307 /* 308 * Set up glue for MI code early; we use some of it here. 309 */ 310 sc->sc_glue = gluep; 311 312 /* gimme Mhz */ 313 sc->sc_freq /= 1000000; 314 315 /* 316 * XXX More of this should be in ncr53c9x_attach(), but 317 * XXX should we really poke around the chip that much in 318 * XXX the MI code? Think about this more... 319 */ 320 321 /* 322 * It is necessary to try to load the 2nd config register here, 323 * to find out what rev the esp chip is, else the ncr53c9x_reset 324 * will not set up the defaults correctly. 325 */ 326 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 327 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_RPE; 328 sc->sc_cfg3 = NCRCFG3_CDB; 329 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 330 331 if ((NCR_READ_REG(sc, NCR_CFG2) & ~NCRCFG2_RSVD) != 332 (NCRCFG2_SCSI2 | NCRCFG2_RPE)) { 333 sc->sc_rev = NCR_VARIANT_ESP100; 334 } else { 335 sc->sc_cfg2 = NCRCFG2_SCSI2; 336 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 337 sc->sc_cfg3 = 0; 338 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 339 sc->sc_cfg3 = (NCRCFG3_CDB | NCRCFG3_FCLK); 340 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 341 if (NCR_READ_REG(sc, NCR_CFG3) != 342 (NCRCFG3_CDB | NCRCFG3_FCLK)) { 343 sc->sc_rev = NCR_VARIANT_ESP100A; 344 } else { 345 /* NCRCFG2_FE enables > 64K transfers */ 346 sc->sc_cfg2 |= NCRCFG2_FE; 347 sc->sc_cfg3 = 0; 348 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 349 sc->sc_rev = NCR_VARIANT_ESP200; 350 } 351 } 352 353 /* 354 * XXX minsync and maxxfer _should_ be set up in MI code, 355 * XXX but it appears to have some dependency on what sort 356 * XXX of DMA we're hooked up to, etc. 357 */ 358 359 /* 360 * This is the value used to start sync negotiations 361 * Note that the NCR register "SYNCTP" is programmed 362 * in "clocks per byte", and has a minimum value of 4. 363 * The SCSI period used in negotiation is one-fourth 364 * of the time (in nanoseconds) needed to transfer one byte. 365 * Since the chip's clock is given in MHz, we have the following 366 * formula: 4 * period = (1000 / freq) * 4 367 */ 368 sc->sc_minsync = 1000 / sc->sc_freq; 369 370 /* 371 * Alas, we must now modify the value a bit, because it's 372 * only valid when can switch on FASTCLK and FASTSCSI bits 373 * in config register 3... 374 */ 375 switch (sc->sc_rev) { 376 case NCR_VARIANT_ESP100: 377 sc->sc_maxxfer = 64 * 1024; 378 sc->sc_minsync = 0; /* No synch on old chip? */ 379 break; 380 381 case NCR_VARIANT_ESP100A: 382 sc->sc_maxxfer = 64 * 1024; 383 /* Min clocks/byte is 5 */ 384 sc->sc_minsync = ncr53c9x_cpb2stp(sc, 5); 385 break; 386 387 case NCR_VARIANT_ESP200: 388 sc->sc_maxxfer = 16 * 1024 * 1024; 389 /* XXX - do actually set FAST* bits */ 390 break; 391 } 392 393 /* Establish interrupt channel */ 394 icookie = bus_intr_establish(esc->sc_bustag, 395 esc->sc_pri, 0, 396 (int(*)__P((void*)))ncr53c9x_intr, sc); 397 398 /* register interrupt stats */ 399 evcnt_attach_dynamic(&sc->sc_intrcnt, EVCNT_TYPE_INTR, NULL, 400 sc->sc_dev.dv_xname, "intr"); 401 402 /* Do the common parts of attachment. */ 403 sc->sc_adapter.scsipi_cmd = ncr53c9x_scsi_cmd; 404 sc->sc_adapter.scsipi_minphys = minphys; 405 ncr53c9x_attach(sc, &esp_sbus_dev); 406 407 /* Turn on target selection using the `dma' method */ 408 ncr53c9x_dmaselect = 1; 409 } 410 411 /* 412 * Glue functions. 413 */ 414 415 u_char 416 esp_read_reg(sc, reg) 417 struct ncr53c9x_softc *sc; 418 int reg; 419 { 420 struct esp_softc *esc = (struct esp_softc *)sc; 421 422 return (bus_space_read_1(esc->sc_bustag, esc->sc_reg, reg * 4)); 423 } 424 425 void 426 esp_write_reg(sc, reg, v) 427 struct ncr53c9x_softc *sc; 428 int reg; 429 u_char v; 430 { 431 struct esp_softc *esc = (struct esp_softc *)sc; 432 433 bus_space_write_1(esc->sc_bustag, esc->sc_reg, reg * 4, v); 434 } 435 436 u_char 437 esp_rdreg1(sc, reg) 438 struct ncr53c9x_softc *sc; 439 int reg; 440 { 441 struct esp_softc *esc = (struct esp_softc *)sc; 442 443 return (bus_space_read_1(esc->sc_bustag, esc->sc_reg, reg)); 444 } 445 446 void 447 esp_wrreg1(sc, reg, v) 448 struct ncr53c9x_softc *sc; 449 int reg; 450 u_char v; 451 { 452 struct esp_softc *esc = (struct esp_softc *)sc; 453 454 bus_space_write_1(esc->sc_bustag, esc->sc_reg, reg, v); 455 } 456 457 int 458 esp_dma_isintr(sc) 459 struct ncr53c9x_softc *sc; 460 { 461 struct esp_softc *esc = (struct esp_softc *)sc; 462 463 return (DMA_ISINTR(esc->sc_dma)); 464 } 465 466 void 467 esp_dma_reset(sc) 468 struct ncr53c9x_softc *sc; 469 { 470 struct esp_softc *esc = (struct esp_softc *)sc; 471 472 DMA_RESET(esc->sc_dma); 473 } 474 475 int 476 esp_dma_intr(sc) 477 struct ncr53c9x_softc *sc; 478 { 479 struct esp_softc *esc = (struct esp_softc *)sc; 480 481 return (DMA_INTR(esc->sc_dma)); 482 } 483 484 int 485 esp_dma_setup(sc, addr, len, datain, dmasize) 486 struct ncr53c9x_softc *sc; 487 caddr_t *addr; 488 size_t *len; 489 int datain; 490 size_t *dmasize; 491 { 492 struct esp_softc *esc = (struct esp_softc *)sc; 493 494 return (DMA_SETUP(esc->sc_dma, addr, len, datain, dmasize)); 495 } 496 497 void 498 esp_dma_go(sc) 499 struct ncr53c9x_softc *sc; 500 { 501 struct esp_softc *esc = (struct esp_softc *)sc; 502 503 DMA_GO(esc->sc_dma); 504 } 505 506 void 507 esp_dma_stop(sc) 508 struct ncr53c9x_softc *sc; 509 { 510 struct esp_softc *esc = (struct esp_softc *)sc; 511 u_int32_t csr; 512 513 csr = L64854_GCSR(esc->sc_dma); 514 csr &= ~D_EN_DMA; 515 L64854_SCSR(esc->sc_dma, csr); 516 } 517 518 int 519 esp_dma_isactive(sc) 520 struct ncr53c9x_softc *sc; 521 { 522 struct esp_softc *esc = (struct esp_softc *)sc; 523 524 return (DMA_ISACTIVE(esc->sc_dma)); 525 } 526
Indexes created Mon Sep 29 21:09:56 GMT 2025