magma.c revision 1.48 1 1.48 plunky /* $NetBSD: magma.c,v 1.48 2008/07/02 10:16:20 plunky Exp $ */
2 1.48 plunky
3 1.48 plunky /*-
4 1.1 pk * Copyright (c) 1998 Iain Hibbert
5 1.1 pk * All rights reserved.
6 1.1 pk *
7 1.1 pk * Redistribution and use in source and binary forms, with or without
8 1.1 pk * modification, are permitted provided that the following conditions
9 1.1 pk * are met:
10 1.1 pk * 1. Redistributions of source code must retain the above copyright
11 1.1 pk * notice, this list of conditions and the following disclaimer.
12 1.1 pk * 2. Redistributions in binary form must reproduce the above copyright
13 1.1 pk * notice, this list of conditions and the following disclaimer in the
14 1.1 pk * documentation and/or other materials provided with the distribution.
15 1.1 pk *
16 1.1 pk * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 1.1 pk * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 1.1 pk * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 1.1 pk * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 1.1 pk * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21 1.1 pk * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22 1.1 pk * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23 1.1 pk * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 1.1 pk * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25 1.1 pk * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 1.2 pk */
27 1.1 pk
28 1.1 pk /*
29 1.1 pk * Driver for Magma SBus Serial/Parallel cards using the Cirrus Logic
30 1.1 pk * CD1400 & CD1190 chips
31 1.1 pk */
32 1.12 lukem
33 1.12 lukem #include <sys/cdefs.h>
34 1.48 plunky __KERNEL_RCSID(0, "$NetBSD: magma.c,v 1.48 2008/07/02 10:16:20 plunky Exp $");
35 1.12 lukem
36 1.12 lukem #if 0
37 1.12 lukem #define MAGMA_DEBUG
38 1.12 lukem #endif
39 1.1 pk
40 1.1 pk #include "magma.h"
41 1.1 pk #if NMAGMA > 0
42 1.1 pk
43 1.1 pk #include <sys/param.h>
44 1.1 pk #include <sys/systm.h>
45 1.1 pk #include <sys/proc.h>
46 1.1 pk #include <sys/device.h>
47 1.1 pk #include <sys/file.h>
48 1.1 pk #include <sys/ioctl.h>
49 1.1 pk #include <sys/malloc.h>
50 1.1 pk #include <sys/tty.h>
51 1.1 pk #include <sys/time.h>
52 1.1 pk #include <sys/kernel.h>
53 1.1 pk #include <sys/syslog.h>
54 1.1 pk #include <sys/conf.h>
55 1.1 pk #include <sys/errno.h>
56 1.34 yamt #include <sys/kauth.h>
57 1.43 ad #include <sys/intr.h>
58 1.1 pk
59 1.44 ad #include <sys/bus.h>
60 1.4 pk #include <machine/autoconf.h>
61 1.8 pk
62 1.4 pk #include <dev/sbus/sbusvar.h>
63 1.1 pk
64 1.1 pk #include <dev/ic/cd1400reg.h>
65 1.1 pk #include <dev/ic/cd1190reg.h>
66 1.1 pk
67 1.4 pk #include <dev/sbus/mbppio.h>
68 1.4 pk #include <dev/sbus/magmareg.h>
69 1.1 pk
70 1.1 pk /* supported cards
71 1.1 pk *
72 1.1 pk * The table below lists the cards that this driver is likely to
73 1.1 pk * be able to support.
74 1.1 pk *
75 1.1 pk * Cards with parallel ports: except for the LC2+1Sp, they all use
76 1.1 pk * the CD1190 chip which I know nothing about. I've tried to leave
77 1.1 pk * hooks for it so it shouldn't be too hard to add support later.
78 1.1 pk * (I think somebody is working on this separately)
79 1.1 pk *
80 1.1 pk * Thanks to Bruce at Magma for telling me the hardware offsets.
81 1.1 pk */
82 1.1 pk static struct magma_board_info supported_cards[] = {
83 1.1 pk {
84 1.13 pk "MAGMA_Sp", "MAGMA,4_Sp", "Magma 4 Sp", 4, 0,
85 1.1 pk 1, 0xa000, 0xc000, 0xe000, { 0x8000, 0, 0, 0 },
86 1.1 pk 0, { 0, 0 }
87 1.1 pk },
88 1.1 pk {
89 1.13 pk "MAGMA_Sp", "MAGMA,8_Sp", "Magma 8 Sp", 8, 0,
90 1.1 pk 2, 0xa000, 0xc000, 0xe000, { 0x4000, 0x6000, 0, 0 },
91 1.1 pk 0, { 0, 0 }
92 1.1 pk },
93 1.1 pk {
94 1.13 pk "MAGMA_Sp", "MAGMA,_8HS_Sp", "Magma Fast 8 Sp", 8, 0,
95 1.1 pk 2, 0x2000, 0x4000, 0x6000, { 0x8000, 0xa000, 0, 0 },
96 1.1 pk 0, { 0, 0 }
97 1.1 pk },
98 1.1 pk {
99 1.13 pk "MAGMA_Sp", "MAGMA,_8SP_422", "Magma 8 Sp - 422", 8, 0,
100 1.1 pk 2, 0x2000, 0x4000, 0x6000, { 0x8000, 0xa000, 0, 0 },
101 1.1 pk 0, { 0, 0 }
102 1.1 pk },
103 1.1 pk {
104 1.13 pk "MAGMA_Sp", "MAGMA,12_Sp", "Magma 12 Sp", 12, 0,
105 1.1 pk 3, 0xa000, 0xc000, 0xe000, { 0x2000, 0x4000, 0x6000, 0 },
106 1.1 pk 0, { 0, 0 }
107 1.1 pk },
108 1.1 pk {
109 1.13 pk "MAGMA_Sp", "MAGMA,16_Sp", "Magma 16 Sp", 16, 0,
110 1.1 pk 4, 0xd000, 0xe000, 0xf000, { 0x8000, 0x9000, 0xa000, 0xb000 },
111 1.1 pk 0, { 0, 0 }
112 1.1 pk },
113 1.1 pk {
114 1.13 pk "MAGMA_Sp", "MAGMA,16_Sp_2", "Magma 16 Sp", 16, 0,
115 1.1 pk 4, 0x2000, 0x4000, 0x6000, { 0x8000, 0xa000, 0xc000, 0xe000 },
116 1.1 pk 0, { 0, 0 }
117 1.1 pk },
118 1.1 pk {
119 1.13 pk "MAGMA_Sp", "MAGMA,16HS_Sp", "Magma Fast 16 Sp", 16, 0,
120 1.1 pk 4, 0x2000, 0x4000, 0x6000, { 0x8000, 0xa000, 0xc000, 0xe000 },
121 1.1 pk 0, { 0, 0 }
122 1.1 pk },
123 1.1 pk {
124 1.13 pk "MAGMA_Sp", "MAGMA,21_Sp", "Magma LC 2+1 Sp", 2, 1,
125 1.1 pk 1, 0xa000, 0xc000, 0xe000, { 0x8000, 0, 0, 0 },
126 1.1 pk 0, { 0, 0 }
127 1.1 pk },
128 1.1 pk {
129 1.13 pk "MAGMA_Sp", "MAGMA,21HS_Sp", "Magma 2+1 Sp", 2, 1,
130 1.1 pk 1, 0xa000, 0xc000, 0xe000, { 0x4000, 0, 0, 0 },
131 1.1 pk 1, { 0x6000, 0 }
132 1.1 pk },
133 1.1 pk {
134 1.13 pk "MAGMA_Sp", "MAGMA,41_Sp", "Magma 4+1 Sp", 4, 1,
135 1.1 pk 1, 0xa000, 0xc000, 0xe000, { 0x4000, 0, 0, 0 },
136 1.1 pk 1, { 0x6000, 0 }
137 1.1 pk },
138 1.1 pk {
139 1.13 pk "MAGMA_Sp", "MAGMA,82_Sp", "Magma 8+2 Sp", 8, 2,
140 1.1 pk 2, 0xd000, 0xe000, 0xf000, { 0x8000, 0x9000, 0, 0 },
141 1.1 pk 2, { 0xa000, 0xb000 }
142 1.1 pk },
143 1.1 pk {
144 1.13 pk "MAGMA_Sp", "MAGMA,P1_Sp", "Magma P1 Sp", 0, 1,
145 1.1 pk 0, 0, 0, 0, { 0, 0, 0, 0 },
146 1.1 pk 1, { 0x8000, 0 }
147 1.1 pk },
148 1.1 pk {
149 1.13 pk "MAGMA_Sp", "MAGMA,P2_Sp", "Magma P2 Sp", 0, 2,
150 1.1 pk 0, 0, 0, 0, { 0, 0, 0, 0 },
151 1.1 pk 2, { 0x4000, 0x8000 }
152 1.1 pk },
153 1.1 pk {
154 1.13 pk "MAGMA 2+1HS Sp", "", "Magma 2+1HS Sp", 2, 0,
155 1.13 pk 1, 0xa000, 0xc000, 0xe000, { 0x4000, 0, 0, 0 },
156 1.13 pk 1, { 0x8000, 0 }
157 1.13 pk },
158 1.13 pk {
159 1.13 pk NULL, NULL, NULL, 0, 0,
160 1.1 pk 0, 0, 0, 0, { 0, 0, 0, 0 },
161 1.1 pk 0, { 0, 0 }
162 1.1 pk }
163 1.1 pk };
164 1.1 pk
165 1.1 pk /************************************************************************
166 1.1 pk *
167 1.1 pk * Autoconfig Stuff
168 1.1 pk */
169 1.1 pk
170 1.19 thorpej CFATTACH_DECL(magma, sizeof(struct magma_softc),
171 1.20 thorpej magma_match, magma_attach, NULL, NULL);
172 1.1 pk
173 1.19 thorpej CFATTACH_DECL(mtty, sizeof(struct mtty_softc),
174 1.20 thorpej mtty_match, mtty_attach, NULL, NULL);
175 1.1 pk
176 1.19 thorpej CFATTACH_DECL(mbpp, sizeof(struct mbpp_softc),
177 1.20 thorpej mbpp_match, mbpp_attach, NULL, NULL);
178 1.1 pk
179 1.1 pk extern struct cfdriver mtty_cd;
180 1.1 pk extern struct cfdriver mbpp_cd;
181 1.1 pk
182 1.17 gehenna dev_type_open(mttyopen);
183 1.17 gehenna dev_type_close(mttyclose);
184 1.17 gehenna dev_type_read(mttyread);
185 1.17 gehenna dev_type_write(mttywrite);
186 1.17 gehenna dev_type_ioctl(mttyioctl);
187 1.17 gehenna dev_type_stop(mttystop);
188 1.17 gehenna dev_type_tty(mttytty);
189 1.17 gehenna dev_type_poll(mttypoll);
190 1.17 gehenna
191 1.17 gehenna const struct cdevsw mtty_cdevsw = {
192 1.17 gehenna mttyopen, mttyclose, mttyread, mttywrite, mttyioctl,
193 1.21 jdolecek mttystop, mttytty, mttypoll, nommap, ttykqfilter, D_TTY
194 1.17 gehenna };
195 1.17 gehenna
196 1.17 gehenna dev_type_open(mbppopen);
197 1.17 gehenna dev_type_close(mbppclose);
198 1.17 gehenna dev_type_read(mbpp_rw);
199 1.17 gehenna dev_type_ioctl(mbppioctl);
200 1.17 gehenna
201 1.17 gehenna const struct cdevsw mbpp_cdevsw = {
202 1.17 gehenna mbppopen, mbppclose, mbpp_rw, mbpp_rw, mbppioctl,
203 1.42 macallan nostop, notty, nopoll, nommap, nokqfilter, D_OTHER
204 1.17 gehenna };
205 1.17 gehenna
206 1.1 pk /************************************************************************
207 1.1 pk *
208 1.1 pk * CD1400 Routines
209 1.1 pk *
210 1.1 pk * cd1400_compute_baud calculate COR/BPR register values
211 1.1 pk * cd1400_write_ccr write a value to CD1400 ccr
212 1.1 pk * cd1400_read_reg read from a CD1400 register
213 1.1 pk * cd1400_write_reg write to a CD1400 register
214 1.1 pk * cd1400_enable_transmitter enable transmitting on CD1400 channel
215 1.1 pk */
216 1.1 pk
217 1.1 pk /*
218 1.1 pk * compute the bpr/cor pair for any baud rate
219 1.1 pk * returns 0 for success, 1 for failure
220 1.1 pk */
221 1.1 pk int
222 1.1 pk cd1400_compute_baud(speed, clock, cor, bpr)
223 1.1 pk speed_t speed;
224 1.1 pk int clock;
225 1.1 pk int *cor, *bpr;
226 1.1 pk {
227 1.1 pk int c, co, br;
228 1.1 pk
229 1.1 pk if( speed < 50 || speed > 150000 )
230 1.1 pk return(1);
231 1.1 pk
232 1.1 pk for( c = 0, co = 8 ; co <= 2048 ; co <<= 2, c++ ) {
233 1.1 pk br = ((clock * 1000000) + (co * speed) / 2) / (co * speed);
234 1.1 pk if( br < 0x100 ) {
235 1.1 pk *bpr = br;
236 1.1 pk *cor = c;
237 1.1 pk return(0);
238 1.1 pk }
239 1.1 pk }
240 1.1 pk
241 1.1 pk return(1);
242 1.1 pk }
243 1.1 pk
244 1.1 pk /*
245 1.1 pk * Write a CD1400 channel command, should have a timeout?
246 1.1 pk */
247 1.32 perry inline void
248 1.1 pk cd1400_write_ccr(cd, cmd)
249 1.1 pk struct cd1400 *cd;
250 1.1 pk u_char cmd;
251 1.1 pk {
252 1.1 pk while( cd1400_read_reg(cd, CD1400_CCR) )
253 1.1 pk ;
254 1.1 pk
255 1.1 pk cd1400_write_reg(cd, CD1400_CCR, cmd);
256 1.1 pk }
257 1.1 pk
258 1.1 pk /*
259 1.1 pk * read a value from a cd1400 register
260 1.1 pk */
261 1.32 perry inline u_char
262 1.1 pk cd1400_read_reg(cd, reg)
263 1.1 pk struct cd1400 *cd;
264 1.1 pk int reg;
265 1.1 pk {
266 1.1 pk return(cd->cd_reg[reg]);
267 1.1 pk }
268 1.1 pk
269 1.1 pk /*
270 1.1 pk * write a value to a cd1400 register
271 1.1 pk */
272 1.32 perry inline void
273 1.1 pk cd1400_write_reg(cd, reg, value)
274 1.1 pk struct cd1400 *cd;
275 1.1 pk int reg;
276 1.1 pk u_char value;
277 1.1 pk {
278 1.1 pk cd->cd_reg[reg] = value;
279 1.1 pk }
280 1.1 pk
281 1.1 pk /*
282 1.1 pk * enable transmit service requests for cd1400 channel
283 1.1 pk */
284 1.1 pk void
285 1.1 pk cd1400_enable_transmitter(cd, channel)
286 1.1 pk struct cd1400 *cd;
287 1.1 pk int channel;
288 1.1 pk {
289 1.1 pk int s, srer;
290 1.1 pk
291 1.1 pk s = spltty();
292 1.1 pk cd1400_write_reg(cd, CD1400_CAR, channel);
293 1.1 pk srer = cd1400_read_reg(cd, CD1400_SRER);
294 1.1 pk SET(srer, CD1400_SRER_TXRDY);
295 1.1 pk cd1400_write_reg(cd, CD1400_SRER, srer);
296 1.1 pk splx(s);
297 1.1 pk }
298 1.1 pk
299 1.1 pk /************************************************************************
300 1.1 pk *
301 1.1 pk * CD1190 Routines
302 1.1 pk */
303 1.1 pk
304 1.1 pk /* well, there are none yet */
305 1.1 pk
306 1.1 pk /************************************************************************
307 1.1 pk *
308 1.1 pk * Magma Routines
309 1.1 pk *
310 1.1 pk * magma_match reports if we have a magma board available
311 1.1 pk * magma_attach attaches magma boards to the sbus
312 1.1 pk * magma_hard hardware level interrupt routine
313 1.1 pk * magma_soft software level interrupt routine
314 1.1 pk */
315 1.1 pk
316 1.1 pk int
317 1.1 pk magma_match(parent, cf, aux)
318 1.1 pk struct device *parent;
319 1.1 pk struct cfdata *cf;
320 1.1 pk void *aux;
321 1.1 pk {
322 1.1 pk struct sbus_attach_args *sa = aux;
323 1.13 pk struct magma_board_info *card;
324 1.1 pk
325 1.13 pk /* See if we support this device */
326 1.13 pk for (card = supported_cards; ; card++) {
327 1.13 pk if (card->mb_sbusname == NULL)
328 1.13 pk /* End of table: no match */
329 1.13 pk return (0);
330 1.13 pk if (strcmp(sa->sa_name, card->mb_sbusname) == 0)
331 1.13 pk break;
332 1.13 pk }
333 1.1 pk
334 1.3 pk dprintf(("magma: matched `%s'\n", sa->sa_name));
335 1.3 pk dprintf(("magma: magma_prom `%s'\n",
336 1.28 pk prom_getpropstring(sa->sa_node, "magma_prom")));
337 1.3 pk dprintf(("magma: intlevels `%s'\n",
338 1.28 pk prom_getpropstring(sa->sa_node, "intlevels")));
339 1.3 pk dprintf(("magma: chiprev `%s'\n",
340 1.28 pk prom_getpropstring(sa->sa_node, "chiprev")));
341 1.3 pk dprintf(("magma: clock `%s'\n",
342 1.28 pk prom_getpropstring(sa->sa_node, "clock")));
343 1.1 pk
344 1.1 pk return (1);
345 1.1 pk }
346 1.1 pk
347 1.1 pk void
348 1.1 pk magma_attach(parent, self, aux)
349 1.1 pk struct device *parent;
350 1.1 pk struct device *self;
351 1.1 pk void *aux;
352 1.1 pk {
353 1.1 pk struct sbus_attach_args *sa = aux;
354 1.47 drochner struct magma_softc *sc = device_private(self);
355 1.13 pk struct magma_board_info *card;
356 1.1 pk bus_space_handle_t bh;
357 1.13 pk char *magma_prom, *clockstr;
358 1.13 pk int cd_clock;
359 1.1 pk int node, chip;
360 1.1 pk
361 1.1 pk node = sa->sa_node;
362 1.13 pk
363 1.13 pk /*
364 1.13 pk * Find the card model.
365 1.13 pk * Older models all have sbus node name `MAGMA_Sp' (see
366 1.13 pk * `supported_cards[]' above), and must be distinguished
367 1.13 pk * by the `magma_prom' property.
368 1.13 pk */
369 1.28 pk magma_prom = prom_getpropstring(node, "magma_prom");
370 1.1 pk
371 1.13 pk for (card = supported_cards; card->mb_name != NULL; card++) {
372 1.13 pk if (strcmp(sa->sa_name, card->mb_sbusname) != 0)
373 1.13 pk /* Sbus node name doesn't match */
374 1.13 pk continue;
375 1.13 pk if (strcmp(magma_prom, card->mb_name) == 0)
376 1.13 pk /* Model name match */
377 1.13 pk break;
378 1.13 pk }
379 1.1 pk
380 1.1 pk if( card->mb_name == NULL ) {
381 1.13 pk printf(": %s (unsupported)\n", magma_prom);
382 1.1 pk return;
383 1.1 pk }
384 1.1 pk
385 1.13 pk dprintf((" addr %p", sc));
386 1.22 pk printf(": %s\n", card->mb_realname);
387 1.1 pk
388 1.1 pk sc->ms_board = card;
389 1.1 pk sc->ms_ncd1400 = card->mb_ncd1400;
390 1.1 pk sc->ms_ncd1190 = card->mb_ncd1190;
391 1.1 pk
392 1.1 pk if (sbus_bus_map(sa->sa_bustag,
393 1.14 pk sa->sa_slot, sa->sa_offset, sa->sa_size,
394 1.14 pk BUS_SPACE_MAP_LINEAR, &bh) != 0) {
395 1.46 cegger aprint_error("%s @ sbus: cannot map registers\n",
396 1.46 cegger device_xname(self));
397 1.1 pk return;
398 1.1 pk }
399 1.1 pk
400 1.1 pk /* the SVCACK* lines are daisychained */
401 1.40 mrg sc->ms_svcackr = (char *)bus_space_vaddr(sa->sa_bustag, bh)
402 1.16 eeh + card->mb_svcackr;
403 1.40 mrg sc->ms_svcackt = (char *)bus_space_vaddr(sa->sa_bustag, bh)
404 1.16 eeh + card->mb_svcackt;
405 1.40 mrg sc->ms_svcackm = (char *)bus_space_vaddr(sa->sa_bustag, bh)
406 1.16 eeh + card->mb_svcackm;
407 1.1 pk
408 1.13 pk /*
409 1.13 pk * Find the clock speed; it's the same for all CD1400 chips
410 1.13 pk * on the board.
411 1.13 pk */
412 1.28 pk clockstr = prom_getpropstring(node, "clock");
413 1.13 pk if (*clockstr == '\0')
414 1.13 pk /* Default to 25MHz */
415 1.13 pk cd_clock = 25;
416 1.13 pk else {
417 1.13 pk cd_clock = 0;
418 1.13 pk while (*clockstr != '\0')
419 1.13 pk cd_clock = (cd_clock * 10) + (*clockstr++ - '0');
420 1.13 pk }
421 1.13 pk
422 1.1 pk /* init the cd1400 chips */
423 1.1 pk for( chip = 0 ; chip < card->mb_ncd1400 ; chip++ ) {
424 1.1 pk struct cd1400 *cd = &sc->ms_cd1400[chip];
425 1.1 pk
426 1.13 pk cd->cd_clock = cd_clock;
427 1.42 macallan cd->cd_reg = (char *)bus_space_vaddr(sa->sa_bustag, bh) +
428 1.42 macallan card->mb_cd1400[chip];
429 1.1 pk
430 1.28 pk /* prom_getpropstring(node, "chiprev"); */
431 1.1 pk /* seemingly the Magma drivers just ignore the propstring */
432 1.1 pk cd->cd_chiprev = cd1400_read_reg(cd, CD1400_GFRCR);
433 1.1 pk
434 1.25 tsutsui dprintf(("%s attach CD1400 %d addr %p rev %x clock %dMHz\n",
435 1.46 cegger device_xname(&sc->ms_dev), chip,
436 1.1 pk cd->cd_reg, cd->cd_chiprev, cd->cd_clock));
437 1.1 pk
438 1.1 pk /* clear GFRCR */
439 1.1 pk cd1400_write_reg(cd, CD1400_GFRCR, 0x00);
440 1.1 pk
441 1.1 pk /* reset whole chip */
442 1.1 pk cd1400_write_ccr(cd, CD1400_CCR_CMDRESET | CD1400_CCR_FULLRESET);
443 1.1 pk
444 1.1 pk /* wait for revision code to be restored */
445 1.1 pk while( cd1400_read_reg(cd, CD1400_GFRCR) != cd->cd_chiprev )
446 1.1 pk ;
447 1.1 pk
448 1.1 pk /* set the Prescaler Period Register to tick at 1ms */
449 1.1 pk cd1400_write_reg(cd, CD1400_PPR,
450 1.1 pk ((cd->cd_clock * 1000000 / CD1400_PPR_PRESCALER + 500) / 1000));
451 1.1 pk
452 1.1 pk /* The LC2+1Sp card is the only card that doesn't have
453 1.1 pk * a CD1190 for the parallel port, but uses channel 0 of
454 1.1 pk * the CD1400, so we make a note of it for later and set up
455 1.1 pk * the CD1400 for parallel mode operation.
456 1.1 pk */
457 1.1 pk if( card->mb_npar && card->mb_ncd1190 == 0 ) {
458 1.1 pk cd1400_write_reg(cd, CD1400_GCR, CD1400_GCR_PARALLEL);
459 1.1 pk cd->cd_parmode = 1;
460 1.1 pk }
461 1.1 pk }
462 1.1 pk
463 1.1 pk /* init the cd1190 chips */
464 1.1 pk for( chip = 0 ; chip < card->mb_ncd1190 ; chip++ ) {
465 1.1 pk struct cd1190 *cd = &sc->ms_cd1190[chip];
466 1.1 pk
467 1.42 macallan cd->cd_reg = (char *)bus_space_vaddr(sa->sa_bustag, bh) +
468 1.42 macallan card->mb_cd1190[chip];
469 1.13 pk
470 1.1 pk /* XXX don't know anything about these chips yet */
471 1.13 pk printf("%s: CD1190 %d addr %p (unsupported)\n",
472 1.46 cegger device_xname(self), chip, cd->cd_reg);
473 1.1 pk }
474 1.1 pk
475 1.1 pk sbus_establish(&sc->ms_sd, &sc->ms_dev);
476 1.1 pk
477 1.1 pk /* configure the children */
478 1.1 pk (void)config_found(self, mtty_match, NULL);
479 1.1 pk (void)config_found(self, mbpp_match, NULL);
480 1.1 pk
481 1.1 pk /*
482 1.1 pk * Establish the interrupt handlers.
483 1.1 pk */
484 1.5 pk if (sa->sa_nintr == 0)
485 1.5 pk return; /* No interrupts to service!? */
486 1.5 pk
487 1.24 pk (void)bus_intr_establish(sa->sa_bustag, sa->sa_pri, IPL_SERIAL,
488 1.23 pk magma_hard, sc);
489 1.43 ad sc->ms_sicookie = softint_establish(SOFTINT_SERIAL, magma_soft, sc);
490 1.22 pk if (sc->ms_sicookie == NULL) {
491 1.46 cegger aprint_normal("\n");
492 1.46 cegger aprint_error_dev(&sc->ms_dev, "cannot establish soft int handler\n");
493 1.22 pk return;
494 1.22 pk }
495 1.7 cgd evcnt_attach_dynamic(&sc->ms_intrcnt, EVCNT_TYPE_INTR, NULL,
496 1.46 cegger device_xname(&sc->ms_dev), "intr");
497 1.1 pk }
498 1.1 pk
499 1.1 pk /*
500 1.1 pk * hard interrupt routine
501 1.1 pk *
502 1.1 pk * returns 1 if it handled it, otherwise 0
503 1.1 pk *
504 1.36 jmcneill * runs at IPL_SERIAL
505 1.1 pk */
506 1.1 pk int
507 1.1 pk magma_hard(arg)
508 1.1 pk void *arg;
509 1.1 pk {
510 1.1 pk struct magma_softc *sc = arg;
511 1.1 pk struct cd1400 *cd;
512 1.1 pk int chip, status = 0;
513 1.1 pk int serviced = 0;
514 1.1 pk int needsoftint = 0;
515 1.1 pk
516 1.1 pk /*
517 1.1 pk * check status of all the CD1400 chips
518 1.1 pk */
519 1.1 pk for( chip = 0 ; chip < sc->ms_ncd1400 ; chip++ )
520 1.1 pk status |= cd1400_read_reg(&sc->ms_cd1400[chip], CD1400_SVRR);
521 1.1 pk
522 1.1 pk if( ISSET(status, CD1400_SVRR_RXRDY) ) {
523 1.1 pk u_char rivr = *sc->ms_svcackr; /* enter rx service context */
524 1.1 pk int port = rivr >> 4;
525 1.1 pk
526 1.1 pk if( rivr & (1<<3) ) { /* parallel port */
527 1.3 pk struct mbpp_port *mbpp;
528 1.3 pk int n_chars;
529 1.1 pk
530 1.3 pk mbpp = &sc->ms_mbpp->ms_port[port];
531 1.1 pk cd = mbpp->mp_cd1400;
532 1.29 perry
533 1.3 pk /* don't think we have to handle exceptions */
534 1.3 pk n_chars = cd1400_read_reg(cd, CD1400_RDCR);
535 1.3 pk while (n_chars--) {
536 1.3 pk if( mbpp->mp_cnt == 0 ) {
537 1.3 pk SET(mbpp->mp_flags, MBPPF_WAKEUP);
538 1.3 pk needsoftint = 1;
539 1.3 pk break;
540 1.3 pk }
541 1.3 pk *mbpp->mp_ptr = cd1400_read_reg(cd,CD1400_RDSR);
542 1.3 pk mbpp->mp_ptr++;
543 1.3 pk mbpp->mp_cnt--;
544 1.3 pk }
545 1.1 pk } else { /* serial port */
546 1.1 pk struct mtty_port *mtty;
547 1.1 pk u_char *ptr, n_chars, line_stat;
548 1.1 pk
549 1.1 pk mtty = &sc->ms_mtty->ms_port[port];
550 1.1 pk cd = mtty->mp_cd1400;
551 1.1 pk
552 1.1 pk if( ISSET(rivr, CD1400_RIVR_EXCEPTION) ) {
553 1.1 pk line_stat = cd1400_read_reg(cd, CD1400_RDSR);
554 1.1 pk n_chars = 1;
555 1.1 pk } else { /* no exception, received data OK */
556 1.1 pk line_stat = 0;
557 1.1 pk n_chars = cd1400_read_reg(cd, CD1400_RDCR);
558 1.1 pk }
559 1.1 pk
560 1.1 pk ptr = mtty->mp_rput;
561 1.1 pk while( n_chars-- ) {
562 1.1 pk *ptr++ = line_stat;
563 1.1 pk *ptr++ = cd1400_read_reg(cd, CD1400_RDSR);
564 1.1 pk if( ptr == mtty->mp_rend ) ptr = mtty->mp_rbuf;
565 1.1 pk if( ptr == mtty->mp_rget ) {
566 1.1 pk if( ptr == mtty->mp_rbuf )
567 1.1 pk ptr = mtty->mp_rend;
568 1.1 pk ptr -= 2;
569 1.1 pk SET(mtty->mp_flags, MTTYF_RING_OVERFLOW);
570 1.1 pk break;
571 1.1 pk }
572 1.1 pk }
573 1.1 pk mtty->mp_rput = ptr;
574 1.1 pk
575 1.1 pk needsoftint = 1;
576 1.1 pk }
577 1.1 pk
578 1.1 pk cd1400_write_reg(cd, CD1400_EOSRR, 0); /* end service context */
579 1.1 pk serviced = 1;
580 1.1 pk } /* if(rx_service...) */
581 1.1 pk
582 1.1 pk if( ISSET(status, CD1400_SVRR_MDMCH) ) {
583 1.1 pk u_char mivr = *sc->ms_svcackm; /* enter mdm service context */
584 1.1 pk int port = mivr >> 4;
585 1.1 pk struct mtty_port *mtty;
586 1.1 pk int carrier;
587 1.1 pk u_char msvr;
588 1.1 pk
589 1.1 pk /*
590 1.1 pk * Handle CD (LC2+1Sp = DSR) changes.
591 1.1 pk */
592 1.1 pk mtty = &sc->ms_mtty->ms_port[port];
593 1.1 pk cd = mtty->mp_cd1400;
594 1.1 pk msvr = cd1400_read_reg(cd, CD1400_MSVR2);
595 1.1 pk carrier = ISSET(msvr, cd->cd_parmode ? CD1400_MSVR2_DSR : CD1400_MSVR2_CD);
596 1.1 pk
597 1.1 pk if( mtty->mp_carrier != carrier ) {
598 1.1 pk SET(mtty->mp_flags, MTTYF_CARRIER_CHANGED);
599 1.1 pk mtty->mp_carrier = carrier;
600 1.1 pk needsoftint = 1;
601 1.1 pk }
602 1.1 pk
603 1.1 pk cd1400_write_reg(cd, CD1400_EOSRR, 0); /* end service context */
604 1.1 pk serviced = 1;
605 1.1 pk } /* if(mdm_service...) */
606 1.1 pk
607 1.1 pk if( ISSET(status, CD1400_SVRR_TXRDY) ) {
608 1.2 pk u_char tivr = *sc->ms_svcackt; /* enter tx service context */
609 1.1 pk int port = tivr >> 4;
610 1.1 pk
611 1.1 pk if( tivr & (1<<3) ) { /* parallel port */
612 1.1 pk struct mbpp_port *mbpp;
613 1.1 pk
614 1.1 pk mbpp = &sc->ms_mbpp->ms_port[port];
615 1.1 pk cd = mbpp->mp_cd1400;
616 1.1 pk
617 1.3 pk if( mbpp->mp_cnt ) {
618 1.1 pk int count = 0;
619 1.1 pk
620 1.3 pk /* fill the fifo */
621 1.3 pk while (mbpp->mp_cnt &&
622 1.3 pk count++ < CD1400_PAR_FIFO_SIZE) {
623 1.3 pk cd1400_write_reg(cd, CD1400_TDR,
624 1.3 pk *mbpp->mp_ptr);
625 1.3 pk mbpp->mp_ptr++;
626 1.3 pk mbpp->mp_cnt--;
627 1.1 pk }
628 1.1 pk } else {
629 1.3 pk /*
630 1.3 pk * fifo is empty and we got no more data
631 1.3 pk * to send, so shut off interrupts and
632 1.3 pk * signal for a wakeup, which can't be
633 1.3 pk * done here in case we beat mbpp_send to
634 1.3 pk * the tsleep call (we are running at >spltty)
635 1.3 pk */
636 1.3 pk cd1400_write_reg(cd, CD1400_SRER, 0);
637 1.3 pk SET(mbpp->mp_flags, MBPPF_WAKEUP);
638 1.1 pk needsoftint = 1;
639 1.1 pk }
640 1.1 pk } else { /* serial port */
641 1.1 pk struct mtty_port *mtty;
642 1.1 pk struct tty *tp;
643 1.1 pk
644 1.1 pk mtty = &sc->ms_mtty->ms_port[port];
645 1.1 pk cd = mtty->mp_cd1400;
646 1.1 pk tp = mtty->mp_tty;
647 1.1 pk
648 1.1 pk if( !ISSET(mtty->mp_flags, MTTYF_STOP) ) {
649 1.1 pk int count = 0;
650 1.1 pk
651 1.1 pk /* check if we should start/stop a break */
652 1.1 pk if( ISSET(mtty->mp_flags, MTTYF_SET_BREAK) ) {
653 1.1 pk cd1400_write_reg(cd, CD1400_TDR, 0);
654 1.1 pk cd1400_write_reg(cd, CD1400_TDR, 0x81);
655 1.1 pk /* should we delay too? */
656 1.1 pk CLR(mtty->mp_flags, MTTYF_SET_BREAK);
657 1.1 pk count += 2;
658 1.1 pk }
659 1.1 pk
660 1.1 pk if( ISSET(mtty->mp_flags, MTTYF_CLR_BREAK) ) {
661 1.1 pk cd1400_write_reg(cd, CD1400_TDR, 0);
662 1.1 pk cd1400_write_reg(cd, CD1400_TDR, 0x83);
663 1.1 pk CLR(mtty->mp_flags, MTTYF_CLR_BREAK);
664 1.1 pk count += 2;
665 1.1 pk }
666 1.1 pk
667 1.1 pk /* I don't quite fill the fifo in case the last one is a
668 1.1 pk * NULL which I have to double up because its the escape
669 1.1 pk * code for embedded transmit characters.
670 1.1 pk */
671 1.1 pk while( mtty->mp_txc > 0 && count < CD1400_TX_FIFO_SIZE - 1 ) {
672 1.2 pk u_char ch;
673 1.1 pk
674 1.1 pk ch = *mtty->mp_txp;
675 1.1 pk
676 1.1 pk mtty->mp_txc--;
677 1.1 pk mtty->mp_txp++;
678 1.1 pk
679 1.1 pk if( ch == 0 ) {
680 1.1 pk cd1400_write_reg(cd, CD1400_TDR, ch);
681 1.1 pk count++;
682 1.1 pk }
683 1.1 pk
684 1.1 pk cd1400_write_reg(cd, CD1400_TDR, ch);
685 1.1 pk count++;
686 1.1 pk }
687 1.1 pk }
688 1.1 pk
689 1.1 pk /* if we ran out of work or are requested to STOP then
690 1.1 pk * shut off the txrdy interrupts and signal DONE to flush
691 1.1 pk * out the chars we have sent.
692 1.1 pk */
693 1.1 pk if( mtty->mp_txc == 0 || ISSET(mtty->mp_flags, MTTYF_STOP) ) {
694 1.2 pk register int srer;
695 1.1 pk
696 1.1 pk srer = cd1400_read_reg(cd, CD1400_SRER);
697 1.1 pk CLR(srer, CD1400_SRER_TXRDY);
698 1.1 pk cd1400_write_reg(cd, CD1400_SRER, srer);
699 1.1 pk CLR(mtty->mp_flags, MTTYF_STOP);
700 1.1 pk
701 1.1 pk SET(mtty->mp_flags, MTTYF_DONE);
702 1.1 pk needsoftint = 1;
703 1.1 pk }
704 1.1 pk }
705 1.1 pk
706 1.1 pk cd1400_write_reg(cd, CD1400_EOSRR, 0); /* end service context */
707 1.1 pk serviced = 1;
708 1.1 pk } /* if(tx_service...) */
709 1.1 pk
710 1.1 pk /* XXX service CD1190 interrupts too
711 1.1 pk for( chip = 0 ; chip < sc->ms_ncd1190 ; chip++ ) {
712 1.1 pk }
713 1.1 pk */
714 1.1 pk
715 1.22 pk if (needsoftint)
716 1.22 pk /* trigger the soft interrupt */
717 1.43 ad softint_schedule(sc->ms_sicookie);
718 1.1 pk
719 1.1 pk return(serviced);
720 1.1 pk }
721 1.1 pk
722 1.1 pk /*
723 1.1 pk * magma soft interrupt handler
724 1.1 pk *
725 1.36 jmcneill * runs at IPL_SOFTSERIAL
726 1.1 pk */
727 1.22 pk void
728 1.1 pk magma_soft(arg)
729 1.1 pk void *arg;
730 1.1 pk {
731 1.1 pk struct magma_softc *sc = arg;
732 1.1 pk struct mtty_softc *mtty = sc->ms_mtty;
733 1.1 pk struct mbpp_softc *mbpp = sc->ms_mbpp;
734 1.1 pk int port;
735 1.1 pk int s, flags;
736 1.1 pk
737 1.2 pk if (mtty == NULL)
738 1.2 pk goto chkbpp;
739 1.2 pk
740 1.1 pk /*
741 1.1 pk * check the tty ports to see what needs doing
742 1.1 pk */
743 1.1 pk for( port = 0 ; port < mtty->ms_nports ; port++ ) {
744 1.2 pk struct mtty_port *mp = &mtty->ms_port[port];
745 1.2 pk struct tty *tp = mp->mp_tty;
746 1.1 pk
747 1.2 pk if( !ISSET(tp->t_state, TS_ISOPEN) )
748 1.2 pk continue;
749 1.1 pk
750 1.1 pk /*
751 1.1 pk * handle any received data
752 1.1 pk */
753 1.1 pk while( mp->mp_rget != mp->mp_rput ) {
754 1.2 pk u_char stat;
755 1.2 pk int data;
756 1.1 pk
757 1.1 pk stat = mp->mp_rget[0];
758 1.1 pk data = mp->mp_rget[1];
759 1.2 pk mp->mp_rget = ((mp->mp_rget + 2) == mp->mp_rend)
760 1.2 pk ? mp->mp_rbuf : (mp->mp_rget + 2);
761 1.1 pk
762 1.1 pk if( stat & (CD1400_RDSR_BREAK | CD1400_RDSR_FE) )
763 1.1 pk data |= TTY_FE;
764 1.1 pk if( stat & CD1400_RDSR_PE )
765 1.1 pk data |= TTY_PE;
766 1.1 pk
767 1.1 pk if( stat & CD1400_RDSR_OE )
768 1.2 pk log(LOG_WARNING, "%s%x: fifo overflow\n",
769 1.46 cegger device_xname(&mtty->ms_dev), port);
770 1.1 pk
771 1.9 eeh (*tp->t_linesw->l_rint)(data, tp);
772 1.1 pk }
773 1.1 pk
774 1.36 jmcneill s = splserial(); /* block out hard interrupt routine */
775 1.1 pk flags = mp->mp_flags;
776 1.1 pk CLR(mp->mp_flags, MTTYF_DONE | MTTYF_CARRIER_CHANGED | MTTYF_RING_OVERFLOW);
777 1.1 pk splx(s); /* ok */
778 1.1 pk
779 1.1 pk if( ISSET(flags, MTTYF_CARRIER_CHANGED) ) {
780 1.46 cegger dprintf(("%s%x: cd %s\n", device_xname(&mtty->ms_dev),
781 1.3 pk port, mp->mp_carrier ? "on" : "off"));
782 1.9 eeh (*tp->t_linesw->l_modem)(tp, mp->mp_carrier);
783 1.1 pk }
784 1.1 pk
785 1.1 pk if( ISSET(flags, MTTYF_RING_OVERFLOW) ) {
786 1.3 pk log(LOG_WARNING, "%s%x: ring buffer overflow\n",
787 1.46 cegger device_xname(&mtty->ms_dev), port);
788 1.1 pk }
789 1.1 pk
790 1.1 pk if( ISSET(flags, MTTYF_DONE) ) {
791 1.1 pk ndflush(&tp->t_outq, mp->mp_txp - tp->t_outq.c_cf);
792 1.1 pk CLR(tp->t_state, TS_BUSY);
793 1.9 eeh (*tp->t_linesw->l_start)(tp); /* might be some more */
794 1.1 pk }
795 1.1 pk } /* for(each mtty...) */
796 1.1 pk
797 1.2 pk
798 1.2 pk chkbpp:
799 1.1 pk /*
800 1.2 pk * Check the bpp ports (if any) to see what needs doing
801 1.1 pk */
802 1.2 pk if (mbpp == NULL)
803 1.22 pk return;
804 1.2 pk
805 1.1 pk for( port = 0 ; port < mbpp->ms_nports ; port++ ) {
806 1.2 pk struct mbpp_port *mp = &mbpp->ms_port[port];
807 1.1 pk
808 1.2 pk if( !ISSET(mp->mp_flags, MBPPF_OPEN) )
809 1.2 pk continue;
810 1.1 pk
811 1.36 jmcneill s = splserial();
812 1.1 pk flags = mp->mp_flags;
813 1.3 pk CLR(mp->mp_flags, MBPPF_WAKEUP);
814 1.1 pk splx(s);
815 1.1 pk
816 1.3 pk if( ISSET(flags, MBPPF_WAKEUP) ) {
817 1.1 pk wakeup(mp);
818 1.1 pk }
819 1.1 pk
820 1.1 pk } /* for(each mbpp...) */
821 1.1 pk }
822 1.1 pk
823 1.1 pk /************************************************************************
824 1.1 pk *
825 1.1 pk * MTTY Routines
826 1.1 pk *
827 1.1 pk * mtty_match match one mtty device
828 1.1 pk * mtty_attach attach mtty devices
829 1.1 pk * mttyopen open mtty device
830 1.1 pk * mttyclose close mtty device
831 1.1 pk * mttyread read from mtty
832 1.1 pk * mttywrite write to mtty
833 1.1 pk * mttyioctl do ioctl on mtty
834 1.1 pk * mttytty return tty pointer for mtty
835 1.1 pk * mttystop stop mtty device
836 1.1 pk * mtty_start start mtty device
837 1.1 pk * mtty_param set mtty parameters
838 1.1 pk * mtty_modem_control set modem control lines
839 1.1 pk */
840 1.1 pk
841 1.1 pk int
842 1.1 pk mtty_match(parent, cf, args)
843 1.1 pk struct device *parent;
844 1.1 pk struct cfdata *cf;
845 1.1 pk void *args;
846 1.1 pk {
847 1.47 drochner struct magma_softc *sc = device_private(parent);
848 1.1 pk
849 1.1 pk return( args == mtty_match && sc->ms_board->mb_nser && sc->ms_mtty == NULL );
850 1.1 pk }
851 1.1 pk
852 1.1 pk void
853 1.1 pk mtty_attach(parent, dev, args)
854 1.1 pk struct device *parent;
855 1.1 pk struct device *dev;
856 1.1 pk void *args;
857 1.1 pk {
858 1.47 drochner struct magma_softc *sc = device_private(parent);
859 1.47 drochner struct mtty_softc *ms = device_private(dev);
860 1.1 pk int port, chip, chan;
861 1.1 pk
862 1.1 pk sc->ms_mtty = ms;
863 1.2 pk dprintf((" addr %p", ms));
864 1.1 pk
865 1.1 pk for( port = 0, chip = 0, chan = 0 ; port < sc->ms_board->mb_nser ; port++ ) {
866 1.2 pk struct mtty_port *mp = &ms->ms_port[port];
867 1.2 pk struct tty *tp;
868 1.1 pk
869 1.1 pk mp->mp_cd1400 = &sc->ms_cd1400[chip];
870 1.13 pk if (mp->mp_cd1400->cd_parmode && chan == 0)
871 1.2 pk chan = 1; /* skip channel 0 if parmode */
872 1.1 pk mp->mp_channel = chan;
873 1.1 pk
874 1.1 pk tp = ttymalloc();
875 1.13 pk if (tp == NULL) break;
876 1.1 pk tty_attach(tp);
877 1.1 pk tp->t_oproc = mtty_start;
878 1.1 pk tp->t_param = mtty_param;
879 1.1 pk
880 1.1 pk mp->mp_tty = tp;
881 1.1 pk
882 1.1 pk mp->mp_rbuf = malloc(MTTY_RBUF_SIZE, M_DEVBUF, M_NOWAIT);
883 1.13 pk if (mp->mp_rbuf == NULL) break;
884 1.1 pk
885 1.1 pk mp->mp_rend = mp->mp_rbuf + MTTY_RBUF_SIZE;
886 1.1 pk
887 1.1 pk chan = (chan + 1) % CD1400_NO_OF_CHANNELS;
888 1.13 pk if (chan == 0)
889 1.13 pk chip++;
890 1.1 pk }
891 1.1 pk
892 1.1 pk ms->ms_nports = port;
893 1.1 pk printf(": %d tty%s\n", port, port == 1 ? "" : "s");
894 1.1 pk }
895 1.1 pk
896 1.1 pk /*
897 1.1 pk * open routine. returns zero if successful, else error code
898 1.1 pk */
899 1.1 pk int
900 1.31 christos mttyopen(dev, flags, mode, l)
901 1.1 pk dev_t dev;
902 1.1 pk int flags;
903 1.1 pk int mode;
904 1.31 christos struct lwp *l;
905 1.1 pk {
906 1.1 pk int card = MAGMA_CARD(dev);
907 1.1 pk int port = MAGMA_PORT(dev);
908 1.1 pk struct mtty_softc *ms;
909 1.1 pk struct mtty_port *mp;
910 1.1 pk struct tty *tp;
911 1.1 pk struct cd1400 *cd;
912 1.1 pk int error, s;
913 1.1 pk
914 1.47 drochner if ((ms = device_lookup_private(&mtty_cd, card)) == NULL
915 1.47 drochner || port >= ms->ms_nports )
916 1.1 pk return(ENXIO); /* device not configured */
917 1.1 pk
918 1.1 pk mp = &ms->ms_port[port];
919 1.1 pk tp = mp->mp_tty;
920 1.1 pk tp->t_dev = dev;
921 1.1 pk
922 1.37 elad if (kauth_authorize_device_tty(l->l_cred, KAUTH_DEVICE_TTY_OPEN, tp))
923 1.1 pk return (EBUSY);
924 1.1 pk
925 1.1 pk s = spltty();
926 1.1 pk
927 1.1 pk if( !ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) {
928 1.1 pk
929 1.1 pk /* set defaults */
930 1.1 pk ttychars(tp);
931 1.1 pk tp->t_iflag = TTYDEF_IFLAG;
932 1.1 pk tp->t_oflag = TTYDEF_OFLAG;
933 1.1 pk tp->t_cflag = TTYDEF_CFLAG;
934 1.1 pk if( ISSET(mp->mp_openflags, TIOCFLAG_CLOCAL) )
935 1.1 pk SET(tp->t_cflag, CLOCAL);
936 1.1 pk if( ISSET(mp->mp_openflags, TIOCFLAG_CRTSCTS) )
937 1.1 pk SET(tp->t_cflag, CRTSCTS);
938 1.1 pk if( ISSET(mp->mp_openflags, TIOCFLAG_MDMBUF) )
939 1.1 pk SET(tp->t_cflag, MDMBUF);
940 1.1 pk tp->t_lflag = TTYDEF_LFLAG;
941 1.1 pk tp->t_ispeed = tp->t_ospeed = TTYDEF_SPEED;
942 1.1 pk
943 1.1 pk /* init ring buffer */
944 1.1 pk mp->mp_rput = mp->mp_rget = mp->mp_rbuf;
945 1.1 pk
946 1.1 pk /* reset CD1400 channel */
947 1.1 pk cd = mp->mp_cd1400;
948 1.1 pk cd1400_write_reg(cd, CD1400_CAR, mp->mp_channel);
949 1.1 pk cd1400_write_ccr(cd, CD1400_CCR_CMDRESET);
950 1.1 pk
951 1.1 pk /* encode the port number in top half of LIVR */
952 1.1 pk cd1400_write_reg(cd, CD1400_LIVR, port << 4 );
953 1.1 pk
954 1.1 pk /* sets parameters and raises DTR */
955 1.1 pk (void)mtty_param(tp, &tp->t_termios);
956 1.1 pk
957 1.1 pk /* set tty watermarks */
958 1.1 pk ttsetwater(tp);
959 1.1 pk
960 1.1 pk /* enable service requests */
961 1.1 pk cd1400_write_reg(cd, CD1400_SRER,
962 1.1 pk CD1400_SRER_RXDATA | CD1400_SRER_MDMCH);
963 1.1 pk
964 1.1 pk /* tell the tty about the carrier status */
965 1.1 pk if( ISSET(mp->mp_openflags, TIOCFLAG_SOFTCAR) ||
966 1.1 pk mp->mp_carrier )
967 1.1 pk SET(tp->t_state, TS_CARR_ON);
968 1.1 pk else
969 1.1 pk CLR(tp->t_state, TS_CARR_ON);
970 1.1 pk }
971 1.1 pk splx(s);
972 1.1 pk
973 1.1 pk error = ttyopen(tp, MTTY_DIALOUT(dev), ISSET(flags, O_NONBLOCK));
974 1.1 pk if (error != 0)
975 1.1 pk goto bad;
976 1.1 pk
977 1.9 eeh error = (*tp->t_linesw->l_open)(dev, tp);
978 1.1 pk if (error != 0)
979 1.1 pk goto bad;
980 1.1 pk
981 1.1 pk bad:
982 1.1 pk if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) {
983 1.1 pk /*
984 1.1 pk * We failed to open the device, and nobody else had it opened.
985 1.1 pk * Clean up the state as appropriate.
986 1.1 pk */
987 1.1 pk /* XXX - do that here */
988 1.1 pk }
989 1.1 pk
990 1.1 pk return (error);
991 1.1 pk }
992 1.1 pk
993 1.1 pk /*
994 1.1 pk * close routine. returns zero if successful, else error code
995 1.1 pk */
996 1.1 pk int
997 1.31 christos mttyclose(dev, flag, mode, l)
998 1.1 pk dev_t dev;
999 1.1 pk int flag;
1000 1.1 pk int mode;
1001 1.31 christos struct lwp *l;
1002 1.1 pk {
1003 1.47 drochner struct mtty_softc *ms = device_lookup_private(&mtty_cd,
1004 1.47 drochner MAGMA_CARD(dev));
1005 1.1 pk struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(dev)];
1006 1.1 pk struct tty *tp = mp->mp_tty;
1007 1.1 pk int s;
1008 1.1 pk
1009 1.9 eeh (*tp->t_linesw->l_close)(tp, flag);
1010 1.1 pk ttyclose(tp);
1011 1.1 pk
1012 1.1 pk s = spltty();
1013 1.1 pk
1014 1.1 pk /* if HUPCL is set, and the tty is no longer open
1015 1.1 pk * shut down the port
1016 1.1 pk */
1017 1.1 pk if( ISSET(tp->t_cflag, HUPCL) || !ISSET(tp->t_state, TS_ISOPEN) ) {
1018 1.1 pk /* XXX wait until FIFO is empty before turning off the channel
1019 1.1 pk struct cd1400 *cd = mp->mp_cd1400;
1020 1.1 pk */
1021 1.1 pk
1022 1.1 pk /* drop DTR and RTS */
1023 1.1 pk (void)mtty_modem_control(mp, 0, DMSET);
1024 1.1 pk
1025 1.1 pk /* turn off the channel
1026 1.1 pk cd1400_write_reg(cd, CD1400_CAR, mp->mp_channel);
1027 1.1 pk cd1400_write_ccr(cd, CD1400_CCR_CMDRESET);
1028 1.1 pk */
1029 1.1 pk }
1030 1.1 pk
1031 1.1 pk splx(s);
1032 1.1 pk
1033 1.1 pk return(0);
1034 1.1 pk }
1035 1.1 pk
1036 1.1 pk /*
1037 1.1 pk * Read routine
1038 1.1 pk */
1039 1.1 pk int
1040 1.1 pk mttyread(dev, uio, flags)
1041 1.1 pk dev_t dev;
1042 1.1 pk struct uio *uio;
1043 1.1 pk int flags;
1044 1.1 pk {
1045 1.47 drochner struct mtty_softc *ms = device_lookup_private(&mtty_cd,
1046 1.47 drochner MAGMA_CARD(dev));
1047 1.1 pk struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(dev)];
1048 1.1 pk struct tty *tp = mp->mp_tty;
1049 1.1 pk
1050 1.9 eeh return( (*tp->t_linesw->l_read)(tp, uio, flags) );
1051 1.1 pk }
1052 1.1 pk
1053 1.1 pk /*
1054 1.1 pk * Write routine
1055 1.1 pk */
1056 1.1 pk int
1057 1.1 pk mttywrite(dev, uio, flags)
1058 1.1 pk dev_t dev;
1059 1.1 pk struct uio *uio;
1060 1.1 pk int flags;
1061 1.1 pk {
1062 1.47 drochner struct mtty_softc *ms = device_lookup_private(&mtty_cd,
1063 1.47 drochner MAGMA_CARD(dev));
1064 1.1 pk struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(dev)];
1065 1.1 pk struct tty *tp = mp->mp_tty;
1066 1.1 pk
1067 1.9 eeh return( (*tp->t_linesw->l_write)(tp, uio, flags) );
1068 1.10 scw }
1069 1.10 scw
1070 1.10 scw /*
1071 1.10 scw * Poll routine
1072 1.10 scw */
1073 1.10 scw int
1074 1.31 christos mttypoll(dev, events, l)
1075 1.10 scw dev_t dev;
1076 1.10 scw int events;
1077 1.31 christos struct lwp *l;
1078 1.10 scw {
1079 1.47 drochner struct mtty_softc *ms = device_lookup_private(&mtty_cd,
1080 1.47 drochner MAGMA_CARD(dev));
1081 1.10 scw struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(dev)];
1082 1.10 scw struct tty *tp = mp->mp_tty;
1083 1.29 perry
1084 1.31 christos return ((*tp->t_linesw->l_poll)(tp, events, l));
1085 1.1 pk }
1086 1.1 pk
1087 1.1 pk /*
1088 1.1 pk * return tty pointer
1089 1.1 pk */
1090 1.1 pk struct tty *
1091 1.1 pk mttytty(dev)
1092 1.1 pk dev_t dev;
1093 1.1 pk {
1094 1.47 drochner struct mtty_softc *ms = device_lookup_private(&mtty_cd,
1095 1.47 drochner MAGMA_CARD(dev));
1096 1.1 pk struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(dev)];
1097 1.1 pk
1098 1.1 pk return(mp->mp_tty);
1099 1.1 pk }
1100 1.1 pk
1101 1.1 pk /*
1102 1.1 pk * ioctl routine
1103 1.1 pk */
1104 1.1 pk int
1105 1.31 christos mttyioctl(dev, cmd, data, flags, l)
1106 1.1 pk dev_t dev;
1107 1.1 pk u_long cmd;
1108 1.39 christos void *data;
1109 1.1 pk int flags;
1110 1.31 christos struct lwp *l;
1111 1.1 pk {
1112 1.47 drochner struct mtty_softc *ms = device_lookup_private(&mtty_cd,
1113 1.47 drochner MAGMA_CARD(dev));
1114 1.1 pk struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(dev)];
1115 1.1 pk struct tty *tp = mp->mp_tty;
1116 1.1 pk int error;
1117 1.1 pk
1118 1.31 christos error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flags, l);
1119 1.15 atatat if( error != EPASSTHROUGH ) return(error);
1120 1.1 pk
1121 1.31 christos error = ttioctl(tp, cmd, data, flags, l);
1122 1.15 atatat if( error != EPASSTHROUGH ) return(error);
1123 1.1 pk
1124 1.1 pk error = 0;
1125 1.1 pk
1126 1.1 pk switch(cmd) {
1127 1.1 pk case TIOCSBRK: /* set break */
1128 1.1 pk SET(mp->mp_flags, MTTYF_SET_BREAK);
1129 1.1 pk cd1400_enable_transmitter(mp->mp_cd1400, mp->mp_channel);
1130 1.1 pk break;
1131 1.1 pk
1132 1.1 pk case TIOCCBRK: /* clear break */
1133 1.1 pk SET(mp->mp_flags, MTTYF_CLR_BREAK);
1134 1.1 pk cd1400_enable_transmitter(mp->mp_cd1400, mp->mp_channel);
1135 1.1 pk break;
1136 1.1 pk
1137 1.1 pk case TIOCSDTR: /* set DTR */
1138 1.1 pk mtty_modem_control(mp, TIOCM_DTR, DMBIS);
1139 1.1 pk break;
1140 1.1 pk
1141 1.1 pk case TIOCCDTR: /* clear DTR */
1142 1.1 pk mtty_modem_control(mp, TIOCM_DTR, DMBIC);
1143 1.1 pk break;
1144 1.1 pk
1145 1.1 pk case TIOCMSET: /* set modem lines */
1146 1.1 pk mtty_modem_control(mp, *((int *)data), DMSET);
1147 1.1 pk break;
1148 1.1 pk
1149 1.1 pk case TIOCMBIS: /* bit set modem lines */
1150 1.1 pk mtty_modem_control(mp, *((int *)data), DMBIS);
1151 1.1 pk break;
1152 1.1 pk
1153 1.1 pk case TIOCMBIC: /* bit clear modem lines */
1154 1.1 pk mtty_modem_control(mp, *((int *)data), DMBIC);
1155 1.1 pk break;
1156 1.1 pk
1157 1.1 pk case TIOCMGET: /* get modem lines */
1158 1.1 pk *((int *)data) = mtty_modem_control(mp, 0, DMGET);
1159 1.1 pk break;
1160 1.1 pk
1161 1.1 pk case TIOCGFLAGS:
1162 1.1 pk *((int *)data) = mp->mp_openflags;
1163 1.1 pk break;
1164 1.1 pk
1165 1.1 pk case TIOCSFLAGS:
1166 1.38 elad if (kauth_authorize_device_tty(l->l_cred,
1167 1.38 elad KAUTH_DEVICE_TTY_PRIVSET, tp))
1168 1.1 pk error = EPERM;
1169 1.1 pk else
1170 1.1 pk mp->mp_openflags = *((int *)data) &
1171 1.1 pk (TIOCFLAG_SOFTCAR | TIOCFLAG_CLOCAL |
1172 1.1 pk TIOCFLAG_CRTSCTS | TIOCFLAG_MDMBUF);
1173 1.1 pk break;
1174 1.1 pk
1175 1.1 pk default:
1176 1.15 atatat error = EPASSTHROUGH;
1177 1.1 pk }
1178 1.1 pk
1179 1.1 pk return(error);
1180 1.1 pk }
1181 1.1 pk
1182 1.1 pk /*
1183 1.1 pk * Stop output, e.g., for ^S or output flush.
1184 1.1 pk */
1185 1.1 pk void
1186 1.1 pk mttystop(tp, flags)
1187 1.1 pk struct tty *tp;
1188 1.1 pk int flags;
1189 1.1 pk {
1190 1.47 drochner struct mtty_softc *ms = device_lookup_private(&mtty_cd,
1191 1.47 drochner MAGMA_CARD(tp->t_dev));
1192 1.1 pk struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(tp->t_dev)];
1193 1.1 pk int s;
1194 1.1 pk
1195 1.1 pk s = spltty();
1196 1.1 pk
1197 1.1 pk if( ISSET(tp->t_state, TS_BUSY) ) {
1198 1.1 pk if( !ISSET(tp->t_state, TS_TTSTOP) )
1199 1.1 pk SET(tp->t_state, TS_FLUSH);
1200 1.1 pk
1201 1.1 pk /*
1202 1.1 pk * the transmit interrupt routine will disable transmit when it
1203 1.1 pk * notices that MTTYF_STOP has been set.
1204 1.1 pk */
1205 1.1 pk SET(mp->mp_flags, MTTYF_STOP);
1206 1.1 pk }
1207 1.1 pk
1208 1.1 pk splx(s);
1209 1.1 pk }
1210 1.1 pk
1211 1.1 pk /*
1212 1.1 pk * Start output, after a stop.
1213 1.1 pk */
1214 1.1 pk void
1215 1.1 pk mtty_start(tp)
1216 1.1 pk struct tty *tp;
1217 1.1 pk {
1218 1.47 drochner struct mtty_softc *ms = device_lookup_private(&mtty_cd,
1219 1.47 drochner MAGMA_CARD(tp->t_dev));
1220 1.1 pk struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(tp->t_dev)];
1221 1.1 pk int s;
1222 1.1 pk
1223 1.1 pk s = spltty();
1224 1.1 pk
1225 1.1 pk /* we only need to do something if we are not already busy
1226 1.1 pk * or delaying or stopped
1227 1.1 pk */
1228 1.1 pk if( !ISSET(tp->t_state, TS_TTSTOP | TS_TIMEOUT | TS_BUSY) ) {
1229 1.45 ad if (ttypull(tp)) {
1230 1.1 pk mp->mp_txc = ndqb(&tp->t_outq, 0);
1231 1.1 pk mp->mp_txp = tp->t_outq.c_cf;
1232 1.1 pk SET(tp->t_state, TS_BUSY);
1233 1.1 pk cd1400_enable_transmitter(mp->mp_cd1400, mp->mp_channel);
1234 1.1 pk }
1235 1.1 pk }
1236 1.1 pk
1237 1.1 pk splx(s);
1238 1.1 pk }
1239 1.1 pk
1240 1.1 pk /*
1241 1.1 pk * set/get modem line status
1242 1.1 pk *
1243 1.1 pk * bits can be: TIOCM_DTR, TIOCM_RTS, TIOCM_CTS, TIOCM_CD, TIOCM_RI, TIOCM_DSR
1244 1.1 pk *
1245 1.1 pk * note that DTR and RTS lines are exchanged, and that DSR is
1246 1.1 pk * not available on the LC2+1Sp card (used as CD)
1247 1.1 pk *
1248 1.1 pk * only let them fiddle with RTS if CRTSCTS is not enabled
1249 1.1 pk */
1250 1.1 pk int
1251 1.1 pk mtty_modem_control(mp, bits, howto)
1252 1.1 pk struct mtty_port *mp;
1253 1.1 pk int bits;
1254 1.1 pk int howto;
1255 1.1 pk {
1256 1.1 pk struct cd1400 *cd = mp->mp_cd1400;
1257 1.1 pk struct tty *tp = mp->mp_tty;
1258 1.1 pk int s, msvr;
1259 1.1 pk
1260 1.1 pk s = spltty();
1261 1.1 pk
1262 1.1 pk cd1400_write_reg(cd, CD1400_CAR, mp->mp_channel);
1263 1.1 pk
1264 1.1 pk switch(howto) {
1265 1.1 pk case DMGET: /* get bits */
1266 1.1 pk bits = 0;
1267 1.1 pk
1268 1.1 pk bits |= TIOCM_LE;
1269 1.1 pk
1270 1.1 pk msvr = cd1400_read_reg(cd, CD1400_MSVR1);
1271 1.1 pk if( msvr & CD1400_MSVR1_RTS ) bits |= TIOCM_DTR;
1272 1.1 pk
1273 1.1 pk msvr = cd1400_read_reg(cd, CD1400_MSVR2);
1274 1.1 pk if( msvr & CD1400_MSVR2_DTR ) bits |= TIOCM_RTS;
1275 1.1 pk if( msvr & CD1400_MSVR2_CTS ) bits |= TIOCM_CTS;
1276 1.1 pk if( msvr & CD1400_MSVR2_RI ) bits |= TIOCM_RI;
1277 1.1 pk if( msvr & CD1400_MSVR2_DSR ) bits |= (cd->cd_parmode ? TIOCM_CD : TIOCM_DSR);
1278 1.1 pk if( msvr & CD1400_MSVR2_CD ) bits |= (cd->cd_parmode ? 0 : TIOCM_CD);
1279 1.1 pk
1280 1.1 pk break;
1281 1.1 pk
1282 1.1 pk case DMSET: /* reset bits */
1283 1.1 pk if( !ISSET(tp->t_cflag, CRTSCTS) )
1284 1.1 pk cd1400_write_reg(cd, CD1400_MSVR2, ((bits & TIOCM_RTS) ? CD1400_MSVR2_DTR : 0));
1285 1.1 pk
1286 1.1 pk cd1400_write_reg(cd, CD1400_MSVR1, ((bits & TIOCM_DTR) ? CD1400_MSVR1_RTS : 0));
1287 1.1 pk
1288 1.1 pk break;
1289 1.1 pk
1290 1.1 pk case DMBIS: /* set bits */
1291 1.1 pk if( (bits & TIOCM_RTS) && !ISSET(tp->t_cflag, CRTSCTS) )
1292 1.1 pk cd1400_write_reg(cd, CD1400_MSVR2, CD1400_MSVR2_DTR);
1293 1.1 pk
1294 1.1 pk if( bits & TIOCM_DTR )
1295 1.1 pk cd1400_write_reg(cd, CD1400_MSVR1, CD1400_MSVR1_RTS);
1296 1.1 pk
1297 1.1 pk break;
1298 1.1 pk
1299 1.1 pk case DMBIC: /* clear bits */
1300 1.1 pk if( (bits & TIOCM_RTS) && !ISSET(tp->t_cflag, CRTSCTS) )
1301 1.1 pk cd1400_write_reg(cd, CD1400_MSVR2, 0);
1302 1.1 pk
1303 1.1 pk if( bits & TIOCM_DTR )
1304 1.1 pk cd1400_write_reg(cd, CD1400_MSVR1, 0);
1305 1.1 pk
1306 1.1 pk break;
1307 1.1 pk }
1308 1.1 pk
1309 1.1 pk splx(s);
1310 1.1 pk return(bits);
1311 1.1 pk }
1312 1.1 pk
1313 1.1 pk /*
1314 1.1 pk * Set tty parameters, returns error or 0 on success
1315 1.1 pk */
1316 1.1 pk int
1317 1.1 pk mtty_param(tp, t)
1318 1.1 pk struct tty *tp;
1319 1.1 pk struct termios *t;
1320 1.1 pk {
1321 1.47 drochner struct mtty_softc *ms = device_lookup_private(&mtty_cd,
1322 1.47 drochner MAGMA_CARD(tp->t_dev));
1323 1.1 pk struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(tp->t_dev)];
1324 1.1 pk struct cd1400 *cd = mp->mp_cd1400;
1325 1.1 pk int rbpr, tbpr, rcor, tcor;
1326 1.1 pk u_char mcor1 = 0, mcor2 = 0;
1327 1.1 pk int s, opt;
1328 1.1 pk
1329 1.1 pk if( t->c_ospeed && cd1400_compute_baud(t->c_ospeed, cd->cd_clock, &tcor, &tbpr) )
1330 1.1 pk return(EINVAL);
1331 1.1 pk
1332 1.1 pk if( t->c_ispeed && cd1400_compute_baud(t->c_ispeed, cd->cd_clock, &rcor, &rbpr) )
1333 1.1 pk return(EINVAL);
1334 1.1 pk
1335 1.1 pk s = spltty();
1336 1.1 pk
1337 1.1 pk /* hang up the line if ospeed is zero, else raise DTR */
1338 1.1 pk (void)mtty_modem_control(mp, TIOCM_DTR, (t->c_ospeed == 0 ? DMBIC : DMBIS));
1339 1.1 pk
1340 1.1 pk /* select channel, done in mtty_modem_control() */
1341 1.1 pk /* cd1400_write_reg(cd, CD1400_CAR, mp->mp_channel); */
1342 1.1 pk
1343 1.1 pk /* set transmit speed */
1344 1.1 pk if( t->c_ospeed ) {
1345 1.1 pk cd1400_write_reg(cd, CD1400_TCOR, tcor);
1346 1.1 pk cd1400_write_reg(cd, CD1400_TBPR, tbpr);
1347 1.1 pk }
1348 1.1 pk
1349 1.1 pk /* set receive speed */
1350 1.1 pk if( t->c_ispeed ) {
1351 1.1 pk cd1400_write_reg(cd, CD1400_RCOR, rcor);
1352 1.1 pk cd1400_write_reg(cd, CD1400_RBPR, rbpr);
1353 1.1 pk }
1354 1.1 pk
1355 1.1 pk /* enable transmitting and receiving on this channel */
1356 1.1 pk opt = CD1400_CCR_CMDCHANCTL | CD1400_CCR_XMTEN | CD1400_CCR_RCVEN;
1357 1.1 pk cd1400_write_ccr(cd, opt);
1358 1.1 pk
1359 1.1 pk /* set parity, data and stop bits */
1360 1.1 pk opt = 0;
1361 1.1 pk if( ISSET(t->c_cflag, PARENB) )
1362 1.1 pk opt |= (ISSET(t->c_cflag, PARODD) ? CD1400_COR1_PARODD : CD1400_COR1_PARNORMAL);
1363 1.1 pk
1364 1.1 pk if( !ISSET(t->c_iflag, INPCK) )
1365 1.1 pk opt |= CD1400_COR1_NOINPCK; /* no parity checking */
1366 1.1 pk
1367 1.1 pk if( ISSET(t->c_cflag, CSTOPB) )
1368 1.1 pk opt |= CD1400_COR1_STOP2;
1369 1.1 pk
1370 1.1 pk switch( t->c_cflag & CSIZE ) {
1371 1.1 pk case CS5:
1372 1.1 pk opt |= CD1400_COR1_CS5;
1373 1.1 pk break;
1374 1.1 pk
1375 1.1 pk case CS6:
1376 1.1 pk opt |= CD1400_COR1_CS6;
1377 1.1 pk break;
1378 1.1 pk
1379 1.1 pk case CS7:
1380 1.1 pk opt |= CD1400_COR1_CS7;
1381 1.1 pk break;
1382 1.1 pk
1383 1.1 pk default:
1384 1.1 pk opt |= CD1400_COR1_CS8;
1385 1.1 pk break;
1386 1.1 pk }
1387 1.1 pk
1388 1.1 pk cd1400_write_reg(cd, CD1400_COR1, opt);
1389 1.1 pk
1390 1.1 pk /*
1391 1.1 pk * enable Embedded Transmit Commands (for breaks)
1392 1.1 pk * use the CD1400 automatic CTS flow control if CRTSCTS is set
1393 1.1 pk */
1394 1.1 pk opt = CD1400_COR2_ETC;
1395 1.1 pk if( ISSET(t->c_cflag, CRTSCTS) ) opt |= CD1400_COR2_CCTS_OFLOW;
1396 1.1 pk cd1400_write_reg(cd, CD1400_COR2, opt);
1397 1.1 pk
1398 1.1 pk cd1400_write_reg(cd, CD1400_COR3, MTTY_RX_FIFO_THRESHOLD);
1399 1.1 pk
1400 1.1 pk cd1400_write_ccr(cd, CD1400_CCR_CMDCORCHG | CD1400_CCR_COR1 | CD1400_CCR_COR2 | CD1400_CCR_COR3);
1401 1.1 pk
1402 1.1 pk cd1400_write_reg(cd, CD1400_COR4, CD1400_COR4_PFO_EXCEPTION);
1403 1.1 pk cd1400_write_reg(cd, CD1400_COR5, 0);
1404 1.1 pk
1405 1.1 pk /*
1406 1.1 pk * if automatic RTS handshaking enabled, set DTR threshold
1407 1.1 pk * (RTS and DTR lines are switched, CD1400 thinks its DTR)
1408 1.1 pk */
1409 1.1 pk if( ISSET(t->c_cflag, CRTSCTS) )
1410 1.1 pk mcor1 = MTTY_RX_DTR_THRESHOLD;
1411 1.1 pk
1412 1.1 pk /* set up `carrier detect' interrupts */
1413 1.1 pk if( cd->cd_parmode ) {
1414 1.1 pk SET(mcor1, CD1400_MCOR1_DSRzd);
1415 1.1 pk SET(mcor2, CD1400_MCOR2_DSRod);
1416 1.1 pk } else {
1417 1.1 pk SET(mcor1, CD1400_MCOR1_CDzd);
1418 1.1 pk SET(mcor2, CD1400_MCOR2_CDod);
1419 1.1 pk }
1420 1.1 pk
1421 1.1 pk cd1400_write_reg(cd, CD1400_MCOR1, mcor1);
1422 1.1 pk cd1400_write_reg(cd, CD1400_MCOR2, mcor2);
1423 1.1 pk
1424 1.1 pk /* receive timeout 2ms */
1425 1.1 pk cd1400_write_reg(cd, CD1400_RTPR, 2);
1426 1.1 pk
1427 1.1 pk splx(s);
1428 1.1 pk return(0);
1429 1.1 pk }
1430 1.1 pk
1431 1.1 pk /************************************************************************
1432 1.1 pk *
1433 1.1 pk * MBPP Routines
1434 1.1 pk *
1435 1.1 pk * mbpp_match match one mbpp device
1436 1.1 pk * mbpp_attach attach mbpp devices
1437 1.1 pk * mbppopen open mbpp device
1438 1.1 pk * mbppclose close mbpp device
1439 1.1 pk * mbppioctl do ioctl on mbpp
1440 1.3 pk * mbpp_rw general rw routine
1441 1.3 pk * mbpp_timeout rw timeout
1442 1.3 pk * mbpp_start rw start after delay
1443 1.3 pk * mbpp_send send data
1444 1.3 pk * mbpp_recv recv data
1445 1.1 pk */
1446 1.1 pk
1447 1.1 pk int
1448 1.1 pk mbpp_match(parent, cf, args)
1449 1.1 pk struct device *parent;
1450 1.1 pk struct cfdata *cf;
1451 1.1 pk void *args;
1452 1.1 pk {
1453 1.47 drochner struct magma_softc *sc = device_private(parent);
1454 1.1 pk
1455 1.1 pk return( args == mbpp_match && sc->ms_board->mb_npar && sc->ms_mbpp == NULL );
1456 1.1 pk }
1457 1.1 pk
1458 1.1 pk void
1459 1.1 pk mbpp_attach(parent, dev, args)
1460 1.1 pk struct device *parent;
1461 1.1 pk struct device *dev;
1462 1.1 pk void *args;
1463 1.1 pk {
1464 1.47 drochner struct magma_softc *sc = device_private(parent);
1465 1.47 drochner struct mbpp_softc *ms = device_private(dev);
1466 1.1 pk struct mbpp_port *mp;
1467 1.3 pk int port;
1468 1.1 pk
1469 1.1 pk sc->ms_mbpp = ms;
1470 1.2 pk dprintf((" addr %p", ms));
1471 1.1 pk
1472 1.1 pk for( port = 0 ; port < sc->ms_board->mb_npar ; port++ ) {
1473 1.1 pk mp = &ms->ms_port[port];
1474 1.1 pk
1475 1.41 ad callout_init(&mp->mp_timeout_ch, 0);
1476 1.41 ad callout_init(&mp->mp_start_ch, 0);
1477 1.6 thorpej
1478 1.1 pk if( sc->ms_ncd1190 )
1479 1.1 pk mp->mp_cd1190 = &sc->ms_cd1190[port];
1480 1.1 pk else
1481 1.1 pk mp->mp_cd1400 = &sc->ms_cd1400[0];
1482 1.1 pk }
1483 1.1 pk
1484 1.1 pk ms->ms_nports = port;
1485 1.1 pk printf(": %d port%s\n", port, port == 1 ? "" : "s");
1486 1.1 pk }
1487 1.1 pk
1488 1.1 pk /*
1489 1.1 pk * open routine. returns zero if successful, else error code
1490 1.1 pk */
1491 1.1 pk int
1492 1.31 christos mbppopen(dev, flags, mode, l)
1493 1.1 pk dev_t dev;
1494 1.1 pk int flags;
1495 1.1 pk int mode;
1496 1.31 christos struct lwp *l;
1497 1.1 pk {
1498 1.1 pk int card = MAGMA_CARD(dev);
1499 1.1 pk int port = MAGMA_PORT(dev);
1500 1.1 pk struct mbpp_softc *ms;
1501 1.1 pk struct mbpp_port *mp;
1502 1.3 pk int s;
1503 1.1 pk
1504 1.47 drochner if ((ms = device_lookup_private(&mbpp_cd, card)) == NULL
1505 1.47 drochner || port >= ms->ms_nports )
1506 1.1 pk return(ENXIO);
1507 1.1 pk
1508 1.1 pk mp = &ms->ms_port[port];
1509 1.1 pk
1510 1.1 pk s = spltty();
1511 1.1 pk if( ISSET(mp->mp_flags, MBPPF_OPEN) ) {
1512 1.1 pk splx(s);
1513 1.1 pk return(EBUSY);
1514 1.1 pk }
1515 1.1 pk SET(mp->mp_flags, MBPPF_OPEN);
1516 1.1 pk splx(s);
1517 1.1 pk
1518 1.3 pk /* set defaults */
1519 1.3 pk mp->mp_burst = MBPP_BURST;
1520 1.3 pk mp->mp_timeout = mbpp_mstohz(MBPP_TIMEOUT);
1521 1.3 pk mp->mp_delay = mbpp_mstohz(MBPP_DELAY);
1522 1.3 pk
1523 1.3 pk /* init chips */
1524 1.3 pk if( mp->mp_cd1400 ) { /* CD1400 */
1525 1.2 pk struct cd1400 *cd = mp->mp_cd1400;
1526 1.1 pk
1527 1.1 pk /* set up CD1400 channel */
1528 1.1 pk s = spltty();
1529 1.1 pk cd1400_write_reg(cd, CD1400_CAR, 0);
1530 1.1 pk cd1400_write_ccr(cd, CD1400_CCR_CMDRESET);
1531 1.1 pk cd1400_write_reg(cd, CD1400_LIVR, (1<<3));
1532 1.1 pk splx(s);
1533 1.3 pk } else { /* CD1190 */
1534 1.3 pk mp->mp_flags = 0;
1535 1.3 pk return (ENXIO);
1536 1.1 pk }
1537 1.1 pk
1538 1.3 pk return (0);
1539 1.1 pk }
1540 1.1 pk
1541 1.1 pk /*
1542 1.1 pk * close routine. returns zero if successful, else error code
1543 1.1 pk */
1544 1.1 pk int
1545 1.31 christos mbppclose(dev, flag, mode, l)
1546 1.1 pk dev_t dev;
1547 1.1 pk int flag;
1548 1.1 pk int mode;
1549 1.31 christos struct lwp *l;
1550 1.1 pk {
1551 1.47 drochner struct mbpp_softc *ms = device_lookup_private(&mbpp_cd,
1552 1.47 drochner MAGMA_CARD(dev));
1553 1.1 pk struct mbpp_port *mp = &ms->ms_port[MAGMA_PORT(dev)];
1554 1.1 pk
1555 1.1 pk mp->mp_flags = 0;
1556 1.1 pk return(0);
1557 1.1 pk }
1558 1.1 pk
1559 1.1 pk /*
1560 1.1 pk * ioctl routine
1561 1.1 pk */
1562 1.1 pk int
1563 1.31 christos mbppioctl(dev, cmd, data, flags, l)
1564 1.1 pk dev_t dev;
1565 1.1 pk u_long cmd;
1566 1.39 christos void *data;
1567 1.1 pk int flags;
1568 1.31 christos struct lwp *l;
1569 1.1 pk {
1570 1.47 drochner struct mbpp_softc *ms = device_lookup_private(&mbpp_cd,
1571 1.47 drochner MAGMA_CARD(dev));
1572 1.3 pk struct mbpp_port *mp = &ms->ms_port[MAGMA_PORT(dev)];
1573 1.3 pk struct mbpp_param *bp;
1574 1.3 pk int error = 0;
1575 1.3 pk int s;
1576 1.3 pk
1577 1.3 pk switch(cmd) {
1578 1.3 pk case MBPPIOCSPARAM:
1579 1.3 pk bp = (struct mbpp_param *)data;
1580 1.3 pk if( bp->bp_burst < MBPP_BURST_MIN || bp->bp_burst > MBPP_BURST_MAX ||
1581 1.3 pk bp->bp_delay < MBPP_DELAY_MIN || bp->bp_delay > MBPP_DELAY_MIN ) {
1582 1.3 pk error = EINVAL;
1583 1.3 pk } else {
1584 1.3 pk mp->mp_burst = bp->bp_burst;
1585 1.3 pk mp->mp_timeout = mbpp_mstohz(bp->bp_timeout);
1586 1.3 pk mp->mp_delay = mbpp_mstohz(bp->bp_delay);
1587 1.3 pk }
1588 1.3 pk break;
1589 1.3 pk case MBPPIOCGPARAM:
1590 1.3 pk bp = (struct mbpp_param *)data;
1591 1.3 pk bp->bp_burst = mp->mp_burst;
1592 1.3 pk bp->bp_timeout = mbpp_hztoms(mp->mp_timeout);
1593 1.3 pk bp->bp_delay = mbpp_hztoms(mp->mp_delay);
1594 1.3 pk break;
1595 1.3 pk case MBPPIOCGSTAT:
1596 1.3 pk /* XXX make this more generic */
1597 1.3 pk s = spltty();
1598 1.3 pk cd1400_write_reg(mp->mp_cd1400, CD1400_CAR, 0);
1599 1.3 pk *(int *)data = cd1400_read_reg(mp->mp_cd1400, CD1400_PSVR);
1600 1.3 pk splx(s);
1601 1.3 pk break;
1602 1.3 pk default:
1603 1.3 pk error = ENOTTY;
1604 1.3 pk }
1605 1.3 pk
1606 1.3 pk return(error);
1607 1.1 pk }
1608 1.1 pk
1609 1.3 pk int
1610 1.17 gehenna mbpp_rw(dev, uio, flag)
1611 1.3 pk dev_t dev;
1612 1.3 pk struct uio *uio;
1613 1.17 gehenna int flag;
1614 1.3 pk {
1615 1.3 pk int card = MAGMA_CARD(dev);
1616 1.3 pk int port = MAGMA_PORT(dev);
1617 1.47 drochner struct mbpp_softc *ms = device_lookup_private(&mbpp_cd, card);
1618 1.3 pk struct mbpp_port *mp = &ms->ms_port[port];
1619 1.40 mrg char *buffer, *ptr;
1620 1.3 pk int buflen, cnt, len;
1621 1.3 pk int s, error = 0;
1622 1.3 pk int gotdata = 0;
1623 1.3 pk
1624 1.3 pk if( uio->uio_resid == 0 )
1625 1.3 pk return(0);
1626 1.3 pk
1627 1.3 pk buflen = min(uio->uio_resid, mp->mp_burst);
1628 1.3 pk buffer = malloc(buflen, M_DEVBUF, M_WAITOK);
1629 1.3 pk if( buffer == NULL )
1630 1.3 pk return(ENOMEM);
1631 1.3 pk
1632 1.3 pk SET(mp->mp_flags, MBPPF_UIO);
1633 1.3 pk
1634 1.3 pk /*
1635 1.3 pk * start timeout, if needed
1636 1.3 pk */
1637 1.3 pk if( mp->mp_timeout > 0 ) {
1638 1.3 pk SET(mp->mp_flags, MBPPF_TIMEOUT);
1639 1.6 thorpej callout_reset(&mp->mp_timeout_ch, mp->mp_timeout,
1640 1.6 thorpej mbpp_timeout, mp);
1641 1.3 pk }
1642 1.3 pk
1643 1.3 pk len = cnt = 0;
1644 1.3 pk while( uio->uio_resid > 0 ) {
1645 1.3 pk len = min(buflen, uio->uio_resid);
1646 1.3 pk ptr = buffer;
1647 1.3 pk
1648 1.3 pk if( uio->uio_rw == UIO_WRITE ) {
1649 1.3 pk error = uiomove(ptr, len, uio);
1650 1.3 pk if( error ) break;
1651 1.3 pk }
1652 1.3 pk again: /* goto bad */
1653 1.3 pk /* timed out? */
1654 1.3 pk if( !ISSET(mp->mp_flags, MBPPF_UIO) )
1655 1.3 pk break;
1656 1.3 pk
1657 1.3 pk /*
1658 1.3 pk * perform the operation
1659 1.3 pk */
1660 1.3 pk if( uio->uio_rw == UIO_WRITE ) {
1661 1.3 pk cnt = mbpp_send(mp, ptr, len);
1662 1.3 pk } else {
1663 1.3 pk cnt = mbpp_recv(mp, ptr, len);
1664 1.3 pk }
1665 1.3 pk
1666 1.3 pk if( uio->uio_rw == UIO_READ ) {
1667 1.3 pk if( cnt ) {
1668 1.3 pk error = uiomove(ptr, cnt, uio);
1669 1.3 pk if( error ) break;
1670 1.3 pk gotdata++;
1671 1.3 pk }
1672 1.3 pk else if( gotdata ) /* consider us done */
1673 1.3 pk break;
1674 1.3 pk }
1675 1.3 pk
1676 1.3 pk /* timed out? */
1677 1.3 pk if( !ISSET(mp->mp_flags, MBPPF_UIO) )
1678 1.3 pk break;
1679 1.3 pk
1680 1.3 pk /*
1681 1.3 pk * poll delay?
1682 1.3 pk */
1683 1.3 pk if( mp->mp_delay > 0 ) {
1684 1.3 pk s = splsoftclock();
1685 1.3 pk SET(mp->mp_flags, MBPPF_DELAY);
1686 1.6 thorpej callout_reset(&mp->mp_start_ch, mp->mp_delay,
1687 1.6 thorpej mbpp_start, mp);
1688 1.3 pk error = tsleep(mp, PCATCH | PZERO, "mbppdelay", 0);
1689 1.3 pk splx(s);
1690 1.3 pk if( error ) break;
1691 1.3 pk }
1692 1.3 pk
1693 1.3 pk /*
1694 1.3 pk * don't call uiomove again until we used all the data we grabbed
1695 1.3 pk */
1696 1.3 pk if( uio->uio_rw == UIO_WRITE && cnt != len ) {
1697 1.3 pk ptr += cnt;
1698 1.3 pk len -= cnt;
1699 1.3 pk cnt = 0;
1700 1.3 pk goto again;
1701 1.3 pk }
1702 1.3 pk }
1703 1.3 pk
1704 1.3 pk /*
1705 1.3 pk * clear timeouts
1706 1.3 pk */
1707 1.3 pk s = splsoftclock();
1708 1.3 pk if( ISSET(mp->mp_flags, MBPPF_TIMEOUT) ) {
1709 1.6 thorpej callout_stop(&mp->mp_timeout_ch);
1710 1.3 pk CLR(mp->mp_flags, MBPPF_TIMEOUT);
1711 1.3 pk }
1712 1.3 pk if( ISSET(mp->mp_flags, MBPPF_DELAY) ) {
1713 1.6 thorpej callout_stop(&mp->mp_start_ch);
1714 1.3 pk CLR(mp->mp_flags, MBPPF_DELAY);
1715 1.3 pk }
1716 1.3 pk splx(s);
1717 1.3 pk
1718 1.3 pk /*
1719 1.3 pk * adjust for those chars that we uiomoved but never actually wrote
1720 1.3 pk */
1721 1.3 pk if( uio->uio_rw == UIO_WRITE && cnt != len ) {
1722 1.3 pk uio->uio_resid += (len - cnt);
1723 1.3 pk }
1724 1.3 pk
1725 1.3 pk free(buffer, M_DEVBUF);
1726 1.3 pk return(error);
1727 1.3 pk }
1728 1.3 pk
1729 1.3 pk void
1730 1.3 pk mbpp_timeout(arg)
1731 1.3 pk void *arg;
1732 1.3 pk {
1733 1.3 pk struct mbpp_port *mp = arg;
1734 1.3 pk
1735 1.3 pk CLR(mp->mp_flags, MBPPF_UIO | MBPPF_TIMEOUT);
1736 1.3 pk wakeup(mp);
1737 1.3 pk }
1738 1.3 pk
1739 1.3 pk void
1740 1.3 pk mbpp_start(arg)
1741 1.3 pk void *arg;
1742 1.3 pk {
1743 1.3 pk struct mbpp_port *mp = arg;
1744 1.3 pk
1745 1.3 pk CLR(mp->mp_flags, MBPPF_DELAY);
1746 1.3 pk wakeup(mp);
1747 1.3 pk }
1748 1.3 pk
1749 1.3 pk int
1750 1.3 pk mbpp_send(mp, ptr, len)
1751 1.3 pk struct mbpp_port *mp;
1752 1.39 christos void *ptr;
1753 1.3 pk int len;
1754 1.3 pk {
1755 1.3 pk int s;
1756 1.3 pk struct cd1400 *cd = mp->mp_cd1400;
1757 1.3 pk
1758 1.3 pk /* set up io information */
1759 1.3 pk mp->mp_ptr = ptr;
1760 1.3 pk mp->mp_cnt = len;
1761 1.3 pk
1762 1.3 pk /* start transmitting */
1763 1.3 pk s = spltty();
1764 1.3 pk if( cd ) {
1765 1.3 pk cd1400_write_reg(cd, CD1400_CAR, 0);
1766 1.3 pk
1767 1.3 pk /* output strobe width ~1microsecond */
1768 1.3 pk cd1400_write_reg(cd, CD1400_TBPR, 10);
1769 1.3 pk
1770 1.3 pk /* enable channel */
1771 1.3 pk cd1400_write_ccr(cd, CD1400_CCR_CMDCHANCTL | CD1400_CCR_XMTEN);
1772 1.3 pk cd1400_write_reg(cd, CD1400_SRER, CD1400_SRER_TXRDY);
1773 1.3 pk }
1774 1.3 pk
1775 1.3 pk /* ZZzzz... */
1776 1.3 pk tsleep(mp, PCATCH | PZERO, "mbpp_send", 0);
1777 1.3 pk
1778 1.3 pk /* stop transmitting */
1779 1.3 pk if( cd ) {
1780 1.3 pk cd1400_write_reg(cd, CD1400_CAR, 0);
1781 1.3 pk
1782 1.3 pk /* disable transmitter */
1783 1.3 pk cd1400_write_reg(cd, CD1400_SRER, 0);
1784 1.3 pk cd1400_write_ccr(cd, CD1400_CCR_CMDCHANCTL | CD1400_CCR_XMTDIS);
1785 1.3 pk
1786 1.3 pk /* flush fifo */
1787 1.3 pk cd1400_write_ccr(cd, CD1400_CCR_CMDRESET | CD1400_CCR_FTF);
1788 1.3 pk }
1789 1.3 pk splx(s);
1790 1.3 pk
1791 1.3 pk /* return number of chars sent */
1792 1.3 pk return(len - mp->mp_cnt);
1793 1.3 pk }
1794 1.3 pk
1795 1.3 pk int
1796 1.3 pk mbpp_recv(mp, ptr, len)
1797 1.3 pk struct mbpp_port *mp;
1798 1.39 christos void *ptr;
1799 1.3 pk int len;
1800 1.3 pk {
1801 1.3 pk int s;
1802 1.3 pk struct cd1400 *cd = mp->mp_cd1400;
1803 1.3 pk
1804 1.3 pk /* set up io information */
1805 1.3 pk mp->mp_ptr = ptr;
1806 1.3 pk mp->mp_cnt = len;
1807 1.3 pk
1808 1.3 pk /* start receiving */
1809 1.3 pk s = spltty();
1810 1.3 pk if( cd ) {
1811 1.3 pk int rcor, rbpr;
1812 1.3 pk
1813 1.3 pk cd1400_write_reg(cd, CD1400_CAR, 0);
1814 1.3 pk
1815 1.3 pk /* input strobe at 100kbaud (10microseconds) */
1816 1.3 pk cd1400_compute_baud(100000, cd->cd_clock, &rcor, &rbpr);
1817 1.3 pk cd1400_write_reg(cd, CD1400_RCOR, rcor);
1818 1.3 pk cd1400_write_reg(cd, CD1400_RBPR, rbpr);
1819 1.3 pk
1820 1.3 pk /* rx threshold */
1821 1.3 pk cd1400_write_reg(cd, CD1400_COR3, MBPP_RX_FIFO_THRESHOLD);
1822 1.3 pk cd1400_write_ccr(cd, CD1400_CCR_CMDCORCHG | CD1400_CCR_COR3);
1823 1.3 pk
1824 1.3 pk /* enable channel */
1825 1.3 pk cd1400_write_ccr(cd, CD1400_CCR_CMDCHANCTL | CD1400_CCR_RCVEN);
1826 1.3 pk cd1400_write_reg(cd, CD1400_SRER, CD1400_SRER_RXDATA);
1827 1.3 pk }
1828 1.3 pk
1829 1.3 pk /* ZZzzz... */
1830 1.3 pk tsleep(mp, PCATCH | PZERO, "mbpp_recv", 0);
1831 1.3 pk
1832 1.3 pk /* stop receiving */
1833 1.3 pk if( cd ) {
1834 1.3 pk cd1400_write_reg(cd, CD1400_CAR, 0);
1835 1.3 pk
1836 1.3 pk /* disable receiving */
1837 1.3 pk cd1400_write_reg(cd, CD1400_SRER, 0);
1838 1.3 pk cd1400_write_ccr(cd, CD1400_CCR_CMDCHANCTL | CD1400_CCR_RCVDIS);
1839 1.3 pk }
1840 1.3 pk splx(s);
1841 1.3 pk
1842 1.3 pk /* return number of chars received */
1843 1.3 pk return(len - mp->mp_cnt);
1844 1.3 pk }
1845 1.3 pk
1846 1.3 pk int
1847 1.3 pk mbpp_hztoms(h)
1848 1.3 pk int h;
1849 1.3 pk {
1850 1.3 pk int m = h;
1851 1.3 pk
1852 1.3 pk if( m > 0 )
1853 1.3 pk m = m * 1000 / hz;
1854 1.3 pk return(m);
1855 1.3 pk }
1856 1.3 pk
1857 1.3 pk int
1858 1.3 pk mbpp_mstohz(m)
1859 1.3 pk int m;
1860 1.3 pk {
1861 1.3 pk int h = m;
1862 1.3 pk
1863 1.3 pk if( h > 0 ) {
1864 1.3 pk h = h * hz / 1000;
1865 1.3 pk if( h == 0 )
1866 1.3 pk h = 1000 / hz;
1867 1.3 pk }
1868 1.3 pk return(h);
1869 1.1 pk }
1870 1.1 pk
1871 1.1 pk #endif /* NMAGMA */
1872