magma.c revision 1.10.4.3
1 /* $NetBSD: magma.c,v 1.10.4.3 2001/10/13 17:42:49 fvdl Exp $ */ 2 /* 3 * magma.c 4 * 5 * Copyright (c) 1998 Iain Hibbert 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Iain Hibbert 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 */ 34 #if 0 35 #define MAGMA_DEBUG 36 #endif 37 38 /* 39 * Driver for Magma SBus Serial/Parallel cards using the Cirrus Logic 40 * CD1400 & CD1190 chips 41 */ 42 43 #include "magma.h" 44 #if NMAGMA > 0 45 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/proc.h> 49 #include <sys/device.h> 50 #include <sys/file.h> 51 #include <sys/ioctl.h> 52 #include <sys/malloc.h> 53 #include <sys/tty.h> 54 #include <sys/time.h> 55 #include <sys/kernel.h> 56 #include <sys/syslog.h> 57 #include <sys/conf.h> 58 #include <sys/errno.h> 59 #include <sys/vnode.h> 60 61 #include <machine/bus.h> 62 #include <machine/intr.h> 63 #include <machine/autoconf.h> 64 #include <machine/conf.h> 65 66 #include <dev/sbus/sbusvar.h> 67 68 #include <dev/ic/cd1400reg.h> 69 #include <dev/ic/cd1190reg.h> 70 71 #include <dev/sbus/mbppio.h> 72 #include <dev/sbus/magmareg.h> 73 74 /* 75 * Select tty soft interrupt bit based on TTY ipl. (stole from zs.c) 76 */ 77 #if PIL_TTY == 1 78 # define IE_MSOFT IE_L1 79 #elif PIL_TTY == 4 80 # define IE_MSOFT IE_L4 81 #elif PIL_TTY == 6 82 # define IE_MSOFT IE_L6 83 #else 84 # error "no suitable software interrupt bit" 85 #endif 86 87 /* supported cards 88 * 89 * The table below lists the cards that this driver is likely to 90 * be able to support. 91 * 92 * Cards with parallel ports: except for the LC2+1Sp, they all use 93 * the CD1190 chip which I know nothing about. I've tried to leave 94 * hooks for it so it shouldn't be too hard to add support later. 95 * (I think somebody is working on this separately) 96 * 97 * Thanks to Bruce at Magma for telling me the hardware offsets. 98 */ 99 static struct magma_board_info supported_cards[] = { 100 { 101 "MAGMA,4_Sp", "Magma 4 Sp", 4, 0, 102 1, 0xa000, 0xc000, 0xe000, { 0x8000, 0, 0, 0 }, 103 0, { 0, 0 } 104 }, 105 { 106 "MAGMA,8_Sp", "Magma 8 Sp", 8, 0, 107 2, 0xa000, 0xc000, 0xe000, { 0x4000, 0x6000, 0, 0 }, 108 0, { 0, 0 } 109 }, 110 { 111 "MAGMA,_8HS_Sp", "Magma Fast 8 Sp", 8, 0, 112 2, 0x2000, 0x4000, 0x6000, { 0x8000, 0xa000, 0, 0 }, 113 0, { 0, 0 } 114 }, 115 { 116 "MAGMA,_8SP_422", "Magma 8 Sp - 422", 8, 0, 117 2, 0x2000, 0x4000, 0x6000, { 0x8000, 0xa000, 0, 0 }, 118 0, { 0, 0 } 119 }, 120 { 121 "MAGMA,12_Sp", "Magma 12 Sp", 12, 0, 122 3, 0xa000, 0xc000, 0xe000, { 0x2000, 0x4000, 0x6000, 0 }, 123 0, { 0, 0 } 124 }, 125 { 126 "MAGMA,16_Sp", "Magma 16 Sp", 16, 0, 127 4, 0xd000, 0xe000, 0xf000, { 0x8000, 0x9000, 0xa000, 0xb000 }, 128 0, { 0, 0 } 129 }, 130 { 131 "MAGMA,16_Sp_2", "Magma 16 Sp", 16, 0, 132 4, 0x2000, 0x4000, 0x6000, { 0x8000, 0xa000, 0xc000, 0xe000 }, 133 0, { 0, 0 } 134 }, 135 { 136 "MAGMA,16HS_Sp", "Magma Fast 16 Sp", 16, 0, 137 4, 0x2000, 0x4000, 0x6000, { 0x8000, 0xa000, 0xc000, 0xe000 }, 138 0, { 0, 0 } 139 }, 140 { 141 "MAGMA,21_Sp", "Magma LC 2+1 Sp", 2, 1, 142 1, 0xa000, 0xc000, 0xe000, { 0x8000, 0, 0, 0 }, 143 0, { 0, 0 } 144 }, 145 { 146 "MAGMA,21HS_Sp", "Magma 2+1 Sp", 2, 1, 147 1, 0xa000, 0xc000, 0xe000, { 0x4000, 0, 0, 0 }, 148 1, { 0x6000, 0 } 149 }, 150 { 151 "MAGMA,41_Sp", "Magma 4+1 Sp", 4, 1, 152 1, 0xa000, 0xc000, 0xe000, { 0x4000, 0, 0, 0 }, 153 1, { 0x6000, 0 } 154 }, 155 { 156 "MAGMA,82_Sp", "Magma 8+2 Sp", 8, 2, 157 2, 0xd000, 0xe000, 0xf000, { 0x8000, 0x9000, 0, 0 }, 158 2, { 0xa000, 0xb000 } 159 }, 160 { 161 "MAGMA,P1_Sp", "Magma P1 Sp", 0, 1, 162 0, 0, 0, 0, { 0, 0, 0, 0 }, 163 1, { 0x8000, 0 } 164 }, 165 { 166 "MAGMA,P2_Sp", "Magma P2 Sp", 0, 2, 167 0, 0, 0, 0, { 0, 0, 0, 0 }, 168 2, { 0x4000, 0x8000 } 169 }, 170 { 171 NULL, NULL, 0, 0, 172 0, 0, 0, 0, { 0, 0, 0, 0 }, 173 0, { 0, 0 } 174 } 175 }; 176 177 /************************************************************************ 178 * 179 * Autoconfig Stuff 180 */ 181 182 struct cfattach magma_ca = { 183 sizeof(struct magma_softc), magma_match, magma_attach 184 }; 185 186 struct cfattach mtty_ca = { 187 sizeof(struct mtty_softc), mtty_match, mtty_attach 188 }; 189 190 struct cfattach mbpp_ca = { 191 sizeof(struct mbpp_softc), mbpp_match, mbpp_attach 192 }; 193 194 extern struct cfdriver mtty_cd; 195 extern struct cfdriver mbpp_cd; 196 197 /************************************************************************ 198 * 199 * CD1400 Routines 200 * 201 * cd1400_compute_baud calculate COR/BPR register values 202 * cd1400_write_ccr write a value to CD1400 ccr 203 * cd1400_read_reg read from a CD1400 register 204 * cd1400_write_reg write to a CD1400 register 205 * cd1400_enable_transmitter enable transmitting on CD1400 channel 206 */ 207 208 /* 209 * compute the bpr/cor pair for any baud rate 210 * returns 0 for success, 1 for failure 211 */ 212 int 213 cd1400_compute_baud(speed, clock, cor, bpr) 214 speed_t speed; 215 int clock; 216 int *cor, *bpr; 217 { 218 int c, co, br; 219 220 if( speed < 50 || speed > 150000 ) 221 return(1); 222 223 for( c = 0, co = 8 ; co <= 2048 ; co <<= 2, c++ ) { 224 br = ((clock * 1000000) + (co * speed) / 2) / (co * speed); 225 if( br < 0x100 ) { 226 *bpr = br; 227 *cor = c; 228 return(0); 229 } 230 } 231 232 return(1); 233 } 234 235 /* 236 * Write a CD1400 channel command, should have a timeout? 237 */ 238 __inline void 239 cd1400_write_ccr(cd, cmd) 240 struct cd1400 *cd; 241 u_char cmd; 242 { 243 while( cd1400_read_reg(cd, CD1400_CCR) ) 244 ; 245 246 cd1400_write_reg(cd, CD1400_CCR, cmd); 247 } 248 249 /* 250 * read a value from a cd1400 register 251 */ 252 __inline u_char 253 cd1400_read_reg(cd, reg) 254 struct cd1400 *cd; 255 int reg; 256 { 257 return(cd->cd_reg[reg]); 258 } 259 260 /* 261 * write a value to a cd1400 register 262 */ 263 __inline void 264 cd1400_write_reg(cd, reg, value) 265 struct cd1400 *cd; 266 int reg; 267 u_char value; 268 { 269 cd->cd_reg[reg] = value; 270 } 271 272 /* 273 * enable transmit service requests for cd1400 channel 274 */ 275 void 276 cd1400_enable_transmitter(cd, channel) 277 struct cd1400 *cd; 278 int channel; 279 { 280 int s, srer; 281 282 s = spltty(); 283 cd1400_write_reg(cd, CD1400_CAR, channel); 284 srer = cd1400_read_reg(cd, CD1400_SRER); 285 SET(srer, CD1400_SRER_TXRDY); 286 cd1400_write_reg(cd, CD1400_SRER, srer); 287 splx(s); 288 } 289 290 /************************************************************************ 291 * 292 * CD1190 Routines 293 */ 294 295 /* well, there are none yet */ 296 297 /************************************************************************ 298 * 299 * Magma Routines 300 * 301 * magma_match reports if we have a magma board available 302 * magma_attach attaches magma boards to the sbus 303 * magma_hard hardware level interrupt routine 304 * magma_soft software level interrupt routine 305 */ 306 307 int 308 magma_match(parent, cf, aux) 309 struct device *parent; 310 struct cfdata *cf; 311 void *aux; 312 { 313 struct sbus_attach_args *sa = aux; 314 315 /* is it a magma Sp card? */ 316 if( strcmp(sa->sa_name, "MAGMA_Sp") != 0 ) 317 return(0); 318 319 dprintf(("magma: matched `%s'\n", sa->sa_name)); 320 dprintf(("magma: magma_prom `%s'\n", 321 PROM_getpropstring(sa->sa_node, "magma_prom"))); 322 dprintf(("magma: intlevels `%s'\n", 323 PROM_getpropstring(sa->sa_node, "intlevels"))); 324 dprintf(("magma: chiprev `%s'\n", 325 PROM_getpropstring(sa->sa_node, "chiprev"))); 326 dprintf(("magma: clock `%s'\n", 327 PROM_getpropstring(sa->sa_node, "clock"))); 328 329 return (1); 330 } 331 332 void 333 magma_attach(parent, self, aux) 334 struct device *parent; 335 struct device *self; 336 void *aux; 337 { 338 struct sbus_attach_args *sa = aux; 339 struct magma_softc *sc = (struct magma_softc *)self; 340 struct magma_board_info *card = supported_cards; 341 bus_space_handle_t bh; 342 char *magma_prom; 343 int node, chip; 344 345 node = sa->sa_node; 346 magma_prom = PROM_getpropstring(node, "magma_prom"); 347 348 /* find the card type */ 349 while (card->mb_name && strcmp(magma_prom, card->mb_name) != 0) 350 card++; 351 352 dprintf((" addr %p", sc)); 353 printf(" softpri %d:", PIL_TTY); 354 355 if( card->mb_name == NULL ) { 356 printf(" %s (unsupported)\n", magma_prom); 357 return; 358 } 359 360 printf(" %s\n", card->mb_realname); 361 362 sc->ms_board = card; 363 sc->ms_ncd1400 = card->mb_ncd1400; 364 sc->ms_ncd1190 = card->mb_ncd1190; 365 366 if (sbus_bus_map(sa->sa_bustag, 367 sa->sa_slot, 368 sa->sa_offset, 369 sa->sa_size, 370 BUS_SPACE_MAP_LINEAR, 371 0, &bh) != 0) { 372 printf("%s @ sbus: cannot map registers\n", self->dv_xname); 373 return; 374 } 375 376 /* the SVCACK* lines are daisychained */ 377 sc->ms_svcackr = (caddr_t)bh + card->mb_svcackr; 378 sc->ms_svcackt = (caddr_t)bh + card->mb_svcackt; 379 sc->ms_svcackm = (caddr_t)bh + card->mb_svcackm; 380 381 /* init the cd1400 chips */ 382 for( chip = 0 ; chip < card->mb_ncd1400 ; chip++ ) { 383 struct cd1400 *cd = &sc->ms_cd1400[chip]; 384 385 cd->cd_reg = (caddr_t)bh + card->mb_cd1400[chip]; 386 387 /* XXX PROM_getpropstring(node, "clock") */ 388 cd->cd_clock = 25; 389 390 /* PROM_getpropstring(node, "chiprev"); */ 391 /* seemingly the Magma drivers just ignore the propstring */ 392 cd->cd_chiprev = cd1400_read_reg(cd, CD1400_GFRCR); 393 394 dprintf(("%s attach CD1400 %d addr %p rev %x clock %dMhz\n", 395 sc->ms_dev.dv_xname, chip, 396 cd->cd_reg, cd->cd_chiprev, cd->cd_clock)); 397 398 /* clear GFRCR */ 399 cd1400_write_reg(cd, CD1400_GFRCR, 0x00); 400 401 /* reset whole chip */ 402 cd1400_write_ccr(cd, CD1400_CCR_CMDRESET | CD1400_CCR_FULLRESET); 403 404 /* wait for revision code to be restored */ 405 while( cd1400_read_reg(cd, CD1400_GFRCR) != cd->cd_chiprev ) 406 ; 407 408 /* set the Prescaler Period Register to tick at 1ms */ 409 cd1400_write_reg(cd, CD1400_PPR, 410 ((cd->cd_clock * 1000000 / CD1400_PPR_PRESCALER + 500) / 1000)); 411 412 /* The LC2+1Sp card is the only card that doesn't have 413 * a CD1190 for the parallel port, but uses channel 0 of 414 * the CD1400, so we make a note of it for later and set up 415 * the CD1400 for parallel mode operation. 416 */ 417 if( card->mb_npar && card->mb_ncd1190 == 0 ) { 418 cd1400_write_reg(cd, CD1400_GCR, CD1400_GCR_PARALLEL); 419 cd->cd_parmode = 1; 420 } 421 } 422 423 /* init the cd1190 chips */ 424 for( chip = 0 ; chip < card->mb_ncd1190 ; chip++ ) { 425 struct cd1190 *cd = &sc->ms_cd1190[chip]; 426 427 cd->cd_reg = (caddr_t)bh + card->mb_cd1190[chip]; 428 dprintf(("%s attach CD1190 %d addr %p (failed)\n", 429 self->dv_xname, chip, cd->cd_reg)); 430 /* XXX don't know anything about these chips yet */ 431 } 432 433 sbus_establish(&sc->ms_sd, &sc->ms_dev); 434 435 /* configure the children */ 436 (void)config_found(self, mtty_match, NULL); 437 (void)config_found(self, mbpp_match, NULL); 438 439 /* 440 * Establish the interrupt handlers. 441 */ 442 if (sa->sa_nintr == 0) 443 return; /* No interrupts to service!? */ 444 445 (void)bus_intr_establish(sa->sa_bustag, sa->sa_pri, IPL_TTY, 446 0, magma_hard, sc); 447 (void)bus_intr_establish(sa->sa_bustag, PIL_TTY, IPL_SOFTSERIAL, 448 BUS_INTR_ESTABLISH_SOFTINTR, 449 magma_soft, sc); 450 evcnt_attach_dynamic(&sc->ms_intrcnt, EVCNT_TYPE_INTR, NULL, 451 sc->ms_dev.dv_xname, "intr"); 452 } 453 454 /* 455 * hard interrupt routine 456 * 457 * returns 1 if it handled it, otherwise 0 458 * 459 * runs at interrupt priority 460 */ 461 int 462 magma_hard(arg) 463 void *arg; 464 { 465 struct magma_softc *sc = arg; 466 struct cd1400 *cd; 467 int chip, status = 0; 468 int serviced = 0; 469 int needsoftint = 0; 470 471 /* 472 * check status of all the CD1400 chips 473 */ 474 for( chip = 0 ; chip < sc->ms_ncd1400 ; chip++ ) 475 status |= cd1400_read_reg(&sc->ms_cd1400[chip], CD1400_SVRR); 476 477 if( ISSET(status, CD1400_SVRR_RXRDY) ) { 478 u_char rivr = *sc->ms_svcackr; /* enter rx service context */ 479 int port = rivr >> 4; 480 481 if( rivr & (1<<3) ) { /* parallel port */ 482 struct mbpp_port *mbpp; 483 int n_chars; 484 485 mbpp = &sc->ms_mbpp->ms_port[port]; 486 cd = mbpp->mp_cd1400; 487 488 /* don't think we have to handle exceptions */ 489 n_chars = cd1400_read_reg(cd, CD1400_RDCR); 490 while (n_chars--) { 491 if( mbpp->mp_cnt == 0 ) { 492 SET(mbpp->mp_flags, MBPPF_WAKEUP); 493 needsoftint = 1; 494 break; 495 } 496 *mbpp->mp_ptr = cd1400_read_reg(cd,CD1400_RDSR); 497 mbpp->mp_ptr++; 498 mbpp->mp_cnt--; 499 } 500 } else { /* serial port */ 501 struct mtty_port *mtty; 502 u_char *ptr, n_chars, line_stat; 503 504 mtty = &sc->ms_mtty->ms_port[port]; 505 cd = mtty->mp_cd1400; 506 507 if( ISSET(rivr, CD1400_RIVR_EXCEPTION) ) { 508 line_stat = cd1400_read_reg(cd, CD1400_RDSR); 509 n_chars = 1; 510 } else { /* no exception, received data OK */ 511 line_stat = 0; 512 n_chars = cd1400_read_reg(cd, CD1400_RDCR); 513 } 514 515 ptr = mtty->mp_rput; 516 while( n_chars-- ) { 517 *ptr++ = line_stat; 518 *ptr++ = cd1400_read_reg(cd, CD1400_RDSR); 519 if( ptr == mtty->mp_rend ) ptr = mtty->mp_rbuf; 520 if( ptr == mtty->mp_rget ) { 521 if( ptr == mtty->mp_rbuf ) 522 ptr = mtty->mp_rend; 523 ptr -= 2; 524 SET(mtty->mp_flags, MTTYF_RING_OVERFLOW); 525 break; 526 } 527 } 528 mtty->mp_rput = ptr; 529 530 needsoftint = 1; 531 } 532 533 cd1400_write_reg(cd, CD1400_EOSRR, 0); /* end service context */ 534 serviced = 1; 535 } /* if(rx_service...) */ 536 537 if( ISSET(status, CD1400_SVRR_MDMCH) ) { 538 u_char mivr = *sc->ms_svcackm; /* enter mdm service context */ 539 int port = mivr >> 4; 540 struct mtty_port *mtty; 541 int carrier; 542 u_char msvr; 543 544 /* 545 * Handle CD (LC2+1Sp = DSR) changes. 546 */ 547 mtty = &sc->ms_mtty->ms_port[port]; 548 cd = mtty->mp_cd1400; 549 msvr = cd1400_read_reg(cd, CD1400_MSVR2); 550 carrier = ISSET(msvr, cd->cd_parmode ? CD1400_MSVR2_DSR : CD1400_MSVR2_CD); 551 552 if( mtty->mp_carrier != carrier ) { 553 SET(mtty->mp_flags, MTTYF_CARRIER_CHANGED); 554 mtty->mp_carrier = carrier; 555 needsoftint = 1; 556 } 557 558 cd1400_write_reg(cd, CD1400_EOSRR, 0); /* end service context */ 559 serviced = 1; 560 } /* if(mdm_service...) */ 561 562 if( ISSET(status, CD1400_SVRR_TXRDY) ) { 563 u_char tivr = *sc->ms_svcackt; /* enter tx service context */ 564 int port = tivr >> 4; 565 566 if( tivr & (1<<3) ) { /* parallel port */ 567 struct mbpp_port *mbpp; 568 569 mbpp = &sc->ms_mbpp->ms_port[port]; 570 cd = mbpp->mp_cd1400; 571 572 if( mbpp->mp_cnt ) { 573 int count = 0; 574 575 /* fill the fifo */ 576 while (mbpp->mp_cnt && 577 count++ < CD1400_PAR_FIFO_SIZE) { 578 cd1400_write_reg(cd, CD1400_TDR, 579 *mbpp->mp_ptr); 580 mbpp->mp_ptr++; 581 mbpp->mp_cnt--; 582 } 583 } else { 584 /* 585 * fifo is empty and we got no more data 586 * to send, so shut off interrupts and 587 * signal for a wakeup, which can't be 588 * done here in case we beat mbpp_send to 589 * the tsleep call (we are running at >spltty) 590 */ 591 cd1400_write_reg(cd, CD1400_SRER, 0); 592 SET(mbpp->mp_flags, MBPPF_WAKEUP); 593 needsoftint = 1; 594 } 595 } else { /* serial port */ 596 struct mtty_port *mtty; 597 struct tty *tp; 598 599 mtty = &sc->ms_mtty->ms_port[port]; 600 cd = mtty->mp_cd1400; 601 tp = mtty->mp_tty; 602 603 if( !ISSET(mtty->mp_flags, MTTYF_STOP) ) { 604 int count = 0; 605 606 /* check if we should start/stop a break */ 607 if( ISSET(mtty->mp_flags, MTTYF_SET_BREAK) ) { 608 cd1400_write_reg(cd, CD1400_TDR, 0); 609 cd1400_write_reg(cd, CD1400_TDR, 0x81); 610 /* should we delay too? */ 611 CLR(mtty->mp_flags, MTTYF_SET_BREAK); 612 count += 2; 613 } 614 615 if( ISSET(mtty->mp_flags, MTTYF_CLR_BREAK) ) { 616 cd1400_write_reg(cd, CD1400_TDR, 0); 617 cd1400_write_reg(cd, CD1400_TDR, 0x83); 618 CLR(mtty->mp_flags, MTTYF_CLR_BREAK); 619 count += 2; 620 } 621 622 /* I don't quite fill the fifo in case the last one is a 623 * NULL which I have to double up because its the escape 624 * code for embedded transmit characters. 625 */ 626 while( mtty->mp_txc > 0 && count < CD1400_TX_FIFO_SIZE - 1 ) { 627 u_char ch; 628 629 ch = *mtty->mp_txp; 630 631 mtty->mp_txc--; 632 mtty->mp_txp++; 633 634 if( ch == 0 ) { 635 cd1400_write_reg(cd, CD1400_TDR, ch); 636 count++; 637 } 638 639 cd1400_write_reg(cd, CD1400_TDR, ch); 640 count++; 641 } 642 } 643 644 /* if we ran out of work or are requested to STOP then 645 * shut off the txrdy interrupts and signal DONE to flush 646 * out the chars we have sent. 647 */ 648 if( mtty->mp_txc == 0 || ISSET(mtty->mp_flags, MTTYF_STOP) ) { 649 register int srer; 650 651 srer = cd1400_read_reg(cd, CD1400_SRER); 652 CLR(srer, CD1400_SRER_TXRDY); 653 cd1400_write_reg(cd, CD1400_SRER, srer); 654 CLR(mtty->mp_flags, MTTYF_STOP); 655 656 SET(mtty->mp_flags, MTTYF_DONE); 657 needsoftint = 1; 658 } 659 } 660 661 cd1400_write_reg(cd, CD1400_EOSRR, 0); /* end service context */ 662 serviced = 1; 663 } /* if(tx_service...) */ 664 665 /* XXX service CD1190 interrupts too 666 for( chip = 0 ; chip < sc->ms_ncd1190 ; chip++ ) { 667 } 668 */ 669 670 if( needsoftint ) { /* trigger the soft interrupt */ 671 #if defined(SUN4M) 672 if( CPU_ISSUN4M ) 673 raise(0, PIL_TTY); 674 else 675 #endif 676 ienab_bis(IE_MSOFT); 677 } 678 679 return(serviced); 680 } 681 682 /* 683 * magma soft interrupt handler 684 * 685 * returns 1 if it handled it, 0 otherwise 686 * 687 * runs at spltty() 688 */ 689 int 690 magma_soft(arg) 691 void *arg; 692 { 693 struct magma_softc *sc = arg; 694 struct mtty_softc *mtty = sc->ms_mtty; 695 struct mbpp_softc *mbpp = sc->ms_mbpp; 696 int port; 697 int serviced = 0; 698 int s, flags; 699 700 if (mtty == NULL) 701 goto chkbpp; 702 703 /* 704 * check the tty ports to see what needs doing 705 */ 706 for( port = 0 ; port < mtty->ms_nports ; port++ ) { 707 struct mtty_port *mp = &mtty->ms_port[port]; 708 struct tty *tp = mp->mp_tty; 709 710 if( !ISSET(tp->t_state, TS_ISOPEN) ) 711 continue; 712 713 /* 714 * handle any received data 715 */ 716 while( mp->mp_rget != mp->mp_rput ) { 717 u_char stat; 718 int data; 719 720 stat = mp->mp_rget[0]; 721 data = mp->mp_rget[1]; 722 mp->mp_rget = ((mp->mp_rget + 2) == mp->mp_rend) 723 ? mp->mp_rbuf : (mp->mp_rget + 2); 724 725 if( stat & (CD1400_RDSR_BREAK | CD1400_RDSR_FE) ) 726 data |= TTY_FE; 727 if( stat & CD1400_RDSR_PE ) 728 data |= TTY_PE; 729 730 if( stat & CD1400_RDSR_OE ) 731 log(LOG_WARNING, "%s%x: fifo overflow\n", 732 mtty->ms_dev.dv_xname, port); 733 734 (*tp->t_linesw->l_rint)(data, tp); 735 serviced = 1; 736 } 737 738 s = splhigh(); /* block out hard interrupt routine */ 739 flags = mp->mp_flags; 740 CLR(mp->mp_flags, MTTYF_DONE | MTTYF_CARRIER_CHANGED | MTTYF_RING_OVERFLOW); 741 splx(s); /* ok */ 742 743 if( ISSET(flags, MTTYF_CARRIER_CHANGED) ) { 744 dprintf(("%s%x: cd %s\n", mtty->ms_dev.dv_xname, 745 port, mp->mp_carrier ? "on" : "off")); 746 (*tp->t_linesw->l_modem)(tp, mp->mp_carrier); 747 serviced = 1; 748 } 749 750 if( ISSET(flags, MTTYF_RING_OVERFLOW) ) { 751 log(LOG_WARNING, "%s%x: ring buffer overflow\n", 752 mtty->ms_dev.dv_xname, port); 753 serviced = 1; 754 } 755 756 if( ISSET(flags, MTTYF_DONE) ) { 757 ndflush(&tp->t_outq, mp->mp_txp - tp->t_outq.c_cf); 758 CLR(tp->t_state, TS_BUSY); 759 (*tp->t_linesw->l_start)(tp); /* might be some more */ 760 serviced = 1; 761 } 762 } /* for(each mtty...) */ 763 764 765 chkbpp: 766 /* 767 * Check the bpp ports (if any) to see what needs doing 768 */ 769 if (mbpp == NULL) 770 return (serviced); 771 772 for( port = 0 ; port < mbpp->ms_nports ; port++ ) { 773 struct mbpp_port *mp = &mbpp->ms_port[port]; 774 775 if( !ISSET(mp->mp_flags, MBPPF_OPEN) ) 776 continue; 777 778 s = splhigh(); 779 flags = mp->mp_flags; 780 CLR(mp->mp_flags, MBPPF_WAKEUP); 781 splx(s); 782 783 if( ISSET(flags, MBPPF_WAKEUP) ) { 784 wakeup(mp); 785 serviced = 1; 786 } 787 788 } /* for(each mbpp...) */ 789 790 return(serviced); 791 } 792 793 /************************************************************************ 794 * 795 * MTTY Routines 796 * 797 * mtty_match match one mtty device 798 * mtty_attach attach mtty devices 799 * mttyopen open mtty device 800 * mttyclose close mtty device 801 * mttyread read from mtty 802 * mttywrite write to mtty 803 * mttyioctl do ioctl on mtty 804 * mttytty return tty pointer for mtty 805 * mttystop stop mtty device 806 * mtty_start start mtty device 807 * mtty_param set mtty parameters 808 * mtty_modem_control set modem control lines 809 */ 810 811 int 812 mtty_match(parent, cf, args) 813 struct device *parent; 814 struct cfdata *cf; 815 void *args; 816 { 817 struct magma_softc *sc = (struct magma_softc *)parent; 818 819 return( args == mtty_match && sc->ms_board->mb_nser && sc->ms_mtty == NULL ); 820 } 821 822 void 823 mtty_attach(parent, dev, args) 824 struct device *parent; 825 struct device *dev; 826 void *args; 827 { 828 struct magma_softc *sc = (struct magma_softc *)parent; 829 struct mtty_softc *ms = (struct mtty_softc *)dev; 830 int port, chip, chan; 831 832 sc->ms_mtty = ms; 833 dprintf((" addr %p", ms)); 834 835 for( port = 0, chip = 0, chan = 0 ; port < sc->ms_board->mb_nser ; port++ ) { 836 struct mtty_port *mp = &ms->ms_port[port]; 837 struct tty *tp; 838 839 mp->mp_cd1400 = &sc->ms_cd1400[chip]; 840 if( mp->mp_cd1400->cd_parmode && chan == 0 ) 841 chan = 1; /* skip channel 0 if parmode */ 842 mp->mp_channel = chan; 843 844 tp = ttymalloc(); 845 if( tp == NULL ) break; 846 tty_attach(tp); 847 tp->t_oproc = mtty_start; 848 tp->t_param = mtty_param; 849 850 mp->mp_tty = tp; 851 852 mp->mp_rbuf = malloc(MTTY_RBUF_SIZE, M_DEVBUF, M_NOWAIT); 853 if( mp->mp_rbuf == NULL ) break; 854 855 mp->mp_rend = mp->mp_rbuf + MTTY_RBUF_SIZE; 856 857 chan = (chan + 1) % CD1400_NO_OF_CHANNELS; 858 if( chan == 0 ) chip++; 859 } 860 861 ms->ms_nports = port; 862 printf(": %d tty%s\n", port, port == 1 ? "" : "s"); 863 } 864 865 /* 866 * open routine. returns zero if successful, else error code 867 */ 868 int 869 mttyopen(devvp, flags, mode, p) 870 struct vnode *devvp; 871 int flags; 872 int mode; 873 struct proc *p; 874 { 875 dev_t dev = vdev_rdev(devvp); 876 int card = MAGMA_CARD(dev); 877 int port = MAGMA_PORT(dev); 878 struct mtty_softc *ms; 879 struct mtty_port *mp; 880 struct tty *tp; 881 struct cd1400 *cd; 882 int error, s; 883 884 if( card >= mtty_cd.cd_ndevs || 885 (ms = mtty_cd.cd_devs[card]) == NULL || port >= ms->ms_nports ) 886 return(ENXIO); /* device not configured */ 887 888 mp = &ms->ms_port[port]; 889 tp = mp->mp_tty; 890 tp->t_dev = dev; 891 892 if (ISSET(tp->t_state, TS_ISOPEN) && 893 ISSET(tp->t_state, TS_XCLUDE) && 894 p->p_ucred->cr_uid != 0) 895 return (EBUSY); 896 897 vdev_setprivdata(devvp, ms); 898 899 s = spltty(); 900 901 if( !ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 902 903 /* set defaults */ 904 ttychars(tp); 905 tp->t_iflag = TTYDEF_IFLAG; 906 tp->t_oflag = TTYDEF_OFLAG; 907 tp->t_cflag = TTYDEF_CFLAG; 908 if( ISSET(mp->mp_openflags, TIOCFLAG_CLOCAL) ) 909 SET(tp->t_cflag, CLOCAL); 910 if( ISSET(mp->mp_openflags, TIOCFLAG_CRTSCTS) ) 911 SET(tp->t_cflag, CRTSCTS); 912 if( ISSET(mp->mp_openflags, TIOCFLAG_MDMBUF) ) 913 SET(tp->t_cflag, MDMBUF); 914 tp->t_lflag = TTYDEF_LFLAG; 915 tp->t_ispeed = tp->t_ospeed = TTYDEF_SPEED; 916 917 /* init ring buffer */ 918 mp->mp_rput = mp->mp_rget = mp->mp_rbuf; 919 920 /* reset CD1400 channel */ 921 cd = mp->mp_cd1400; 922 cd1400_write_reg(cd, CD1400_CAR, mp->mp_channel); 923 cd1400_write_ccr(cd, CD1400_CCR_CMDRESET); 924 925 /* encode the port number in top half of LIVR */ 926 cd1400_write_reg(cd, CD1400_LIVR, port << 4 ); 927 928 /* sets parameters and raises DTR */ 929 (void)mtty_param(tp, &tp->t_termios); 930 931 /* set tty watermarks */ 932 ttsetwater(tp); 933 934 /* enable service requests */ 935 cd1400_write_reg(cd, CD1400_SRER, 936 CD1400_SRER_RXDATA | CD1400_SRER_MDMCH); 937 938 /* tell the tty about the carrier status */ 939 if( ISSET(mp->mp_openflags, TIOCFLAG_SOFTCAR) || 940 mp->mp_carrier ) 941 SET(tp->t_state, TS_CARR_ON); 942 else 943 CLR(tp->t_state, TS_CARR_ON); 944 } 945 splx(s); 946 947 error = ttyopen(tp, MTTY_DIALOUT(dev), ISSET(flags, O_NONBLOCK)); 948 if (error != 0) 949 goto bad; 950 951 error = (*tp->t_linesw->l_open)(devvp, tp); 952 if (error != 0) 953 goto bad; 954 955 bad: 956 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 957 /* 958 * We failed to open the device, and nobody else had it opened. 959 * Clean up the state as appropriate. 960 */ 961 /* XXX - do that here */ 962 } 963 964 return (error); 965 } 966 967 /* 968 * close routine. returns zero if successful, else error code 969 */ 970 int 971 mttyclose(devvp, flag, mode, p) 972 struct vnode *devvp; 973 int flag; 974 int mode; 975 struct proc *p; 976 { 977 dev_t dev = vdev_rdev(devvp); 978 struct mtty_softc *ms = vdev_privdata(devvp); 979 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(dev)]; 980 struct tty *tp = mp->mp_tty; 981 int s; 982 983 (*tp->t_linesw->l_close)(tp, flag); 984 ttyclose(tp); 985 986 s = spltty(); 987 988 /* if HUPCL is set, and the tty is no longer open 989 * shut down the port 990 */ 991 if( ISSET(tp->t_cflag, HUPCL) || !ISSET(tp->t_state, TS_ISOPEN) ) { 992 /* XXX wait until FIFO is empty before turning off the channel 993 struct cd1400 *cd = mp->mp_cd1400; 994 */ 995 996 /* drop DTR and RTS */ 997 (void)mtty_modem_control(mp, 0, DMSET); 998 999 /* turn off the channel 1000 cd1400_write_reg(cd, CD1400_CAR, mp->mp_channel); 1001 cd1400_write_ccr(cd, CD1400_CCR_CMDRESET); 1002 */ 1003 } 1004 1005 splx(s); 1006 1007 return(0); 1008 } 1009 1010 /* 1011 * Read routine 1012 */ 1013 int 1014 mttyread(devvp, uio, flags) 1015 struct vnode *devvp; 1016 struct uio *uio; 1017 int flags; 1018 { 1019 dev_t dev = vdev_rdev(devvp); 1020 struct mtty_softc *ms = vdev_privdata(devvp); 1021 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(dev)]; 1022 struct tty *tp = mp->mp_tty; 1023 1024 return( (*tp->t_linesw->l_read)(tp, uio, flags) ); 1025 } 1026 1027 /* 1028 * Write routine 1029 */ 1030 int 1031 mttywrite(devvp, uio, flags) 1032 struct vnode *devvp; 1033 struct uio *uio; 1034 int flags; 1035 { 1036 dev_t dev = vdev_rdev(devvp); 1037 struct mtty_softc *ms = vdev_privdata(devvp); 1038 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(dev)]; 1039 struct tty *tp = mp->mp_tty; 1040 1041 return( (*tp->t_linesw->l_write)(tp, uio, flags) ); 1042 } 1043 1044 /* 1045 * Poll routine 1046 */ 1047 int 1048 mttypoll(devvp, events, p) 1049 struct vnode *devvp; 1050 int events; 1051 struct proc *p; 1052 { 1053 dev_t dev = vdev_rdev(devvp); 1054 struct mtty_softc *ms = vdev_privdata(devvp); 1055 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(dev)]; 1056 struct tty *tp = mp->mp_tty; 1057 1058 return ((*tp->t_linesw->l_poll)(tp, events, p)); 1059 } 1060 1061 /* 1062 * return tty pointer 1063 */ 1064 struct tty * 1065 mttytty(devvp) 1066 struct vnode *devvp; 1067 { 1068 dev_t dev = vdev_rdev(devvp); 1069 struct mtty_softc *ms = vdev_privdata(devvp); 1070 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(dev)]; 1071 1072 return(mp->mp_tty); 1073 } 1074 1075 /* 1076 * ioctl routine 1077 */ 1078 int 1079 mttyioctl(devvp, cmd, data, flags, p) 1080 struct vnode *devvp; 1081 u_long cmd; 1082 caddr_t data; 1083 int flags; 1084 struct proc *p; 1085 { 1086 dev_t dev = vdev_rdev(devvp); 1087 struct mtty_softc *ms = vdev_privdata(devvp); 1088 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(dev)]; 1089 struct tty *tp = mp->mp_tty; 1090 int error; 1091 1092 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flags, p); 1093 if( error >= 0 ) return(error); 1094 1095 error = ttioctl(tp, devvp, cmd, data, flags, p); 1096 if( error >= 0 ) return(error); 1097 1098 error = 0; 1099 1100 switch(cmd) { 1101 case TIOCSBRK: /* set break */ 1102 SET(mp->mp_flags, MTTYF_SET_BREAK); 1103 cd1400_enable_transmitter(mp->mp_cd1400, mp->mp_channel); 1104 break; 1105 1106 case TIOCCBRK: /* clear break */ 1107 SET(mp->mp_flags, MTTYF_CLR_BREAK); 1108 cd1400_enable_transmitter(mp->mp_cd1400, mp->mp_channel); 1109 break; 1110 1111 case TIOCSDTR: /* set DTR */ 1112 mtty_modem_control(mp, TIOCM_DTR, DMBIS); 1113 break; 1114 1115 case TIOCCDTR: /* clear DTR */ 1116 mtty_modem_control(mp, TIOCM_DTR, DMBIC); 1117 break; 1118 1119 case TIOCMSET: /* set modem lines */ 1120 mtty_modem_control(mp, *((int *)data), DMSET); 1121 break; 1122 1123 case TIOCMBIS: /* bit set modem lines */ 1124 mtty_modem_control(mp, *((int *)data), DMBIS); 1125 break; 1126 1127 case TIOCMBIC: /* bit clear modem lines */ 1128 mtty_modem_control(mp, *((int *)data), DMBIC); 1129 break; 1130 1131 case TIOCMGET: /* get modem lines */ 1132 *((int *)data) = mtty_modem_control(mp, 0, DMGET); 1133 break; 1134 1135 case TIOCGFLAGS: 1136 *((int *)data) = mp->mp_openflags; 1137 break; 1138 1139 case TIOCSFLAGS: 1140 if( suser(p->p_ucred, &p->p_acflag) ) 1141 error = EPERM; 1142 else 1143 mp->mp_openflags = *((int *)data) & 1144 (TIOCFLAG_SOFTCAR | TIOCFLAG_CLOCAL | 1145 TIOCFLAG_CRTSCTS | TIOCFLAG_MDMBUF); 1146 break; 1147 1148 default: 1149 error = ENOTTY; 1150 } 1151 1152 return(error); 1153 } 1154 1155 /* 1156 * Stop output, e.g., for ^S or output flush. 1157 */ 1158 void 1159 mttystop(tp, flags) 1160 struct tty *tp; 1161 int flags; 1162 { 1163 dev_t dev = tp->t_dev; 1164 struct mtty_softc *ms = mtty_cd.cd_devs[MAGMA_CARD(dev)]; 1165 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(dev)]; 1166 int s; 1167 1168 s = spltty(); 1169 1170 if( ISSET(tp->t_state, TS_BUSY) ) { 1171 if( !ISSET(tp->t_state, TS_TTSTOP) ) 1172 SET(tp->t_state, TS_FLUSH); 1173 1174 /* 1175 * the transmit interrupt routine will disable transmit when it 1176 * notices that MTTYF_STOP has been set. 1177 */ 1178 SET(mp->mp_flags, MTTYF_STOP); 1179 } 1180 1181 splx(s); 1182 } 1183 1184 /* 1185 * Start output, after a stop. 1186 */ 1187 void 1188 mtty_start(tp) 1189 struct tty *tp; 1190 { 1191 dev_t dev = tp->t_dev; 1192 struct mtty_softc *ms = mtty_cd.cd_devs[MAGMA_CARD(dev)]; 1193 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(dev)]; 1194 int s; 1195 1196 s = spltty(); 1197 1198 /* we only need to do something if we are not already busy 1199 * or delaying or stopped 1200 */ 1201 if( !ISSET(tp->t_state, TS_TTSTOP | TS_TIMEOUT | TS_BUSY) ) { 1202 1203 /* if we are sleeping and output has drained below 1204 * low water mark, awaken 1205 */ 1206 if( tp->t_outq.c_cc <= tp->t_lowat ) { 1207 if( ISSET(tp->t_state, TS_ASLEEP) ) { 1208 CLR(tp->t_state, TS_ASLEEP); 1209 wakeup(&tp->t_outq); 1210 } 1211 1212 selwakeup(&tp->t_wsel); 1213 } 1214 1215 /* if something to send, start transmitting 1216 */ 1217 if( tp->t_outq.c_cc ) { 1218 mp->mp_txc = ndqb(&tp->t_outq, 0); 1219 mp->mp_txp = tp->t_outq.c_cf; 1220 SET(tp->t_state, TS_BUSY); 1221 cd1400_enable_transmitter(mp->mp_cd1400, mp->mp_channel); 1222 } 1223 } 1224 1225 splx(s); 1226 } 1227 1228 /* 1229 * set/get modem line status 1230 * 1231 * bits can be: TIOCM_DTR, TIOCM_RTS, TIOCM_CTS, TIOCM_CD, TIOCM_RI, TIOCM_DSR 1232 * 1233 * note that DTR and RTS lines are exchanged, and that DSR is 1234 * not available on the LC2+1Sp card (used as CD) 1235 * 1236 * only let them fiddle with RTS if CRTSCTS is not enabled 1237 */ 1238 int 1239 mtty_modem_control(mp, bits, howto) 1240 struct mtty_port *mp; 1241 int bits; 1242 int howto; 1243 { 1244 struct cd1400 *cd = mp->mp_cd1400; 1245 struct tty *tp = mp->mp_tty; 1246 int s, msvr; 1247 1248 s = spltty(); 1249 1250 cd1400_write_reg(cd, CD1400_CAR, mp->mp_channel); 1251 1252 switch(howto) { 1253 case DMGET: /* get bits */ 1254 bits = 0; 1255 1256 bits |= TIOCM_LE; 1257 1258 msvr = cd1400_read_reg(cd, CD1400_MSVR1); 1259 if( msvr & CD1400_MSVR1_RTS ) bits |= TIOCM_DTR; 1260 1261 msvr = cd1400_read_reg(cd, CD1400_MSVR2); 1262 if( msvr & CD1400_MSVR2_DTR ) bits |= TIOCM_RTS; 1263 if( msvr & CD1400_MSVR2_CTS ) bits |= TIOCM_CTS; 1264 if( msvr & CD1400_MSVR2_RI ) bits |= TIOCM_RI; 1265 if( msvr & CD1400_MSVR2_DSR ) bits |= (cd->cd_parmode ? TIOCM_CD : TIOCM_DSR); 1266 if( msvr & CD1400_MSVR2_CD ) bits |= (cd->cd_parmode ? 0 : TIOCM_CD); 1267 1268 break; 1269 1270 case DMSET: /* reset bits */ 1271 if( !ISSET(tp->t_cflag, CRTSCTS) ) 1272 cd1400_write_reg(cd, CD1400_MSVR2, ((bits & TIOCM_RTS) ? CD1400_MSVR2_DTR : 0)); 1273 1274 cd1400_write_reg(cd, CD1400_MSVR1, ((bits & TIOCM_DTR) ? CD1400_MSVR1_RTS : 0)); 1275 1276 break; 1277 1278 case DMBIS: /* set bits */ 1279 if( (bits & TIOCM_RTS) && !ISSET(tp->t_cflag, CRTSCTS) ) 1280 cd1400_write_reg(cd, CD1400_MSVR2, CD1400_MSVR2_DTR); 1281 1282 if( bits & TIOCM_DTR ) 1283 cd1400_write_reg(cd, CD1400_MSVR1, CD1400_MSVR1_RTS); 1284 1285 break; 1286 1287 case DMBIC: /* clear bits */ 1288 if( (bits & TIOCM_RTS) && !ISSET(tp->t_cflag, CRTSCTS) ) 1289 cd1400_write_reg(cd, CD1400_MSVR2, 0); 1290 1291 if( bits & TIOCM_DTR ) 1292 cd1400_write_reg(cd, CD1400_MSVR1, 0); 1293 1294 break; 1295 } 1296 1297 splx(s); 1298 return(bits); 1299 } 1300 1301 /* 1302 * Set tty parameters, returns error or 0 on success 1303 */ 1304 int 1305 mtty_param(tp, t) 1306 struct tty *tp; 1307 struct termios *t; 1308 { 1309 dev_t dev = tp->t_dev; 1310 struct mtty_softc *ms = mtty_cd.cd_devs[MAGMA_CARD(dev)]; 1311 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(dev)]; 1312 struct cd1400 *cd = mp->mp_cd1400; 1313 int rbpr, tbpr, rcor, tcor; 1314 u_char mcor1 = 0, mcor2 = 0; 1315 int s, opt; 1316 1317 if( t->c_ospeed && cd1400_compute_baud(t->c_ospeed, cd->cd_clock, &tcor, &tbpr) ) 1318 return(EINVAL); 1319 1320 if( t->c_ispeed && cd1400_compute_baud(t->c_ispeed, cd->cd_clock, &rcor, &rbpr) ) 1321 return(EINVAL); 1322 1323 s = spltty(); 1324 1325 /* hang up the line if ospeed is zero, else raise DTR */ 1326 (void)mtty_modem_control(mp, TIOCM_DTR, (t->c_ospeed == 0 ? DMBIC : DMBIS)); 1327 1328 /* select channel, done in mtty_modem_control() */ 1329 /* cd1400_write_reg(cd, CD1400_CAR, mp->mp_channel); */ 1330 1331 /* set transmit speed */ 1332 if( t->c_ospeed ) { 1333 cd1400_write_reg(cd, CD1400_TCOR, tcor); 1334 cd1400_write_reg(cd, CD1400_TBPR, tbpr); 1335 } 1336 1337 /* set receive speed */ 1338 if( t->c_ispeed ) { 1339 cd1400_write_reg(cd, CD1400_RCOR, rcor); 1340 cd1400_write_reg(cd, CD1400_RBPR, rbpr); 1341 } 1342 1343 /* enable transmitting and receiving on this channel */ 1344 opt = CD1400_CCR_CMDCHANCTL | CD1400_CCR_XMTEN | CD1400_CCR_RCVEN; 1345 cd1400_write_ccr(cd, opt); 1346 1347 /* set parity, data and stop bits */ 1348 opt = 0; 1349 if( ISSET(t->c_cflag, PARENB) ) 1350 opt |= (ISSET(t->c_cflag, PARODD) ? CD1400_COR1_PARODD : CD1400_COR1_PARNORMAL); 1351 1352 if( !ISSET(t->c_iflag, INPCK) ) 1353 opt |= CD1400_COR1_NOINPCK; /* no parity checking */ 1354 1355 if( ISSET(t->c_cflag, CSTOPB) ) 1356 opt |= CD1400_COR1_STOP2; 1357 1358 switch( t->c_cflag & CSIZE ) { 1359 case CS5: 1360 opt |= CD1400_COR1_CS5; 1361 break; 1362 1363 case CS6: 1364 opt |= CD1400_COR1_CS6; 1365 break; 1366 1367 case CS7: 1368 opt |= CD1400_COR1_CS7; 1369 break; 1370 1371 default: 1372 opt |= CD1400_COR1_CS8; 1373 break; 1374 } 1375 1376 cd1400_write_reg(cd, CD1400_COR1, opt); 1377 1378 /* 1379 * enable Embedded Transmit Commands (for breaks) 1380 * use the CD1400 automatic CTS flow control if CRTSCTS is set 1381 */ 1382 opt = CD1400_COR2_ETC; 1383 if( ISSET(t->c_cflag, CRTSCTS) ) opt |= CD1400_COR2_CCTS_OFLOW; 1384 cd1400_write_reg(cd, CD1400_COR2, opt); 1385 1386 cd1400_write_reg(cd, CD1400_COR3, MTTY_RX_FIFO_THRESHOLD); 1387 1388 cd1400_write_ccr(cd, CD1400_CCR_CMDCORCHG | CD1400_CCR_COR1 | CD1400_CCR_COR2 | CD1400_CCR_COR3); 1389 1390 cd1400_write_reg(cd, CD1400_COR4, CD1400_COR4_PFO_EXCEPTION); 1391 cd1400_write_reg(cd, CD1400_COR5, 0); 1392 1393 /* 1394 * if automatic RTS handshaking enabled, set DTR threshold 1395 * (RTS and DTR lines are switched, CD1400 thinks its DTR) 1396 */ 1397 if( ISSET(t->c_cflag, CRTSCTS) ) 1398 mcor1 = MTTY_RX_DTR_THRESHOLD; 1399 1400 /* set up `carrier detect' interrupts */ 1401 if( cd->cd_parmode ) { 1402 SET(mcor1, CD1400_MCOR1_DSRzd); 1403 SET(mcor2, CD1400_MCOR2_DSRod); 1404 } else { 1405 SET(mcor1, CD1400_MCOR1_CDzd); 1406 SET(mcor2, CD1400_MCOR2_CDod); 1407 } 1408 1409 cd1400_write_reg(cd, CD1400_MCOR1, mcor1); 1410 cd1400_write_reg(cd, CD1400_MCOR2, mcor2); 1411 1412 /* receive timeout 2ms */ 1413 cd1400_write_reg(cd, CD1400_RTPR, 2); 1414 1415 splx(s); 1416 return(0); 1417 } 1418 1419 /************************************************************************ 1420 * 1421 * MBPP Routines 1422 * 1423 * mbpp_match match one mbpp device 1424 * mbpp_attach attach mbpp devices 1425 * mbppopen open mbpp device 1426 * mbppclose close mbpp device 1427 * mbppread read from mbpp 1428 * mbppwrite write to mbpp 1429 * mbppioctl do ioctl on mbpp 1430 * mbppselect do select on mbpp 1431 * mbpp_rw general rw routine 1432 * mbpp_timeout rw timeout 1433 * mbpp_start rw start after delay 1434 * mbpp_send send data 1435 * mbpp_recv recv data 1436 */ 1437 1438 int 1439 mbpp_match(parent, cf, args) 1440 struct device *parent; 1441 struct cfdata *cf; 1442 void *args; 1443 { 1444 struct magma_softc *sc = (struct magma_softc *)parent; 1445 1446 return( args == mbpp_match && sc->ms_board->mb_npar && sc->ms_mbpp == NULL ); 1447 } 1448 1449 void 1450 mbpp_attach(parent, dev, args) 1451 struct device *parent; 1452 struct device *dev; 1453 void *args; 1454 { 1455 struct magma_softc *sc = (struct magma_softc *)parent; 1456 struct mbpp_softc *ms = (struct mbpp_softc *)dev; 1457 struct mbpp_port *mp; 1458 int port; 1459 1460 sc->ms_mbpp = ms; 1461 dprintf((" addr %p", ms)); 1462 1463 for( port = 0 ; port < sc->ms_board->mb_npar ; port++ ) { 1464 mp = &ms->ms_port[port]; 1465 1466 callout_init(&mp->mp_timeout_ch); 1467 callout_init(&mp->mp_start_ch); 1468 1469 if( sc->ms_ncd1190 ) 1470 mp->mp_cd1190 = &sc->ms_cd1190[port]; 1471 else 1472 mp->mp_cd1400 = &sc->ms_cd1400[0]; 1473 } 1474 1475 ms->ms_nports = port; 1476 printf(": %d port%s\n", port, port == 1 ? "" : "s"); 1477 } 1478 1479 /* 1480 * open routine. returns zero if successful, else error code 1481 */ 1482 int 1483 mbppopen(devvp, flags, mode, p) 1484 struct vnode *devvp; 1485 int flags; 1486 int mode; 1487 struct proc *p; 1488 { 1489 dev_t dev = vdev_rdev(devvp); 1490 int card = MAGMA_CARD(dev); 1491 int port = MAGMA_PORT(dev); 1492 struct mbpp_softc *ms; 1493 struct mbpp_port *mp; 1494 int s; 1495 1496 if( card >= mbpp_cd.cd_ndevs || 1497 (ms = mbpp_cd.cd_devs[card]) == NULL || port >= ms->ms_nports ) 1498 return(ENXIO); 1499 1500 mp = &ms->ms_port[port]; 1501 1502 s = spltty(); 1503 if( ISSET(mp->mp_flags, MBPPF_OPEN) ) { 1504 splx(s); 1505 return(EBUSY); 1506 } 1507 SET(mp->mp_flags, MBPPF_OPEN); 1508 splx(s); 1509 1510 vdev_setprivdata(devvp, ms); 1511 1512 /* set defaults */ 1513 mp->mp_burst = MBPP_BURST; 1514 mp->mp_timeout = mbpp_mstohz(MBPP_TIMEOUT); 1515 mp->mp_delay = mbpp_mstohz(MBPP_DELAY); 1516 1517 /* init chips */ 1518 if( mp->mp_cd1400 ) { /* CD1400 */ 1519 struct cd1400 *cd = mp->mp_cd1400; 1520 1521 /* set up CD1400 channel */ 1522 s = spltty(); 1523 cd1400_write_reg(cd, CD1400_CAR, 0); 1524 cd1400_write_ccr(cd, CD1400_CCR_CMDRESET); 1525 cd1400_write_reg(cd, CD1400_LIVR, (1<<3)); 1526 splx(s); 1527 } else { /* CD1190 */ 1528 mp->mp_flags = 0; 1529 return (ENXIO); 1530 } 1531 1532 return (0); 1533 } 1534 1535 /* 1536 * close routine. returns zero if successful, else error code 1537 */ 1538 int 1539 mbppclose(devvp, flag, mode, p) 1540 struct vnode *devvp; 1541 int flag; 1542 int mode; 1543 struct proc *p; 1544 { 1545 dev_t dev = vdev_rdev(devvp); 1546 struct mbpp_softc *ms = vdev_privdata(devvp); 1547 struct mbpp_port *mp = &ms->ms_port[MAGMA_PORT(dev)]; 1548 1549 mp->mp_flags = 0; 1550 return(0); 1551 } 1552 1553 /* 1554 * Read routine 1555 */ 1556 int 1557 mbppread(devvp, uio, flags) 1558 struct vnode *devvp; 1559 struct uio *uio; 1560 int flags; 1561 { 1562 1563 return mbpp_rw(devvp, uio); 1564 } 1565 1566 /* 1567 * Write routine 1568 */ 1569 int 1570 mbppwrite(devvp, uio, flags) 1571 struct vnode *devvp; 1572 struct uio *uio; 1573 int flags; 1574 { 1575 1576 return mbpp_rw(devvp, uio); 1577 } 1578 1579 /* 1580 * ioctl routine 1581 */ 1582 int 1583 mbppioctl(devvp, cmd, data, flags, p) 1584 struct vnode *devvp; 1585 u_long cmd; 1586 caddr_t data; 1587 int flags; 1588 struct proc *p; 1589 { 1590 dev_t dev = vdev_rdev(devvp); 1591 struct mbpp_softc *ms = vdev_privdata(devvp); 1592 struct mbpp_port *mp = &ms->ms_port[MAGMA_PORT(dev)]; 1593 struct mbpp_param *bp; 1594 int error = 0; 1595 int s; 1596 1597 switch(cmd) { 1598 case MBPPIOCSPARAM: 1599 bp = (struct mbpp_param *)data; 1600 if( bp->bp_burst < MBPP_BURST_MIN || bp->bp_burst > MBPP_BURST_MAX || 1601 bp->bp_delay < MBPP_DELAY_MIN || bp->bp_delay > MBPP_DELAY_MIN ) { 1602 error = EINVAL; 1603 } else { 1604 mp->mp_burst = bp->bp_burst; 1605 mp->mp_timeout = mbpp_mstohz(bp->bp_timeout); 1606 mp->mp_delay = mbpp_mstohz(bp->bp_delay); 1607 } 1608 break; 1609 case MBPPIOCGPARAM: 1610 bp = (struct mbpp_param *)data; 1611 bp->bp_burst = mp->mp_burst; 1612 bp->bp_timeout = mbpp_hztoms(mp->mp_timeout); 1613 bp->bp_delay = mbpp_hztoms(mp->mp_delay); 1614 break; 1615 case MBPPIOCGSTAT: 1616 /* XXX make this more generic */ 1617 s = spltty(); 1618 cd1400_write_reg(mp->mp_cd1400, CD1400_CAR, 0); 1619 *(int *)data = cd1400_read_reg(mp->mp_cd1400, CD1400_PSVR); 1620 splx(s); 1621 break; 1622 default: 1623 error = ENOTTY; 1624 } 1625 1626 return(error); 1627 } 1628 1629 /* 1630 * poll routine 1631 */ 1632 int 1633 mbpppoll(devvp, rw, p) 1634 struct vnode *devvp; 1635 int rw; 1636 struct proc *p; 1637 { 1638 1639 return(ENODEV); 1640 } 1641 1642 int 1643 mbpp_rw(devvp, uio) 1644 struct vnode *devvp; 1645 struct uio *uio; 1646 { 1647 dev_t dev = vdev_rdev(devvp); 1648 int port = MAGMA_PORT(dev); 1649 struct mbpp_softc *ms = vdev_privdata(devvp); 1650 struct mbpp_port *mp = &ms->ms_port[port]; 1651 caddr_t buffer, ptr; 1652 int buflen, cnt, len; 1653 int s, error = 0; 1654 int gotdata = 0; 1655 1656 if( uio->uio_resid == 0 ) 1657 return(0); 1658 1659 buflen = min(uio->uio_resid, mp->mp_burst); 1660 buffer = malloc(buflen, M_DEVBUF, M_WAITOK); 1661 if( buffer == NULL ) 1662 return(ENOMEM); 1663 1664 SET(mp->mp_flags, MBPPF_UIO); 1665 1666 /* 1667 * start timeout, if needed 1668 */ 1669 if( mp->mp_timeout > 0 ) { 1670 SET(mp->mp_flags, MBPPF_TIMEOUT); 1671 callout_reset(&mp->mp_timeout_ch, mp->mp_timeout, 1672 mbpp_timeout, mp); 1673 } 1674 1675 len = cnt = 0; 1676 while( uio->uio_resid > 0 ) { 1677 len = min(buflen, uio->uio_resid); 1678 ptr = buffer; 1679 1680 if( uio->uio_rw == UIO_WRITE ) { 1681 error = uiomove(ptr, len, uio); 1682 if( error ) break; 1683 } 1684 again: /* goto bad */ 1685 /* timed out? */ 1686 if( !ISSET(mp->mp_flags, MBPPF_UIO) ) 1687 break; 1688 1689 /* 1690 * perform the operation 1691 */ 1692 if( uio->uio_rw == UIO_WRITE ) { 1693 cnt = mbpp_send(mp, ptr, len); 1694 } else { 1695 cnt = mbpp_recv(mp, ptr, len); 1696 } 1697 1698 if( uio->uio_rw == UIO_READ ) { 1699 if( cnt ) { 1700 error = uiomove(ptr, cnt, uio); 1701 if( error ) break; 1702 gotdata++; 1703 } 1704 else if( gotdata ) /* consider us done */ 1705 break; 1706 } 1707 1708 /* timed out? */ 1709 if( !ISSET(mp->mp_flags, MBPPF_UIO) ) 1710 break; 1711 1712 /* 1713 * poll delay? 1714 */ 1715 if( mp->mp_delay > 0 ) { 1716 s = splsoftclock(); 1717 SET(mp->mp_flags, MBPPF_DELAY); 1718 callout_reset(&mp->mp_start_ch, mp->mp_delay, 1719 mbpp_start, mp); 1720 error = tsleep(mp, PCATCH | PZERO, "mbppdelay", 0); 1721 splx(s); 1722 if( error ) break; 1723 } 1724 1725 /* 1726 * don't call uiomove again until we used all the data we grabbed 1727 */ 1728 if( uio->uio_rw == UIO_WRITE && cnt != len ) { 1729 ptr += cnt; 1730 len -= cnt; 1731 cnt = 0; 1732 goto again; 1733 } 1734 } 1735 1736 /* 1737 * clear timeouts 1738 */ 1739 s = splsoftclock(); 1740 if( ISSET(mp->mp_flags, MBPPF_TIMEOUT) ) { 1741 callout_stop(&mp->mp_timeout_ch); 1742 CLR(mp->mp_flags, MBPPF_TIMEOUT); 1743 } 1744 if( ISSET(mp->mp_flags, MBPPF_DELAY) ) { 1745 callout_stop(&mp->mp_start_ch); 1746 CLR(mp->mp_flags, MBPPF_DELAY); 1747 } 1748 splx(s); 1749 1750 /* 1751 * adjust for those chars that we uiomoved but never actually wrote 1752 */ 1753 if( uio->uio_rw == UIO_WRITE && cnt != len ) { 1754 uio->uio_resid += (len - cnt); 1755 } 1756 1757 free(buffer, M_DEVBUF); 1758 return(error); 1759 } 1760 1761 void 1762 mbpp_timeout(arg) 1763 void *arg; 1764 { 1765 struct mbpp_port *mp = arg; 1766 1767 CLR(mp->mp_flags, MBPPF_UIO | MBPPF_TIMEOUT); 1768 wakeup(mp); 1769 } 1770 1771 void 1772 mbpp_start(arg) 1773 void *arg; 1774 { 1775 struct mbpp_port *mp = arg; 1776 1777 CLR(mp->mp_flags, MBPPF_DELAY); 1778 wakeup(mp); 1779 } 1780 1781 int 1782 mbpp_send(mp, ptr, len) 1783 struct mbpp_port *mp; 1784 caddr_t ptr; 1785 int len; 1786 { 1787 int s; 1788 struct cd1400 *cd = mp->mp_cd1400; 1789 1790 /* set up io information */ 1791 mp->mp_ptr = ptr; 1792 mp->mp_cnt = len; 1793 1794 /* start transmitting */ 1795 s = spltty(); 1796 if( cd ) { 1797 cd1400_write_reg(cd, CD1400_CAR, 0); 1798 1799 /* output strobe width ~1microsecond */ 1800 cd1400_write_reg(cd, CD1400_TBPR, 10); 1801 1802 /* enable channel */ 1803 cd1400_write_ccr(cd, CD1400_CCR_CMDCHANCTL | CD1400_CCR_XMTEN); 1804 cd1400_write_reg(cd, CD1400_SRER, CD1400_SRER_TXRDY); 1805 } 1806 1807 /* ZZzzz... */ 1808 tsleep(mp, PCATCH | PZERO, "mbpp_send", 0); 1809 1810 /* stop transmitting */ 1811 if( cd ) { 1812 cd1400_write_reg(cd, CD1400_CAR, 0); 1813 1814 /* disable transmitter */ 1815 cd1400_write_reg(cd, CD1400_SRER, 0); 1816 cd1400_write_ccr(cd, CD1400_CCR_CMDCHANCTL | CD1400_CCR_XMTDIS); 1817 1818 /* flush fifo */ 1819 cd1400_write_ccr(cd, CD1400_CCR_CMDRESET | CD1400_CCR_FTF); 1820 } 1821 splx(s); 1822 1823 /* return number of chars sent */ 1824 return(len - mp->mp_cnt); 1825 } 1826 1827 int 1828 mbpp_recv(mp, ptr, len) 1829 struct mbpp_port *mp; 1830 caddr_t ptr; 1831 int len; 1832 { 1833 int s; 1834 struct cd1400 *cd = mp->mp_cd1400; 1835 1836 /* set up io information */ 1837 mp->mp_ptr = ptr; 1838 mp->mp_cnt = len; 1839 1840 /* start receiving */ 1841 s = spltty(); 1842 if( cd ) { 1843 int rcor, rbpr; 1844 1845 cd1400_write_reg(cd, CD1400_CAR, 0); 1846 1847 /* input strobe at 100kbaud (10microseconds) */ 1848 cd1400_compute_baud(100000, cd->cd_clock, &rcor, &rbpr); 1849 cd1400_write_reg(cd, CD1400_RCOR, rcor); 1850 cd1400_write_reg(cd, CD1400_RBPR, rbpr); 1851 1852 /* rx threshold */ 1853 cd1400_write_reg(cd, CD1400_COR3, MBPP_RX_FIFO_THRESHOLD); 1854 cd1400_write_ccr(cd, CD1400_CCR_CMDCORCHG | CD1400_CCR_COR3); 1855 1856 /* enable channel */ 1857 cd1400_write_ccr(cd, CD1400_CCR_CMDCHANCTL | CD1400_CCR_RCVEN); 1858 cd1400_write_reg(cd, CD1400_SRER, CD1400_SRER_RXDATA); 1859 } 1860 1861 /* ZZzzz... */ 1862 tsleep(mp, PCATCH | PZERO, "mbpp_recv", 0); 1863 1864 /* stop receiving */ 1865 if( cd ) { 1866 cd1400_write_reg(cd, CD1400_CAR, 0); 1867 1868 /* disable receiving */ 1869 cd1400_write_reg(cd, CD1400_SRER, 0); 1870 cd1400_write_ccr(cd, CD1400_CCR_CMDCHANCTL | CD1400_CCR_RCVDIS); 1871 } 1872 splx(s); 1873 1874 /* return number of chars received */ 1875 return(len - mp->mp_cnt); 1876 } 1877 1878 int 1879 mbpp_hztoms(h) 1880 int h; 1881 { 1882 int m = h; 1883 1884 if( m > 0 ) 1885 m = m * 1000 / hz; 1886 return(m); 1887 } 1888 1889 int 1890 mbpp_mstohz(m) 1891 int m; 1892 { 1893 int h = m; 1894 1895 if( h > 0 ) { 1896 h = h * hz / 1000; 1897 if( h == 0 ) 1898 h = 1000 / hz; 1899 } 1900 return(h); 1901 } 1902 1903 #endif /* NMAGMA */ 1904
Indexes created Thu Oct 02 14:10:14 GMT 2025